Semiconductor equipment

Abstract

This semiconductor device is provided with: a high-voltage die pad and a low-voltage die pad, which are insulated from each other; a resistive element which is mounted on the high-voltage die pad; and a semiconductor element which is mounted on the low-voltage die pad. The resistive element is provided with: a substrate which is mounted on the high-voltage die pad; an insulating layer which is formed on the substrate; and a thin film resistive layer which is formed on the insulating layer.

Description

Technical Field

[0001] This disclosure relates to a semiconductor device.

Background Art

[0002] Conventionally, a device for detecting a high voltage using a resistive voltage divider circuit has been known. For example, Patent Document 1 discloses a power supply device that detects the voltage of a battery unit by means of a voltage detection circuit including a ladder resistor circuit composed of a plurality of series resistors connected in series with each other and a voltage dividing resistor connecting the voltage dividing points of the plurality of series resistors to the connection point of a high voltage battery, and an A / D converter.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] By the way, in the power supply device of Patent Document 1, when each series resistor is composed of discrete resistors, a plurality of series resistors are arranged side by side on the circuit board on which the power supply device is mounted, and each DC resistor and the A / D converter are provided individually, so that the arrangement space for the plurality of series resistors and the A / D converter on the circuit board becomes large. Note that such a problem is not limited to the power supply device, and can occur similarly in any device including a resistive element and an electronic circuit electrically connected to the resistive element.

Means for Solving the Problems

[0005] A semiconductor device that solves the above problems comprises a first conductive layer and a second conductive layer insulated from each other, a resistive element mounted on the first conductive layer, and a semiconductor element mounted on the second conductive layer, wherein the resistive element comprises a substrate mounted on the first conductive layer, an insulating layer formed on the substrate, and a thin-film resistive layer formed on the insulating layer.

[0006] With this configuration, since the semiconductor device includes both a resistive element and a semiconductor element, the resistive element and the semiconductor element can be placed closer together compared to the case where the resistive element is provided separately from the semiconductor device. Therefore, the mounting space on the circuit board can be reduced. [Effects of the Invention]

[0007] The above semiconductor device makes it possible to reduce the mounting space on the circuit board. [Brief explanation of the drawing]

[0008] [Figure 1] Figure 1 is a block diagram showing a schematic circuit configuration of one embodiment of a semiconductor device. [Figure 2] Figure 2 is a plan view showing the internal configuration of a semiconductor device. [Figure 3] Figure 3 is a magnified view of the resistive element and its surroundings in the semiconductor device shown in Figure 2. [Figure 4] Figure 4 is a cross-sectional view of the semiconductor device shown in Figure 2, taken along line 4-4. [Figure 5] Figure 5 is a cross-sectional view of the semiconductor device shown in Figure 2, taken along line 5-5. [Figure 6] Figure 6 is a plan view of the comparative high-voltage monitor. [Figure 7] Figure 7 is a cross-sectional view of the resistive element in the modified semiconductor device. [Figure 8] Figure 8 shows a magnified view of the resistive element and its surroundings in the modified semiconductor device. [Figure 9] Figure 9 is a magnified view of the resistive element and its surroundings in the modified semiconductor device. [Figure 10] Figure 10 is a plan view showing the internal configuration of the modified semiconductor device. [Modes for carrying out the invention]

[0009] The embodiments of the semiconductor device will be described below with reference to the drawings. The embodiments shown below are examples of configurations and methods for realizing the technical concept, and the materials, structure, arrangement, dimensions, etc. of each component are not limited to those described below.

[0010] An embodiment of the semiconductor device 10 will be described with reference to Figures 1 to 5. The semiconductor device 10 of this embodiment is a high-voltage monitor with high voltage resistance. The rated voltage of the semiconductor device 10 is 1200V. In one example, the semiconductor device 10 is used as a high-voltage monitor to monitor the voltage of the battery of an electric vehicle or a hybrid vehicle. Note that the rated voltage of the semiconductor device 10 is arbitrary.

[0011] As shown in Figure 1, the semiconductor device 10 includes input terminals 11 and 12, output terminals 13A, 13B, 14 to 19, a resistive element 20, and a semiconductor element 40. Input terminals 11 and 12 are terminals of the semiconductor device 10 that are electrically connected to the object to be measured. Here, the object to be measured is the object whose voltage is measured by the semiconductor device 10. For example, input terminal 11 is configured as an input terminal connected to the positive terminal of a battery, and input terminal 12 is configured as an input terminal connected to the negative terminal of a battery. A voltage of, for example, 1200V is applied between input terminals 11 and 12. Input terminals 11 and 12 are electrically connected to the resistive element 20. Here, in this embodiment, input terminal 11 corresponds to the first input terminal, and input terminal 12 corresponds to the second input terminal.

[0012] The resistive element 20 has a ladder resistor circuit 20A in which multiple resistors are electrically connected in series. Input terminal 11 is electrically connected to one of the resistors at both ends of the multiple resistors electrically connected in series, and input terminal 12 is electrically connected to the other resistor at both ends. In other words, a voltage of, for example, 1200V is applied to the resistive element 20 through input terminals 11 and 12.

[0013] As shown in Figure 2, the resistive element 20 has a reference electrode 23 between the first input terminal 11 and the second input terminal 12, a first detection electrode 24 between the reference electrode 23 and the second input terminal 12, and a second detection electrode 25 between the reference electrode 23 and the first input terminal 11. The reference electrode 23, the first detection electrode 24, and the second detection electrode 25 are electrodes from which divided voltages are output from the resistive element 20, and are electrically connected to the semiconductor element 40. The divided voltages from the resistive element 20 include a reference voltage, a first voltage lower than the reference voltage, and a second voltage higher than the reference voltage. The first detection electrode 24 outputs the first voltage, and the second detection electrode 25 outputs the second voltage.

[0014] As shown in Figure 1, the semiconductor element 40 is an element that detects voltage using the voltage divided in the resistive element 20. The semiconductor element 40 is electrically connected to output terminals 13A, 13B, 14-19. The semiconductor element 40 has, for example, multiple operational amplifiers. Output terminals 13A and 13B constitute the ground terminal. A drive voltage is supplied to the semiconductor element 40 to drive the operational amplifiers and other components contained in the semiconductor element 40 using one of the output terminals 14-19.

[0015] As shown in FIGS. 1 and 2, the semiconductor element 40 includes a reference voltage generation unit 40A that generates a reference voltage, a voltage detection unit 40B that detects the voltages applied to the input terminals 11 and 12 using the first voltage of the first detection electrode 24 and the second voltage of the second detection electrode 25, and a short-circuit failure detection unit 40C that outputs the first voltage and the second voltage to the outside of the semiconductor device 10 using any one of the output terminals 14 to 19. An integrated circuit (not shown) electrically connected to the semiconductor element 40 detects a short-circuit failure of the measurement object from the first voltage and the second voltage of the short-circuit failure detection unit 40C.

[0016] As shown in FIG. 2, the semiconductor device 10 includes a high-voltage lead frame 50, a low-voltage lead frame 60, and a sealing resin 70. Both lead frames 50 and 60 contain, for example, Cu (copper). The sealing resin 70 contains a material having electrical insulation properties, and in this embodiment, it contains a black epoxy resin. In FIG. 2, for the convenience of explaining the internal structure of the semiconductor device 10, the sealing resin 70 is shown by a two-dot chain line.

[0017] The high-voltage lead frame 50 and the low-voltage lead frame 60 are arranged apart from each other. In the following description, the arrangement direction of these lead frames 50 and 60 is defined as the x direction, the thickness direction of both lead frames 50 and 60 is defined as the z direction, and the direction orthogonal to the x direction and the z direction is defined as the y direction.

[0018] The high-voltage lead frame 50 has a high-voltage die pad 51 and two high-voltage leads 52 and 53. The high-voltage lead 52 constitutes the input terminal 11 in FIG. 1, and the high-voltage lead 53 constitutes the input terminal 12 in FIG. 1. Here, in this embodiment, the high-voltage die pad 51 corresponds to the first conductive layer, the high-voltage lead 52 corresponds to the first input terminal, and the high-voltage lead 53 corresponds to the second input terminal.

[0019] The high-pressure die pad 51 is placed inside the sealing resin 70. When viewed from the z direction, the shape of the high-pressure die pad 51 is rectangular, with the x direction being the shorter side and the y direction being the longer side. The high-pressure die pad 51 has a main surface 51s and a back surface 51r (see Figure 4) that face opposite each other in the z direction, and sides 51a to 51d that are perpendicular to both the main surface 51s and the back surface 51r. Sides 51a and 51b constitute the end faces of the high-pressure die pad 51 in the x direction, and side faces 51c and 51d constitute the end faces of the high-pressure die pad 51 in the y direction. Side 51a is the side of the high-pressure die pad 51 closest to the low-pressure lead frame 60, and side 51b is the side of the high-pressure die pad 51 furthest from the low-pressure lead frame 60.

[0020] The high-pressure leads 52 and 53 are positioned in the x-direction on the opposite side of the high-pressure die pad 51 from the low-pressure lead frame 60. The high-pressure leads 52 and 53 are positioned across the inside and outside of the sealing resin 70. The high-pressure leads 52 and 53 are positioned at both ends of the high-pressure die pad 51 in the y-direction. Viewed from the z-direction, the high-pressure lead 52 is positioned spaced apart in the x-direction from the end of the high-pressure die pad 51 closer to the side surface 51c in the y-direction. Viewed from the z-direction, the high-pressure lead 53 is positioned at the end of the high-pressure die pad 51 closer to the side surface 51d in the y-direction. Thus, the y-direction can also be said to be the direction of arrangement of the high-pressure leads 52 and 53. The high-pressure lead 53 is integrated with the high-pressure die pad 51. The shape of the high-pressure leads 52 and 53, viewed from the z-direction, is a strip extending in the x-direction. Furthermore, the distance between the high-voltage lead 52 and the high-voltage die pad 51 is set such that the dielectric strength between the high-voltage lead 52 and the high-voltage die pad 51 is approximately 1200V.

[0021] The high-voltage lead 52 is positioned at a distance from the high-voltage die pad 51, and a sealing resin 70 is interposed between the high-voltage lead 52 and the high-voltage lead 53, thus insulating them in the y-direction. The distance between the high-voltage lead 52 and the high-voltage lead 53 protruding from the sealing resin 70 is set such that the dielectric strength between the high-voltage lead 52 and the high-voltage lead 53 is approximately 1200V.

[0022] The low-voltage lead frame 60 has a low-voltage die pad 61 and eight low-voltage leads 62A, 62B, 63-68. In other words, the number of high-voltage leads is less than the number of low-voltage leads. The low-voltage leads 62A and 62B constitute output terminals 13A and 13B, and the low-voltage leads 64-68 constitute output terminals 14-19. In this embodiment, the low-voltage die pad 61 corresponds to the second conductive layer, and the low-voltage leads 62A, 62B, 63-68 correspond to three or more output terminals electrically connected to the semiconductor element.

[0023] The low-pressure die pad 61 is placed inside the sealing resin 70. When viewed from the z direction, the low-pressure die pad 61 has a rectangular shape with the x direction being the shorter side and the y direction being the longer side. In one example, the x-length of the low-pressure die pad 61 may be equal to the x-length of the high-pressure die pad 51, and the y-length of the low-pressure die pad 61 may be equal to the y-length of the high-pressure die pad 51. Therefore, when viewed from the z direction, the area of ​​the low-pressure die pad 61 may be equal to the area of ​​the high-pressure die pad 51.

[0024] The low-pressure die pad 61 was positioned spaced apart from the high-pressure die pad 51 in the x-direction. In other words, the x-direction is the alignment direction of the high-pressure die pad 51 and the low-pressure die pad 61. In this embodiment, the x-direction corresponds to the first direction. Therefore, the y-direction, which is orthogonal to the x-direction, corresponds to the second direction.

[0025] A sealing resin 70 is interposed between the high-voltage die pad 51 and the low-voltage die pad 61. The high-voltage die pad 51 and the low-voltage die pad 61 are insulated from each other. The distance between the high-voltage die pad 51 and the low-voltage die pad 61 is greater than the distance between the high-voltage lead 52 and the high-voltage die pad 51.

[0026] The low-pressure leads 62A, 62B, 63-68 are positioned in the x-direction on the opposite side of the low-pressure die pad 61 from the high-pressure lead frame 50. The low-pressure leads 62A, 62B, 63-68 are positioned across the inside and outside of the sealing resin 70. The low-pressure leads 62A, 62B, 63-68 are aligned in the x-direction but spaced apart in the y-direction. Therefore, the y-direction can also be said to be the direction of arrangement for the low-pressure leads 62A, 62B, 63-68. In the y-direction, the low-pressure leads are arranged in the order 62A, 63, 64, 65, 66, 67, 68, 62B. The low-pressure leads 62A and 62B, which are positioned at both ends in the y-direction, are integrated with the low-pressure die pad 61. The distance between adjacent low-voltage leads 62A, 62B, 63-68 is smaller than the distance between high-voltage leads 52 and 53. In other words, the distance between high-voltage leads 52 and 53 in the y-direction is larger than the distance between adjacent low-voltage leads 62A, 62B, 63-68 in the y-direction.

[0027] A resistive element 20 is mounted on the high-voltage die pad 51. In this embodiment, the resistive element 20 is bonded to the main surface 51s of the high-voltage die pad 51 by a conductive bonding material such as solder or Ag (silver) paste. The resistive element 20 consists of multiple resistors integrated into a single chip.

[0028] Viewed from the z direction, the resistive element 20 is positioned in the y direction, biased towards the high-voltage lead 53 on the high-voltage die pad 51. In other words, viewed from the z direction, the resistive element 20 is positioned in the y direction, biased towards the side surface 51d on the high-voltage die pad 51. It can also be said that the resistive element 20 is positioned on the high-voltage die pad 51 such that its center in the y direction is closer to the high-voltage lead 53 than the center of the high-voltage die pad 51 in the y direction.

[0029] The resistive element 20 has an element surface 20s and an element back surface 20r (see Figure 4). The resistive element 20 is positioned so that its element surface 20s faces the same side as the main surface 51s of the high-voltage die pad 51. When viewed from the z direction, the shape of the resistive element 20 is rectangular, with the x direction being the shorter side and the y direction being the longer side. In other words, the resistive element 20 is mounted on the high-voltage die pad 51 such that its longer side is aligned with the y direction and its shorter side is aligned with the x direction. In this embodiment, the length of the resistive element 20 in the y direction is less than or equal to half the length of the high-voltage die pad 51 in the y direction. In this embodiment, the element surface 20s of the resistive element 20 corresponds to the surface of the resistive element.

[0030] The resistive element 20 comprises a plurality of electrodes formed on the element surface 20s. The plurality of electrodes are formed at positions spaced apart from each other on the element surface 20s. In this embodiment, the plurality of electrodes include a first input electrode 21, a second input electrode 22, a reference electrode 23, a first detection electrode 24, and a second detection electrode 25. The first input electrode 21 is an electrode electrically connected to the high-voltage lead 52, and the second input electrode 22 is an electrode electrically connected to the high-voltage lead 53. The reference electrode 23, the first detection electrode 24, and the second detection electrode 25 are electrodes electrically connected to the semiconductor element 40. In other words, the reference electrode 23, the first detection electrode 24, and the second detection electrode 25 are configured to output a reference voltage, a first voltage, and a second voltage to the semiconductor element 40 as voltage divider voltages from the voltage between the first input electrode 21 and the second input electrode 22, respectively.

[0031] The first input electrode 21 is formed in the corners of the element surface 20s of the resistive element 20, near the sides 51b and 51c of the high-voltage die pad 51, when viewed from the z direction. The second input electrode 22 is formed in the corners of the element surface 20s of the resistive element 20, near the sides 51b and 51d of the high-voltage die pad 51, when viewed from the z direction. In other words, both input electrodes 21 and 22 are positioned at the ends of the element surface 20s of the resistive element 20 that are closer to the high-voltage leads 52 and 53 in the x direction, when viewed from the z direction, and are distributed at both ends of the element surface 20s in the y direction.

[0032] The reference electrode 23 is positioned, when viewed from the z direction, at the end of the element surface 20s of the resistive element 20 that is closer to the side surface 51a of the high-voltage die pad 51, and approximately in the center in the y direction.

[0033] Both detection electrodes 24 and 25 are positioned at the end of the element surface 20s of the resistive element 20 that is closer to the side surface 51a of the high-voltage die pad 51, when viewed from the z direction in the x direction. The first detection electrode 24 is positioned closer to the side surface 51d of the high-voltage die pad 51 than the reference electrode 23 on the element surface 20s of the resistive element 20, when viewed from the z direction in the y direction. The first detection electrode 24 is also positioned closer to the reference electrode 23 than the first input electrode 21 on the element surface 20s of the resistive element 20, when viewed from the z direction in the y direction. The second detection electrode 25 is positioned closer to the side surface 51c of the high-voltage die pad 51 than the reference electrode 23 on the element surface 20s of the resistive element 20, when viewed from the z direction in the y direction. The second detection electrode 25 is also positioned closer to the reference electrode 23 than the second input electrode 22 on the element surface 20s of the resistive element 20, when viewed from the z direction in the y direction. As shown in Figure 2, the electrodes 23-25 ​​are aligned in the x-direction and spaced apart in the y-direction.

[0034] The resistive element 20 comprises thin-film resistive layers 32 that constitute the resistive element 20. In this embodiment, multiple thin-film resistive layers 32 are provided. The number of thin-film resistive layers 32 is set according to the resistance value required for the resistive element 20 and the resistance value of each thin-film resistive layer 32. In one example, the number of thin-film resistive layers 32 is set so that the resistance value of the resistive element 20 is 20 MΩ or more. In another example, the number of thin-film resistive layers 32 is greater than the number of electrodes formed on the element surface 20s of the resistive element 20. Multiple thin-film resistive layers 32 are arranged side by side, spaced apart from each other in the y-direction. It can also be said that multiple thin-film resistive layers 32 are arranged in parallel in the y-direction.

[0035] Among the multiple thin-film resistive layers 32, adjacent thin-film resistive layers 32 in the y-direction are connected by connecting wires 33. The connecting wires 33 contain a conductive material, such as Cu. The semiconductor element 40 is mounted on a low-pressure die pad 61. In this embodiment, the semiconductor element 40 is bonded to the low-pressure die pad 61 by a conductive bonding material. The semiconductor element 40 is a single chip containing multiple operational amplifiers.

[0036] When viewed from the z-direction, the semiconductor element 40 has a rectangular shape with the x-direction being the shorter side and the y-direction being the longer side. In this embodiment, the length of the semiconductor element 40 in the y-direction is longer than the length of the resistor element 20 in the y-direction. The size of the semiconductor element 40 is arbitrary; for example, the length of the semiconductor element 40 in the y-direction may be less than or equal to the length of the resistor element 20 in the y-direction.

[0037] The semiconductor element 40 has an element surface 40s and an element back surface (not shown). The semiconductor element 40 is positioned on the low-voltage die pad 61 such that the element surface 40s faces the same side as the element surface 20s of the resistive element 20.

[0038] The semiconductor device 40 comprises a plurality of device electrodes formed on the device surface 40s. The plurality of device electrodes are formed at positions spaced apart from each other on the device surface 40s. The plurality of device electrodes include first to ninth device electrodes 41 to 49. The first device electrode 41, the second device electrode 42, and the third device electrode 43 are electrodes electrically connected to the reference electrode 23, the first detection electrode 24, and the second detection electrode 25 of the resistive device 20. Each of the device electrodes 44 to 49 is an electrode electrically connected to the low-voltage leads 62A, 62B, 63, 65, 66, and 68.

[0039] The two lead frames 50 and 60, the resistive element 20, and the semiconductor element 40 are connected by a plurality of wires. In this embodiment, the plurality of wires include the first to eleventh wires W1 to W11. That is, the semiconductor device 10 is equipped with the first to eleventh wires W1 to W11. Each wire W1 to W11 contains a conductive material such as Au (gold), Cu, or Al (aluminum), and is a bonding wire formed, for example, by a wire bonding apparatus.

[0040] The first input electrode 21 of the resistive element 20 and the high-voltage lead 52 are connected by a first wire W1, and the second input electrode 22 of the resistive element 20 and the high-voltage lead 53 are connected by a second wire W2.

[0041] The reference electrode 23 of the resistive element 20 and the first element electrode 41 of the semiconductor element 40 are connected by a third wire W3, the first detection electrode 24 of the resistive element 20 and the second element electrode 42 of the semiconductor element 40 are connected by a fourth wire W4, and the second detection electrode 25 of the resistive element 20 and the third element electrode 43 of the semiconductor element 40 are connected by a fifth wire W5.

[0042] The fourth element electrode 44 of the semiconductor element 40 and the low-voltage lead 62A are connected by the sixth wire W6, and the fifth element electrode 45 of the semiconductor element 40 and the low-voltage lead 62B are connected by the seventh wire W7. Furthermore, the sixth element electrode 46 of the semiconductor element 40 and the low-voltage lead 63 are connected by the eighth wire W8, the seventh element electrode 47 of the semiconductor element 40 and the low-voltage lead 65 are connected by the ninth wire W9, the eighth element electrode 48 of the semiconductor element 40 and the low-voltage lead 66 are connected by the tenth wire W10, and the ninth element electrode 49 of the semiconductor element 40 and the low-voltage lead 68 are connected by the eleventh wire W11. In this way, the high-voltage leads 52 and 53 are electrically connected to the resistive element 20, the resistive element 20 is electrically connected to the semiconductor element 40, and the semiconductor element 40 is electrically connected to the low-voltage leads 62A, 62B, 63, 65, 66, and 68.

[0043] As shown in Figure 2, the sealing resin 70 seals the high-voltage die pad 51, the low-voltage die pad 61, the resistive element 20, and the semiconductor element 40. The sealing resin 70 also seals each of the wires W1 to W11.

[0044] Next, the detailed configuration of the resistive element 20 will be described with reference to Figures 3 to 5. Figure 4 is a cross-sectional view of the semiconductor device 10 in Figure 2, taken along line 4-4, and Figure 5 is a cross-sectional view of the semiconductor device 10 in Figure 2, taken along line 5-5.

[0045] As shown in Figure 4, the resistive element 20 comprises a substrate 30, an insulating layer 31 formed on the substrate 30, and a plurality of thin-film resistive layers 32 formed on the insulating layer 31. The substrate 30 is formed from a semiconductor substrate with the z-direction as the thickness direction, and in one example, it is formed from a substrate made of a material containing Si (silicon). In this embodiment, the substrate 30 is a Si substrate. The substrate 30 has a main substrate surface 30s and a substrate back surface 30r that face opposite each other in the z-direction. The substrate back surface 30r constitutes the element back surface 20r of the resistive element 20. In other words, the substrate 30 is bonded to the high-voltage die pad 51 via a conductive bonding material. It can also be said that the substrate 30 is mounted on the high-voltage die pad 51. Therefore, the potential of the substrate 30 and the potential of the high-voltage die pad 51 are equal. The z-direction can also be said to be the thickness direction of the substrate 30.

[0046] In this embodiment, multiple insulating layers 31 are laminated on the main surface 30s of the substrate 30 in the z direction. An insulating coating layer 31C is laminated on the uppermost insulating layer 31 of the multiple insulating layers 31. In this embodiment, the total thickness T1 of the multiple insulating layers 31 and the insulating coating layer 31C is greater than the thickness T2 of the substrate 30 (T1 > T2). The number of insulating layers 31 is set according to the required dielectric strength of the resistive element 20.

[0047] The insulating layer 31 comprises a first insulating layer 31A and a second insulating layer 31B formed on the first insulating layer 31A and containing SiO2 (silicon oxide). The first insulating layer 31A includes, for example, SiN (silicon nitride), SiC (silicon carbide), SiCN (nitrogen-doped silicon carbide), etc. In this embodiment, the first insulating layer 31A contains SiN. The second insulating layer 31B is, for example, an interlayer insulating film. The thickness of the first insulating layer 31A is thinner than the thickness of the second insulating layer 31B. The bottom insulating layer 31 that is in contact with the main substrate surface 30s of the substrate 30 is composed only of the second insulating layer 31B.

[0048] The thin-film resistive layer 32 is formed on the insulating layer 31. More specifically, the thin-film resistive layer 32 is formed on the second insulating layer 31B. The thin-film resistive layer 32 contains CrSi (chromium silicide). In this embodiment, the thickness T3 of the thin-film resistive layer 32 is thinner than the thickness T4 of the insulating layer 31.

[0049] The insulating coating layer 31C covers the thin-film resistive layer 32. The insulating coating layer 31C is laminated on the thin-film resistive layer 32. The insulating coating layer 31C is formed of the same material as, for example, the second insulating layer 31B. The thin-film resistive layer 32 is sandwiched between the insulating layer 31 and the insulating coating layer 31C.

[0050] Here, if we consider the insulating layer 31 and the insulating coating layer 31C as a single insulator, then the thin-film resistive layer 32 can be said to be embedded within the insulator. Furthermore, the insulating coating layer 31C constitutes the uppermost layer of the insulator. Here, the element surface 20s of the resistive element 20 is the surface of the insulator, in other words, the surface of the insulating coating layer 31C.

[0051] The thickness of the multiple insulating layers 31 is greater than the thickness of the insulating coating layer 31C. Therefore, the thin-film resistive layer 32 is positioned closer to the element surface 20s of the resistive element 20 than to the substrate 30. In other words, the thin-film resistive layer 32 is provided in the insulator at a position further away from the substrate 30 than the center in the thickness direction (z direction).

[0052] As shown in Figures 3 and 4, each thin-film resistive layer 32 extends in the x-direction. In other words, each thin-film resistive layer 32 can be said to extend in the direction of the arrangement of the high-voltage die pad 51 and the low-voltage die pad 61 (see Figure 2). Furthermore, each thin-film resistive layer 32 can be said to extend along the short-side direction of the resistive element 20.

[0053] As shown in Figure 3, the shape of the thin-film resistive layer 32 viewed from the z direction is a narrow strip with the x direction being the longer side and the y direction being the shorter side. Viewed from the z direction, the multiple thin-film resistive layers 32 are aligned in the x direction and spaced apart in the y direction. In other words, the multiple thin-film resistive layers 32 are spaced apart in a direction perpendicular to the arrangement direction of the high-voltage die pads 51 and low-voltage die pads 61 when viewed from the z direction. It can also be said that the multiple thin-film resistive layers 32 are spaced apart in the arrangement direction of the high-voltage leads 52, 53 (see Figure 2) when viewed from the z direction. Furthermore, it can also be said that the multiple thin-film resistive layers 32 are spaced apart in the arrangement direction of the low-voltage leads 62A, 62B, 63-68 when viewed from the z direction.

[0054] In this embodiment, the sizes of the multiple thin-film resistive layers 32 are equal. That is, the length in the x-direction, the length in the y-direction, and the thickness in the z-direction of each thin-film resistive layer 32 are equal. Furthermore, the multiple thin-film resistive layers 32 are arranged at equal pitches.

[0055] As shown in Figure 5, the multiple thin-film resistive layers 32 are aligned in the z-direction and spaced apart in the direction perpendicular to the z-direction (the y-direction in this embodiment). In other words, the multiple thin-film resistive layers 32 are formed on the same layer of the multiple insulating layers 31. In this embodiment, the distance between adjacent thin-film resistive layers 32 in the y-direction is smaller than the length of the thin-film resistive layer 32 in the y-direction (the width of the thin-film resistive layer 32).

[0056] Next, we will describe in detail the connection configuration between the multiple thin-film resistive layers 32. In the following description, for convenience, three thin-film resistive layers 32 that are adjacent in the y-direction will be referred to as the first thin-film resistive layer 32A, the second thin-film resistive layer 32B, and the third thin-film resistive layer 32C. In other words, the multiple thin-film resistive layers 32 can be said to include the first thin-film resistive layer 32A, the second thin-film resistive layer 32B, and the third thin-film resistive layer 32C. These thin-film resistive layers 32A to 32C are arranged in the order of the first thin-film resistive layer 32A, the second thin-film resistive layer 32B, and the third thin-film resistive layer 32C in the y-direction. The first thin-film resistive layer 32A is positioned closest to the side surface 51d of the high-voltage die pad 51 when viewed from the z-direction. Furthermore, the first thin-film resistive layer 32A, the second thin-film resistive layer 32B, and the third thin-film resistive layer 32C each have a first end 32P and a second end 32Q. The first end 32P and the second end 32Q constitute the x-direction ends of each thin film resistive layer 32A to 32C. The first end 32P is the end of each thin film resistive layer 32A to 32C closest to the low-pressure die pad 61 (see Figure 2), and the second end 32Q is the end of each thin film resistive layer 32A to 32C furthest from the low-pressure die pad 61.

[0057] As shown in Figure 3, the first thin-film resistive layer 32A and the second thin-film resistive layer 32B are electrically connected at their first ends 32P. Specifically, the first end 32P of the first thin-film resistive layer 32A and the first end 32P of the second thin-film resistive layer 32B are connected by a connecting wire 33. The connecting wire 33 extends along the y-direction. Viewed from the z-direction, the connecting wire 33 is positioned to overlap with both the first end 32P of the first thin-film resistive layer 32A and the first end 32P of the second thin-film resistive layer 32B.

[0058] The second thin-film resistive layer 32B and the third thin-film resistive layer 32C are electrically connected at their second ends 32Q. Specifically, the second end 32Q of the second thin-film resistive layer 32B and the second end 32Q of the third thin-film resistive layer 32C are connected by a connecting wire 33. The connecting wire 33 extends along the y-direction. Viewed from the z-direction, the connecting wire 33 is positioned to overlap with both the second end 32Q of the second thin-film resistive layer 32B and the second end 32Q of the third thin-film resistive layer 32C. The thin-film resistive layers 32 other than the individual thin-film resistive layers 32A to 32C also have the same connection structure as the individual thin-film resistive layers 32A to 32C.

[0059] As shown in Figure 3, when viewed from the z direction, each electrode 21-25 of the resistive element 20 is positioned to overlap with multiple thin-film resistive layers 32. More specifically, viewed from the z-direction, the first input electrode 21 is positioned to overlap with the thin-film resistive layer 32 (first thin-film resistive layer 32A) that is closest to the high-voltage lead 52 among the multiple thin-film resistive layers 32. In this embodiment, viewed from the z-direction, the first input electrode 21 is positioned to overlap with the second end 32Q of this thin-film resistive layer 32. The first input electrode 21 is electrically connected to this thin-film resistive layer 32 (first thin-film resistive layer 32A).

[0060] Viewed from the z-direction, the second input electrode 22 is positioned to overlap with the thin-film resistive layer 32 closest to the high-voltage lead 53 among the multiple thin-film resistive layers 32. In this embodiment, viewed from the z-direction, the second input electrode 22 is positioned to overlap with the end of the thin-film resistive layer 32 furthest from the low-voltage die pad 61 (second end 32Q) in the x-direction. The second input electrode 22 is electrically connected to this thin-film resistive layer 32.

[0061] Thus, the first input electrode 21 is electrically connected to one end of the multiple thin-film resistive layers 32 that are electrically connected in series, and the second input electrode 22 is electrically connected to the other end. In other words, the multiple thin-film resistive layers 32 can also be said to be electrically connected in series between the first input electrode 21 and the second input electrode 22.

[0062] Viewed from the z-direction, the reference electrode 23 is positioned to overlap with the thin film resistive layer 32 that is approximately in the center in the y-direction among the multiple thin film resistive layers 32. In this embodiment, viewed from the z-direction, the reference electrode 23 is positioned to overlap with the end of the approximately central thin film resistive layer 32 that is closer to the low-pressure die pad 61 in the x-direction. The reference electrode 23 is electrically connected to this approximately central thin film resistive layer 32.

[0063] Viewed from the z-direction, the first detection electrode 24 is positioned to overlap with a predetermined thin-film resistive layer 32 located between the central thin-film resistive layer 32 and the first thin-film resistive layer 32A in the y-direction. In this embodiment, viewed from the z-direction, the first detection electrode 24 is positioned to overlap with the end of the thin-film resistive layer 32 in the x-direction that is closer to the low-pressure die pad 61. The first detection electrode 24 is electrically connected to this predetermined thin-film resistive layer 32.

[0064] Viewed from the z-direction, the second detection electrode 25 is positioned to overlap with a predetermined thin-film resistive layer 32 located between the central thin-film resistive layer 32 and the thin-film resistive layer 32 closest to the high-voltage lead 53 among the multiple thin-film resistive layers 32. In this embodiment, viewed from the z-direction, the second detection electrode 25 is positioned to overlap with the end of the thin-film resistive layer 32 in the x-direction that is closer to the low-voltage die pad 61. The second detection electrode 25 is electrically connected to this predetermined thin-film resistive layer 32.

[0065] As shown in Figure 4, the first input electrode 21 is formed on the insulating coating layer 31C. Therefore, the first input electrode 21 is formed at a position offset from the thin-film resistive layer 32 in the z direction. The first input electrode 21 is located further from the substrate 30 than the thin-film resistive layer 32. The first input electrode 21 and the thin-film resistive layer 32 are connected by connecting wiring 34. Although not shown, each electrode 22-25 is formed on the insulating coating layer 31C in the same way as the first input electrode 21. Each electrode 22-25 and the thin-film resistive layer 32 to which these electrodes 22-25 are electrically connected are individually connected by connecting wiring 34. When viewed from the z direction, each electrode 21-25 is positioned to overlap with its corresponding thin-film resistive layer 32, so the connecting wiring 34 consists of wiring extending in the z direction. The connecting wiring 34 is a through-wiring that penetrates the insulating coating layer 31C in its thickness direction (z direction).

[0066] As shown in Figures 4 and 5, the resistive element 20 further comprises a protective film 35 formed on the insulating coating layer 31C and a passivation film 36 formed on the protective film 35. The protective film 35 covers a portion of each electrode 21-25. The protective film 35 is a protective film for the insulating layer 31 and the insulating coating layer 31C, and includes, for example, an SiO2 film. The passivation film 36 is a surface protective film for the resistive element 20, and includes, for example, a SiN film. The protective film 35 and the passivation film 36 can also be said to be films that protect the element surface 20s of the resistive element 20.

[0067] (action) The operation of the semiconductor device 10 of this embodiment will now be described. Figure 6 is a plan view showing a partial example of a high-voltage monitor of the comparative example. The high-voltage monitor of the comparative example has a configuration in which multiple discrete resistors 110 and semiconductor elements 120 are mounted on a circuit board 100. The multiple resistors 110 are electrically connected in series with each other to divide the voltage. Here, since the multiple resistors 110 are formed in separate packages, it is necessary to arrange the multiple resistors 110 side by side on the circuit board 100 with space between them. As a result, as shown in Figure 6, the space required for the multiple resistors 110 becomes large. In addition, since each resistor 110 and semiconductor element 120 are formed in separate packages, wiring is formed on the circuit board 100 to connect each resistor 110 and semiconductor element 120, and it is necessary to arrange each resistor 110 and semiconductor element 120 with space between them by the amount of this wiring. Thus, the high-voltage monitor of the comparative example has the problem of becoming large.

[0068] In this respect, in this embodiment, since the resistive element 20 is a single-chip configuration including multiple thin-film resistive layers 32, the installation space can be reduced compared to a configuration in which multiple resistors 110 are arranged on a circuit board 100. In addition, since the semiconductor element 40 and the resistive element 20 are packaged together, the distance between the semiconductor element 40 and the resistive element 20 can be made smaller than the distance between multiple resistors 110 and semiconductor elements 120.

[0069] (effect) The semiconductor device 10 of this embodiment provides the following advantages. (1) The semiconductor device 10 comprises a high-voltage die pad 51 and a low-voltage die pad 61 that are insulated from each other, a resistive element 20 mounted on the high-voltage die pad 51, and a semiconductor element 40 mounted on the low-voltage die pad 61. The resistive element 20 comprises a substrate 30 mounted on the high-voltage die pad 51, an insulating layer 31 formed on the substrate 30, and a thin-film resistive layer 32 formed on the insulating layer 31.

[0070] With this configuration, since the semiconductor device 10 includes a resistive element 20 and a semiconductor element 40, the resistive element 20 and the semiconductor element 40 can be placed closer together compared to the case where the resistive element 20 is provided separately from the semiconductor device 10. Therefore, when the semiconductor device 10 is mounted on a circuit board, the mounting space on the circuit board can be reduced.

[0071] (2) Since the substrate 30 and the high-voltage die pad 51 are electrically connected by a conductive bonding material, the dielectric breakdown voltage of the resistive element 20 is mainly determined by the distance in the z direction between the main surface 30s of the substrate 30 and each electrode 21 to 25.

[0072] In this embodiment, multiple insulating layers 31 are stacked in the thickness direction (z direction) of the substrate 30. Therefore, the distance between the main surface 30s of the substrate 30 and each electrode 21-25 in the z direction can be made large. Consequently, it becomes easier to ensure the dielectric breakdown voltage of the resistive element 20.

[0073] (3) Each of the plurality of insulating layers 31 has a first insulating layer 31A containing SiN, SiC, or SiCN, and a second insulating layer 31B formed on the first insulating layer 31A and containing SiO2.

[0074] With this configuration, when multiple insulating layers 31 are laminated, the first insulating layer 31A is interposed between adjacent second insulating layers 31B, thereby suppressing warping of the insulating layer 31. (4) The resistive element 20 includes a first input electrode 21 and a second input electrode 22. Multiple thin-film resistive layers 32 are provided and are electrically connected in series between the first input electrode 21 and the second input electrode 22.

[0075] This configuration allows for a smaller arrangement space for the resistive elements 20 compared to a configuration in which discrete resistors are electrically connected in series. In addition, with discrete resistors, when these resistors are electrically connected in series, the variation in the resistance values ​​of each resistor is large, making it difficult to obtain a highly accurate resistance ratio. However, in this embodiment, since the resistance is formed by arranging multiple thin-film resistance layers 32 in parallel in the resistance element 20, the variation in the resistance values ​​of each thin-film resistance layer 32 can be reduced, and a highly accurate resistance ratio can be obtained.

[0076] (5) The multiple thin-film resistive layers 32 are arranged so that their positions in the thickness direction (z direction) of the substrate 30 are aligned with each other, and they are spaced apart from each other in a direction perpendicular to the thickness direction (y direction) of the substrate 30.

[0077] With this configuration, by forming multiple thin-film resistive layers 32 on the same insulating layer 31 (the same second insulating layer 31B), the positions of the multiple thin-film resistive layers 32 are aligned with each other in the z direction. Therefore, since multiple thin-film resistive layers 32 can be formed in the same process, the resistive element 20 can be easily manufactured.

[0078] (6) The resistive element 20 is formed in a rectangular shape having a long side and a short side when viewed from the thickness direction (z direction) of the substrate 30, and is mounted on the high-voltage die pad 51 such that the short side is aligned with the first direction (x direction), which is the arrangement direction of the high-voltage die pad 51 and the low-voltage die pad 61. Each thin-film resistive layer 32 extends along the x direction. The multiple thin-film resistive layers 32 are arranged spaced apart from each other in the second direction (y direction), which is perpendicular to the first direction (x direction), when viewed from the thickness direction (z direction) of the substrate 30.

[0079] With this configuration, the short side of the resistive element 20 is aligned with the arrangement direction of the high-voltage die pad 51 and the low-voltage die pad 61, which allows for miniaturization of the semiconductor device 10. In addition, since the multiple thin-film resistive layers 32 are arranged spaced apart from each other along the long side of the resistive element 20, the number of thin-film resistive layers 32 can be increased. Therefore, it becomes easier to adjust the resistance ratio of the resistive element 20.

[0080] (7) The resistive element 20 is provided with a plurality of electrodes 21 to 25. When viewed from the thickness direction (z direction) of the substrate 30, each electrode 21 to 25 is positioned to overlap with a plurality of thin-film resistive layers 32.

[0081] This configuration allows for a shorter distance between each electrode 21-25 and the multiple thin-film resistive layers 32 that overlap these electrodes 21-25. Consequently, the connecting wiring 34 that connects each electrode 21-25 to the multiple thin-film resistive layers 32 penetrates the insulating coating layer 31C, simplifying the configuration of the connecting wiring 34.

[0082] (8) The high-voltage leads 52 and 53 are located at both ends of the high-voltage die pad 51 in the y-direction. The high-voltage lead 52 is located spaced apart from the high-voltage die pad 51, while the high-voltage lead 53 is integrated with the high-voltage die pad 51. The resistive element 20 is located biased toward the high-voltage lead 53 on the high-voltage die pad 51 in the y-direction.

[0083] In this configuration, the high-voltage die pad 51 is supported by the high-voltage leads 53 during the manufacturing process of the semiconductor device 10. Therefore, by positioning the resistive element 20 biased toward the high-voltage leads 53 on the high-voltage die pad 51, it is possible to suppress the tilting of the high-voltage die pad 51 in the z-direction when the resistive element 20 is mounted on the high-voltage die pad 51.

[0084] (9) The high-voltage leads 52 and 53 are insulated from each other, and the number of high-voltage leads 52 and 53 is less than the number of low-voltage leads 62A, 62B, 63-68. This configuration allows for a larger gap between the high-voltage leads 52 and 53, making it easier to secure a sufficient creepage distance between the high-voltage lead 52 and the high-voltage lead 53.

[0085] (10) The thin-film resistive layer 32 contains CrSi. With this configuration, the thin-film resistive layer 32 can be formed on the second insulating layer 31B containing SiO2.

[0086] (11) The semiconductor device 10 includes a high-voltage die pad 51, a low-voltage die pad 61, a resistive element 20, and a sealing resin 70 that seals the semiconductor element 40. The sealing resin 70 also seals each of the wires W1 to W11.

[0087] This configuration protects the high-voltage die pad 51, the low-voltage die pad 61, the resistive element 20, the semiconductor element 40, and each wire W1 to W11. Furthermore, because the relative movement between the high-voltage die pad 51 and the low-voltage die pad 61 can be restricted, excessive load on each wire W1 to W11 can be suppressed.

[0088] (12) The thin-film resistive layer 32 is positioned closer to the element surface 20s of the resistive element 20 than to the center in the thickness direction (z direction) of the insulator which includes the plurality of insulating layers 31 and insulating coating layer 31C.

[0089] With this configuration, since the thin-film resistive layer 32 is positioned further away from the substrate 30 than the center in the thickness direction of the insulator, the distance between the thin-film resistive layer 32 and the substrate 30 can be increased. Therefore, the dielectric breakdown voltage between the thin-film resistive layer 32 and the substrate 30 can be improved.

[0090] [Example of changes] The embodiments described above are illustrative of possible forms of the semiconductor device according to the Disclosure and are not intended to limit its form. The semiconductor device according to the Disclosure may take forms different from those illustrated in the embodiments above. One example is a form in which some of the configurations of the embodiments above are replaced, modified, or omitted, or a form in which new configurations are added to the embodiments above. Furthermore, the following modifications can be combined with each other as long as they do not technically contradict each other. In the following modifications, parts common to the embodiments above are denoted by the same reference numerals as in the embodiments above, and their descriptions are omitted.

[0091] In the above embodiment, the number of high-voltage leads can be arbitrarily changed. For example, there may be three or more high-voltage leads. In the above embodiment, the number of low-pressure leads can be arbitrarily changed. For example, the number of low-pressure leads may be 7 or less, or 9 or more. Also, the number of low-pressure leads may be less than or equal to the number of high-pressure leads.

[0092] In the above embodiment, the high-pressure leads 52 and 53 were arranged across the inside and outside of the sealing resin 70 in the x-direction, but are not limited to this, and may also be arranged across the inside and outside of the sealing resin 70 in the y-direction. In this case, the high-pressure leads 52 and 53 are spaced apart from each other in the x-direction. That is, the arrangement direction of the high-pressure leads 52 and 53 coincides with the arrangement direction of the high-pressure die pad 51 and the low-pressure die pad 61.

[0093] In the above embodiment, the low-pressure leads 62A, 62B, 63-68 were arranged across the inside and outside of the sealing resin 70 in the x-direction, but are not limited to this, and may be arranged across the inside and outside of the sealing resin 70 in the y-direction. In this case, the low-pressure leads 62A, 62B, 63-68 are spaced apart from each other in the x-direction. That is, the arrangement direction of the low-pressure leads 62A, 62B, 63-68 coincides with the arrangement direction of the high-pressure die pad 51 and the low-pressure die pad 61.

[0094] In the above embodiment, the substrate 30 is not limited to a Si substrate and can be changed as desired. For example, the substrate 30 may be a semiconductor substrate formed from a semiconductor material other than Si. Alternatively, the substrate 30 may be an electrically insulating glass substrate or an SOI (Silicon on Insulator) substrate instead of a semiconductor substrate.

[0095] In the above embodiment, the thin-film resistive layers 32 are arranged in a single line in the y direction with their positions aligned in the z direction, but this is not limited to this. For example, multiple thin-film resistive layers 32 arranged spaced apart in the y direction may be arranged in multiple stages in the z direction. In one example, as shown in Figure 7, multiple thin-film resistive layers 32 arranged spaced apart in the y direction may be arranged in two stages in the z direction. In other words, multiple thin-film resistive layers 32 may be spaced apart in the z direction. One or more insulating coating layers 31C may be interposed between the thin-film resistive layers 32 that are spaced apart in the z direction.

[0096] With this configuration, if the resistance values ​​of the resistive elements 20 are the same, the number of thin-film resistive layers 32 arranged in the y-direction can be reduced, thus allowing for miniaturization of the resistive elements 20 when viewed from the z-direction. Note that the thin-film resistive layers 32 are not limited to two layers, but may be three or more layers.

[0097] In the above embodiment, the plurality of thin-film resistive layers 32 extended in the x-direction and were spaced apart from each other in the y-direction, but this is not limited to this. For example, as shown in Figure 8, the plurality of thin-film resistive layers 32 may extend in the y-direction. In this case, the plurality of thin-film resistive layers 32 are aligned in the y-direction and spaced apart from each other in the x-direction. In other words, the plurality of thin-film resistive layers 32 may be spaced apart from each other in the alignment direction of the high-voltage die pad 51 and the low-voltage die pad 61. To put it another way, the plurality of thin-film resistive layers 32 may extend along the long side direction of the resistive element 20 when viewed from the z-direction and be spaced apart from each other in the short side direction of the resistive element 20.

[0098] In the above embodiment, the lengths of the multiple thin-film resistive layers 32 in the x-direction were equal, but this is not limited to this. The length of at least one of the multiple thin-film resistive layers 32 in the x-direction may be different from the lengths of the other thin-film resistive layers 32 in the x-direction.

[0099] In the above embodiment, the lengths of the multiple thin-film resistive layers 32 in the y-direction were equal, but this is not limited to this. The length of at least one of the multiple thin-film resistive layers 32 in the y-direction may be different from the lengths of the other thin-film resistive layers 32 in the y-direction.

[0100] In the above embodiment, the relationship between the length of each thin-film resistive layer 32 in the y-direction and the length of each electrode 21-25 in the y-direction can be arbitrarily changed. For example, the length of each thin-film resistive layer 32 in the y-direction may be less than or equal to the length of each electrode 21-25 in the y-direction. In this case, the connecting wiring 34 is provided only at the position where the first input electrode 21 and the first thin-film resistive layer 32A overlap when viewed from the z-direction, for example. Similarly, for the other electrodes 22-25, the connecting wiring 34 is provided only at the position where it overlaps with the thin-film resistive layer 32 to which the other electrodes 22-25 should be connected.

[0101] In the above embodiment, multiple thin-film resistive layers 32 were provided, but the invention is not limited to this. For example, as shown in Figure 9, a single thin-film resistive layer 32 may extend in a bellows-like manner. More specifically, the thin-film resistive layer 32 has multiple first resistive layers 32a extending along the x-direction, and second resistive layers 32b connecting adjacent first resistive layers 32a in the y-direction. The second resistive layers 32b alternately connect both ends of the first resistive layers 32a in the x-direction in the y-direction. With this configuration, connection wiring 33 is unnecessary, thus simplifying the configuration of the resistive element 20.

[0102] In the above embodiment, the length of the high-voltage die pad 51 in the y-direction can be arbitrarily changed. For example, as shown in Figure 10, the length of the high-voltage die pad 51 in the y-direction is shorter than the length of the high-voltage die pad 51 in the above embodiment. Viewed from the z-direction, the distance between the side surface 51d of the high-voltage die pad 51 and the resistive element 20 is shorter than the distance between the side surface 51d of the high-voltage die pad 51 and the resistive element 20 in the above embodiment (see Figure 2). In other words, the distance between the high-voltage die pad 51 and the high-voltage lead 52 is longer than the distance between the high-voltage die pad 51 and the high-voltage lead 52 in the above embodiment. This configuration makes it easier to ensure the required dielectric strength between the high-voltage die pad 51 and the high-voltage lead 52.

[0103] In the above embodiment, each electrode 21-25 was positioned to overlap with the multiple thin-film resistive layers 32 when viewed from the z direction, but this is not limited to this. At least one of each electrode 21-25 may be positioned not to overlap with the multiple thin-film resistive layers 32 when viewed from the z direction.

[0104] In the above embodiment, the resistive element 20 and the semiconductor element 40 were connected by three wires, the third to fifth wires W3 to W5, but this is not limited to this. For example, the resistive element 20 and the semiconductor element 40 may be connected by four or more wires, or by one or two wires.

[0105] In the above embodiment, the insulating layer 31 was configured such that a second insulating layer 31B containing SiO2 was formed on a first insulating layer 31A containing SiN, SiC, or SiCN, but it is not limited to this configuration. For example, the insulating layer 31 may be composed of a second insulating layer 31B.

[0106] In the above embodiment, the sealing resin 70 may be omitted from the semiconductor device 10. In the above embodiment, the number of layers of insulating layer 31 can be arbitrarily changed. For example, the insulating layer 31 may be just one layer.

[0107] In the above embodiment, the semiconductor device 10 was a high-voltage monitor, but it is not limited to this and may have other functions. For example, the semiconductor device 10 may be a current monitor or a gate driver. In short, the semiconductor device 10 only needs to include a resistive element and a semiconductor element.

[0108] As used in this disclosure, the term “on / above” includes the meanings of “on / above” and “above / beyond” unless the context clearly indicates otherwise. Therefore, the expression “A is formed on B” is intended to mean that in this embodiment, A may be in contact with B and directly positioned on B, but as a modified example, A may be positioned above B without contacting B. In other words, the term “on / above” does not preclude structures in which other members are formed between A and B.

[0109] The z-direction used in this disclosure does not necessarily have to be vertical, nor does it have to coincide perfectly with the vertical. Therefore, the various structures described herein are not limited to the z-direction "up" and "down" being the same as the z-direction "up" and "down" being the same as the vertical. For example, the x-direction may be vertical, or the y-direction may be vertical. [Note] The technical concepts that can be understood from the above embodiments and each of the above modifications are described below. (Note 1) A first conductive layer and a second conductive layer that are insulated from each other, A resistive element mounted on the aforementioned conductive layer, The semiconductor element mounted on the second conductive layer comprises, The aforementioned resistive element is A substrate mounted on the first conductive layer, An insulating layer formed on the substrate, A semiconductor device comprising a thin-film resistive layer formed on the insulating layer. (Note 2) Multiple insulating layers are stacked in the thickness direction of the substrate. The semiconductor device described in Appendix 1. (Note 3) Each of the plurality of insulating layers comprises a first insulating layer containing SiN, SiC, or SiCN, and a second insulating layer formed on the first insulating layer and containing SiO2. Semiconductor device as described in Appendix 2. (Note 4) The thin-film resistive layer is formed on the second insulating layer. Semiconductor device as described in Appendix 3. (Note 5) The aforementioned resistive element is The surface and, The system comprises a plurality of electrodes formed on the surface, The plurality of electrodes are formed at positions spaced apart from each other on the surface and are electrically connected to the thin-film resistive layer. A semiconductor device as described in any one of the appendices 1 to 4. (Note 6) Viewed from the thickness direction of the substrate, the plurality of electrodes are positioned to overlap with the thin-film resistive layer. Semiconductor device as described in Appendix 5. (Note 7) The plurality of electrodes include a first input electrode and a second input electrode, Multiple thin-film resistive layers are provided, The plurality of thin-film resistive layers are electrically connected in series between the first input electrode and the second input electrode. Semiconductor device as described in Appendix 5 or 6. (Note 8) The plurality of thin-film resistive layers are arranged so that their positions in the thickness direction of the substrate are aligned with each other, and they are spaced apart from each other in a direction perpendicular to the thickness direction of the substrate. Semiconductor device as described in Appendix 7. (Note 9) The resistive element is formed in a rectangular shape having a long side and a short side when viewed from the thickness direction of the substrate, and is mounted on the first conductive layer such that the short side is aligned with the first direction which is the arrangement direction of the first conductive layer and the second conductive layer. Each of the plurality of thin-film resistive layers extends along the first direction, The plurality of thin-film resistive layers are arranged spaced apart from each other in a second direction, which is perpendicular to the first direction, when viewed from the thickness direction of the substrate. Semiconductor device as described in Appendix 8. (Note 10) The plurality of thin-film resistive layers include a first thin-film resistive layer, a second thin-film resistive layer, and a third thin-film resistive layer that are adjacent in the second direction. The first thin-film resistive layer, the second thin-film resistive layer, and the third thin-film resistive layer each have a first end, which is the end closest to the second conductive layer, and a second end, which is the end furthest from the second conductive layer, The first end of the first thin-film resistive layer and the first end of the second thin-film resistive layer are electrically connected. The second end of the second thin-film resistive layer and the second end of the third thin-film resistive layer are electrically connected. The semiconductor device described in Appendix 9. (Note 11) The plurality of thin-film resistive layers are arranged spaced apart in the thickness direction of the substrate. A semiconductor device as described in any one of the appendices 7 to 10. (Note 12) The aforementioned semiconductor device is First input terminal and second input terminal, A first wire connecting the first input electrode and the first input terminal, The device comprises a second wire connecting the second input electrode and the second input terminal. A semiconductor device as described in any one of the appendices 7 to 11. (Note 13) Viewed from the thickness direction of the substrate, if the arrangement direction of the first conductive layer and the second conductive layer is defined as the first direction, and the direction perpendicular to the first direction is defined as the second direction, The first input terminal and the second input terminal are located at both ends of the first conductive layer in the second direction. The first input terminal is positioned spaced apart from the first conductive layer. The second input terminal is integrated with the first conductive layer, The resistive element is arranged in the second direction such that it is biased toward the second input terminal within the first conductive layer. Semiconductor device as described in Appendix 12. (Note 14) Viewed from the thickness direction of the substrate, if the arrangement direction of the first conductive layer and the second conductive layer is defined as the first direction, and the direction perpendicular to the first direction is defined as the second direction, The first input terminal and the second input terminal are insulated in the second direction. Semiconductor device as described in Appendix 12. (Note 15) The semiconductor device has three or more output terminals that are electrically connected to the semiconductor element. A semiconductor device as described in any one of the appendices 12 to 14. (Note 16) The resistive element comprises a reference electrode, a first detection electrode, and a second detection electrode, from which a divided voltage is output from the resistive element. The semiconductor device comprises a first element electrode, a second element electrode, and a third element electrode. The aforementioned semiconductor device is A third wire connecting the reference electrode and the first element electrode, A fourth wire connecting the first detection electrode and the second element electrode, The device comprises a fifth wire connecting the second detection electrode and the third element electrode. A semiconductor device as described in any one of the appendices 12 to 15. (Note 17) The thin film resistive layer contains CrSi. A semiconductor device as described in any one of the appendices 1 to 16. (Note 18) Viewed from the thickness direction of the substrate, the area of ​​the first conductive layer and the area of ​​the second conductive layer are different. A semiconductor device as described in any one of the appendices 1 to 17. (Note 19) The semiconductor device comprises the first conductive layer, the second conductive layer, the resistive element, and a sealing resin that seals the semiconductor element. A semiconductor device as described in any one of the appendices 1 to 18. [Explanation of Symbols]

[0110] 10… Semiconductor equipment 11…Input terminal (1st input terminal) 12…Input terminal (2nd input terminal) 13A, 13B, 14~19…Output terminals 20… Resistor element 21...First input electrode (multiple electrodes) 22...Second input electrode (multiple electrodes) 23…Reference electrode (multiple electrodes) 24…First detection electrode (multiple electrodes) 25…Second detection electrode (multiple electrodes) 30... Circuit board 31…Insulating layer 31A...First insulating layer 31B...Second insulating layer 32…Thin film resistive layer 32A...First thin film resistance layer 32B...Second thin film resistance layer 32C...Third thin film resistance layer 32P…1st end 32Q…Second end 40... Semiconductor elements 41...First element electrode 42...Second element electrode 43...Third element electrode 50…High-voltage lead frame 51…High-voltage die pad (first conductive layer) 52…High-voltage lead (first input terminal) 53…High-voltage lead (second input terminal) 60... Low-voltage lead frame 61... Low-voltage die pad (second conductive layer) 62A, 62B, 63~68... Low-voltage leads (output terminals) 70…Sealing resin W1…First wire W2…Second wire W3...Third wire W4...4th wire W5...5th wire

Claims

1. A first conductive layer and a second conductive layer insulated from each other, A resistive element mounted on the first conductive layer, A semiconductor element mounted on the second conductive layer, Equipped with, The aforementioned resistive element is A substrate mounted on the first conductive layer, An insulating layer formed on the substrate, A thin-film resistive layer formed on the insulating layer, The surface and, Multiple electrodes formed on the surface, Equipped with, The plurality of electrodes are formed at positions spaced apart from each other on the surface and are electrically connected to the thin film resistive layer. The plurality of electrodes include a first input electrode and a second input electrode, Multiple thin-film resistive layers are provided, The plurality of thin-film resistive layers are electrically connected in series between the first input electrode and the second input electrode. The plurality of thin-film resistive layers are arranged so that their positions in the thickness direction of the substrate are aligned with each other, and they are spaced apart from each other in a direction perpendicular to the thickness direction of the substrate. The resistive element is formed in a rectangular shape having a long side and a short side when viewed from the thickness direction of the substrate, and is mounted on the first conductive layer such that the short side is aligned with a first direction which is the arrangement direction of the first conductive layer and the second conductive layer. Each of the aforementioned plurality of thin-film resistive layers extends in the first direction, The plurality of thin-film resistive layers are arranged spaced apart from each other in a second direction, which is perpendicular to the first direction, when viewed from the thickness direction of the substrate. Semiconductor equipment.

2. The plurality of thin-film resistive layers include a first thin-film resistive layer, a second thin-film resistive layer, and a third thin-film resistive layer that are adjacent in the second direction. The first thin-film resistive layer, the second thin-film resistive layer, and the third thin-film resistive layer each have a first end, which is the end closest to the second conductive layer, and a second end, which is the end furthest from the second conductive layer, The first end of the first thin-film resistive layer and the first end of the second thin-film resistive layer are electrically connected. The second end of the second thin film resistive layer and the second end of the third thin film resistive layer They are electrically connected The semiconductor device according to claim 1.

3. A semiconductor device, A first conductive layer and a second conductive layer insulated from each other, A resistive element mounted on the first conductive layer, A semiconductor element mounted on the second conductive layer, First input terminal and second input terminal, Equipped with, The aforementioned resistive element is A substrate mounted on the first conductive layer, An insulating layer formed on the substrate, A thin-film resistive layer formed on the insulating layer, The surface and, Multiple electrodes formed on the surface, Equipped with, The plurality of electrodes are formed at positions spaced apart from each other on the surface and are electrically connected to the thin film resistive layer. The plurality of electrodes include a first input electrode and a second input electrode, Multiple thin-film resistive layers are provided, The plurality of thin-film resistive layers are electrically connected in series between the first input electrode and the second input electrode. The aforementioned semiconductor device is A first wire connecting the first input electrode and the first input terminal, A second wire connecting the second input electrode and the second input terminal, Equipped with, Viewed from the thickness direction of the substrate, if the arrangement direction of the first conductive layer and the second conductive layer is defined as the first direction, and the direction perpendicular to the first direction is defined as the second direction, The first input terminal and the second input terminal are located at both ends of the first conductive layer in the second direction. The first input terminal is positioned spaced apart from the first conductive layer. The second input terminal is integrated with the first conductive layer, The resistive element is arranged in the second direction such that it is biased toward the second input terminal within the first conductive layer. A semiconductor device characterized by the following features.

4. A semiconductor device, A first conductive layer and a second conductive layer insulated from each other, A resistive element mounted on the first conductive layer, A semiconductor element mounted on the second conductive layer, First input terminal and second input terminal, Equipped with, The aforementioned resistive element is A substrate mounted on the first conductive layer, An insulating layer formed on the substrate, A thin-film resistive layer formed on the insulating layer, The surface and, Multiple electrodes formed on the surface, Equipped with, The plurality of electrodes are formed at positions spaced apart from each other on the surface and are electrically connected to the thin film resistive layer. The plurality of electrodes include a first input electrode and a second input electrode, Multiple thin-film resistive layers are provided, The plurality of thin-film resistive layers are electrically connected in series between the first input electrode and the second input electrode. The aforementioned semiconductor device is A first wire connecting the first input electrode and the first input terminal, A second wire connecting the second input electrode and the second input terminal, Equipped with, The resistive element comprises a reference electrode, a first detection electrode, and a second detection electrode, from which a divided voltage is output from the resistive element. The semiconductor device comprises a first element electrode, a second element electrode, and a third element electrode. The aforementioned semiconductor device is A third wire connecting the reference electrode and the first element electrode, A fourth wire connecting the first detection electrode and the second element electrode, A fifth wire connecting the second detection electrode and the third element electrode, Equipped with A semiconductor device characterized by the following features.

5. Viewed from the thickness direction of the substrate, if the arrangement direction of the first conductive layer and the second conductive layer is defined as the first direction, and the direction perpendicular to the first direction is defined as the second direction, The first input terminal and the second input terminal are insulated from each other in the second direction. The semiconductor device according to claim 3 or claim 4.

6. The semiconductor device includes three or more output terminals electrically connected to the semiconductor element. A semiconductor device according to any one of claims 3 to 5.

7. Multiple insulating layers are stacked in the thickness direction of the substrate. A semiconductor device according to any one of claims 1 to 6.

8. Each of the plurality of insulating layers comprises a first insulating layer containing SiN, SiC, or SiCN, and a second insulating layer formed on the first insulating layer and containing SiO2. The semiconductor device according to claim 7.

9. The thin-film resistive layer is formed on the second insulating layer. The semiconductor device according to claim 8.

10. Viewed from the thickness direction of the substrate, the plurality of electrodes are positioned to overlap with the thin-film resistive layer. A semiconductor device according to any one of claims 1 to 9.

11. The plurality of thin-film resistive layers are arranged spaced apart in the thickness direction of the substrate. A semiconductor device according to any one of claims 1 to 10.

12. The thin-film resistive layer contains CrSi. A semiconductor device according to any one of claims 1 to 11.

13. Viewed from the thickness direction of the substrate, the area of ​​the first conductive layer and the area of ​​the second conductive layer are different. A semiconductor device according to any one of claims 1 to 12.

14. The semiconductor device comprises the first conductive layer, the second conductive layer, the resistive element, and a sealing resin that seals the semiconductor element. A semiconductor device according to any one of claims 1 to 13.

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