Chip module and method for forming a chip module

Abstract

Disclosed is a chip module (40a, 40b, 62) including an integrated circuit (IC) chip (34, 64), a first flexible substrate layer (18) having a plurality of holes (28), a second adhesive substrate layer (16) having a plurality of holes (26), and a third substrate layer (14) made of a conductive material, the second substrate layer being sandwiched between and fixedly engaged with the first substrate layer and the third substrate layer, the holes in the first substrate layer and the holes in the second substrate layer being aligned with one another to form a plurality of cavities (12, 66) that each accommodate at least a portion of the IC chip.

Description

Technical Field

[0001] Field of Invention The present invention relates to chip modules such as integrated circuit (IC) chip modules, chip module card inlays comprising such chip modules, methods of forming such chip modules, and methods of forming such chip module card inlays.

Background Art

[0002] Background of the Invention Chip module card inlays are frequently used for the manufacture of smart cards such as credit cards, identity cards, etc. Such cards are frequently used, carried around by users, or when used, they may warp or bend. Such warping and bending of the card have an adverse effect on the structural integrity and proper functioning of the card. Further, conventional chip modules in the smart card industry do not provide a flat and uniform upper surface, which has an adverse effect on the manufacturing process of chip module card inlays and smart cards. In particular, chip modules have conventionally been formed as a stepped structure of two heights or with a non-flat upper housing, as in the chip-on-board method.

Summary of the Invention

Problems to be Solved by the Invention

[0003] Therefore, an object of the present invention is to provide a chip module, a chip module card inlay, a method of forming a chip module, and a method of forming a chip module card inlay, in which the above-mentioned drawbacks are alleviated or at least useful alternatives are provided for the industry and the general public.

Means for Solving the Problems

[0004] Summary of the Invention According to a first aspect of the present invention, a chip module is provided comprising an integrated circuit (IC) chip, a first substrate layer having a first hole and made of at least a partially flexible material, a second substrate layer having a second hole and made of at least a partially adhesive material, and a third substrate layer making of at least a partially conductive material, wherein the second substrate layer is sandwiched between the first substrate layer and the third substrate layer and is fixedly engaged with the first substrate layer and the third substrate layer, the first hole in the first substrate layer and the second hole in the second substrate layer are aligned with each other to form a first cavity, and at least a first portion of the IC chip is housed in the first cavity.

[0005] A chip module card inlay is provided, comprising at least one chip module, wherein the chip module comprises an integrated circuit (IC) chip, a first substrate layer having a first hole and made at least partially of a flexible material, a second substrate layer having a second hole and made at least partially of an adhesive material, and a third substrate layer making at least partially of a conductive material, wherein the second substrate layer is sandwiched between the first substrate layer and the third substrate layer and is fixedly engaged with the first substrate layer and the third substrate layer, the first hole in the first substrate layer and the second hole in the second substrate layer are aligned with each other to form a first cavity, and at least a first portion of the IC chip is housed in the first cavity.

[0006] A third aspect of the present invention provides a method for forming a chip module, comprising: preparing a first substrate layer having a plurality of first holes and made at least partially of a flexible material; preparing a second substrate layer having a plurality of second holes and made at least partially of an adhesive material; preparing a third substrate layer making at least partially of a conductive material; aligning the first holes of the first substrate layer with the second holes of the first substrate layer to form a plurality of first cavities; sandwiching the second substrate layer between the first substrate layer and the third substrate layer; position-fixed engagement of the first substrate layer, the second substrate layer and the third substrate layer to form a first laminated structure; position-fixed engagement of at least a first portion of an integrated circuit (IC) chip into one of the first cavities of the first laminated structure; and cutting out at least one chip module from the first laminated structure that is position-fixed engagement of the IC chip.

[0007] A fourth aspect of the present invention provides a method for forming a chip module card inlay, comprising forming at least one chip module, comprising: preparing a first substrate layer having a plurality of first holes and made of at least a partially flexible material; preparing a second substrate layer having a plurality of second holes and made of at least a partially adhesive material; preparing a third substrate layer making of at least a partially conductive material; and forming a plurality of first cavities by moving the first holes of the first substrate layer to the second holes of the first substrate layer. A method is provided which includes aligning the second substrate layer in a hole, sandwiching the second substrate layer between the first substrate layer and the third substrate layer, positionally engaging the first substrate layer, the second substrate layer and the third substrate layer to form a first stacked structure, positionally engaging at least a first portion of an integrated circuit (IC) chip into one of the cavities of the first cavity of the first stacked structure, and cutting out at least one chip module from the stacked structure that is positionally engaged with the IC chip.

[0008] Embodiments of the present invention will be described simply by reference to the accompanying drawings. [Brief explanation of the drawing]

[0009] [Figure 1] This is a perspective view showing a single chip housing carrier formed from five substrate layers, suitable for forming a chip module and a chip module card inlay, according to one embodiment of the present invention. [Figure 2] Figure 1 is an exploded perspective view of a single chip housing carrier. [Figure 3] Figure 1 is a plan view showing the five substrate layers that form a single chip housing carrier. [Figure 4] This is a front view showing a flip-flop integrated circuit (IC) chip. [Figure 5] This figure shows the steps involved in forming a chip module from a single chip housing carrier shown in Figure 1 and a flip IC chip shown in Figure 4. [Figure 6] This figure shows the steps involved in forming a chip module card inlay from the chip module formed in Figure 5. [Figure 7] Another figure shows the step of forming a chip module card inlay from the chip module formed in Figure 5. [Figure 8] Another figure showing the step of forming a chip module card inlay from the chip module formed in Figure 5. [Figure 9] Another figure showing the step of forming a chip module card inlay from the chip module formed in Figure 5. [Figure 10] This is a cross-sectional view showing a chip module card inlay according to one embodiment of the present invention. [Modes for carrying out the invention]

[0010] Description of the Embodiment Figure 1 shows a single chip housing carrier 10 formed from five substrate layers for forming a chip module and a chip module card inlay, according to one embodiment of the present invention. The chip housing carrier 10 is elongated and may be wound in the form of a reel, and thus unwound for the subsequent steps of forming the chip module and the chip module card inlay. Multiple cavities 12 are formed along the chip housing carrier 10. The cavities 12 may have a square, rectangular, or circular cross-sectional shape. As shown in Figure 1 as an example, the cavities 12 are arranged in three rows, but it should be understood that the chip housing carrier 10 may be formed with a different number of rows of cavities 12.

[0011] Figure 2 is an exploded perspective view of one chip housing carrier 10 shown in Figure 1. The chip housing carrier 10 according to this embodiment consists of five base material layers 14, 16, 18, 20, and 22 stacked on top of each other. According to the present invention, the chip housing carrier 10 may be formed from a different number of base material layers, for example, it may be formed from only base material layers 14, 16, and 18.

[0012] Five substrate layers 14, 16, 18, 20, and 22 are shown individually in Figure 3. Substrate layer 14 is made of copper (or another conductive material). Three rows of slits 24 are formed along the length of substrate layer 14. Substrate layer 16 is provided on top of substrate layer 14, and substrate layer 16 has three rows of holes 26 along its length. Substrate layer 16 is made of an adhesive material. Substrate layer 18 is provided on top of substrate layer 16, and substrate layer 18 has three rows of holes 28 along its length. Substrate layer 18 is flexible and is made of a flexible material such as one or more of the following materials: polyimide (PI), polyethylene terephthalate (PET), and glass-reinforced epoxy laminate materials (such as "FR-4", which is a composite material made of glass fiber woven fabric with a flame-retardant epoxy resin binder).

[0013] A base layer 20 is provided on the base layer 18, and the base layer 20 has three rows of holes 30 along its length. The base layer 20 is made of an adhesive material. A base layer 22 is provided on the base layer 20, and the base layer 22 has three rows of holes 32. The base layer 22 is made of one or more conductive materials, for example, copper and nickel, or is electroplated with one or more conductive materials.

[0014] The holes 26, 28, 30, and 32 in each of the base material layers 16, 18, 20, and 22 are of the same size and shape, and when the base material layers 16, 18, 20, and 22 are properly assembled and stacked on top of each other, the holes 26, 28, 30, and 32 in each of those base material layers 16, 18, 20, and 22 are aligned with each other, so that these holes 26, 28, 30, and 32 collectively form multiple cavities 12 that extend through the base material layer 16 to the base material layer 22. The base material layer 16 is positioned below and in contact with the base material layer 14 such that each slit 24 is positioned below each cavity 12 formed by the rows of aligned holes 26, 28, 30, and 32.

[0015] Figure 4 shows an integrated circuit (IC) chip 34. The IC chip 34 may be a contactless chip or another type of chip. In electronics manufacturing, integrated circuit (IC) packaging is the final stage of semiconductor device manufacturing, in which a block of semiconductor material is sealed within a support case (also known as a “package”) that prevents physical damage and corrosion. A common plastic used to form the package is cresol novolac type epoxy resin (also known as “epoxy-cresol-novolac”). In the IC chip 34, two conductive legs 36 are shown extending from the package 38 of the IC chip 34.

[0016] Referring to FIG. 5, FIG. 5 shows a single chip housing carrier 10 having a plurality of cavities 12 formed by the alignment of holes 26, 28, 30, 32 of respective substrate layers 16, 18, 20, 22 with the substrate layer 14 forming the bottom. The substrate layers 14, 16, 18, 20, 22 are laminated so as to engage with each other in a position - fixing manner to form the chip housing carrier 10 which is a laminated structure. The IC chip 34 is positioned within one of the plurality of cavities 12 such that the legs 36 (and thus the IC chip 34) are in contact with the substrate layer 14 and the IC chip 34 is completely housed within the cavity 12 so that an electrical and physical connection is established between the legs 36 of the IC chip 34 and the substrate layer 14. The depth of the cavity 12 formed by the alignment of the holes 26, 28, 30, 32 of the substrate layers 16, 18, 20, 22 is greater than or equal to the total height h of the IC chip 34. A part of the IC chip 34 is housed within the cavity formed by the holes 26, 28, and another part of the IC chip 34 is housed within the cavity formed by the holes 30, 32.

[0017] When the IC chip 34 is housed within the cavity 12 (and when the legs 36 of the IC chip 34 are physically and electrically connected to the substrate layer 14), an adhesive (glue) is filled into any space within the cavity 12 not occupied by the IC chip 34, thereby strengthening the position - fixing engagement of the IC chip 34 within the cavity 12 and within the chip housing carrier 10.

[0018] When the IC chip 34 is fixedly engaged and housed within the cavity 12 of the chip housing carrier 10, a plurality of chip modules 40a, 40b can be cut out from the chip housing carrier 10, for example, by die cutting. Each of the chip modules 40b, 40c includes an IC chip 34 fixedly housed and engaged within the base material layers 14, 16, 18, 20, 22. In this case, the base material layer 14 is fixedly engaged with the leg portion 36 of the IC chip 34. The respective shapes of the chip modules 40b, 40c are different from each other. Here, the chip module 40b generally has a rectangular prism shape, and the chip module 40c generally has an elliptical cylinder shape. Generally speaking, the chip modules 40a, 40b according to the present invention both have a shape of a relatively short prism, cylinder or elliptical cylinder in terms of thickness / height. More specifically, they may have a shape of a right prism, a straight cylinder or a straight elliptical cylinder. Two opposing main surfaces of the chip module 40a (only one of these main surfaces, i.e., the main surface 41a, is shown in FIG. 5) are flat, have the same shape, and are parallel to each other. Similarly, two opposing main surfaces of the chip module 40b (only one of these main surfaces is shown in FIG. 5) are flat, have the same shape, and are parallel to each other. Therefore, the chip modules 40a, 40b are not a two-step structure in terms of height, nor are they formed with a non-flat upper housing as in the case of conventional chip modules.

[0019] FIGS. 6 to 9 show the steps of forming a chip module card inlay while using the chip module 40a as an example.

[0020] As shown in Figure 6, the chip module 40a is positioned within a hole 42 in a substrate layer 44, which may be made of a plastic material such as polycarbonate (PC), polyvinyl chloride (PVC), or glycol-modified polyethylene terephthalate (PETG). In the case of a conventional chip module with a stepped structure of two heights, at least two such substrate layers (also called "compensation layers") are required to satisfy the requirement of two different shapes of two heights. On the other hand, since the chip module according to the present invention may be in the shape of a prism, cylinder, or ellipse, more specifically a right prism, right circular, or right ellipse, only one compensation layer is required. This facilitates the manufacture of the chip module card inlay (described below) and the subsequent smart card.

[0021] Furthermore, as shown in Figure 7, a conductive wire 46 (made of, for example, copper) is embedded in the main surface 48 of the substrate layer 44. The wire 46 may be bent several times and embedded in the main surface 48 of the substrate layer 44, for example, to form an antenna. The two free ends of the wire 46 are joined to the chip module 40a, for example, by thermal bonding.

[0022] The base layer 44 is sandwiched between two protective base layers 50 and 52. The two base layers 50 and 52 may be made of PC, PVC, or PETG. The base layers 44, 50, and 52, thus stacked on top of each other, are then laminated so as to engage in a fixed position with the base layers 44, 50, and 52 in order to form a laminated structure, which is a chip module card inlay 54.

[0023] Figure 10 shows a cross-sectional view of a chip module card inlay 60 equipped with a chip module 62. The chip module 62 has an IC chip 64 housed in a cavity 66 formed by the alignment of holes 26, 28 in the respective substrate layers 16, 18. The legs 36 of the IC chip 64 are physically and electrically connected to the substrate layer 14 on top of the substrate layer 16. Thus, the substrate layer 16 is sandwiched between the substrate layers 14 and 18 and is fixedly engaged with the substrate layers 14 and 18.

[0024] The chip module 62 is housed within a hole 68 in the inner substrate layer 70 and is electrically connected (e.g., by bonding) to an antenna formed from a conductive wire 72 (which may be made of copper). The inner substrate layer 70 is sandwiched between two outer substrate layers 74, 76. The substrate layers 70, 74, 76 are stacked and therefore fixedly engaged with each other to form the chip module card inlay 60 of the stacked structure. The depth of the cavity 66 formed by the alignment of holes 26, 28 in the substrate layers 16, 18 is greater than or equal to the total height of the IC chip 64.

[0025] The above is merely an illustrative example of how the present invention can be implemented, and it should be understood that modifications and / or changes may be made without departing from the spirit of the invention.

[0026] For clarity, it should be understood that certain features of the invention described in relation to separate embodiments may be provided in combination in one embodiment. Conversely, for the sake of brevity, various features of the invention described in the context of one embodiment may also be provided separately or in any suitable partial combination.

Claims

1. It is a chip module, Integrated circuit (IC) chips, A first substrate layer having a first hole, which is made of at least a partially flexible material, A second substrate layer having a second hole, which is at least partially made of an adhesive material, A third substrate layer consisting of at least partially conductive material and A fourth substrate layer having a third hole, which is at least partially made of adhesive material, A fifth substrate layer having a fourth hole, Includes, The second substrate layer is sandwiched between the first substrate layer and the third substrate layer, and is fixed to the first substrate layer and the third substrate layer. The first holes in the first substrate layer and the second holes in the second substrate layer are aligned with each other to form a first cavity, and At least the first portion of the IC chip is housed within the first cavity. The third hole and the fourth hole are aligned with each other to form a second cavity, and at least the second portion of the IC chip is housed within the second cavity. The depth of the cavity formed by the first cavity and the second cavity is greater than or equal to the total height of the IC chip. Chip module.

2. The chip module according to claim 1, wherein the third substrate layer is at least partially made of copper.

3. The chip module according to claim 1, wherein the third substrate layer includes at least one slit that engages with the legs of the IC chip in order to electrically connect the IC chip to the third substrate layer.

4. The chip module according to claim 1, wherein the first hole and the second hole are substantially the same size and shape.

5. The chip module according to claim 1, wherein the first substrate layer is made of polyimide (PI), polyethylene terephthalate (PET), and / or glass-reinforced epoxy laminate material.

6. The chip module according to claim 1, wherein the third hole and the fourth hole are substantially the same size and shape.

7. The chip module according to claim 1, wherein the fifth substrate layer is made of a conductive material or is electroplated with a conductive material.

8. The chip module according to claim 1, wherein the chip module has the shape of a rectangular prism, a cylinder, or an elliptical prism.

9. A chip module card inlay comprising at least one chip module according to any one of claims 1 to 8.

10. The chip module card inlay according to claim 9, wherein the chip module is housed in a fifth hole of a sixth substrate layer.

11. The chip module card inlay according to claim 10, wherein the sixth substrate layer is sandwiched between the seventh substrate layer and the eighth substrate layer and fixed to the seventh substrate layer and the eighth substrate layer.

12. The chip module card inlay according to claim 9, wherein the chip module is electrically connected to at least one conductive wire.

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