Power conversion system

Abstract

To provide a power conversion system in which cost reduction can be achieved while a capacitor neutral point is present and an insulation transformer is included.SOLUTION: A power conversion system 1A includes an insulation-type DC / DC converter 11 having an insulation transformer 111, a primary side bridge circuit 112P, and a secondary side bridge circuit 112S, primary side capacitors 113P and 114P that are connected to the primary side bridge circuit 112P while being connected in series, a primary side DC voltage detection unit 13P that detects DC voltages respectively generated in the primary side capacitors 113P and 114P, a pulse signal generation unit 14 that generates a pulse signal having a duty ratio corresponding to the ratio of the DC voltages, and an insulation signal transmission unit 15 that transmits, to a control device 16, a signal which is based on the pulse signal inputted from the pulse signal generation unit 14 in a state where the primary side and the secondary side of the insulation-type DC / DC converter 11 are electrically insulated.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] The present invention relates to a power conversion system having a switching element.

Background Art

[0002] In a circuit having a plurality of capacitors connected in series, such as a three-level circuit or a half-bridge circuit, there is a capacitor midpoint which is the connection point of the plurality of capacitors. In a circuit where a capacitor midpoint exists, in order to prevent the voltages generated in each capacitor from becoming unbalanced due to the current difference flowing into each capacitor, it is known to control the potential of the capacitor midpoint to control the balance of the voltages (capacitor voltages) generated in each capacitor (for example, Patent Documents 1 and 2).

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Patent Document 2

Non-Patent Documents

[0004]

Non-Patent Document 1

Non-Patent Document 2

Summary of the Invention

[0005] In a circuit with a capacitor midpoint, controlling the balance of the capacitor voltage applied to each capacitor requires individually detecting the capacitor voltage generated at each capacitor. Furthermore, if the circuit with the capacitor midpoint has an isolation transformer, insulating components such as optical insulating components are used to transmit signals to each other while ensuring electrical isolation between the primary and secondary sides. However, such insulating components are expensive, so if a circuit with a capacitor midpoint has a large number of capacitors, the circuit becomes costly.

[0006] The object of the present invention is to provide a power conversion system that can reduce costs even when a capacitor midpoint exists and an isolation transformer is present. [Means for solving the problem]

[0007] To achieve the above objective, a power conversion system according to one aspect of the present invention includes an isolation transformer, an isolated DC / DC converter having an isolation transformer, a primary bridge circuit provided on the primary side of the isolation transformer and having at least two switch elements, and a secondary bridge circuit provided on the secondary side of the isolation transformer and having at least two switch elements, a control unit that controls the primary bridge circuit and the secondary bridge circuit, a plurality of primary capacitors connected in series to the primary bridge circuit, a plurality of secondary capacitors connected in series to the secondary bridge circuit, and The device comprises: a primary DC voltage detection unit that individually detects the DC voltage generated in each of the plurality of primary capacitors; a secondary DC voltage detection unit that individually detects the DC voltage generated in each of the plurality of secondary capacitors; a pulse signal generation unit that generates a pulse signal with a duty cycle corresponding to the ratio of the plurality of DC voltages detected by either the primary DC voltage detection unit or the secondary DC voltage detection unit; and an isolated signal transmission unit that transmits a signal based on the pulse signal input from the pulse signal generation unit to the control unit while the primary and secondary sides of the isolated DC / DC converter are electrically isolated.

[0008] Furthermore, in order to achieve the above objective, a power conversion system according to another aspect of the present invention comprises: [Effects of the Invention]

[0009] According to each aspect of the present invention, cost reduction can be achieved even when a capacitor midpoint exists and an isolation transformer is present. [Brief explanation of the drawing]

[0010] [Figure 1] This is a block diagram showing an example of a schematic configuration of a power conversion system according to the first embodiment of the present invention. [Figure 2] This is a timing chart showing an example of the operation of a power conversion system according to the first embodiment of the present invention. [Figure 3]This is a diagram illustrating a filter section provided in a power conversion system according to a modified example 1 of the first embodiment of the present invention. [Figure 4] This is a timing chart showing an example of the operation of a power conversion system according to Modification 1 of the First Embodiment of the present invention. [Figure 5] This is a circuit diagram showing an example of a 3-level inverter circuit provided in the primary bridge circuit and the secondary bridge circuit of a power conversion system according to a modified example 2 of the first embodiment of the present invention. [Figure 6] This is a block diagram showing an example of a schematic configuration of a power conversion system according to a second embodiment of the present invention. [Figure 7] This is a circuit diagram showing an example of a primary bridge circuit and a full bridge circuit provided in a secondary bridge circuit in a power conversion system according to a second embodiment of the present invention. [Figure 8] This is a timing chart showing an example of the operation of a power conversion system according to a second embodiment of the present invention. [Figure 9] This is a block diagram showing an example of a schematic configuration of a power conversion system according to a third embodiment of the present invention. [Figure 10] This is a timing chart showing an example of the operation of a power conversion system according to a third embodiment of the present invention. [Modes for carrying out the invention]

[0011] Each embodiment of the present invention illustrates an apparatus or method for embodying the technical concept of the present invention, and the technical concept of the present invention does not limit the materials, shapes, structures, arrangements, etc. of the components to those described below. The technical concept of the present invention can be modified in various ways within the technical scope defined by the claims described in the patent claims.

[0012] [First Embodiment] The power conversion system according to the first embodiment of the present invention will be described with reference to FIGS. 1 to 4. First, the schematic configuration of the power conversion system according to this embodiment will be described with reference to FIG. 1. FIG. 1 is a block diagram showing an example of the schematic configuration of the power conversion system 1A according to this embodiment. In FIG. 1, for ease of understanding, the primary device 2P and the secondary device 2S connected to the power conversion system 1A are shown together.

[0013] (Schematic Configuration of Power Conversion System) The power conversion system 1A includes an isolated DC / DC converter 11 and can supply power bidirectionally between the primary device 2P connected to the primary side PS and the secondary device 2S connected to the secondary side SS. The isolated DC / DC converter 11 is a bidirectional DC / DC (hereinafter sometimes abbreviated as "DC / DC") converter such as a DAB (Dual Active Bridge) converter.

[0014] As shown in Fig. 1, the primary-side device 2P and the secondary-side device 2S are devices connected to the power conversion system 1A. Each of the primary-side device 2P and the secondary-side device 2S may exhibit a function of outputting power and a function of receiving power. For example, one of the primary-side device 2P and the secondary-side device 2S (as an example, the primary-side device 2P) may be a power storage device. When the primary-side device 2P is a power storage device, the primary-side device 2P receives and charges the power transmitted from the other of the primary-side device 2P and the secondary-side device 2S (as an example, the secondary-side device 2S) via the power conversion system 1A. The primary-side device 2P may supply the charged power to the secondary-side device 2S via the power conversion system 1A as needed. Also, for example, one of the primary-side device 2P and the secondary-side device 2S (as an example, the secondary-side device 2S) may be a driving device such as a motor. When the secondary-side device 2S is a driving device, the secondary-side device 2S is driven using the power supplied from the other of the primary-side device 2P and the secondary-side device 2S (as an example, the primary-side device 2P). The secondary-side device 2S may supply the power obtained by regeneration during the regeneration operation to the primary-side device 2P via the power conversion system 1A. Also, each of the primary-side device 2P and the secondary-side device 2S may be, for example, a system combining a solar power generation device and a power storage device. In the present embodiment, the primary-side device 2P is the device on the power supply side, and the secondary-side device 2S is the device on the power receiving side. However, the primary-side device 2P may be the device on the power receiving side, and the secondary-side device 2S may be the device on the power supply side.

[0015] As shown in Fig. 1, the power conversion system 1A includes an isolation type DC / DC converter 11 having an isolation transformer 111, a primary-side bridge circuit 112P provided on the primary side PS of the isolation transformer 111 and having transistors Q11, Q12 (an example of at least two switching elements), and a secondary-side bridge circuit 112S provided on the secondary side SS of the isolation transformer 111 and having transistors Q11, Q12 (an example of at least two switching elements).

[0016] The isolation transformer 111 has a primary winding and a secondary winding. A primary bridge circuit 112P is electrically connected to the primary winding of the isolation transformer 111, and a secondary bridge circuit 112S is electrically connected to the secondary winding of the isolation transformer 111. The winding ratio of the primary and secondary windings of the isolation transformer 111 may be determined according to the ratio of the rated voltages of the primary device 2P and the secondary device 2S.

[0017] The power conversion system 1A has a primary side positive electrode line P1 connected to the positive side of the primary side bridge circuit 112P, and a primary side negative electrode line N1 connected to the negative side of the primary side bridge circuit 112P. The primary side positive electrode line P1 is connected to the positive side terminal of the primary side device 2P. The primary side negative electrode line N1 is connected to the negative side terminal of the primary side device 2P. As a result, the primary side bridge circuit 112P can exchange power with the primary side device 2P and can exchange power with the primary winding of the isolation transformer 111.

[0018] Transistors Q11 and Q12, located in the primary bridge circuit 112P, are connected in series between the primary positive line P1 and the primary negative line N1. Transistors Q11 and Q12 are composed of, for example, metal-oxide-semiconductor field-effect transistors (MOSFETs).

[0019] The primary bridge circuit 112P has a freewheeling diode D11 connected in antiparallel to transistor Q11 and a freewheeling diode D12 connected in antiparallel to transistor Q12. The drain of transistor Q11 is connected to the cathode of freewheeling diode D11. The source of transistor Q11 is connected to the anode of freewheeling diode D11, the drain of transistor Q12, and the cathode of freewheeling diode D12. The gate of transistor Q11 is connected to a gate drive unit (GDU) 12P (details described later) provided in the power conversion system 1A on the primary side PS of the isolated DC / DC converter 11. As a result, the gate pulse signal Sg11 output from the gate drive unit 12P is input to the gate of transistor Q11, and the on (conducting) / off (non-conducting) state of transistor Q11 is controlled.

[0020] The source of transistor Q12 is connected to the anode of freewheeling diode D12. The gate of transistor Q12 is connected to gate drive unit 12P. As a result, the gate pulse signal Sg12 output from gate drive unit 12P is input to the gate of transistor Q12, controlling the on (conducting) / off (non-conducting) state of transistor Q12. The gate drive unit 12P drives transistors Q11 and Q12 using pulse width modulation (PWM) control with gate pulse signals Sg11 and Sg12.

[0021] The drain of transistor Q11 and the cathode of freewheeling diode D11 are connected to the primary side positive line P1. The source of transistor Q12 and the anode of freewheeling diode D12 are connected to the primary side negative line N1. Thus, the primary side bridge circuit 112P has a half-bridge circuit composed of transistors Q11 and Q12 and freewheeling diodes D11 and D12.

[0022] As shown in Figure 1, the isolated DC / DC converter 11 has an inductor 115P positioned between the primary bridge circuit 112P and the primary winding of the isolation transformer 111. One terminal of the inductor 115P is connected to the source of transistor Q11, the anode of freewheeling diode D11, the drain of transistor Q12, and the cathode of freewheeling diode D12. In other words, one terminal of the inductor 115P is connected to the connection point a1 between the source of transistor Q11 and the anode of freewheeling diode D11, and the drain of transistor Q12 and the cathode of freewheeling diode D12. The other terminal of the inductor 115P is connected to one terminal of the primary winding of the isolation transformer 111.

[0023] As shown in Figure 1, the power conversion system 1A includes a plurality (two in this embodiment) of primary capacitors 113P and 114P connected in series to the primary bridge circuit 112P. Primary capacitors 113P and 114P are connected in series between the primary positive line P1 and the primary negative line N1. Therefore, the series-connected primary capacitors 113P and 114P are connected in parallel to the series-connected transistors Q11 and Q12. Primary capacitors 113P and 114P are located between the primary bridge circuit 112P and the primary device 2P. One electrode of primary capacitor 113P is connected to the primary positive line P1, and the other electrode of primary capacitor 113P is connected to one electrode of primary capacitor 114P. The other electrode of primary capacitor 114P is connected to the primary negative line N1. The connection point between the other electrode of primary capacitor 113P and the one electrode of primary capacitor 114P becomes the primary neutral point NP.

[0024] The primary neutral point NP is connected to the other terminal of the primary winding of the isolation transformer 111. Therefore, the inductor 115P and the primary winding of the isolation transformer 111 are connected in series between connection point a1 and the primary neutral point NP, in other words, between the primary bridge circuit 112P and the primary capacitors 113P and 114P. In addition, one electrode of the primary capacitor 113P is connected to the drain of transistor Q11 and the cathode of freewheeling diode D11 via the primary positive line P1. The other electrode of the primary capacitor 114P is connected to the source of transistor Q12 and the anode of freewheeling diode D12 via the primary negative line N1.

[0025] As will be explained in more detail later, when transistor Q11 is controlled to be ON and transistor Q12 is controlled to be OFF, a voltage equal to the DC voltage V113p generated across the primary capacitor 113P is applied between one terminal of inductor 115P and the other terminal of the primary winding of isolation transformer 111. On the other hand, when transistor Q11 is controlled to be OFF and transistor Q12 is controlled to be ON, a voltage equal to the DC voltage V114p generated across the primary capacitor 114P is applied between one terminal of inductor 115P and the other terminal of the primary winding of isolation transformer 111. In power conversion system 1A, the primary capacitors 113P and 114P are designed to have the same capacitance. Therefore, the DC voltage V113p generated across primary capacitor 113P and the DC voltage V114p generated across primary capacitor 114P are the same voltage value (half the voltage value of the DC voltage between the primary positive line P1 and the primary negative line N1 (the input voltage input from primary device 2P)). Consequently, in power conversion system 1A, the primary winding of the isolation transformer 111 flows with a current of constant magnitude and polarity reversal in accordance with the on / off control of transistors Q11 and Q12.

[0026] However, due to various factors such as the component precision of the primary capacitors 113P and 114P and transistors Q11 and Q12, and the operating environment of the power conversion system 1A, a difference may occur between the amount of current flowing through the primary capacitor 113P and the amount of current flowing through the primary capacitor 114P during the operation of the power conversion system 1A. In this case, the DC voltage V113p generated at the primary capacitor 113P and the DC voltage V114p generated at the primary capacitor 114P will have different voltage values. Therefore, the voltage value applied to the primary winding of the isolation transformer 111 when transistor Q11 is ON will be different from the voltage value applied to the primary winding of the isolation transformer 111 when transistor Q12 is ON. As a result, the induced electromotive force generated in the primary winding of the isolation transformer 111 due to the ON / OFF control of transistors Q11 and Q12 may not be constant, and the mutual induced electromotive force generated in the secondary winding of the isolation transformer 111 may also not be constant. In this case, the output voltage output by the isolated DC / DC converter 11 may fluctuate. Therefore, the power conversion system 1A according to this embodiment controls the potential of the primary neutral point NP so that the DC voltage V113p generated at the primary capacitor 113P and the DC voltage V114p generated at the primary capacitor 114P are the same voltage value.

[0027] As shown in Figure 1, the power conversion system 1A includes a primary DC voltage detection unit 13P that individually detects the DC voltages V113p and V114p generated at each of the primary capacitors 113P and 114P (an example of multiple primary capacitors). The primary DC voltage detection unit 13P includes a detection unit 131P that detects the DC voltage V113p generated at the primary capacitor 113P, and a detection unit 132P that detects the DC voltage V114p generated at the primary capacitor 114P.

[0028] One input terminal of the detection unit 131P is connected to the primary side positive electrode line P1, and the other input terminal of the detection unit 131P is connected to the primary side neutral point NP. This allows the detection unit 131P to detect a DC voltage V113p, which is the potential difference between the potential at one electrode of the primary side capacitor 113P and the potential at the other electrode of the primary side capacitor 113P. One input terminal of the detection unit 132P is connected to the primary side neutral point NP, and the other input terminal of the detection unit 132P is connected to the primary side negative electrode line N1. This allows the detection unit 132P to detect a DC voltage V114p, which is the potential difference between the potential at one electrode of the primary side capacitor 114P and the potential at the other electrode of the primary side capacitor 114P.

[0029] As shown in Figure 1, the power conversion system 1A includes a pulse signal generation unit 14 that generates a pulse signal Spls1 with a duty cycle corresponding to the ratio of multiple DC voltages detected by either the primary DC voltage detection unit 13P or the secondary DC voltage detection unit 13S (details described later). The pulse signal generation unit 14 is provided on the side of the primary side PS and secondary side SS that is electrically isolated from the control device 16 (details described later). In this embodiment, since the control device 16 is located on the secondary side SS, the pulse signal generation unit 14 is provided on the primary side PS.

[0030] The pulse signal generation unit 14 is connected to the output terminals of the detection units 131P and 132P, which are provided on the primary DC voltage detection unit 13P. As a result, the pulse signal generation unit 14 receives the DC voltage detected by the detection units 131P and 132P, respectively. The pulse signal generation unit 14 generates a pulse signal Spls1 with a duty cycle corresponding to the ratio of the DC voltage value input from the detection unit 131P to the DC voltage value input from the detection unit 132P.

[0031] The pulse signal generation unit 14 generates a pulse signal with a duty cycle of, for example, 50% if the division (VP1 / VP2) obtained by dividing the detected DC voltage VP1 input from the detection unit 131P by the detected DC voltage VP2 input from the detection unit 132P is 1 or within a predetermined range relative to 1. The pulse signal generation unit 14 outputs the generated pulse signal Spls1 to the isolated signal transmission unit 15 (details described later). The duty cycle is the ratio of the period τ during which the signal level is high relative to one period T of the pulse signal ((τ / T) × 100).

[0032] Furthermore, even though the voltage values ​​of DC voltage V113p and DC voltage V114p are inherently the same, the pulse signal generation unit 14 may determine that the division value obtained by dividing the detected value VP1 by the detected value VP2 is not 1, due to the component precision of the components constituting the primary DC voltage detection unit 13P and the pulse signal generation unit 14, respectively. For this reason, the power conversion system 1A is configured to consider the division value to be 1 (i.e., the detected values ​​VP1 and VP2 are the same) if the division value is within a predetermined range relative to 1.

[0033] If the division value obtained by dividing the detected DC voltage VP1 input from the detection unit 131P by the detected DC voltage VP2 input from the detection unit 132P (VP1 / VP2) is greater than the maximum value within the predetermined range described above, the pulse signal generation unit 14 generates a pulse signal Spls1 with a duty cycle that is greater than, for example, 50% and corresponds to the division value. On the other hand, if the division value obtained by dividing the detected DC voltage VP1 input from the detection unit 131P by the detected DC voltage VP2 input from the detection unit 132P (VP1 / VP2) is less than the minimum value within the predetermined range, the pulse signal generation unit 14 generates a pulse signal Spls1 with a duty cycle that is less than, for example, 50% and corresponds to the division value.

[0034] As shown in Figure 1, the power conversion system 1A has a secondary positive electrode line P2 connected to the positive side of the secondary bridge circuit 112S and a secondary negative electrode line N2 connected to the negative side of the secondary bridge circuit 112S. The secondary positive electrode line P2 is connected to the positive terminal of the secondary device 2S. The secondary negative electrode line N2 is connected to the negative terminal of the secondary device 2S. As a result, the secondary bridge circuit 112S can exchange power with the secondary device 2S and with the secondary winding of the isolation transformer 111.

[0035] Transistors Q21 and Q22, provided in the secondary bridge circuit 112S, are connected in series between the secondary positive line P2 and the secondary negative line N2. Transistors Q21 and Q22 in the secondary bridge circuit 112S are, for example, composed of MOSFETs.

[0036] The secondary bridge circuit 112S has a freewheeling diode D21 connected in antiparallel to transistor Q1 and a freewheeling diode D22 connected in antiparallel to transistor Q22. The connection relationships between transistors Q21, Q22 and freewheeling diodes D21, D22 are the same as the connection relationships between transistors Q11, Q12 and freewheeling diodes D11, D12 in the primary bridge circuit 112P when the arrows are read from left to right as shown below, so a detailed explanation is omitted. Transistor Q11 → Transistor Q21 Transistor Q12 → Transistor Q22 Freewheel diode D11 → Freewheel diode D21 Freewheel diode D12 → Freewheel diode D22

[0037] The gate of transistor Q21 is connected to a gate drive unit (GDU) 12S (details described later) provided in the power conversion system 1A on the secondary side SS of the isolated DC / DC converter 11. As a result, the gate pulse signal Sg21 output from the gate drive unit 12S is input to the gate of transistor Q21, controlling the on / off (non-conductive) state of transistor Q21. The gate of transistor Q22 is also connected to the gate drive unit 12S. As a result, the gate pulse signal Sg22 output from the gate drive unit 12S is input to the gate of transistor Q22, controlling the on / off (non-conductive) state of transistor Q22. The gate drive unit 12S drives transistors Q21 and Q22 by PWM control using the gate pulse signals Sg21 and Sg22.

[0038] The drain of transistor Q21 and the cathode of freewheeling diode D21 are connected to the secondary positive line P2. The source of transistor Q22 and the anode of freewheeling diode D22 are connected to the secondary negative line N2. Thus, the secondary bridge circuit 112S has a half-bridge circuit composed of transistors Q21 and Q22 and freewheeling diodes D21 and D22.

[0039] As shown in Figure 1, the isolated DC / DC converter 11 has an inductor 115S positioned between the secondary bridge circuit 112S and the secondary winding of the isolation transformer 111. One terminal of the inductor 115S is connected to the source of transistor Q21, the anode of freewheeling diode D21, the drain of transistor Q22, and the cathode of freewheeling diode D22. In other words, one terminal of the inductor 115S is connected to the connection point b1 between the source of transistor Q21 and the anode of freewheeling diode D21, and the drain of transistor Q22 and the cathode of freewheeling diode D22. The other terminal of the inductor 115S is connected to one terminal of the secondary winding of the isolation transformer 111.

[0040] As shown in Figure 1, the power conversion system 1A includes a plurality (two in this embodiment) of secondary capacitors 113S and 114S connected in series to the secondary bridge circuit 112S. The secondary capacitors 113S and 114S are connected in series between the secondary positive electrode line P2 and the secondary negative electrode line N2. Therefore, the series-connected secondary capacitors 113S and 114S are connected in parallel to the series-connected transistors Q21 and Q22. The secondary capacitors 113S and 114S are located between the secondary bridge circuit 112S and the secondary device 2S. One electrode of the secondary capacitor 113S is connected to the secondary positive electrode line P2, and the other electrode of the secondary capacitor 113S is connected to one electrode of the secondary capacitor 114S. The other electrode of the secondary capacitor 114S is connected to the secondary negative electrode line N2. The connection point between the other electrode of secondary capacitor 113S and the one electrode of secondary capacitor 114S becomes the secondary neutral point NS.

[0041] The secondary neutral point NS is connected to the other terminal of the secondary winding of the isolation transformer 111. Therefore, the inductor 115S and the secondary winding of the isolation transformer 111 are connected in series between the connection point b1 and the secondary neutral point NS, in other words, between the secondary bridge circuit 112S and the secondary capacitors 113S and 114S. In addition, one electrode of the secondary capacitor 113S is connected to the drain of transistor Q21 and the cathode of freewheeling diode D21 via the secondary positive electrode line P2. The other electrode of the secondary capacitor 114S is connected to the source of transistor Q22 and the anode of freewheeling diode D22 via the secondary negative electrode line N2.

[0042] As will be explained in detail later, when transistor Q21 is controlled to be ON and transistor Q22 is controlled to be OFF, the induced current generated in the secondary winding of the isolation transformer 111 flows from the secondary positive electrode line P2 toward the connection point b1 to the secondary capacitor 113S. Also, when transistor Q21 is controlled to be OFF and transistor Q22 is controlled to be ON, the induced current generated in the secondary winding of the isolation transformer 111 flows from the connection point b1 toward the secondary negative electrode line N2 to the secondary capacitor 114S. The current flowing through the secondary capacitor 113S and the current flowing through the secondary capacitor 114S may differ due to various factors such as component precision and the operating environment of the power conversion system 1A, even if the DC voltages generated across the primary capacitor 113P and primary capacitor 114P are controlled to be the same. In this case, at least one of the DC voltages generated across the secondary capacitors 113S and 114S may differ from the design value, potentially preventing the isolated DC / DC converter 11 from supplying the desired DC voltage to the secondary device 2S. Therefore, as will be described in detail later, the power conversion system 1A detects the DC voltages generated across the secondary capacitors 113S and 114S and controls the secondary bridge circuit 112S based on the detected DC voltages. This enables the power conversion system 1A to supply the desired DC voltage to the isolated DC / DC converter 11S.

[0043] As shown in Figure 1, the power conversion system 1A includes a secondary DC voltage detection unit 13S that individually detects the DC voltages V113s and V114s generated in each of the secondary capacitors 113S and 114S (an example of multiple secondary capacitors). The secondary DC voltage detection unit 13S includes a detection unit 131S that detects the DC voltage V113s generated in the secondary capacitor 113S, and a detection unit 132S that detects the DC voltage V114s generated in the secondary capacitor 114S.

[0044] One input terminal of the detection unit 131S is connected to the secondary positive electrode line P2, and the other input terminal of the detection unit 131S is connected to the secondary neutral point NS. This allows the detection unit 131S to detect the DC voltage V113s, which is the potential difference between the potential at one electrode of the secondary capacitor 113S and the potential at the other electrode of the secondary capacitor 113S. One input terminal of the detection unit 132S is connected to the secondary neutral point NS, and the other input terminal of the detection unit 132S is connected to the secondary negative electrode line N2. This allows the detection unit 132S to detect the DC voltage V114s, which is the potential difference between the potential at one electrode of the secondary capacitor 114S and the potential at the other electrode of the secondary capacitor 114S. The secondary DC voltage detection unit 13S outputs the detected values ​​of the DC voltages V113p and V114s to the control device 16 (details described later).

[0045] As shown in Figure 1, the power conversion system 1A includes an isolated signal transmission unit 15 that transmits a pulse signal Spls2 (an example of a signal based on a pulse signal) based on a pulse signal Spls1 input from the pulse signal generation unit 14 to the control device 16 while the primary side PS and secondary side SS of the isolated DC / DC converter 11 are electrically isolated.

[0046] The isolated signal transmission unit 15 includes optical transmission units 151, 152, and 153. The optical transmission unit 151 receives a pulse signal Spls1 output from the pulse signal generation unit 14. The optical transmission unit 151 includes, for example, a photocoupler (not shown) that converts the electrical pulse signal Spls1 into an optical signal. The optical transmission unit 151 also includes peripheral circuits (not shown) that include, for example, a circuit for inputting the pulse signal Spls1 into the photocoupler and a circuit for converting the optical signal transmitted by the photocoupler into an electrical pulse signal Spls2. The optical transmission unit 151 converts the optical signal transmitted by the photocoupler into a pulse signal Spls2 with the same voltage waveform as the pulse signal Spls1, and outputs the pulse signal Spls2 to the control device 16.

[0047] The optical transmission unit 152 receives the input signal Si11a output from the control device 16. As will be described in detail later, the input signal Si11a is a signal for generating the gate pulse signal Sg11 which is input to the gate of transistor Q11 provided in the primary bridge circuit 112P. The optical transmission unit 152 has, for example, a photocoupler (not shown) that converts the electrical signal input signal Si11a into an optical signal. The optical transmission unit 152 also has peripheral circuits (not shown) that include, for example, a circuit for inputting the input signal Si11a to the photocoupler and a circuit for converting the optical signal transmitted by the photocoupler into an electrical signal input signal Si11b. The optical transmission unit 152 converts the optical signal transmitted by the photocoupler into an input signal Si11b with the same voltage waveform as the input signal Si11a, and outputs the input signal Si11b to the gate drive unit 12P.

[0048] The optical transmission unit 153 receives the input signal Si12a output from the control device 16. As will be described in detail later, the input signal Si12a is a signal for generating the gate pulse signal Sg12 which is input to the gate of transistor Q12 provided in the primary bridge circuit 112P. The optical transmission unit 153 generates the input signal Si12b based on the input signal Si12a input from the control device 16 and outputs it to the gate drive unit 12P. The optical transmission unit 153 has the same configuration as the optical transmission unit 152 and performs the same functions, except that the input and output signals are different, so a description will be omitted.

[0049] In this embodiment, the isolated signal transmission unit 15 is configured to output a signal with the same voltage waveform as the input signal, but it may also be configured to output a signal with a voltage waveform of opposite polarity to the input signal.

[0050] As shown in Figure 1, the power conversion system 1A includes a control device (an example of a control unit) 16 that controls the primary bridge circuit 112P and the secondary bridge circuit 112S. The control device 16 uses a signal based on a pulse signal output from the isolation signal transmission unit 15 to control the bridge circuit connected to the capacitor whose DC voltage is detected by one of the detection units, either the primary DC voltage detection unit 13P or the secondary DC voltage detection unit 13S. In other words, in this embodiment, the control device 16 uses a pulse signal Spls2 based on a pulse signal Spls1 output from the isolation signal transmission unit 15 to control the primary bridge circuit 112P connected to the primary capacitors 113P and 114P whose DC voltage is detected by the primary DC voltage detection unit 13P.

[0051] The control device 16 generates input signals Si11a and Si12a with duty cycles corresponding to the duty cycle of the pulse signal Spls2 input from the isolated signal transmission unit 15 (i.e., the duty cycle of the pulse signal Spls1).

[0052] If the DC voltage V113p generated at the primary capacitor 113P is higher than the DC voltage V114p generated at the primary capacitor 114P, it is necessary to decrease the DC voltage V113p and increase the DC voltage V114p. To do this, it is necessary to shorten the period during which transistor Q12, provided in the primary bridge circuit 112P, is in the conduction state (on state), and to lengthen the period during which transistor Q11, provided in the primary bridge circuit 112P, is in the conduction state (on state). In order to operate transistors Q11 and Q12 in this way, the control device 16 generates, for example, an input signal Si11a with a higher duty cycle than the current one and an input signal Si12a with a lower duty cycle than the current one, when the duty cycle of pulse signal Spls2 (i.e., the duty cycle of pulse signal Spls1) is greater than 50%.

[0053] On the other hand, if the DC voltage V113p generated at the primary capacitor 113P is lower than the DC voltage V114p generated at the primary capacitor 114P, it is necessary to increase the DC voltage V113p and decrease the DC voltage V114p. To do this, it is necessary to lengthen the period during which transistor Q12 is in the conduction state (on state) and shorten the period during which transistor Q11 is in the conduction state (on state). In order to operate transistors Q11 and Q12 in this way, the control device 16 generates, for example, an input signal Si11a with a smaller duty cycle than the current one and an input signal Si12a with a larger duty cycle than the current one, when the duty cycle of pulse signal Spls2 (i.e., the duty cycle of pulse signal Spls1) is less than 50%.

[0054] Furthermore, if the DC voltage V113p generated at the primary capacitor 113P and the DC voltage V114p generated at the primary capacitor 114P are the same or within a predetermined range of the same value, it is necessary to maintain the DC voltages V113p and V114p at their current voltage values. To achieve this, it is necessary to maintain the conduction state (on state) of transistors Q11 and Q12 for the current period. In order to operate transistors Q11 and Q12 in this way, the control device 16 generates input signals Si11a and Si12a with the same duty cycle as the current state, for example, when the duty cycle of pulse signal Spls2 (i.e., the duty cycle of pulse signal Spls1) is 50%.

[0055] The gate drive unit 12P generates a gate pulse signal Sg11 with the same duty cycle as the input signal Si11b input from the isolated signal transmission unit 15, and outputs the generated gate pulse signal Sg11 to the gate of transistor Q11. The gate drive unit 12P also generates a gate pulse signal Sg12 with the same duty cycle as the input signal Si12b input from the isolated signal transmission unit 15, and outputs the generated gate pulse signal Sg12 to the gate of transistor Q12. The input signal Si11b is, for example, a signal having the same duty cycle as the input signal Si11a, and the input signal Si12b is, for example, a signal having the same duty cycle as the input signal Si12a.

[0056] Therefore, when the DC voltages V113p and V114p are different values, the gate drive unit 12P can drive transistors Q11 and Q12 in such a way that the difference between these voltage values ​​is minimized. Also, when the DC voltages V113p and V114p are the same value, the gate drive unit 12P can drive transistors Q11 and Q12 in such a way that the current voltage values ​​are maintained. Thus, the gate drive unit 12P can change the voltage values ​​of DC voltages V113p and V114p to bring them closer to the design values, or it can maintain the voltage values ​​of DC voltages V113p and V114p at the design values.

[0057] The control device 16 controls the secondary bridge circuit 112S connected to the secondary capacitors 113S and 114S using the detection signal output from the secondary DC voltage detection unit 13S. If the voltage level of the detection signal input from the detection unit 131S provided in the secondary DC voltage detection unit 13S is higher than, for example, a preset comparison voltage level, the control device 16 outputs an input signal Si21a with a smaller duty cycle than the current one to the gate drive unit 12S. The comparison voltage level set in the control device 16 is, for example, set to half the voltage value of the DC voltage output by the isolated DC / DC converter 11. That is, the comparison voltage level is set to the design values ​​of the DC voltage V113s generated at the secondary capacitor 113S and the DC voltage V114s generated at the secondary capacitor 114S when the isolated DC / DC converter 11 is operating.

[0058] On the other hand, if the voltage level of the detection signal input from the detection unit 131S is lower than, for example, the comparison voltage level, the control device 16 outputs an input signal Si21a with a duty cycle that is, for example, larger than the current one to the gate drive unit 12S. Furthermore, if the voltage level of the detection signal input from the detection unit 131S is the same as, for example, the comparison voltage level, the control device 16 outputs an input signal Si21a with the same duty cycle as the current one to the gate drive unit 12S.

[0059] Furthermore, if the voltage level of the detection signal input from the detection unit 132S provided in the secondary DC voltage detection unit 13S is higher than, for example, the comparison voltage level, the control device 16 outputs an input signal Si22a with a duty cycle smaller than the current one to the gate drive unit 12S. On the other hand, if the voltage level of the detection signal input from the detection unit 132S is lower than, for example, the comparison voltage level, the control device 16 outputs an input signal Si22a with a duty cycle larger than the current one to the gate drive unit 12S. Moreover, if the voltage level of the detection signal input from the detection unit 132S is the same as, for example, the comparison voltage level, the control device 16 outputs an input signal Si22a with the same duty cycle as the current one to the gate drive unit 12S.

[0060] The gate drive unit 12S generates a gate pulse signal Sg21 with the same duty cycle as the input signal Si21a input from the control device 16, and outputs the generated gate pulse signal Sg21 to the gate of transistor Q21. Similarly, the gate drive unit 12P generates a gate pulse signal Sg22 with the same duty cycle as the input signal Si22a input from the control device 16, and outputs the generated gate pulse signal Sg22 to the gate of transistor Q22. The input signals Si21a and Si22a are signals with duty cycles that reflect the voltage values ​​of the DC voltages V113s and V114s.

[0061] Therefore, when the DC voltages V113s and V114s are different values, the gate drive unit 12S can drive transistors Q21 and Q22 to minimize the difference between these voltage values. Also, when the DC voltages V113s and V114s are the same value, the gate drive unit 12S can drive transistors Q21 and Q22 to maintain the current voltage values. Thus, the gate drive unit 12S can change the voltage values ​​of the DC voltages V113s and V114s to approach the design values, or maintain the voltage values ​​of the DC voltages V113s and V114s at the design values.

[0062] Incidentally, conventional power conversion systems do not have a pulse signal generation unit. Therefore, in order to transmit a detection signal, which is obtained by detecting the DC voltage of a capacitor electrically isolated from the control unit, to the control unit, a conventional power conversion system requires an optical transmission unit for each capacitor.

[0063] In contrast, the power conversion system 1A includes a pulse signal generation unit 14 that generates a pulse signal Spls1 based on the ratio of DC voltages of multiple capacitors (primary capacitors 113P, 114P in this embodiment) that are electrically isolated from the control device 16, among the primary capacitors 113P, 114P and secondary capacitors 113S, 114S. This allows the power conversion system 1A to transmit a single pulse signal Spls1, which combines the detected multiple DC voltages, to the control device 16 via the isolated signal transmission unit 15. For this reason, the isolated signal transmission unit 15 only needs to have one optical transmission unit 151 to transmit the pulse signal Spls1 to the control device 16. The optical transmission unit 151 provided in the isolated signal transmission unit 15 is an expensive component among the components that make up the power conversion system 1A. For this reason, although the power conversion system 1A includes a pulse signal generation unit 14, it can reduce costs compared to conventional power conversion systems because it has fewer optical transmission units. Therefore, even though the power conversion system 1A has a primary neutral point NP which is the midpoint of the capacitor and an isolation transformer 111, it is possible to reduce costs.

[0064] Furthermore, in conventional power conversion systems, if detection signals related to the DC voltage of multiple capacitors are transmitted by separate optical transmission units, the transmission accuracy of these detection signals may vary due to variations in the precision of the optical transmission components. In this case, conventional power conversion systems cannot adequately balance the DC voltages generated across each of the multiple capacitors, resulting in a decrease in the output accuracy of the isolated DC / DC converter.

[0065] In contrast, the power conversion system 1A can transmit pulse signals Spls1, based on detection signals related to the DC voltages of multiple capacitors, to the control device 16 using a single optical transmission unit (optical transmission unit 151 in this embodiment). Therefore, the power conversion system 1A does not suffer from the problem of reduced output accuracy of the isolated DC / DC converter 11 due to the transmission accuracy of each of the multiple optical transmission units. As a result, the power conversion system 1A can improve the output accuracy of the isolated DC / DC converter 11.

[0066] (Operation of the power conversion system) The operation of the power conversion system 1A according to this embodiment will be explained using Figure 2 with reference to Figure 1. Before explaining the balance control of the DC voltages V113p and V114p generated in the primary capacitors 113P and 114P, the basic operation of the power conversion system 1A will be explained using Figure 1.

[0067] The power conversion system 1A operates by repeating four operating modes. In the first operating mode, the control device 16 provided in the power conversion system 1A controls the gate drive unit 12P to operate transistor Q11 in the primary bridge circuit 112P in a conductive state (on state) and transistor Q12 in a non-conductive state (off state). Also in the first operating mode, the control device 16 controls the gate drive unit 12S to operate transistor Q21 in the secondary bridge circuit 112S in a conductive state and transistor Q22 in a non-conductive state.

[0068] Therefore, primary current flows through the first path ("primary side device 2P → transistor Q11 → connection a1 → inductor 115P → primary winding of isolation transformer 111 → primary side neutral point NP → primary side capacitor 114P → primary side device 2P") in the primary side PS of the isolated DC / DC converter 11. As a result, the primary side capacitor 114P is charged. Simultaneously with the flow of current through the first path, primary current also flows through the second path ("primary side capacitor 113P → transistor Q11 → connection a1 → inductor 115P → primary winding of isolation transformer 111 → primary side neutral point NP → primary side capacitor 114P"). As a result, the primary side capacitor 113P is discharged. Due to the flow of current through the first and second paths, the primary side current flowing through the primary winding of the isolation transformer 111 increases in the positive direction.

[0069] In the first operating mode, the DC voltage V114p generated across the primary capacitor 114P rises to a voltage value equal to half the voltage supplied from the primary device 2P, according to the design. Also, in the first operating mode, a voltage equal to the DC voltage V114p generated across the primary capacitor 114P is applied across both ends of the primary winding of the isolation transformer 111, according to the design.

[0070] As a primary current increases in the positive direction flows through the primary winding of the isolation transformer 111, an induced electromotive force is generated in the primary winding. Furthermore, due to mutual induction in the isolation transformer 111, a mutual induced electromotive force is generated in the secondary winding of the isolation transformer 111. The isolation transformer 111 is configured such that the applied voltage to the primary winding and the applied voltage to the secondary winding have the same polarity. Therefore, in the first operating mode, the applied voltage to the secondary winding of the isolation transformer 111 begins to increase in the positive direction. As a result, a secondary current flows through the secondary side SS of the isolated DC / DC converter 11 via the path (third path) "secondary winding of isolation transformer 111 → inductor 115S → connection b1 → transistor Q21 → secondary side capacitor 113S → secondary side neutral point NS → secondary winding of isolation transformer 111", and the secondary side capacitor 113S is charged. Simultaneously with the flow of current through the third path, secondary current flows through the path (fourth path) of "secondary capacitor 114S → secondary neutral point NS → secondary winding of isolation transformer 111 → inductor 115S → transistor Q21 → secondary capacitor 113S". As a result, secondary capacitor 114S is discharged. Thus, in the first operating mode, current flows through the third and fourth paths in the secondary SS of the isolated DC / DC converter 11.

[0071] In the first operating mode, the voltage generated at both ends of the secondary winding of the isolation transformer 111 is, by design, the sum of the voltage applied at both ends of the primary winding and the ratio of the number of turns of the secondary winding to the number of turns of the primary winding of the isolation transformer 111. Furthermore, the output voltage of the isolated DC / DC converter 11 is the sum of the DC voltage V113s generated at the secondary capacitor 113S and the DC voltage V114s generated at the secondary capacitor 114S. In the first operating mode, the voltage value of the DC voltage V113s is, by design, the same as the voltage generated at both ends of the secondary winding of the isolation transformer 111. Also, in the third operating mode (details described later), the voltage value of the DC voltage V113s generated at the secondary capacitor 113S is, by design, the same as the voltage generated at both ends of the secondary winding of the isolation transformer 111. Although the voltage value of the secondary capacitor 113S decreases slightly due to discharge in the first operating mode, it maintains approximately the same voltage value as the DC voltage V113s in the third operating mode. Therefore, in the first operating mode, the output voltage of the isolated DC / DC converter 11 is designed to be approximately twice the voltage across the secondary winding of the isolation transformer 111.

[0072] In the second operating mode following the first operating mode, the control device 16 provided in the power conversion system 1A controls the gate drive units 12P and 12S to operate all transistors Q11, Q12, Q21, and Q22 in a non-conductive state (off state).

[0073] In the second operating mode, transistor Q11 is turned off, so the energy stored in the secondary winding of the isolation transformer 111 and inductor 115S is commutated to the secondary side. As a result, in the second operating mode, secondary current flows through the path (fifth path) of "secondary winding of isolation transformer 111 → inductor 115S → connection b1 → freewheeling diode D21 → secondary capacitor 113S → secondary neutral point NS → secondary winding of isolation transformer 111". Due to the flow of this secondary current, the DC voltage V113s generated across the secondary capacitor 113S in the second operating mode rises to the same voltage value as the voltage generated across the secondary winding of the isolation transformer 111, according to the design. In the second operating mode, no charging or discharging path is created for the secondary capacitor 114S. Therefore, in the second operating mode, the DC voltage V114s of the secondary capacitor 114S maintains the voltage value at the end of the first operating mode. Therefore, in the second operating mode, the output voltage of the isolated DC / DC converter 11 is, by design, twice the voltage generated across the secondary winding of the isolation transformer 111.

[0074] In the third operating mode following the second operating mode, the control device 16 provided in the power conversion system 1A controls the gate drive unit 12P to operate transistor Q11 in the primary bridge circuit 112P in a non-conductive state (off state) and transistor Q12 in a conductive state (on state). Also in the third operating mode, the control device 16 controls the gate drive unit 12S to operate transistor Q21 in the secondary bridge circuit 112S in a non-conductive state and transistor Q22 in a conductive state.

[0075] Therefore, primary current flows through the sixth path ("Primary device 2P → Primary capacitor 113P → Primary neutral point NP → Primary winding of isolation transformer 111 → Inductor 115P → Connection a1 → Transistor Q12 → Primary device 2P") on the primary side PS of the isolated DC / DC converter 11. As a result, the primary capacitor 113P is charged. Simultaneously with the flow of current through the sixth path, primary current also flows through the seventh path ("Primary capacitor 114P → Primary neutral point NP → Primary winding of isolation transformer 111 → Inductor 115P → Connection a1 → Transistor Q12 → Primary device 2P"). As a result, the primary capacitor 114P is discharged. Due to the current flowing through the sixth and seventh paths, the primary current flowing through the primary winding of the isolation transformer 111 increases in the negative direction.

[0076] In the third operating mode, the DC voltage V113p generated across the primary capacitor 113P rises to a voltage value equal to half the voltage supplied from the primary device 2P, according to the design. Also, in the third operating mode, a voltage with the same absolute value as the DC voltage V113p generated across the primary capacitor 113P is applied across both ends of the primary winding of the isolation transformer 111, according to the design.

[0077] As a primary current increases in the negative direction flows through the primary winding of the isolation transformer 111, an induced electromotive force is generated in the primary winding in the opposite direction to that of the first operating mode. Furthermore, due to mutual induction in the isolation transformer 111, a mutual induced electromotive force is generated in the secondary winding of the isolation transformer 111 in the opposite direction to that of the first operating mode. As a result, a secondary current flows through the secondary side SS of the isolated DC / DC converter 11 via the path (8th path) of "secondary winding of isolation transformer 111 → secondary neutral point NS → secondary capacitor 114S → transistor Q22 → connection b1 → inductor 115S → secondary winding of isolation transformer 111", and the secondary capacitor 114S is charged. Consequently, in the third operating mode, current flows through the secondary side SS of the isolated DC / DC converter 11 via the 7th path.

[0078] In the third operating mode, a voltage is generated at both ends of the secondary winding of the isolation transformer 111, similar to the first operating mode, by design, which is the ratio of the number of turns of the secondary winding to the number of turns of the primary winding of the isolation transformer 111, multiplied by the voltage applied at both ends of the primary winding. Also, similar to the first operating mode, the output voltage of the isolated DC / DC converter 11 in the third operating mode is the sum of the DC voltage V113s generated at the secondary capacitor 113S and the DC voltage V114s generated at the secondary capacitor 114S. In the third operating mode, the voltage value of the DC voltage V114s is, by design, the same as the voltage generated at both ends of the secondary winding of the isolation transformer 111. In the third operating mode, there is no charging or discharging path for the secondary capacitor 113S. Therefore, the output voltage of the isolated DC / DC converter 11 in the third operating mode is, by design, twice the voltage generated at both ends of the secondary winding of the isolation transformer 111.

[0079] In the fourth operating mode following the third operating mode, the control device 16 provided in the power conversion system 1A controls the gate drive units 12P and 12S to operate all transistors Q11, Q12, Q21, and Q22 in a non-conductive (off) state.

[0080] In the fourth operating mode, transistor Q12 is turned off, so the energy stored in the secondary winding of the isolation transformer 111 and inductor 115S is commutated to the secondary side SS. As a result, in the fourth operating mode, secondary current flows through the path (ninth path) of "secondary winding of isolation transformer 111 → secondary neutral point NS → secondary capacitor 114S → freewheeling diode D22 → connection b1 → inductor 115S → secondary winding of isolation transformer 111". Due to the flow of this secondary current, the DC voltage V114s generated across the secondary capacitor 114S in the fourth operating mode rises to the same voltage value as the voltage generated across the secondary winding of the isolation transformer 111, according to the design. In the fourth operating mode, no charging or discharging path is created for the secondary capacitor 113S. Therefore, the output voltage of the isolated DC / DC converter 11 in the fourth operating mode is, according to the design, twice the voltage generated across the secondary winding of the isolation transformer 111.

[0081] When the fourth operating mode ends, the power conversion system 1A starts the first operating mode. In this way, the power conversion system 1A operates by repeatedly switching between the first, second, and fourth operating modes.

[0082] In the first operating mode, the DC voltage V114p generated at the primary capacitor 114P and in the third operating mode, the DC voltage V113p generated at the primary capacitor 113P are, in design terms, the same voltage value. Therefore, the absolute value of the voltage across the secondary winding of the isolation transformer 111 is the same in the first and third operating modes, and the stored energy commutated to the secondary SS is the same in the second and fourth operating modes. As a result, the power conversion system 1A can, in design terms, output almost the same output voltage from the isolated DC / DC converter 11 to the secondary device 2S in the first through fourth operating modes.

[0083] However, the amount of current flowing through the primary capacitor 114P in the first operating mode may differ from the amount of current flowing through the primary capacitor 113P in the third operating mode. In this case, the absolute value of the voltage across the secondary winding of the isolation transformer 111 may differ between the first and third operating modes, or the stored energy commutated to the secondary SS may differ between the second and fourth operating modes. As a result, the power conversion system 1A will no longer be able to output an output voltage from the isolated DC / DC converter 11 that can be considered to have the same voltage value from the first to the fourth operating modes.

[0084] Therefore, the power conversion system 1A controls the primary bridge circuit 112P based on the ratio of the DC voltage V113p generated at the primary capacitor 113P and the DC voltage V114p generated at the primary capacitor 114P, so that the voltage value of the DC voltage V114p generated at the primary capacitor 114P in the first operating mode is the same as the voltage value of the DC voltage V113p generated at the primary capacitor 113P in the third operating mode. As a result, the power conversion system 1A can make the absolute value of the voltage generated across the secondary winding of the isolation transformer 111 the same in the first and third operating modes, and make the stored energy commutated to the secondary SS the same in the second and fourth operating modes.

[0085] Figure 2 is a timing chart showing an example of the operating waveform of the power conversion system 1A. Figure 2 illustrates the operating waveform of the power conversion system 1A related to voltage balancing control that makes the DC voltages V113p and V114p generated at the primary side capacitors 113P and 114P the same. The power conversion system 1A is configured to detect the DC voltages V113p and V114p generated at the primary side capacitors 113P and 114P each time it performs a series of operations from the first to the fourth operating mode multiple times. However, the power conversion system 1A may also be configured to detect the DC voltages V113p and V114p generated at the primary side capacitors 113P and 114P each time it performs a series of operations from the first to the fourth operating mode.

[0086] The first row of Figure 2 shows the voltage waveforms of the DC voltages V113p and V114p generated at the primary side capacitors 113P and 114P. The second row of Figure 2 shows the change over time of the capacitor DC voltage ratio Vr calculated by the pulse signal generation unit 14. The capacitor DC voltage ratio Vr is the ratio of the detected value VP1 of the DC voltage V113p to the detected value VP2 of the DC voltage V114p. The third row of Figure 2 shows the voltage waveform of the pulse signal Spls1 generated and output by the pulse signal generation unit 14 based on the capacitor DC voltage ratio Vr. The vertical axis in the first row of Figure 2 represents voltage, the vertical axis in the second row of Figure 2 represents dimensionless quantities, and the vertical axis in the third row of Figure 2 also represents voltage. In Figure 2, time is shown from left to right.

[0087] As shown in Figure 2, during the period prior to time t0, the DC voltage V113p of the primary capacitor 113P (see Figure 1) is higher than the DC voltage V114p of the primary capacitor 114P (see Figure 1). Furthermore, the DC voltage V113p is higher than half the input voltage Edc (i.e., the voltage between the primary positive line P1 and the primary negative line N1) input from the primary device 2P (see Figure 1) (Edc / 2), while the DC voltage V114p is lower than half the input voltage Edc. In other words, the voltage value of DC voltage V113p is higher than the design value, and the voltage value of DC voltage V114p is lower than the design value. Therefore, at a predetermined time (not shown) prior to time t0, the control device 16 (see Figure 1) controls the gate drive unit 12P to operate the primary bridge circuit 112P such that the DC voltage V113p becomes lower than its current value and the DC voltage V114p becomes higher than its current value. As a result, for example, the DC voltage V113p detected by the primary DC voltage detection unit 13P at time t0 when the fourth operating mode ends will be lower than the voltage value before time t0. On the other hand, the DC voltage V114p detected by the primary DC voltage detection unit 13P at time t0 will be higher than the voltage value before time t0.

[0088] At time t0, the detected values ​​VP1 and VP2 of DC voltages V113p and V114p detected by the primary DC voltage detection unit 13P are input to the pulse signal generation unit 14 (see Figure 1). The pulse signal generation unit 14 calculates the capacitor DC voltage ratio Vr based on the detected values ​​VP1 and VP2 of DC voltages V113p and V114p input from the primary DC voltage detection unit 13P. Furthermore, the pulse signal generation unit 14 generates a pulse signal Spls1 based on the calculated capacitor DC voltage ratio Vr. At time t0, the capacitor DC voltage ratio Vr is greater than 1, so the pulse signal generation unit 14 generates a pulse signal Spls1 with a duty cycle (=(τ / T)×100) greater than 50%. In this embodiment, the period T of the pulse signal Spls1 is set to be longer than, for example, the period from the first operating mode to the fourth operating mode in the operation of the power conversion system 1A.

[0089] The pulse signal generation unit 14 outputs the generated pulse signal Spls1 to the isolated signal transmission unit 15 (see Figure 1). The isolated signal transmission unit 15 outputs a pulse signal Spls2 having the same voltage waveform as the input pulse signal Spls1 to the control device 16 (see Figure 1).

[0090] The control device 16 calculates the duty cycle of the pulse signal Spls2 input from the isolated signal transmission unit 15 at time t1, when one period T of the pulse signal Spls1 has elapsed from time t0. Based on the calculated duty cycle of the pulse signal Spls2, the control device 16 determines the duty cycles of the input signals Si11a and Si12a. At time t0, the detected value VP1 of the DC voltage V113p detected by the detection unit 131P provided in the primary side DC voltage detection unit 13P is greater than the design value, so the control device 16 generates an input signal Si12a to shorten the period during which the transistor Q12 provided in the primary side bridge circuit 112P is in the conduction state (on state) compared to the current period. On the other hand, at time t0, the detected value VP2 of the DC voltage V114p detected by the detection unit 132P provided in the primary side DC voltage detection unit 13P is smaller than the design value, so the control device 16 generates an input signal Si11a to make the period of conduction (on state) of transistor Q11 provided in the primary side bridge circuit 112P longer than the current period.

[0091] The control device 16 outputs the generated input signals Si11a and Si12a to the isolated signal transmission unit 15 at a time between time t1 and time t2 (for example, time t1a). Time t2 is the time when one period T of the pulse signal Spls1 has elapsed since time t1. The isolated signal transmission unit 15 outputs input signals Si11b and Si12b, which have the same voltage waveform as the input signals Si11a and Si12a input from the control device 16, to the gate drive unit 12P (see Figure 1).

[0092] The gate drive unit 12P generates gate pulse signals Sg11 and Sg12 based on input signals Si11b and Si12b received from the isolated signal transmission unit 15. The gate drive unit 12P drives transistor Q11, which is located in the primary bridge circuit 112P, with the generated gate pulse signal Sg11. The gate drive unit 12P also drives transistor Q12, which is located in the primary bridge circuit 112P, with the generated gate pulse signal Sg12. Transistors Q11 and Q12 are driven by the gate pulse signals Sg11 and Sg12 through the first to fourth operating modes. As a result, transistor Q11 has a longer conduction state (on state) than it does now at a predetermined time after time t1a. On the other hand, transistor Q12 has a shorter conduction state (on state) at a predetermined time after time t1a. As a result, the DC voltage V113p generated across the primary capacitor 113P becomes lower than it is currently, and the DC voltage V114p generated across the primary capacitor 114P becomes higher than it is currently.

[0093] The timing at which the DC voltages V113p and V114p generated at the primary capacitors 113P and 114P change is actually after a predetermined time has elapsed from time t1a, due to factors such as the generation time of the gate pulse signals Sg11 and Sg12 at the gate drive unit 12P and the time elapsed from the first to the fourth operating mode. However, in Figure 2, for the sake of ease of understanding, the DC voltages V113p and V114p are shown as changing at time t1a. The timing at which the DC voltages V113p and V114p generated at the primary capacitors 113P and 114P change is also shown in the same way at time t3a, time t5a, and time t7a, which will be described later.

[0094] Incidentally, the detected values ​​VP1 and VP2 of the DC voltages V113p and V114p detected by the primary DC voltage detection unit 13P at time t1 are the same as the detected values ​​VP1 and VP2 of the DC voltages V113p and V114p detected by the primary DC voltage detection unit 13P at time t0. Therefore, as shown in Figure 2, the pulse signal generation unit 14 outputs a pulse signal Spls1 with the same duty cycle as the pulse signal Spls1 output between time t0 and time t1, even between time t1 and time t2.

[0095] At time t2, the primary DC voltage detection unit 13P detects the DC voltages V113p and V114p generated in the primary capacitors 113P and 114P, and outputs the detected values ​​VP1 and VP2 of the detected DC voltages V113p and V114p to the pulse signal generation unit 14 (see Figure 1). The transistor Q12 provided in the primary bridge circuit 112P is controlled so that the conduction state (on state) is shorter at time t2 than at time t0. As a result, the amount of current flowing through the primary capacitor 113P is reduced. Consequently, as shown in Figure 2, the DC voltage V113p detected by the detection unit 131P of the primary DC voltage detection unit 13P is lower at time t2 than at time t0. In addition, the transistor Q11 provided in the primary bridge circuit 112P is controlled so that the conduction state (on state) is longer at time t2 than at time t0. As a result, the amount of current flowing through the primary capacitor 114P increases. Consequently, as shown in Figure 2, the DC voltage V114p detected by the detection unit 132P of the primary DC voltage detection unit 13P is higher at time t2 than at time t0.

[0096] The pulse signal generation unit 14 calculates the capacitor DC voltage ratio Vr based on the detected values ​​VP1 and VP2 of DC voltages V113p and V114p input from the primary DC voltage detection unit 13P. Furthermore, the pulse signal generation unit 14 generates a pulse signal Spls1 based on the calculated capacitor DC voltage ratio Vr. As shown in Figure 2, at time t2, the DC voltage V113p is higher than the DC voltage V114p. Furthermore, the voltage difference between DC voltages V113p and V114p is smaller at time t2 than at time t0. Therefore, at time t2, the capacitor DC voltage ratio Vr is greater than 1 and smaller than the value at time t0. As a result, as shown in Figure 2, the pulse signal generation unit 14 generates a pulse signal Spls1 with a duty cycle greater than 50% and smaller than the value from time t0 to time t2.

[0097] The pulse signal generation unit 14 outputs the generated pulse signal Spls1 to the isolated signal transmission unit 15. The isolated signal transmission unit 15 outputs a pulse signal Spls2 having the same voltage waveform as the input pulse signal Spls1 to the control device 16.

[0098] The control device 16 calculates the duty cycle of the pulse signal Spls2 input from the isolated signal transmission unit 15 at time t3, when one period T of the pulse signal Spls1 has elapsed from time t2. Based on the calculated duty cycle of the pulse signal Spls2, the control device 16 determines the duty cycles of the input signals Si11a and Si12a. At time t2, the detected value VP1 of the DC voltage V113p detected by the detection unit 131P of the primary side DC voltage detection unit 13P is greater than the design value, so the control device 16 generates an input signal Si12a to shorten the period of conduction (on state) of transistor Q12 compared to the current period. On the other hand, at time t2, the detected value VP2 of the DC voltage V114p detected by the detection unit 132P of the primary side DC voltage detection unit 13P is smaller than the design value, so the control device 16 generates an input signal Si11a to lengthen the period of conduction (on state) of transistor Q11 compared to the current period.

[0099] The control device 16 outputs the generated input signals Si11a and Si12a to the isolated signal transmission unit 15 at a time between time t3 and time t4 (for example, time t3a). Time t4 is the time when one period T of the pulse signal Spls1 has elapsed since time t3. The isolated signal transmission unit 15 outputs input signals Si11b and Si12b, which have the same voltage waveform as the input signals Si11a and Si12a input from the control device 16, to the gate drive unit 12P.

[0100] The gate drive unit 12P generates gate pulse signals Sg11 and Sg12 based on input signals Si11b and Si12b received from the isolated signal transmission unit 15. The gate drive unit 12P drives transistor Q11 with the generated gate pulse signal Sg11. The gate drive unit 12P also drives transistor Q12 with the generated gate pulse signal Sg12. Transistors Q11 and Q12 are driven by these gate pulse signals Sg11 and Sg12 throughout the first to fourth operating modes. As a result, transistor Q11 has a longer conduction state (on state) at a predetermined time after time t3a than at the time t2 to time t4. On the other hand, transistor Q12 has a shorter conduction state (on state) at a predetermined time after time t3a than at the time t2 to time t4. As a result, the DC voltage V113p generated across the primary capacitor 113P becomes lower than it is currently, and the DC voltage V114p generated across the primary capacitor 114P becomes higher than it is currently.

[0101] Incidentally, the detected values ​​VP1 and VP2 of the DC voltages V113p and V114p detected by the primary DC voltage detection unit 13P at time t3 are the same as the detected values ​​VP1 and VP2 of the DC voltages V113p and V114p detected by the primary DC voltage detection unit 13P at time t2. Therefore, as shown in Figure 2, the pulse signal generation unit 14 outputs a pulse signal Spls1 with the same duty cycle as the pulse signal Spls1 output between time t2 and time t3, from time t3 to time t4.

[0102] Although a detailed explanation is omitted, the power conversion system 1A operates at times t3, t5, and t7 in the same way as at time t1. Furthermore, the power conversion system 1A operates at times t4 and t6 in the same way as at time t2. In addition, the power conversion system 1A operates at times t5a and t7a in the same way as at time t3a.

[0103] Based on the detected values ​​VP1 and VP2 of the DC voltages V113p and V114p generated at the primary side capacitors 113P and 114P at times t4 and t6, the voltage difference between the DC voltages V113p and V114p gradually decreases. As a result, as shown in Figure 2, at time t7a, the DC voltages V113p and V114p have the same voltage value, and at time t8, the primary side DC voltage detection unit 13P detects DC voltages V113p and V114p with the same voltage value. Therefore, the pulse signal generation unit 14 calculates the capacitor DC voltage ratio Vr with a value of "1" based on the DC voltages V113p and V114p with the same detected values ​​VP1 and VP2 input from the primary side DC voltage detection unit 13P. As a result, the pulse signal generation unit 14 generates a pulse signal Spls1 with a duty cycle (=(τ / T) × 100) of 50%.

[0104] The control device 16 receives a pulse signal Spls2 from the isolated signal transmission unit 15, which has the same voltage waveform as the pulse signal Spls1 generated by the pulse signal generation unit 14. At time t9, when one period T of pulse signal Spls1 has elapsed from time t8, the control device 16 calculates the duty cycle of the pulse signal Spls2 input from the isolated signal transmission unit 15. Since the calculated duty cycle of pulse signal Spls2 is 50%, the control device 16 decides to maintain the duty cycles of the input signals Si11a and Si12a determined at time t7.

[0105] As a result, the gate drive unit 12P drives transistors Q11 and Q12 so that they remain in the same conductive (on) state for the same duration as before. Therefore, as shown in Figure 2, the power conversion system 1A can control the primary side PS of the isolated DC / DC converter 11 so that the DC voltages V113p and V114p generated at the primary side capacitors 113P and 114P are maintained at half the input voltage Edc of the primary side device 2P (i.e., the design voltage) from time t9 onward through the first to fourth operating modes.

[0106] Thus, the power conversion system 1A according to this embodiment can control the voltage balance of the DC voltages V113p and V114p generated in the primary capacitors 113P and 114P, even if the number of optical transmission units used in the isolated signal transmission unit 15 is smaller compared to conventional power conversion systems.

[0107] In power conversion system 1A, the voltage balance of DC voltages V113p and V114p generated in primary side capacitors 113P and 114P is controlled based on the ratio of these voltages, rather than on their detected values. Therefore, even if the voltage values ​​of DC voltages V113p and V114p in primary side capacitors 113P and 114P are controlled to be the same in power conversion system 1A, their absolute values ​​may not be the same as the design values ​​(i.e., their absolute values ​​may be larger or smaller than the design values). Even if the voltage values ​​of DC voltages V113p and V114p after voltage balancing are not the same as the design values, power conversion system 1A can control the voltage balance of DC voltages V113s and V114s generated in secondary side capacitors 113S and 114S using the secondary side DC voltage detection unit 13S. The power conversion system 1A controls the voltage balance of DC voltages V113s and V114s generated at secondary capacitors 113S and 114S using detected values, thereby enabling the control of the DC voltages V113s and V114s to be identical to the design values. Therefore, even if the absolute values ​​of the DC voltages V113p and V114p at primary capacitors 113P and 114P deviate from the design values ​​when the power conversion system 1A controls the voltage balance, the design DC voltage can still be supplied to the secondary device 2S.

[0108] As described above, the power conversion system 1A according to this embodiment includes an isolation transformer 111, an isolated DC / DC converter 11 having an isolation transformer 111, a primary bridge circuit 112P provided on the primary side PS of the isolation transformer 111 and having transistors Q11 and Q12, and a secondary bridge circuit 112S provided on the secondary side SS of the isolation transformer 111 and having transistors Q21 and Q22, a control device 16 that controls the primary bridge circuit 112P and the secondary bridge circuit 112S, primary capacitors 113P and 114P connected in series to the primary bridge circuit 112P, secondary capacitors 113S and 114S connected in series to the secondary bridge circuit 112S, and primary capacitors The device includes a primary-side DC voltage detection unit 13P that individually detects the DC voltages V113p and V114p generated in each of the capacitors 113P and 114P, a secondary-side DC voltage detection unit 13S that individually detects the DC voltages V113s and V114s generated in each of the secondary-side capacitors 113S and 114S, a pulse signal generation unit 14 that generates a pulse signal Spls1 with a duty cycle corresponding to the ratio of the DC voltages V113p and V114p detected by the primary-side DC voltage detection unit 13P, and an isolated signal transmission unit 15 that transmits a pulse signal Spls2 based on the pulse signal Spls1 input from the pulse signal generation unit 14 to the control device 16 while the primary-side PS and secondary-side SS of the isolated DC / DC converter 11 are electrically isolated.

[0109] As a result, the power conversion system 1A can be made more cost-effective even if it has a primary neutral point NP (i.e., the capacitor midpoint) to which primary capacitors 113P and 114P are connected, and also has an isolation transformer 111.

[0110] [Modification of the first embodiment] (Variation 1) A power conversion system according to Modification 1 of this embodiment will be described with reference to Figure 1, and with reference to Figures 3 and 4. This modified power conversion system is characterized by having a filter unit between the isolated signal transmission unit and the control device. This modified power conversion system 1B has the same configuration as the power conversion system 1A of this embodiment, except that it has a filter unit 17. Therefore, in describing this modified system, the reference numerals of the components of the power conversion system 1A, other than the filter unit 17, will be used with reference to Figure 1.

[0111] (Configuration of the power conversion system according to this modified example) Figure 3 is a block diagram illustrating an example of the main components of the power conversion system 1B according to this modified example. Figure 3 shows the connection relationship between the filter unit 17 and other components of the power conversion system 1B.

[0112] As shown in Figure 3, the power conversion system 1B extracts a filter signal (an example of a signal) Sf having an amplitude corresponding to the ratio of DC voltages V113p and V114p (see Figure 1) detected by the primary DC voltage detection unit (an example of one detection unit) 13P (see Figure 1) based on the duty cycle of the pulse signal Spls1 generated by the pulse signal generation unit 14, and includes a filter unit 17 provided on the output side of the isolated signal transmission unit 15. In this way, the filter unit 17 generates the filter signal Sf based on the pulse signal Spls1. Therefore, the filter signal Sf corresponds to a signal based on the pulse signal Spls1 input from the pulse signal generation unit 14.

[0113] The filter section 17 may be composed of either a passive filter or an active filter, as long as it has a frequency characteristic that allows the pulse signal Spls1 to pass through. Furthermore, the filter section 17 may be configured as a low-pass filter, a high-pass filter, or a band-pass filter, as long as it has a frequency characteristic that allows the pulse signal Spls1 to pass through.

[0114] As shown in Figure 3, the input terminal of the filter unit 17 is connected to the optical transmission unit 151 provided in the isolated signal transmission unit 15. The output terminal of the filter unit 17 is connected to the control device 16. As a result, the filter unit 17 outputs a filter signal Sf to the control device 16 with an amplitude (i.e., voltage value) corresponding to the duty cycle of the pulse signal Spls2 input from the optical transmission unit 151. The larger the duty cycle of the pulse signal Spls2 (i.e., the duty cycle of the pulse signal Spls1), the larger the amplitude of the filter signal Sf that the filter unit 17 outputs to the control device 16. When the filter signal Sf is divided into periods of the pulse signal Spls2, it is a DC signal with a voltage value corresponding to the duty cycle of the pulse signal Spls2.

[0115] The control device 16 outputs an input signal Si11a with the same duty cycle as the current one to the gate drive unit 12S if the amplitude of the filter signal Sf input from the filter unit 17 is the same as, for example, a preset comparison voltage level or within a predetermined voltage level range relative to that comparison voltage level. The comparison voltage level set in the control device 16 is set to the design value of the amplitude of the filter signal Sf output by the filter unit 17 when the duty cycle of the pulse signal Spls1 is 50%. Furthermore, due to the component precision of the components constituting the filter unit 17 and the control device 16, the amplitude of the filter signal Sf and the comparison voltage level may be judged as different voltage levels even though they are actually the same. For this reason, in the power conversion system 1B, the control device 16 is set to consider the filter signal Sf and the comparison voltage level to be the same if the amplitude of the filter signal Sf is within a predetermined voltage level range relative to the comparison voltage level.

[0116] If the amplitude of the filter signal Sf input from the filter unit 17 is greater than the maximum value of the predetermined voltage level set with respect to the comparison voltage level, the control device 16 outputs an input signal Si11a with a duty cycle, for example, smaller than the current one, to the gate drive unit 12S. On the other hand, if the amplitude of the filter signal Sf input from the filter unit 17 is less than the minimum value of the predetermined voltage level set with respect to the comparison voltage level, the control device 16 outputs an input signal Si11a with a duty cycle, for example, larger than the current one, to the gate drive unit 12S.

[0117] As a result, the control device 16 can control the gate drive unit 12P in accordance with the duty cycle of the pulse signal Spls1 output from the pulse signal generation unit 14. Therefore, the power conversion system 1B can control the voltage balance of the primary side capacitors 113P and 114P.

[0118] (Operation of the power conversion system according to this modified example) The operation of the power conversion system 1B according to this modification will be explained using Figure 4, with reference to Figures 1 and 3. The basic operation of the power conversion system 1B according to this modification is the same as the basic operation of the power conversion system 1A according to this modification, so the explanation will be omitted.

[0119] Figure 4 is a timing chart showing an example of the operating waveform of the power conversion system 1B. Figure 4 illustrates the operating waveform of the power conversion system 1B related to voltage balance control that makes the DC voltages V113p and V114p generated at the primary side capacitors 113P and 114P the same. The power conversion system 1B is configured to detect the DC voltages V113p and V114p generated at the primary side capacitors 113P and 114P each time it performs a series of operations from the first to the fourth operating mode multiple times. However, the power conversion system 1B may also be configured to detect the DC voltages V113p and V114p generated at the primary side capacitors 113P and 114P each time it performs a series of operations from the first to the fourth operating mode.

[0120] The "primary capacitor DC voltage," "capacitor DC voltage ratio," and "pulse signal" in the first to third rows of Figure 4 are the same as those in the first to third rows of Figure 2, so no explanation is provided. The fourth row of Figure 4 shows the voltage waveform of the filter signal Sf output from the filter unit 17. The vertical axis in the fourth row of Figure 4 represents voltage. In Figure 4, time progresses from left to right. For ease of understanding, in Figure 4, the magnitudes and relative magnitudes of the DC voltages V113p and V114p generated at the primary capacitor 113P and the primary capacitor 114P during the time progression from time t0 to time t9 are the same as those of the DC voltages V113p and V114p shown in Figure 2.

[0121] Therefore, at time t0, the primary DC voltage detection unit 13P and the pulse signal generation unit 14 operate in the same manner as described in Figure 2. As a result, as shown in Figure 4, the pulse signal generation unit 14 outputs a pulse signal Spls1 with a duty cycle (=(τ / T) × 100) greater than 50% to the isolated signal transmission unit 15 during the period from time t0 to time t1.

[0122] The filter unit 17 receives a pulse signal Spls2 from the isolated signal transmission unit 15, which has the same voltage waveform as the input pulse signal Spls1. The filter unit 17 generates a filter signal Sf with an amplitude corresponding to the duty cycle of the input pulse signal Spls2 during the period from time t0 to time t1 (i.e., the same length as one period T of pulse signal Spls1). The filter unit 17 starts outputting the generated filter signal Sf to the control device 16 from time t1.

[0123] The control device 16 generates input signals Si11a and Si12b with duty cycles corresponding to the amplitude of the filter signal Sf input from the filter unit 17. As shown in Figure 4, the control device 16 outputs the generated input signals Si11a and Si12b to the isolated signal transmission unit 15 at a time between time t1 and time t2 (for example, time t1a). Time t2 is the time when one period T of the pulse signal Spls1 has elapsed since time t1.

[0124] After the control device 16 outputs the input signals Si11a and Si12a to the isolated signal transmission unit 15 at time t1a, the isolated signal transmission unit 15 and the gate drive unit 12P operate in the same manner as described in Figure 2. As a result, as shown in Figure 4, at a predetermined time elapsed from time t1a, the DC voltage V113p generated at the primary capacitor 113P becomes lower than its current value, and the DC voltage V114p generated at the primary capacitor 114P becomes higher than its current value.

[0125] Similar to the first embodiment described above, the timing at which the DC voltages V113p and V114p generated in the primary capacitors 113P and 114P change is actually after a predetermined time has elapsed from time t1a, due to factors such as the generation time of the gate pulse signals Sg11 and Sg12 in the gate drive unit 12P and the time elapsed from the first operating mode to the fourth operating mode. However, in Figure 4, for the sake of ease of understanding, the DC voltages V113p and V114p are shown to change at time t1a. The timing at which the DC voltages V113p and V114p generated in the primary capacitors 113P and 114P change is also shown in the same way at time t3a, time t5a, and time t7a, which will be described later.

[0126] Similar to the first embodiment described above, the detected values ​​VP1 and VP2 of the DC voltages V113p and V114p detected by the primary DC voltage detection unit 13P at time t1 are the same as the detected values ​​VP1 and VP2 of the DC voltages V113p and V114p detected by the primary DC voltage detection unit 13P at time t0. Therefore, as shown in Figure 4, the pulse signal generation unit 14 outputs a pulse signal Spls1 with the same duty cycle as the pulse signal Spls1 output between time t0 and time t1, even between time t1 and time t2.

[0127] As shown in Figure 4, the DC voltage V113p generated at the primary capacitor 113P is smaller at time t2 than at time t1. Also, the DC voltage V114p generated at the primary capacitor 114P is larger at time t2 than at time t1. For this reason, the pulse signal generation unit 14 outputs a pulse signal Spls1 to the isolated signal transmission unit 15 that is greater than 50% and has a smaller duty cycle than the pulse signal Spls1 output at time t1.

[0128] As a result, as shown in Figure 4, the filter unit 17 generates a filter signal Sf with an amplitude corresponding to the duty cycle of the pulse signal Spls2 input during the period from time t2 to time t3 (i.e., the same length as one period T of the pulse signal Spls1). The filter unit 17 starts outputting the generated filter signal Sf to the control device 16 from time t3.

[0129] The control device 16 generates input signals Si11a and Si12b with duty cycles corresponding to the amplitude of the filter signal Sf input from the filter unit 17. The control device 16 outputs the generated input signals Si11a and Si12b to the isolated signal transmission unit 15 at a time between time t3 and time t4 (for example, time t3a). Time t4 is the time when one period T of the pulse signal Spls1 has elapsed since time t3.

[0130] After the control device 16 outputs the input signals Si11a and Si12a to the isolated signal transmission unit 15 at time t3a, the isolated signal transmission unit 15 and the gate drive unit 12P operate in the same manner as described in Figure 2. As a result, as shown in Figure 4, at a predetermined time elapsed from time t3a, the DC voltage V113p generated at the primary capacitor 113P becomes lower than its current value, and the DC voltage V114p generated at the primary capacitor 114P becomes higher than its current value.

[0131] Similar to the first embodiment described above, the detected values ​​VP1 and VP2 of the DC voltages V113p and V114p detected by the primary DC voltage detection unit 13P at time t3 are the same as the detected values ​​VP1 and VP2 of the DC voltages V113p and V114p detected by the primary DC voltage detection unit 13P at time t2. Therefore, as shown in Figure 4, the pulse signal generation unit 14 outputs a pulse signal Spls1 with the same duty cycle as the pulse signal Spls1 output between time t2 and time t3, between time t3 and time t4.

[0132] Although a detailed explanation is omitted, power conversion system 1B operates in the same way at time t1 at times t3, t5, and t7. Furthermore, power conversion system 1B operates in the same way at time t2 at times t4 and t6. Additionally, power conversion system 1B operates in the same way at time t3a at times t5a and t7a.

[0133] Based on the detected values ​​VP1 and VP2 of the DC voltages V113p and V114p generated at the primary side capacitors 113P and 114P at times t4 and t6, the voltage difference between DC voltages V113p and V114p gradually decreases. As a result, as shown in Figure 4, at time t7a, DC voltages V113p and V114p have the same voltage value, and at time t8, DC voltages V113p and V114p with the same voltage value are detected by the primary side DC voltage detection unit 13P. Therefore, the pulse signal generation unit 14 calculates the capacitor DC voltage ratio Vr with a value of "1" based on the DC voltages V113p and V114p with the same detected values ​​VP1 and VP2 input from the primary side DC voltage detection unit 13P. As a result, the pulse signal generation unit 14 generates a pulse signal Spls1 with a duty cycle (=(τ / T) × 100) of 50%.

[0134] As a result, as shown in Figure 4, the filter unit 17 generates a filter signal Sf with an amplitude corresponding to the duty cycle of the pulse signal Spls2 input during the period from time t8 to time t9 (i.e., the same length as one period T of the pulse signal Spls1). The filter unit 17 starts outputting the generated filter signal Sf to the control device 16 from time t9.

[0135] The control device 16 generates input signals Si11a and Si12b with duty cycles corresponding to the amplitude of the filter signal Sf input from the filter unit 17. The amplitude of the filter signal Sf input from the filter unit 17 is the same as the comparison voltage level or within a predetermined voltage level range relative to the comparison voltage level. Therefore, the control device 16 outputs input signals Si11a and Si12a with the same voltage waveform as the input signals Si11a and Si12a generated at time t7a to the isolated signal transmission unit 15 at a time after time t9 (for example, time t9a). As a result, the gate drive unit 12P drives transistors Q11 and Q12 so that they remain in a conductive state (on state) for the same period as before. Therefore, as shown in Figure 4, the power conversion system 1B can control the primary side PS of the isolated DC / DC converter 11 so that the DC voltages V113p and V114p generated at the primary side capacitors 113P and 114P are maintained at half the input voltage Edc of the primary side device 2P (i.e., the design voltage) from time t9a onward through the first to fourth operating modes.

[0136] Thus, the power conversion system 1B according to this modification can control the voltage balance of the DC voltages V113p and V114p generated in the primary capacitors 113P and 114P, even if the number of optical transmission units used in the isolated signal transmission unit 15 is smaller compared to the conventional power conversion system.

[0137] As described above, the power conversion system 1B according to this modified example includes a filter unit 17 in addition to the components of the power conversion system 1A according to this embodiment. Thus, even with the inclusion of the filter unit 17, the power conversion system 1B can achieve the same effects as the power conversion system 1A according to this embodiment.

[0138] (Modification 2) A power conversion system according to Modification 2 of the First Embodiment of the present invention will be described with reference to Figure 1 and with reference to Figure 5. This modified power conversion system is characterized by having a DC / AC (hereinafter sometimes abbreviated as "DC / AC") converter connected to either the primary or secondary side of the isolated DC / DC converter 11. In this modified power conversion system, for example, the power receiving side has a DC / AC converter. In this modified system, the secondary side device is the power receiving device. Therefore, as shown in Figure 5, the power conversion system 1C according to this modified system has a DC / AC converter 116 connected to the secondary side SS of the isolated DC / DC converter 11. The DC / AC converter 116 is located between the secondary side capacitors 113S, 114S and the secondary side device 2S.

[0139] The power conversion system 1C according to this modified example has the same configuration as the power conversion system 1A according to this embodiment, except that it includes a DC / AC converter 116. Therefore, in describing this modified example, for components of the power conversion system 1C other than the DC / AC converter 116, the reference numerals of the components provided in the power conversion system 1A will be used with reference to Figure 1.

[0140] Figure 5 shows an example of the circuit configuration of the DC / AC converter 116 provided in the power conversion system 1C according to this modified example. In Figure 5, the secondary bridge circuit 112S and the secondary device 2S are also shown for ease of understanding.

[0141] As shown in Figure 5, the DC / AC converter 116 has transistors Q1, Q2, Q3, and Q4 connected in series between the secondary positive electrode line P2 and the secondary negative electrode line N2. Transistors Q1, Q2, Q3, and Q4 are composed of, for example, N-type MOSFETs. The DC / AC converter 116 also has a freewheeling diode D1 connected in antiparallel to transistor Q1, a freewheeling diode D2 connected in antiparallel to transistor Q2, a freewheeling diode D3 connected in antiparallel to transistor Q3, and a freewheeling diode D4 connected in antiparallel to transistor Q4.

[0142] The drain of transistor Q1 is connected to the cathode of freewheeling diode D1, and the source of transistor Q1 is connected to the anode of freewheeling diode D1. The drain of transistor Q2 is connected to the cathode of freewheeling diode D2, and the source of transistor Q2 is connected to the anode of freewheeling diode D2. The drain of transistor Q3 is connected to the cathode of freewheeling diode D3, and the source of transistor Q3 is connected to the anode of freewheeling diode D3. The drain of transistor Q4 is connected to the cathode of freewheeling diode D4, and the source of transistor Q4 is connected to the anode of freewheeling diode D4.

[0143] The drain of transistor Q1 and the cathode of freewheeling diode D1 are connected to the secondary positive line P2. The source of transistor Q4 and the anode of freewheeling diode D4 are connected to the primary negative line N1. The source of transistor Q1 and the anode of freewheeling diode D1 are connected to the drain of transistor Q2 and the cathode of freewheeling diode D2. The source of transistor Q2 and the anode of freewheeling diode D2 are connected to the drain of transistor Q3 and the cathode of freewheeling diode D3. The source of transistor Q3 and the anode of freewheeling diode D3 are connected to the drain of transistor Q4 and the cathode of freewheeling diode D4.

[0144] The DC / AC converter 116 has transistor Q2 and freewheeling diode D2 connected in series, and diodes D5 and D6 connected in parallel to transistor Q3 and freewheeling diode D3. The cathode of diode D5 is connected to the source of transistor Q1, the anode of freewheeling diode D1, the drain of transistor Q2, and the cathode of freewheeling diode D2. The anode of diode D5 is connected to the cathode of diode D6. The anode of diode D6 is connected to the source of transistor Q3, the anode of freewheeling diode D3, the drain of transistor Q4, and the cathode of freewheeling diode D4. The connection between the anode of diode D5 and the cathode of diode D6 is connected to the secondary neutral point NS.

[0145] The connection point where transistor Q2, freewheeling diode D2, transistor Q3, and freewheeling diode D3 are connected to each other becomes the output terminal of the DC / AC converter 116. This connection point is connected to the secondary side device 2S.

[0146] Although a detailed explanation is omitted, the DC / AC converter 116 is controlled by the control device 16 to enable the conduction state (on state) and non-conduction state (off state) of transistors Q1, Q2, Q3, and Q4 in a predetermined order and number. As a result, the DC / AC converter 116 can convert the DC voltage output from the isolated DC / DC converter 11 via the secondary positive electrode line P2 and secondary negative electrode line N2 into an AC voltage Vac and output it to the secondary device 2S.

[0147] Furthermore, the connection between the anode of diode D5 and the cathode of diode D6, both located in the DC / AC converter 116, is connected to the secondary neutral point NS. Therefore, the DC / AC converter 116 converts the DC voltage output from the isolated DC / DC converter 11, with its voltage balance controlled, into an AC voltage Vac. This prevents the DC / AC converter 116 from generating offset voltages in the positive and negative center voltages (e.g., 0V). As a result, the DC / AC converter 116 can output an AC voltage Vac to the secondary device 2S, with the positive and negative voltages controlled to a balanced state (i.e., voltage balance controlled).

[0148] As shown in Figure 5, in this modified example, the DC / AC converter 116 is configured as a three-level inverter circuit using the Neutral Point Clamped (NPC) method. However, the DC / AC converter 116 is not limited to the NPC method and may be configured as a three-level inverter circuit using the T-type Neutral Point Clamped (TNPC) method. Also, in this modified example, since the secondary device 2S is the power receiving device, the DC / AC converter 116 is provided on the secondary SS. However, if the primary device 2P is the power receiving device, the DC / AC converter 116 is connected to the primary PS of the isolated DC / DC converter 11 and is placed, for example, between the primary capacitors 113P and 114P and the primary device 2P. In this case, the connection points of diodes D5 and D6 provided on the DC / AC converter 116 are connected to the primary neutral point NP (see Figure 1). As a result, even if the DC / AC converter 116 is installed on the primary side PS, it can output an AC voltage to the primary side device 2P in which the positive and negative voltages are controlled to be in a balanced state (i.e., the voltage balance is controlled).

[0149] [Second Embodiment] A power conversion system according to a second embodiment of the present invention will be described with reference to Figures 6 to 8. First, the schematic configuration of the power conversion system according to this embodiment will be described with reference to Figures 6 and 7. Figure 6 is a block diagram showing an example of the schematic configuration of the power conversion system 1D according to this embodiment. In Figure 6, for ease of understanding, the primary side device 2P and the secondary side device 2S connected to the power conversion system 1D are also shown together. Furthermore, components that perform the same operation and function as the components of the power conversion system 1A according to the first embodiment are given the same reference numerals, and detailed explanations are omitted.

[0150] (Outline configuration of the power conversion system) The power conversion system 1D includes isolated DC / DC converters 11 and 21, and can supply power bidirectionally between the primary device 2P connected to the primary PS and the secondary device 2S connected to the secondary SS. The isolated DC / DC converter 11 is a bidirectional DC / DC converter such as a DAB converter. The power conversion system 1D also has a multi-cell circuit configuration that includes isolated DC / DC converters 11 and 21.

[0151] As shown in Figure 6, the primary device 2P and the secondary device 2S are connected to the power conversion system 1D. The primary device 2P and the secondary device 2S are each connected to the isolated DC / DC converters 11 and 21. In this embodiment, the primary device 2P is the device that supplies power and the secondary device 2S is the device that receives power, but it is also possible for the primary device 2P to be the device that receives power and the secondary device 2S to be the device that supplies power.

[0152] As shown in Figure 6, the power conversion system 1D comprises a plurality of isolated DC / DC converters 11, 21, each having isolation transformers 111, 211, primary bridge circuits 112P, 212P provided on the primary side PS of the isolation transformers 111, 211 and having transistors Q11, Q12, Q13, Q14, Q31, Q32, Q33, Q34 (an example of at least two switching elements), and secondary bridge circuits 112S, 212S provided on the secondary side SS of the isolation transformers 111, 211 and having transistors Q21, Q22, Q23, Q24, Q41, Q42, Q43, Q44 (an example of at least two switching elements).

[0153] Specifically, the isolated DC / DC converter 11 includes an isolation transformer 111, a primary bridge circuit 112P, and a secondary bridge circuit 112S. The isolated DC / DC converter 21 also includes an isolation transformer 211, a primary bridge circuit 212P, and a secondary bridge circuit 212S.

[0154] The negative terminal side of the primary side PS of the isolation transformer 111, which is provided in the isolated DC / DC converter 11 of the power conversion system 1D, is connected to the primary side neutral point NP. The primary side PS of the isolation transformer 111 has the same configuration as the primary side PS of the isolation transformer 111 in the first embodiment described above, except that the negative terminal side is connected to the primary side neutral point NP, so a detailed explanation is omitted.

[0155] The isolation transformer 211 has a primary winding and a secondary winding. The primary side bridge circuit 212P is electrically connected to the primary winding of the isolation transformer 211, and the secondary side bridge circuit 212S is electrically connected to the secondary winding of the isolation transformer 211. The winding ratio of the primary and secondary windings of the isolation transformer 211 may be determined according to the ratio of the rated voltages of the primary side device 2P and the secondary side device 2S.

[0156] The power conversion system 1D has a primary side positive electrode line P1 connected to the positive side of the primary side bridge circuit 112P, and a primary side negative electrode line N1 connected to the negative side of the primary side bridge circuit 212P. The primary side positive electrode line P1 is connected to the positive terminal of the primary side device 2P. The primary side negative electrode line N1 is connected to the negative terminal of the primary side device 2P. The positive side of the primary side bridge circuit 212P is connected to the primary side neutral point NP. Therefore, the primary side bridge circuit 212P is connected to the negative side of the primary side bridge circuit 212P via the primary side neutral point NP. In this way, the primary side bridge circuits 112P and 212P are connected in series between the primary side positive electrode line P1 and the primary side negative electrode line N1 at the primary side PS.

[0157] Therefore, the isolated DC / DC converter 11 and the isolated DC / DC converter 21 are connected in series between the primary side positive line P1 and the primary side negative line N1 at the primary side PS. As a result, the primary side bridge circuit 112P can exchange power with the primary side device 2P and can exchange power with the primary winding of the isolation transformer 111. Similarly, the primary side bridge circuit 212P can exchange power with the primary side device 2P and can exchange power with the primary winding of the isolation transformer 211.

[0158] As shown in Figure 7(a), the primary bridge circuit 112P provided in the isolated DC / DC converter 11 has transistors Q11 and Q12 (an example of at least two switching elements) connected in series, and transistors Q13 and Q14 (an example of at least two switching elements) connected in series. Transistors Q11, Q12, Q13, and Q14 (hereinafter sometimes abbreviated as "transistors Q11 to Q14") are composed of, for example, N-type MOSFETs. Transistors Q11 and Q12 and transistors Q13 and Q14 are connected in parallel.

[0159] The primary bridge circuit 112P includes a freewheeling diode D11 connected in reverse parallel to transistor Q11, a freewheeling diode D12 connected in reverse parallel to transistor Q12, a freewheeling diode D13 connected in reverse parallel to transistor Q13, and a freewheeling diode D14 connected in reverse parallel to transistor Q14.

[0160] The drain of transistor Q11 is connected to the cathode of freewheeling diode D11, the drain of transistor Q13, and the cathode terminal of freewheeling diode D13. The source of transistor Q11 is connected to the anode of freewheeling diode D11, the drain of transistor Q12, and the cathode of freewheeling diode D12. The gate of transistor Q11 is connected to a gate drive unit 12P provided on the primary bridge circuit 112P. As a result, the gate pulse signal Sg11 output from the gate drive unit 12P is input to the gate of transistor Q11, and the conduction state (on state) / non-conduction state (off state) of transistor Q11 is controlled.

[0161] The source of transistor Q12 is connected to the anode of freewheeling diode D12, the source of transistor Q14, and the anode of freewheeling diode D14. The gate of transistor Q12 is connected to gate drive unit 12P. As a result, the gate pulse signal Sg12 output from gate drive unit 12P is input to the gate of transistor Q12, controlling the conduction state (on state) / non-conduction state (off state) of transistor Q12.

[0162] The source of transistor Q13 is connected to the anode of freewheeling diode D13, the drain of transistor Q14, and the cathode of freewheeling diode D14. The gate of transistor Q13 is connected to gate drive unit 12P. As a result, the gate pulse signal Sg13 output from gate drive unit 12P is input to the gate of transistor Q13, controlling the conduction state (on state) / non-conduction state (off state) of transistor Q13.

[0163] The gate of transistor Q14 is connected to the gate drive unit 12P. As a result, the gate pulse signal Sg14 output from the gate drive unit 12P is input to the gate of transistor Q14, controlling the conduction state (on state) / non-conduction state (off state) of transistor Q14. The gate drive unit 12P drives transistors Q11 to Q14 by PWM control using gate pulse signals Sg11, Sg12, Sg13, and Sg14 (hereinafter sometimes abbreviated as "gate pulse signals Sg11 to Sg14").

[0164] The drain of transistor Q11 and the cathode of freewheeling diode D11, the drain of transistor Q13 and the cathode of freewheeling diode D13 are connected to the primary side positive line P1. The source of transistor Q12 and the anode of freewheeling diode D12, the source of transistor Q14 and the anode of freewheeling diode D14 are connected to the primary side neutral point NP. Thus, the primary side bridge circuit 112P has a full bridge circuit composed of transistors Q11 to Q14 and freewheeling diodes D11, D12, D13, and D14 (hereinafter sometimes abbreviated as "freewheeling diodes D11 to D14"). The connection point a1 between the source of transistor Q11 and the anode of freewheeling diode D11, and the drain of transistor Q12 and the cathode of freewheeling diode D12 is connected to one terminal of inductor 115P (see Figure 6). The connection point a2 between the drain of transistor Q13 and the anode of freewheel diode D13, and the drain of transistor Q14 and the cathode of freewheel diode D14, is connected to the other terminal of the primary winding of isolation transformer 111.

[0165] As shown in Figure 7(a), the primary bridge circuit 212P provided in the isolated DC / DC converter 21 (see Figure 6) has transistors Q31 and Q32 (an example of at least two switching elements) connected in series, and transistors Q33 and Q34 (an example of at least two switching elements) connected in series. Transistors Q31, Q32, Q33, and Q34 (hereinafter sometimes abbreviated as "transistors Q31 to Q34") are composed of, for example, N-type MOSFETs. Transistors Q31 and Q32 and transistors Q33 and Q34 are connected in parallel.

[0166] The primary bridge circuit 212P includes a freewheeling diode D31 connected in reverse parallel to transistor Q31, a freewheeling diode D32 connected in reverse parallel to transistor Q32, a freewheeling diode D33 connected in reverse parallel to transistor Q33, and a freewheeling diode D34 connected in reverse parallel to transistor Q34. Hereafter, freewheeling diodes D31, D32, D33, and D34 may be abbreviated as "freewheeling diodes D31~D34".

[0167] The drain of transistor Q31, the cathode of freewheeling diode D31, the drain of transistor Q33, and the cathode of freewheeling diode D33 are connected to the primary side neutral point NP. The drain of transistor Q31, the cathode of freewheeling diode D31, the drain of transistor Q33, and the cathode of freewheeling diode D33 are connected to the source of transistor Q12, the anode of freewheeling diode D12, the source of transistor Q14, and the anode of freewheeling diode D14 via the primary side neutral point NP. The source of transistor Q32, the anode of freewheeling diode D32, the source of transistor Q34, and the anode of freewheeling diode D34 are connected to the primary side negative line N1.

[0168] The connections between transistors Q31-Q34 and freewheeling diodes D31-D34 are the same as the connections between transistors Q11-Q14 and freewheeling diodes D11-D14 in the primary bridge circuit 112P when the arrows are read from left to right as shown below, so a detailed explanation is omitted. Transistor Q11 → Transistor Q31 Transistor Q12 → Transistor Q32 Transistor Q13 → Transistor Q33 Transistor Q14 → Transistor Q34 Freewheel diode D11 → Freewheel diode D31 Freewheel diode D12 → Freewheel diode D32 Freewheel diode D13 → Freewheel diode D33 Freewheel diode D14 → Freewheel diode D34

[0169] Thus, the primary bridge circuit 212P has a full bridge circuit composed of transistors Q31 to Q34 and freewheeling diodes D31 to D34.

[0170] The gates of transistors Q31 to Q34 are connected to the gate drive unit 12P (see Figure 6). The gate pulse signal Sg31 is input to the gate of transistor Q31 from the gate drive unit 12P. The gate pulse signal Sg32 is input to the gate of transistor Q32 from the gate drive unit 12P. The gate pulse signal Sg33 is input to the gate of transistor Q33 from the gate drive unit 12P. The gate pulse signal Sg34 is input to the gate of transistor Q34 from the gate drive unit 12P. As a result, the gate drive unit 12P drives transistors Q31 to Q34 by PWM control using the gate pulse signals Sg31, Sg32, Sg33, and Sg34.

[0171] Returning to Figure 6, the isolated DC / DC converter 11 has an inductor 215P positioned between the primary bridge circuit 212P and the primary winding of the isolation transformer 211. One terminal of inductor 215P is connected to the source of transistor Q31, the anode of freewheeling diode D31, the drain of transistor Q32, and the cathode of freewheeling diode D32 (see Figure 7(a)). In other words, one terminal of inductor 215P is connected to the connection point c1 (see Figure 7(a)) between the source of transistor Q31 and the anode of freewheeling diode D31, and the drain of transistor Q32 and the cathode of freewheeling diode D32. The other terminal of inductor 215P is connected to one terminal of the primary winding of the isolation transformer 211. The other terminals of the primary winding of isolation transformer 211 are connected to the source of transistor Q33 and the anode of freewheeling diode D33, and to the connection point c2 (see Figure 7(a)) between the drain of transistor Q34 and the cathode of freewheeling diode D34.

[0172] As shown in Figure 6, the power conversion system 1D includes primary capacitors 113P and 213P connected in parallel to primary bridge circuits 112P and 212P (an example of multiple primary bridge circuits), respectively. Specifically, primary capacitor 113P is connected in parallel to primary bridge circuit 112P, and primary capacitor 213P is connected in parallel to primary bridge circuit 212P. One electrode of primary capacitor 113P is connected to the primary positive electrode line P1, and the other electrode of primary capacitor 113P is connected to the primary neutral point NP. One electrode of primary capacitor 213P is connected to the primary neutral point NP, and the other electrode of primary capacitor 213P is connected to the primary negative electrode line N1. Therefore, the other electrode of primary capacitor 113P and one electrode of primary capacitor 213P are connected via the primary neutral point NP. In other words, the connection point between primary capacitor 113P and primary capacitor 213P becomes the primary neutral point NP.

[0173] Primary capacitors 113P and 213P are connected in series between the primary positive line P1 and the primary negative line N1. Primary capacitor 113P is located between the primary bridge circuit 112P and the primary device 2P. Primary capacitor 213P is located between the primary bridge circuit 212P and the primary device 2P.

[0174] As will be explained in detail later, when transistors Q11 and Q14 are controlled to be ON and transistors Q12 and Q13 are controlled to be OFF, a DC voltage V113p with the same polarity as the input voltage generated at the primary capacitor 113P and input from the primary device 2P is applied between one terminal of inductor 115P and the other terminal of the primary winding of isolation transformer 111. Similarly, when transistors Q31 and Q34 are controlled to be ON and transistors Q32 and Q33 are controlled to be OFF, a voltage with the same value as the DC voltage V213p with the same polarity as the input voltage generated at the primary capacitor 213P and input from the primary device 2P is applied between one terminal of inductor 215P and the other terminal of the primary winding of isolation transformer 211.

[0175] On the other hand, when transistors Q11 and Q14 are controlled to be in the off state and transistors Q12 and Q13 are controlled to be in the on state, a DC voltage V113p, which is in the opposite polarity to the input voltage generated in the primary capacitor 113P and input from the primary device 2P, is applied between one terminal of inductor 115P and the other terminal of the primary winding of isolation transformer 111. Similarly, when transistors Q31 and Q34 are controlled to be in the off state and transistors Q32 and Q33 are controlled to be in the on state, a DC voltage V213p, which is in the opposite polarity to the input voltage generated in the primary capacitor 213P and input from the primary device 2P, is applied between one terminal of inductor 215P and the other terminal of the primary winding of isolation transformer 211.

[0176] In the power conversion system 1D, the primary capacitors 113P and 213P are designed to have the same capacitance. Therefore, the DC voltage V113p generated across primary capacitor 113P and the DC voltage V213p generated across primary capacitor 213P are the same voltage value (half the voltage value of the DC voltage between the primary positive line P1 and the primary negative line N1 (the input voltage input from primary device 2P)). Consequently, in the power conversion system 1D, a current of constant magnitude and polarity reversing flows through the primary winding of the isolation transformer 111 in accordance with the on / off control of transistors Q11 to Q14. Similarly, in the power conversion system 1D, a current of constant magnitude and polarity reversing flow through the primary winding of the isolation transformer 211 in accordance with the on / off control of transistors Q31 to Q34.

[0177] However, similar to the first embodiment, due to various factors such as the component precision of the primary capacitors 113P and 213P and transistors Q11-Q14, Q31-Q34, and the operating environment of the power conversion system 1D, a difference may occur between the amount of current flowing through the primary capacitor 113P and the amount of current flowing through the primary capacitor 213P during the operation of the power conversion system 1D. Therefore, the power conversion system 1D, similar to the power conversion system 1A in the first embodiment, controls the potential of the primary neutral point NP so that the DC voltage V113p generated in the primary capacitor 113P and the DC voltage V213p generated in the primary capacitor 213P have the same voltage value.

[0178] As shown in Figure 6, the power conversion system 1D includes a primary DC voltage detection unit 13P that individually detects the DC voltages V113p and V213p generated in each of the primary capacitors 113P and 213P (an example of multiple primary capacitors). The primary DC voltage detection unit 13P includes a detection unit 131P that detects the DC voltage V113p generated in the primary capacitor 113P, and a detection unit 132P that detects the DC voltage V213p generated in the primary capacitor 213P.

[0179] One input terminal of the detection unit 131P is connected to the primary side positive electrode line P1, and the other input terminal of the detection unit 131P is connected to the primary side neutral point NP. This allows the detection unit 131P to detect a DC voltage V113p, which is the potential difference between the potential at one electrode of the primary side capacitor 113P and the potential at the other electrode of the primary side capacitor 113P. One input terminal of the detection unit 132P is connected to the primary side neutral point NP, and the other input terminal of the detection unit 132P is connected to the primary side negative electrode line N1. This allows the detection unit 132P to detect a DC voltage V213p, which is the potential difference between the potential at one electrode of the primary side capacitor 213P and the potential at the other electrode of the primary side capacitor 213P.

[0180] As shown in Figure 6, the power conversion system 1D includes a pulse signal generation unit 14 that generates a pulse signal Spls1 with a duty cycle corresponding to the ratio of multiple DC voltages detected by either the primary DC voltage detection unit 13P or the secondary DC voltage detection unit 13S (details described later). The pulse signal generation unit 14 is provided on the side of the primary side PS and secondary side SS that is electrically isolated from the control device 16 (details described later). In this embodiment, since the control device 16 is located on the secondary side SS, the pulse signal generation unit 14 is provided on the primary side PS.

[0181] The pulse signal generation unit 14 is connected to the output terminals of the detection units 131P and 132P, which are provided on the primary DC voltage detection unit 13P. As a result, the pulse signal generation unit 14 receives the DC voltages V113p and V213p detected by the detection units 131P and 132P, respectively. The pulse signal generation unit 14 generates a pulse signal Spls1 with a duty cycle corresponding to the ratio of the voltage value of the DC voltage V113p input from the detection unit 131P to the voltage value of the DC voltage V213p input from the detection unit 132P.

[0182] The pulse signal generation unit 14 generates a pulse signal with a duty cycle of, for example, 50% if the division (VP1 / VP2) obtained by dividing the detected value VP1 of the DC voltage V113p input from the detection unit 131P by the detected value VP2 of the DC voltage V213p input from the detection unit 132P is 1 or within a predetermined range relative to 1. The pulse signal generation unit 14 outputs the generated pulse signal Spls1 to the isolated signal transmission unit 15 (details will be described later). The duty cycle is the ratio of the period τ during which the signal level is high relative to one period T of the pulse signal ((τ / T) × 100). The pulse signal generation unit 14 in this embodiment performs the same operation and function as the pulse signal generation unit 14 in the first embodiment described above, except that it generates pulse signals Spls1 based on the detected values ​​VP1 and VP2 of the DC voltages V113p and V213p. For this reason, a detailed explanation of the pulse signal generation unit 14 is omitted.

[0183] As shown in Figure 6, the negative electrode side of the secondary side SS of the isolation transformer 111 provided in the isolated DC / DC converter 21 of the power conversion system 1D is connected to the secondary side neutral point NS. The secondary side SS of the isolation transformer 111 has the same configuration as the secondary side SS of the isolation transformer 111 in the first embodiment described above, except that the negative electrode side is connected to the secondary side neutral point NS, so a detailed explanation is omitted.

[0184] The power conversion system 1D has a secondary positive electrode line P2 connected to the positive side of the secondary bridge circuit 112S, and a secondary negative electrode line N2 connected to the negative side of the secondary bridge circuit 212S. The secondary positive electrode line P2 is connected to the positive terminal of the secondary device 2S. The secondary negative electrode line N2 is connected to the negative terminal of the secondary device 2S. The positive side of the secondary bridge circuit 212S is connected to the secondary neutral point NS. Therefore, the negative side of the secondary bridge circuit 212S is connected via the secondary bridge circuit 212S and the secondary neutral point NS. In this way, the secondary bridge circuits 112S and 212S are connected in series between the secondary positive electrode line P2 and the secondary negative electrode line N2 in the secondary SS.

[0185] Therefore, the isolated DC / DC converter 11 (see Figure 6) and the isolated DC / DC converter 21 are connected in series between the secondary positive electrode line P2 and the secondary negative electrode line N2 on the secondary side SS. As a result, the secondary bridge circuit 112S can exchange power with the secondary device 2S and with the secondary winding of the isolation transformer 111. Similarly, the secondary bridge circuit 212S can exchange power with the secondary device 2S and with the secondary winding of the isolation transformer 211.

[0186] As shown in Figure 7(b), the secondary bridge circuit 112S provided in the isolated DC / DC converter 11 has transistors Q21 and Q22 (an example of at least two switching elements) connected in series, and transistors Q23 and Q24 (an example of at least two switching elements) connected in series. Transistors Q21, Q22, Q23, and Q24 (hereinafter sometimes abbreviated as "transistors Q21 to Q24") are composed of, for example, N-type MOSFETs. Transistors Q21 and Q22 and transistors Q23 and Q24 are connected in parallel.

[0187] The secondary bridge circuit 112S includes a freewheeling diode D21 connected in antiparallel to transistor Q21, a freewheeling diode D22 connected in antiparallel to transistor Q22, a freewheeling diode D23 connected in antiparallel to transistor Q23, and a freewheeling diode D24 connected in antiparallel to transistor Q24. Hereafter, freewheeling diodes D21, D22, D23, and D24 may be abbreviated as "freewheeling diodes D21~D24".

[0188] The drain of transistor Q21, the cathode of freewheeling diode D21, the drain of transistor Q23, and the cathode of freewheeling diode D23 are connected to the secondary positive line P2. The source of transistor Q22, the anode of freewheeling diode D22, the source of transistor Q24, and the anode of freewheeling diode D24 are connected to the secondary neutral point NS.

[0189] The connections between transistors Q21-Q24 and freewheeling diodes D21-D24 are the same as the connections between transistors Q11-Q14 and freewheeling diodes D11-D14 in the primary bridge circuit 112P when the arrows are read from left to right as shown below, so a detailed explanation is omitted. Transistor Q11 → Transistor Q21 Transistor Q12 → Transistor Q22 Transistor Q13 → Transistor Q23 Transistor Q14 → Transistor Q24 Freewheel diode D11 → Freewheel diode D21 Freewheel diode D12 → Freewheel diode D22 Freewheel diode D13 → Freewheel diode D23 Freewheel diode D14 → Freewheel diode D24

[0190] Thus, the secondary bridge circuit 112S has a full bridge circuit composed of transistors Q21 to Q24 and freewheeling diodes D21 to D24.

[0191] The gates of transistors Q21 to Q24 are connected to the gate drive unit 12S (see Figure 6). The gate pulse signal Sg21 is input to the gate of transistor Q21 from the gate drive unit 12S. The gate pulse signal Sg22 is input to the gate of transistor Q22 from the gate drive unit 12S. The gate pulse signal Sg23 is input to the gate of transistor Q23 from the gate drive unit 12S. The gate pulse signal Sg24 is input to the gate of transistor Q24 from the gate drive unit 12S. As a result, the gate drive unit 12S drives transistors Q21 to Q24 by PWM control using the gate pulse signals Sg21, Sg22, Sg23, and Sg24.

[0192] As shown in Figure 7(b), the secondary bridge circuit 212S has transistors Q41 and Q42 (an example of at least two switching elements) connected in series, and transistors Q43 and Q44 (an example of at least two switching elements) connected in series. Transistors Q41, Q42, Q43, and Q44 (hereinafter sometimes abbreviated as "transistors Q41 to Q44") are composed of, for example, N-type MOSFETs. Transistors Q41 and Q42 and transistors Q43 and Q44 are connected in parallel.

[0193] The secondary bridge circuit 212S includes a freewheeling diode D41 connected in antiparallel to transistor Q41, a freewheeling diode D42 connected in antiparallel to transistor Q42, a freewheeling diode D43 connected in antiparallel to transistor Q43, and a freewheeling diode D44 connected in antiparallel to transistor Q44. Hereafter, freewheeling diodes D41, D42, D43, and D44 may be abbreviated as "freewheeling diodes D41-D44".

[0194] The drain of transistor Q41, the cathode of freewheeling diode D41, the drain of transistor Q43, and the cathode of freewheeling diode D43 are connected to the secondary neutral point NS. The drain of transistor Q41, the cathode of freewheeling diode D41, the drain of transistor Q43, and the cathode of freewheeling diode D43 are connected via the secondary neutral point NS to the source of transistor Q22, the anode of freewheeling diode D22, the source of transistor Q24, and the anode of freewheeling diode D24.

[0195] The connections between transistors Q41-Q44 and freewheeling diodes D41-D44 are the same as the connections between transistors Q11-Q14 and freewheeling diodes D11-D14 in the primary bridge circuit 112P when the arrows are read from left to right as shown below, so a detailed explanation is omitted. Transistor Q11 → Transistor Q41 Transistor Q12 → Transistor Q42 Transistor Q13 → Transistor Q43 Transistor Q14 → Transistor Q44 Freewheel diode D11 → Freewheel diode D41 Freewheel diode D12 → Freewheel diode D42 Freewheel diode D13 → Freewheel diode D43 Freewheel diode D14 → Freewheel diode D44

[0196] Thus, the secondary bridge circuit 212S has a full bridge circuit composed of transistors Q41 to Q44 and freewheeling diodes D41 to D44.

[0197] The gates of transistors Q41 to Q44 are connected to the gate drive unit 12S. The gate of transistor Q41 receives a gate pulse signal Sg41 from the gate drive unit 12S. The gate of transistor Q42 receives a gate pulse signal Sg42 from the gate drive unit 12S. The gate of transistor Q43 receives a gate pulse signal Sg43 from the gate drive unit 12S. The gate of transistor Q44 receives a gate pulse signal Sg44 from the gate drive unit 12S. As a result, the gate drive unit 12S drives transistors Q41 to Q44 by PWM control using the gate pulse signals Sg41, Sg42, Sg43, and Sg44.

[0198] Returning to Figure 6, the isolated DC / DC converter 11 has an inductor 115S positioned between the secondary bridge circuit 112S and the secondary winding of the isolation transformer 111. One terminal of the inductor 115S is connected to the source of transistor Q21, the anode of freewheeling diode D21, the drain of transistor Q22, and the cathode of freewheeling diode D22 (see Figure 7(b)). In other words, one terminal of the inductor 115S is connected to the connection point b1 (see Figure 7(b)) between the source of transistor Q21 and the anode of freewheeling diode D21, and the drain of transistor Q22 and the cathode of freewheeling diode D22. The other terminal of the inductor 115S is connected to one terminal of the secondary winding of the isolation transformer 111. The other terminals of the secondary winding of isolation transformer 111 are connected to the connection point b2 (see Figure 7(b)) between the drain of transistor Q23 and the anode of freewheeling diode D23, and the drain of transistor Q24 and the cathode of freewheeling diode D24.

[0199] As shown in Figure 6, the isolated DC / DC converter 21 has an inductor 215S positioned between the secondary bridge circuit 212S and the secondary winding of the isolation transformer 211. One terminal of the inductor 215S is connected to the source of transistor Q41, the anode of freewheeling diode D41, the drain of transistor Q42, and the cathode of freewheeling diode D42 (see Figure 7(b)). In other words, one terminal of the inductor 215S is connected to the connection point d1 (see Figure 7(b)) between the source of transistor Q41 and the anode of freewheeling diode D41, and the drain of transistor Q42 and the cathode of freewheeling diode D42. The other terminal of the inductor 215S is connected to one terminal of the secondary winding of the isolation transformer 211. The other terminals of the secondary winding of isolation transformer 211 are connected to the connection point d2 (see Figure 7(b)) between the drain of transistor Q43 and the anode of freewheeling diode D43, and the drain of transistor Q44 and the cathode of freewheeling diode D44.

[0200] As shown in Figure 6, the power conversion system 1D includes secondary capacitors 113S and 213S connected in parallel to secondary bridge circuits 112S and 212S (an example of multiple secondary bridge circuits). Specifically, secondary capacitor 113S is connected in parallel to secondary bridge circuit 112S, and secondary capacitor 213S is connected in parallel to secondary bridge circuit 212S. One electrode of secondary capacitor 113S is connected to the secondary positive electrode line P2, and the other electrode of secondary capacitor 113S is connected to the secondary neutral point NS. One electrode of secondary capacitor 213S is connected to the secondary neutral point NS, and the other electrode of secondary capacitor 213S is connected to the secondary negative electrode line N2. Therefore, the other electrode of secondary capacitor 113S and one electrode of secondary capacitor 213S are connected via the secondary neutral point NS. In other words, the connection point between secondary capacitor 113S and secondary capacitor 213S becomes the secondary neutral point NS.

[0201] The secondary capacitors 113S and 213S are connected in series between the secondary positive electrode line P2 and the secondary negative electrode line N2. The secondary capacitor 113S is located between the secondary bridge circuit 112S and the secondary device 2S. The secondary capacitor 213S is located between the secondary bridge circuit 212S and the secondary device 2S.

[0202] As will be explained in more detail later, when transistors Q21 and Q24 are controlled to be ON and transistors Q22 and Q23 are controlled to be OFF, the induced current generated in the secondary winding of the isolation transformer 111 flows from the secondary positive electrode line P2 towards the secondary neutral point NS to the secondary capacitor 113S. Also, when transistors Q21 and Q24 are controlled to be OFF and transistors Q22 and Q23 are controlled to be ON, the induced current generated in the secondary winding of the isolation transformer 111 flows from the secondary neutral point NS towards the secondary positive electrode line P2 to the secondary capacitor 113S. Even if the current flowing from the secondary positive electrode line P2 towards the secondary neutral point NS to the secondary capacitor 113S and the current flowing from the secondary neutral point NS towards the secondary positive electrode line P2 to the secondary capacitor 113S are controlled to be the same as the DC voltage V113p generated at the primary capacitor 113P and the DC voltage V213p generated at the primary capacitor 213P, differences may occur due to various factors such as component precision and the operating environment of the power conversion system 1D.

[0203] Similarly, when transistors Q41 and Q44 are controlled to be ON and transistors Q42 and Q43 are controlled to be OFF, the induced current generated in the secondary winding of the isolation transformer 211 flows from the secondary neutral point NS toward the secondary negative line N2 to the secondary capacitor 213S. Also, when transistors Q41 and Q44 are controlled to be OFF and transistors Q42 and Q43 are controlled to be ON, the induced current generated in the secondary winding of the isolation transformer 211 flows from the secondary negative line N2 toward the secondary neutral point NS to the secondary capacitor 213S. Even if the current flowing from the secondary neutral point NS towards the secondary negative electrode line N2 to the secondary capacitor 213S and the current flowing from the secondary negative electrode line N2 towards the secondary neutral point NS are controlled to be the same as the DC voltage V113p generated at the primary capacitor 113P and the DC voltage V213p generated at the primary capacitor 213P, differences may occur due to various factors such as component precision and the operating environment of the power conversion system 1D.

[0204] In this case, at least one of the DC voltages V113s generated at the secondary capacitor 113S and V213s generated at the secondary capacitor 213S may differ from the design value, potentially preventing the isolated DC / DC converters 11 and 21 from supplying the desired DC voltage to the secondary device 2S. Therefore, as will be described in detail later, the power conversion system 1D detects the DC voltages V113s generated at the secondary capacitor 113S and V213s generated at the secondary capacitor 213S, and controls the secondary bridge circuits 112S and 212S based on the detected DC voltages V113s and V213s. This enables the power conversion system 1D to supply the desired DC voltage to the isolated DC / DC converters 11 and 21.

[0205] As shown in Figure 6, the power conversion system 1D includes a secondary DC voltage detection unit 13S that individually detects the DC voltages V113s and V213s generated in each of the secondary capacitors 113S and 213S (an example of multiple secondary capacitors). The secondary DC voltage detection unit 13S includes a detection unit 131S that detects the DC voltage V113s generated in the secondary capacitor 113S, and a detection unit 132S that detects the DC voltage V213s generated in the secondary capacitor 213S.

[0206] One input terminal of the detection unit 131S is connected to the secondary positive electrode line P2, and the other input terminal of the detection unit 131S is connected to the secondary neutral point NS. This allows the detection unit 131S to detect the DC voltage V113s, which is the potential difference between the potential at one electrode of the secondary capacitor 113S and the potential at the other electrode of the secondary capacitor 113S. One input terminal of the detection unit 132S is connected to the secondary neutral point NS, and the other input terminal of the detection unit 132S is connected to the secondary negative electrode line N2. This allows the detection unit 132S to detect the DC voltage V213s, which is the potential difference between the potential at one electrode of the secondary capacitor 213S and the potential at the other electrode of the secondary capacitor 213S. The secondary DC voltage detection unit 13S outputs the detected values ​​of the DC voltages V113s and V213s to the control device 16 (details described later).

[0207] As shown in Figure 6, the power conversion system 1D includes an isolated signal transmission unit 15 that transmits a pulse signal Spls2 (an example of a signal based on a pulse signal) based on a pulse signal Spls1 input from the pulse signal generation unit 14 to the control device 16 while the primary side PS and secondary side SS of the isolated DC / DC converters 11, 21 (an example of multiple isolated DC / DC converters) are electrically isolated.

[0208] The isolated signal transmission unit 15 includes an optical transmission unit 151 and an optical transmission unit 152-i (where i is a natural number from 1 to 8). The pulse signal Spls1 output from the pulse signal generation unit 14 is input to the optical transmission unit 151. The optical transmission unit 151 in this embodiment has the same configuration as the optical transmission unit 151 in the first embodiment described above, and performs the same functions, so a detailed explanation is omitted.

[0209] The optical transmission unit 152-i receives input signals Si1ja and Si3ja (where j is a natural number from 1 to 4) output from the control device 16. As will be described in detail later, input signal Si1ja is a signal for generating gate pulse signals Sg11 to Sg14, which are input to the gates of transistors Q11 to Q14 provided in the primary bridge circuit 112P. Input signal Si3ja is a signal for generating gate pulse signals Sg31 to Sg34, which are input to the gates of transistors Q31 to Q34 provided in the primary bridge circuit 212P. Each of the optical transmission units 152-i in this embodiment has the same configuration as the optical transmission unit 152 in the first embodiment and performs the same functions, so a detailed explanation is omitted.

[0210] The optical transmission unit 152-i generates input signals Si1jb and Si3jb (where j is a natural number from 1 to 4) based on input signals Si1ja and Si3ja input from the control device 16 and outputs them to the gate drive unit 12P. Specifically, the optical transmission unit 152-1 (i=1) generates input signal Si11b based on input signal Si11a (j=1) input from the control device 16 and outputs it to the gate drive unit 12P. The optical transmission unit 152-2 (i=2) generates input signal Si12b (j=2) based on input signal Si12a (j=2) input from the control device 16 and outputs it to the gate drive unit 12P. The optical transmission unit 152-3 (i=3) generates input signal Si13b (j=3) based on input signal Si13a (j=3) input from the control device 16 and outputs it to the gate drive unit 12P. The optical transmission unit 152-4 (i=4) generates an input signal Si14b (j=4) based on the input signal Si14a (j=4) input from the control device 16 and outputs it to the gate drive unit 12P.

[0211] Furthermore, the optical transmission unit 152-5 (i=5) generates an input signal Si31b based on the input signal Si31a (j=1) input from the control device 16 and outputs it to the gate drive unit 12P. The optical transmission unit 152-6 (i=6) generates an input signal Si32b (j=2) based on the input signal Si32a (j=2) input from the control device 16 and outputs it to the gate drive unit 12P. The optical transmission unit 152-7 (i=7) generates an input signal Si33b (j=3) based on the input signal Si33a (j=3) input from the control device 16 and outputs it to the gate drive unit 12P. The optical transmission unit 152-8 (i=8) generates an input signal Si34b (j=4) based on the input signal Si34a (j=3) input from the control device 16 and outputs it to the gate drive unit 12P.

[0212] In this embodiment, the isolated signal transmission unit 15 is configured to output a signal with the same voltage waveform as the input signal, but it may also be configured to output a signal with a voltage waveform of opposite polarity to the input signal.

[0213] As shown in Figure 6, the power conversion system 1D includes a control device (an example of a first control unit) 16 that controls primary bridge circuits 112P, 212P (an example of multiple primary bridge circuits) and secondary bridge circuits 112S, 212S (an example of multiple bridge circuits). The control device 16 uses a signal based on a pulse signal output from the isolation signal transmission unit 15 to control the bridge circuits connected to capacitors whose DC voltage is detected by one of the detection units, either the primary DC voltage detection unit 13P or the secondary DC voltage detection unit 13S. In other words, in this embodiment, the control device 16 uses a pulse signal Spls2 based on a pulse signal Spls1 output from the isolation signal transmission unit 15 to control primary bridge circuits 112P, 212P connected to primary capacitors 113P, 213P, whose DC voltages V113p, V213p are detected by the primary DC voltage detection unit 13P.

[0214] The control device 16 generates input signals Si1ja and Si3ja with duty cycles corresponding to the duty cycle of the pulse signal Spls2 input from the isolated signal transmission unit 15 (i.e., the duty cycle of the pulse signal Spls1).

[0215] If the DC voltage V113p generated at the primary capacitor 113P is higher than the DC voltage V213p generated at the primary capacitor 213P, it is necessary to decrease the DC voltage V113p and increase the DC voltage V213p. To do this, it is necessary to lengthen the conduction period (on state) of transistors Q11 to Q14 provided in the primary bridge circuit 112P, and shorten the conduction period (on state) of transistors Q31 to Q34 provided in the primary bridge circuit 212P. In order to operate transistors Q11 to Q14 and Q31 to Q34 in this way, the control device 16 generates, for example, an input signal Si1ja with a higher duty cycle than the current one and an input signal Si3ja with a lower duty cycle than the current one, when the duty cycle of pulse signal Spls2 (i.e., the duty cycle of pulse signal Spls1) is greater than 50%.

[0216] On the other hand, if the DC voltage V113p generated at the primary capacitor 113P is lower than the DC voltage V213p generated at the primary capacitor 213P, it is necessary to increase the DC voltage V113p and decrease the DC voltage V213p. To do this, it is necessary to shorten the period during which transistors Q11 to Q14 are conducted (on) and lengthen the period during which transistors Q31 to Q34 are conducted (on)

[0217] Furthermore, if the DC voltage V113p generated at the primary capacitor 113P and the DC voltage V213p generated at the primary capacitor 213P are the same or within a predetermined range of the same value, it is necessary to maintain the DC voltages V113p and V213p at their current voltage values. To achieve this, it is necessary to maintain the conduction state (on state) of transistors Q11~Q14 and transistors Q31~Q34 for the current period. In order to operate transistors Q11~Q14 and Q31~Q34 in this manner, the control device 16 generates input signals Si1ja and Si3ja with the same duty cycle as the current state, for example, when the duty cycle of pulse signal Spls2 (i.e., the duty cycle of pulse signal Spls1) is 50%.

[0218] The gate drive unit 12P generates gate pulse signals Sg11 to Sg14 with the same duty cycle as the input signal Si1jb (j=1,2,3,4) input from the isolated signal transmission unit 15, and outputs the generated gate pulse signals Sg11 to Sg14 to the gates of transistors Q11 to Q14.

[0219] Furthermore, the gate drive unit 12P generates gate pulse signals Sg31~Sg34 with the same duty cycle as the input signal Si3jb (j=1,2,3,4) input from the isolated signal transmission unit 15, and outputs the generated gate pulse signals Sg31~Sg34 to the gates of transistors Q31~Q34.

[0220] Therefore, when the DC voltages V113p and V213p are different voltage values, the gate drive unit 12P can drive transistors Q11-Q14 and Q31-Q34 in such a way that the difference between these voltage values ​​is minimized. Also, when the DC voltages V113p and V213p are the same voltage value, the gate drive unit 12P can drive transistors Q11-Q14 and Q31-Q34 in such a way that the current voltage values ​​are maintained. Thus, the gate drive unit 12P in this embodiment, like the gate drive unit 12P in the first embodiment described above, can change the voltage values ​​of the DC voltages V113p and V213p in a direction that brings them closer to the design value, or it can maintain the voltage values ​​of the DC voltages V113p and V213p at the design value.

[0221] The control device 16 controls the secondary bridge circuit 112S connected to the secondary capacitor 113S and the secondary bridge circuit 212S connected to the secondary capacitor 213S using the detection signal output from the secondary DC voltage detection unit 13S. If the voltage level of the detection signal input from the detection unit 131S provided in the secondary DC voltage detection unit 13S is higher than, for example, a preset comparison voltage level, the control device 16 outputs an input signal Si2ja (where j is a natural number from 1 to 4) with a smaller duty cycle than the current one to the gate drive unit 12S. The comparison voltage level set in the control device 16 is, for example, set to half the design value of the DC voltage supplied to the secondary device 2S. That is, the comparison voltage level is set to half the design value of the DC voltage applied between the secondary positive electrode line P2 and the secondary negative electrode line N2 when the isolated DC / DC converters 11 and 21 are operating.

[0222] On the other hand, if the voltage level of the detection signal input from the detection unit 131S is lower than, for example, the comparison voltage level, the control device 16 outputs an input signal Si2ja to the gate drive unit 12S with a duty cycle that is, for example, larger than the current one. Furthermore, if the voltage level of the detection signal input from the detection unit 131S is the same as, for example, the comparison voltage level or within a predetermined range relative to it, the control device 16 outputs an input signal Si2ja to the gate drive unit 12S with the same duty cycle as the current one.

[0223] If the voltage level of the detection signal input from the detection unit 132S provided in the secondary DC voltage detection unit 13S is higher than, for example, the comparison voltage level, the control device 16 outputs an input signal Si4ja (where j is a natural number from 1 to 4) with a smaller duty cycle than the current one to the gate drive unit 12S.

[0224] On the other hand, if the voltage level of the detection signal input from the detection unit 132S is lower than, for example, the comparison voltage level, the control device 16 outputs an input signal Si4ja to the gate drive unit 12S with a duty cycle that is, for example, larger than the current one. Furthermore, if the voltage level of the detection signal input from the detection unit 132S is the same as, for example, the comparison voltage level or within a predetermined range relative to it, the control device 16 outputs an input signal Si4ja to the gate drive unit 12S with the same duty cycle as the current one.

[0225] The gate drive unit 12S generates a gate pulse signal Sg21 with the same duty cycle as the input signal Si21a (j=1) input from the control device 16, and outputs the generated gate pulse signal Sg21 to the gate of transistor Q21. The gate drive unit 12S generates a gate pulse signal Sg22 with the same duty cycle as the input signal Si22a (j=2) input from the control device 16, and outputs the generated gate pulse signal Sg22 to the gate of transistor Q22. The gate drive unit 12S generates a gate pulse signal Sg23 with the same duty cycle as the input signal Si23a (j=3) input from the control device 16, and outputs the generated gate pulse signal Sg23 to the gate of transistor Q23. The gate drive unit 12S generates a gate pulse signal Sg24 with the same duty cycle as the input signal Si24a (j=4) input from the control device 16, and outputs the generated gate pulse signal Sg24 to the gate of transistor Q24.

[0226] Furthermore, the gate drive unit 12S generates a gate pulse signal Sg41 with the same duty cycle as the input signal Si41a (j=1) input from the control device 16, and outputs the generated gate pulse signal Sg41 to the gate of transistor Q41. The gate drive unit 12S generates a gate pulse signal Sg42 with the same duty cycle as the input signal Si42a (j=2) input from the control device 16, and outputs the generated gate pulse signal Sg42 to the gate of transistor Q42. The gate drive unit 12S generates a gate pulse signal Sg43 with the same duty cycle as the input signal Si43a (j=3) input from the control device 16, and outputs the generated gate pulse signal Sg43 to the gate of transistor Q43. The gate drive unit 12S generates a gate pulse signal Sg44 with the same duty cycle as the input signal Si44a (j=4) input from the control device 16, and outputs the generated gate pulse signal Sg44 to the gate of transistor Q44.

[0227] The input signals Si2ja and Si4ja are signals with a duty cycle that reflects the voltage values ​​of the DC voltages V113s and V213s. Therefore, when the DC voltages V113s and V213s are different voltage values, the gate drive unit 12S can drive transistors Q21-Q24 and Q41-Q44 to minimize the difference between these voltage values. Also, when the DC voltages V113s and V213s are the same voltage value, the gate drive unit 12S can drive transistors Q21-Q24 and Q41-Q44 to maintain the current voltage values. Thus, the gate drive unit 12S can change the voltage values ​​of the DC voltages V113s and V213s to approach the design values, or maintain the voltage values ​​of the DC voltages V113s and V213s at the design values.

[0228] The power conversion system 1D includes a pulse signal generation unit 14, similar to the power conversion system 1A according to the first embodiment. As a result, the power conversion system 1D can achieve the same effects as the power conversion system 1A according to the first embodiment.

[0229] (Operation of the power conversion system) The operation of the power conversion system 1D according to this embodiment will be explained using Figure 8 with reference to Figures 6 and 7. Before explaining the balance control of the DC voltages V113p and V213p generated in the primary capacitors 113P and 213P, the basic operation of the power conversion system 1D will be explained using Figures 6 and 7.

[0230] The power conversion system 1D operates by repeating eight operating modes. In the first operating mode, the control device 16 provided in the power conversion system 1D controls the gate drive unit 12P to operate transistors Q11 and Q14 in the primary bridge circuit 112P in a conductive state (on state) and transistors Q12 and Q13 in a non-conductive state (off state). Also in the first operating mode, the control device 16 controls the gate drive unit 12S to operate transistors Q21 and Q24 in the secondary bridge circuit 112S in a conductive state and transistors Q22 and Q23 in a non-conductive state. Furthermore, the control device 16 controls the gate drive unit 12P to operate transistors Q31 to Q34 in the primary bridge circuit 212P and transistors Q41 to Q44 in the secondary bridge circuit 212S in a non-conductive state.

[0231] Therefore, primary current flows through the first path ("Primary side device 2P → Transistor Q11 → Connection a1 → Inductor 115P → Primary winding of isolation transformer 111 → Connection a2 → Transistor Q14 → Primary neutral point NP → Primary side capacitor 213P → Primary side device 2P" in the primary side PS of the isolated DC / DC converter 11. As a result, the primary side capacitor 114P is charged. Simultaneously with the flow of current through the first path, primary current flows through the second path ("Primary side capacitor 113P → Transistor Q11 → Connection a1 → Inductor 115P → Primary winding of isolation transformer 111 → Connection a2 → Inductor 115P → Primary winding of isolation transformer 111 → Connection a2 → Transistor Q14 → Primary neutral point NP → Primary side capacitor 113P"). As a result, the primary side capacitor 113P is discharged. As current flows through the first and second paths, the primary current flowing through the primary winding of the isolation transformer 111 increases in the positive direction.

[0232] In the first operating mode, the DC voltage V213p generated across the primary capacitor 213P rises to a voltage value equal to half the voltage supplied from the primary device 2P, according to the design. Therefore, in the first operating mode, the DC voltage V113p generated across the primary capacitor 113P is, according to the design, half the voltage supplied from the primary device 2P (the voltage obtained by subtracting the DC voltage V213p from the voltage supplied from the primary device 2P). In the first operating mode, a voltage with the same polarity and absolute value as the DC voltage V113p generated across the primary capacitor 113P is applied across both ends of the primary winding of the isolation transformer 111, according to the design.

[0233] As a primary current increases in the positive direction flows through the primary winding of the isolation transformer 111, an induced electromotive force is generated in the primary winding. Furthermore, due to mutual induction in the isolation transformer 111, a mutual induced electromotive force is generated in the secondary winding of the isolation transformer 111. The isolation transformer 111 is configured such that the applied voltage to the primary winding and the applied voltage to the secondary winding have the same polarity. Therefore, in the first operating mode, the applied voltage to the secondary winding of the isolation transformer 111 begins to increase in the positive direction. As a result, a secondary current flows through the secondary side SS of the isolated DC / DC converter 11 via the path (third path) "secondary winding of isolation transformer 111 → inductor 115S → connection b1 → transistor Q21 → secondary side capacitor 113S → secondary side neutral point NS → transistor Q24 → connection b2 → secondary winding of isolation transformer 111", and the secondary side capacitor 113S is charged. Simultaneously with the flow of current through the third path, secondary current flows through the path (fourth path) of "secondary capacitor 213S → secondary neutral point NS → transistor Q24 → connection b2 → secondary winding of isolation transformer 111 → inductor 115S → transistor Q21 → secondary capacitor 113S". As a result, the secondary capacitor 213S is discharged. Thus, in the first operating mode, current flows through the third and fourth paths in the secondary SS of the isolated DC / DC converter 11.

[0234] In the first operating mode, a voltage is generated at both ends of the secondary winding of the isolation transformer 111, calculated by design, by multiplying the ratio of the number of turns of the secondary winding to the number of turns of the primary winding of the isolation transformer 111 by the voltage applied at both ends of the primary winding. The DC voltage V113s generated at the secondary capacitor 113S based on this voltage becomes the output voltage of the isolated DC / DC converter 11 in the first operating mode. In the first operating mode, the voltage value of the DC voltage V113s is, by design, the same as the voltage generated at both ends of the secondary winding of the isolation transformer 111. Therefore, in the first operating mode, the power conversion system 1D supplies a DC voltage to the secondary device 2S that is the sum of the DC voltage V113s in the first operating mode and the DC voltage V213s in the eighth operating mode executed before the first operating mode. Details of the eighth operating mode will be described later.

[0235] In the second operating mode following the first operating mode, the control device 16 provided in the power conversion system 1D controls the gate drive units 12P and 12S to operate all transistors Q11-Q14, Q21-Q24, Q31-Q34, and Q41-Q44 in a non-conductive state (off state).

[0236] In the second operating mode, transistors Q11 to Q14 are turned off, so the energy stored in the secondary winding of the isolation transformer 111 and inductor 115S is commutated to the secondary side SS. As a result, in the second operating mode, secondary current flows through the path (fifth path) "secondary winding of isolation transformer 111 → inductor 115S → connection b1 → freewheeling diode D21 → secondary side capacitor 113S → secondary side neutral point NS → freewheeling diode D24 → secondary winding of isolation transformer 111". This charges the secondary side capacitor 113S. Simultaneously with the flow of current through the fifth path, secondary current flows through the path (sixth path) "secondary side capacitor 213S → secondary side neutral point NS → freewheeling diode D24 → secondary winding of isolation transformer 111 → inductor 115S → connection b1 → freewheeling diode D21 → secondary side capacitor 113S". This discharges the secondary side capacitor 213S.

[0237] Thus, in the second operating mode, the secondary current flows, causing the secondary capacitors 113S and 213S to be charged and discharged. As a result, although the potential of the secondary neutral point NS fluctuates, the DC voltage supplied by the power conversion system 1D to the secondary device 2S in the second operating mode remains the same as at the end of the first operating mode, according to the design.

[0238] In the third operating mode following the second operating mode, the control device 16 provided in the power conversion system 1D controls the gate drive unit 12P to operate transistors Q11 and Q14 in the primary bridge circuit 112P in a non-conductive state (off state), transistors Q12 and Q13 in a conductive state (on state), and transistors Q31 to Q34 in the primary bridge circuit 212P in a non-conductive state (off state). In the third operating mode, the control device 16 also controls the gate drive unit 12S to operate transistors Q21 and Q24 in the secondary bridge circuit 112S in a non-conductive state, transistors Q22 and Q23 in a conductive state, and transistors Q41 to Q44 in the secondary bridge circuit 212S in a non-conductive state.

[0239] Therefore, primary current flows through the primary side PS of the isolated DC / DC converter 11 via the path (7th path) "primary side device 2P → transistor Q13 → connection a2 → primary winding of isolation transformer 111 → inductor 115P → connection a1 → transistor Q12 → primary side neutral point NP → primary side capacitor 213P → primary side device 2P". As a result, the primary side capacitor 213P is charged. Simultaneously with the flow of current through the 7th path, primary current also flows through the path (8th path) "primary side capacitor 113P → transistor Q13 → connection a2 → primary winding of isolation transformer 111 → inductor 115P → connection a1 → transistor Q12 → primary side capacitor 213P". As a result, the primary side capacitor 113P is discharged. Thus, in the third operating mode, the flow of current through the 7th and 8th paths causes the primary side current flowing through the primary winding of the isolation transformer 111 to increase in the negative direction.

[0240] In the third operating mode, the DC voltage V213p generated across the primary capacitor 213P rises to a voltage value equal to half the voltage supplied from the primary device 2P, according to the design. Therefore, in the third operating mode, the DC voltage V113p generated across the primary capacitor 113P is, according to the design, half the voltage supplied from the primary device 2P (the voltage obtained by subtracting the DC voltage V213p from that voltage). In the third operating mode, a voltage with the same absolute value as the DC voltage V113p generated across the primary capacitor 113P is applied across the primary winding of the isolation transformer 111, according to the design.

[0241] As a primary current increasing in the negative direction flows through the primary winding of the isolation transformer 111, an induced electromotive force is generated in the primary winding in the opposite direction to that of the first operating mode. Furthermore, due to mutual induction in the isolation transformer 111, a mutual induced electromotive force is generated in the secondary winding of the isolation transformer 111 in the opposite direction to that of the first operating mode. As a result, a secondary current flows through the secondary side SS of the isolated DC / DC converter 11 via the path (9th path) of "secondary winding of isolation transformer 111 → connection b2 → transistor Q23 → secondary side capacitor 113S → secondary side neutral point NS → transistor Q22 → connection b1 → inductor 115S → secondary winding of isolation transformer 111", and the secondary side capacitor 113S is charged. Simultaneously with the flow of current through the ninth path, secondary current flows through the path (tenth path) "secondary capacitor 213S → secondary neutral point NS → transistor Q22 → connection b1 → inductor 115S → secondary winding of isolation transformer 111 → connection b2 → transistor Q23 → secondary capacitor 113S". As a result, secondary capacitor 213S is discharged. Thus, in the third operating mode, secondary current flows through the ninth and tenth paths in the secondary SS of the isolated DC / DC converter 11.

[0242] In the third operating mode, a voltage is generated at both ends of the secondary winding of the isolation transformer 111, similar to the first operating mode, by design, which is the ratio of the number of turns of the secondary winding to the number of turns of the primary winding of the isolation transformer 111, multiplied by the voltage applied at both ends of the primary winding. Similar to the first operating mode, the output voltage of the isolated DC / DC converter 11 in the third operating mode is the DC voltage V113s generated at the secondary capacitor 113S. In the third operating mode, the secondary current flows, causing the secondary capacitors 113S and 213S to be charged and discharged. As a result, the potential of the secondary neutral point NS fluctuates, but the voltage value of the DC voltage supplied by the power conversion system 1D to the secondary device 2S in the third operating mode is, by design, the same as at the end of the second operating mode.

[0243] In the fourth operating mode following the third operating mode, the control device 16 provided in the power conversion system 1D controls the gate drive units 12P and 12S to operate all transistors Q11-Q14, Q21-Q24, Q31-Q34, and Q41-Q44 in a non-conductive (off) state.

[0244] In the fourth operating mode, transistors Q11 to Q14 are turned off, so the energy stored in the secondary winding of the isolation transformer 111 and inductor 115S is commutated to the secondary side SS. As a result, in the fourth operating mode, secondary current flows through the path (ninth path) "secondary winding of isolation transformer 111 → connection b2 → freewheeling diode D23 → secondary side capacitor 113S → freewheeling diode D22 → connection b1 → inductor 115S → secondary winding of isolation transformer 111". This charges the secondary side capacitor 113S. Simultaneously with the flow of current through the eleventh path, secondary current flows through the path (twelfth path) "secondary side capacitor 213S → secondary side neutral point NS → freewheeling diode D22 → connection b1 → secondary winding of isolation transformer 111 → inductor 115S → connection b2 → freewheeling diode D23 → secondary side capacitor 113S". This discharges the secondary side capacitor 213S.

[0245] Thus, in the fourth operating mode, the secondary current flows, causing the secondary capacitors 113S and 213S to be charged and discharged. As a result, although the potential of the secondary neutral point NS fluctuates, the DC voltage supplied by the power conversion system 1D to the secondary device 2S in the fourth operating mode is, by design, the same as at the end of the third operating mode.

[0246] In the fifth operating mode following the fourth operating mode, the control device 16 provided in the power conversion system 1D controls the gate drive unit 12P to operate transistors Q11 to Q14 in the primary bridge circuit 112P in a non-conductive state (off state), transistors Q31 and Q34 in the primary bridge circuit 212P in a conductive state (off state), and transistors Q32 and Q33 in a non-conductive state. Furthermore, in the first operating mode, the control device 16 controls the gate drive unit 12S to operate transistors Q21 to Q24 in the secondary bridge circuit 112S in a non-conductive state, transistors Q41 and Q44 in the secondary bridge circuit 212S in a conductive state, and transistors Q42 and Q43 in a non-conductive state.

[0247] Therefore, primary current flows through the primary side PS of the isolated DC / DC converter 11 via the path (13th path) "primary side device 2P → primary side capacitor 113P → primary side neutral point NP → transistor Q31 → connection c1 → inductor 215P → primary winding of isolation transformer 211 → connection c2 → transistor Q34 → primary side device 2P". As a result, the primary side capacitor 113P is charged. Simultaneously with the flow of current through the 13th path, primary current also flows through the path (14th path) "primary side capacitor 213P → primary side neutral point NP → transistor Q31 → connection c1 → inductor 215P → primary winding of isolation transformer 211 → connection c2 → transistor Q34 → primary side device 2P". As a result, the primary side capacitor 213P is discharged. Due to the flow of current through the 13th and 14th paths, the primary side current flowing through the primary winding of the isolation transformer 111 becomes a current that increases in the positive direction.

[0248] The operation of the primary bridge circuit 212P and primary capacitors 113P and 213P in the fifth operating mode is the same as the operation of the primary bridge circuit 112P and primary capacitors 113P and 213P in the first operating mode when the components provided on the primary PS are read from left to right as shown by the arrows below, so a detailed explanation is omitted. Transistor Q11 → Transistor Q31 Transistor Q12 → Transistor Q32 Transistor Q13 → Transistor Q33 Transistor Q14 → Transistor Q34 Freewheel diode D11 → Freewheel diode D31 Freewheel diode D12 → Freewheel diode D32 Freewheel diode D13 → Freewheel diode D33 Freewheel diode D14 → Freewheel diode D34 Isolation transformer 111 → Isolation transformer 211 Inductor 115P → Inductor 215P Connection part a1 → Connection part c1 Connection point a2 → Connection point c2 Primary side capacitor 113P → Primary side capacitor 213P Primary side capacitor 213P → Primary side capacitor 113P

[0249] In the fifth operating mode, the DC voltage V113p generated across the primary capacitor 113P rises to a voltage value equal to half the voltage supplied from the primary device 2P, according to the design. Therefore, in the fifth operating mode, the DC voltage V213p generated across the primary capacitor 213P is, according to the design, half the voltage supplied from the primary device 2P (the voltage obtained by subtracting the DC voltage V113p from the voltage supplied from the primary device 2P). In the fifth operating mode, a voltage with the same absolute value as the DC voltage V213p generated across the primary capacitor 213P is applied across both ends of the primary winding of the isolation transformer 211, according to the design.

[0250] The power conversion system 1D operates in the fifth operating mode in much the same way as in the first operating mode, except that, unlike the first operating mode, there is no path for the discharge of the secondary capacitor 113S corresponding to the fourth path. That is, the operation of the secondary bridge circuit 212S and secondary capacitors 113S, 213S in the fifth operating mode is almost the same as the operation of the secondary bridge circuit 212S and secondary capacitors 113S, 213S in the first operating mode when the components provided on the secondary side SS are read from left to right as shown by the arrows below, so a detailed explanation is omitted. Transistor Q21 → Transistor Q41 Transistor Q22 → Transistor Q42 Transistor Q23 → Transistor Q43 Transistor Q24 → Transistor Q44 Freewheel diode D21 → Freewheel diode D41 Freewheel diode D22 → Freewheel diode D42 Freewheel diode D23 → Freewheel diode D43 Freewheel diode D24 → Freewheel diode D44 Isolation transformer 111 → Isolation transformer 211 Inductor 115S → Inductor 215S Connection point b1 → Connection point d1 Connection point b2 → Connection point d2 Secondary capacitor 113S → Secondary capacitor 213S Secondary capacitor 213S → Secondary capacitor 113S

[0251] Therefore, in the fifth operating mode, the power conversion system 1D supplies the secondary device 2S with a DC voltage obtained by adding the DC voltage V213s based on the charging of the secondary capacitor 213S in the fifth operating mode and the DC voltage V113s from the fourth operating mode performed before the fifth operating mode.

[0252] In the sixth operating mode following the fifth operating mode, the control device 16 provided in the power conversion system 1D controls the gate drive units 12P and 12S to operate all transistors Q11-Q14, Q21-Q24, Q31-Q34, and Q41-Q44 in a non-conductive (off) state.

[0253] In the sixth operating mode, transistors Q31 to Q34 are turned off, so the energy stored in the secondary winding of the isolation transformer 211 and inductor 215S is commutated to the secondary side SS. As a result, in the sixth operating mode, secondary current flows through the path "secondary winding of isolation transformer 211 → inductor 215S → connection d1 → freewheeling diode D41 → secondary side neutral point NS → secondary side capacitor 213S → freewheeling diode D44 → connection d2 → secondary winding of isolation transformer 211". This charges the secondary side capacitor 113S. Also, unlike the second operating mode, in the sixth operating mode, there is no path to discharge the secondary side capacitor 113S.

[0254] Thus, in the sixth operating mode, the secondary capacitor 213S is charged by the flow of secondary current. As a result, although the potential of the secondary neutral point NS fluctuates, the DC voltage supplied by the power conversion system 1D to the secondary device 2S in the sixth operating mode is, by design, the same as at the end of the fifth operating mode.

[0255] In the seventh operating mode following the sixth operating mode, the control device 16 provided in the power conversion system 1D controls the gate drive unit 12P to operate transistors Q11 to Q14 in the primary bridge circuit 112P in a non-conductive state (off state), transistors Q32 and Q33 in a conductive state (on state), and transistors Q31 and Q34 in the primary bridge circuit 212P in a non-conductive state. In the seventh operating mode, the control device 16 also controls the gate drive unit 12S to operate transistors Q21 and Q24 in the secondary bridge circuit 112S in a non-conductive state, transistors Q22 and Q23 in a conductive state, and transistors Q41 to Q44 in the secondary bridge circuit 212S in a non-conductive state.

[0256] Therefore, primary current flows through the primary side PS of the isolated DC / DC converter 11 via the following path (path 15): "Primary side device 2P → Primary side capacitor 113P → Primary side neutral point NP → Transistor Q33 → Connection c2 → Primary winding of isolation transformer 211 → Inductor 215P → Connection c1 → Transistor Q32 → Primary side device 2P". As a result, the primary side capacitor 113P is charged.

[0257] The operation of the primary bridge circuit 212P and primary capacitors 113P and 213P in the seventh operating mode is the same as the operation of the primary bridge circuit 112P and primary capacitors 113P and 213P in the third operating mode when the components provided on the primary PS are reinterpreted as described above, similar to the fifth operating mode; therefore, a detailed explanation is omitted.

[0258] In the seventh operation mode, the DC voltage V113p generated in the primary capacitor 113P rises until it reaches the same voltage value as half of the voltage supplied from the primary device 2P by design. Therefore, the DC voltage V213p generated in the primary capacitor 213P in the seventh operation mode becomes half of the voltage supplied from the primary device 2P (the voltage obtained by subtracting the DC voltage V113p from the voltage supplied from the primary device 2P) by design. In the seventh operation mode, voltages with the same absolute value as the DC voltage V213p generated in the primary capacitor 213P are applied to both ends of the primary winding of the isolation transformer 211 by design.

[0259] The power conversion system 1D operates almost the same as in the third operation mode in the seventh operation mode, except that, unlike the third operation mode, there is no path for discharging the secondary capacitor 113S corresponding to the tenth path. That is, the operations of the secondary bridge circuit 212S and the secondary capacitors 113S, 213S in the seventh operation mode are almost the same as the operations of the secondary bridge circuit 212S and the secondary capacitors 113S, 213S in the third operation mode when the components provided in the secondary SS are read as described above in the same manner as in the fifth operation mode. Therefore, detailed description is omitted.

[0260] Therefore, in the seventh operation mode, the power conversion system 1D supplies the secondary device 2S with a DC voltage obtained by adding the DC voltage V213s based on the charging of the secondary capacitor 213S in the seventh operation mode and the DC voltage V113s in the sixth operation mode executed before the seventh operation mode.

[0261] In the eighth operation mode following the seventh operation mode, the control device 16 provided in the power conversion system 1D controls the gate drive units 12P, 12S to operate all of the transistors Q11~Q14, Q21~Q24, Q31~Q34, Q41~Q44 in the non-conducting state (off state).

[0262] In the seventh operation mode, transistors Q31 to Q34 are turned off. Therefore, the energy stored in the secondary winding of isolation transformer 211 and inductor 215S both commutate to the secondary side SS. As a result, in the seventh operation mode, the secondary current flows along the path of "secondary winding of isolation transformer 111 → connection part d2 → freewheeling diode D43 → secondary side neutral point NS → secondary side capacitor 213S → freewheeling diode D42 → connection part d1 → inductor 215S → secondary winding of isolation transformer 211". Thereby, the secondary side capacitor 213S is charged. At the same time as the current flows through the eleventh path, the secondary current also flows along the path of "secondary side capacitor 213S → secondary side neutral point NS → freewheeling diode D22 → connection part b1 → secondary winding of isolation transformer 111 → inductor 115S → connection part b2 → freewheeling diode D23 → secondary side capacitor 113S" (the twelfth path). Thereby, the secondary side capacitor 213S is discharged. Also, in the eighth operation mode, unlike the fourth operation mode, there is no path for discharging the secondary side capacitor 113S.

[0263] Thus, when the secondary current flows in the eighth operation mode, the secondary side capacitor 213S is charged. As a result, although the potential of the secondary side neutral point NS fluctuates, the voltage value of the DC voltage supplied from the power conversion system 1D to the secondary side device 2S in the eighth operation mode is designed to be the same as that at the end of the seventh operation mode.

[0264] When the eighth operation mode ends, the power conversion system 1D starts the first operation mode. Thus, the power conversion system 1D operates while repeating the first operation mode to the eighth operation mode.

[0265] In the first and third operating modes, the DC voltage V213p generated at the primary capacitor 213P is the same voltage value as the DC voltage V113p generated at the primary capacitor 113P in the fifth and seventh operating modes. Therefore, the voltage generated across the secondary winding of the isolation transformer 111 in the first and third operating modes is the same voltage value as the voltage generated across the secondary winding of the isolation transformer 211 in the fifth and seventh operating modes, and the stored energy commutated to the secondary SS is the same in the second and fourth operating modes and in the sixth and eighth operating modes. As a result, the power conversion system 1D can output a nearly identical output voltage (i.e., the DC voltage generated between the secondary positive electrode line P2 and the secondary negative electrode line N2) to the secondary device 2S in the first through eighth operating modes.

[0266] However, the amount of current flowing through the primary capacitor 213P in the first and third operating modes may differ from the amount of current flowing through the primary capacitor 113P in the fifth and seventh operating modes. In this case, the voltage value generated across the secondary winding of the isolation transformer 111 in the first and third operating modes may differ from the voltage value generated across the secondary winding of the isolation transformer 211 in the fifth and seventh operating modes, or the stored energy commutated to the secondary SS may differ between the second and fourth operating modes and the sixth and eighth operating modes. As a result, the power conversion system 1D will no longer be able to output an output voltage to the secondary device 2S that can be considered to have the same voltage value in the first through eighth operating modes.

[0267] Therefore, the power conversion system 1D controls the primary bridge circuits 112P and 212P based on the ratio of the DC voltage V113p generated at the primary capacitor 113P and the DC voltage V213p generated at the primary capacitor 213P, so that the voltage value of the DC voltage V213p generated at the primary capacitor 213P in the first and third operating modes is the same as the voltage value of the DC voltage V113p generated at the primary capacitor 113P in the fifth and seventh operating modes. As a result, the power conversion system 1D makes the voltage generated across the secondary winding of the isolation transformer 111 in the first and third operating modes the same as the voltage generated across the secondary winding of the isolation transformer 211 in the fifth and seventh operating modes, and makes the stored energy commutated to the secondary SS the same in the second and fourth operating modes and the sixth and eighth operating modes.

[0268] Therefore, the power conversion system 1D, similar to the power conversion system 1A according to the first embodiment, controls the primary bridge circuits 112P and 212P based on the ratio of the DC voltage V113p generated at the primary capacitor 113P and the DC voltage V114p generated at the primary capacitor 114P, so that the voltage value of the DC voltage V213p generated at the primary capacitor 213P in the first and third operating modes is the same as the voltage value of the DC voltage V113p generated at the primary capacitor 113P in the fifth and seventh operating modes. As a result, the power conversion system 1D makes the voltage value of the voltage generated at both ends of the secondary winding of the isolation transformer 111 in the first and third operating modes the same as the voltage value of the voltage generated at both ends of the secondary winding of the isolation transformer 211 in the fifth and seventh operating modes, and makes the stored energy commutated to the secondary SS the same in the second and fourth operating modes and the sixth and eighth operating modes.

[0269] Figure 8 is a timing chart showing an example of the operating waveform of the power conversion system 1D. Figure 8 illustrates the operating waveform of the power conversion system 1D related to voltage balancing control that makes the DC voltages V113p and V213p generated at the primary side capacitors 113P and 213P the same. The power conversion system 1D is configured to detect the DC voltages V113p and V213p generated at the primary side capacitors 113P and 213P each time it performs a series of operations from the first to the eighth operating mode multiple times. However, the power conversion system 1D may also be configured to detect the DC voltages V113p and V213p generated at the primary side capacitors 113P and 213P each time it performs a series of operations from the first to the eighth operating mode.

[0270] The first row of Figure 8 shows the voltage waveforms of the DC voltages V113p and V213p generated at the primary side capacitors 113P and 213P. The second row of Figure 8 shows the change over time of the capacitor DC voltage ratio Vr calculated by the pulse signal generation unit 14. The capacitor DC voltage ratio Vr is the ratio of the detected value VP1 of the DC voltage V113p to the detected value VP2 of the DC voltage V213p. The third row of Figure 8 shows the voltage waveform of the pulse signal Spls1 generated and output by the pulse signal generation unit 14 based on the capacitor DC voltage ratio Vr. In Figure 8, the vertical axis of the first row represents voltage, the vertical axis of the second row represents dimensionless quantities, and the vertical axis of the third row represents voltage. In Figure 8, time is shown from left to right.

[0271] The voltage balance control of the DC voltages V113p and V213p generated in the primary side capacitors 113P and 213P, performed by the power conversion system 1D, is the same as the voltage balance control performed by the power conversion system 1A according to the first embodiment, except that the voltage detected by the primary side DC voltage detection unit 13P is different. Therefore, a detailed explanation of the operation of the power conversion system 1D will be omitted below, and the differences from the power conversion system 1A will be explained in detail.

[0272] As shown in Figure 8, in this embodiment, the relative magnitudes of the DC voltage V113p of the primary capacitor 113P (see Figure 6), the DC voltage V213p of the primary capacitor 213P (see Figure 6), and the voltage value of half the input voltage Edc input from the primary device 2P (see Figure 6) during the period prior to time t0 are the same as the relative magnitudes of the voltage values ​​shown in Figure 2 when the DC voltage V114p of the primary capacitor 114P is replaced with the DC voltage V213p of the primary capacitor 213P.

[0273] Therefore, as shown in Figure 8, the capacitor DC voltage ratio Vr obtained from the DC voltages V113p and V213p detected by the primary DC voltage detection unit 13P (see Figure 6) at time t0 is greater than "1". Therefore, the duty cycle of the pulse signal Spls1 output from the pulse signal generation unit 14 (see Figure 6) to the isolated signal transmission unit 15 (see Figure 6) is greater than 50% during the period from time t0 to time t1.

[0274] Therefore, the control device 16 (see Figure 6) controls the gate drive unit 12P to operate the primary bridge circuit 112P so that the DC voltage V113p becomes lower than the current value and the DC voltage V213p becomes higher than the current value. In other words, the control device 16 generates an input signal Si1ja to make the conduction state (on state) of the gate pulse signals Sg11, Sg14 in the first operating mode and the gate pulse signals Sg12, Sg13 in the third operating mode longer than the current value. The control device 16 also generates an input signal Si3ja to make the conduction state (on state) of the gate pulse signals Sg31, Sg34 in the fifth operating mode and the gate pulse signals Sg32, Sg33 in the seventh operating mode shorter than the current value.

[0275] As shown in Figure 8, the control device 16 outputs the generated input signals Si1ja and Si3ja to the isolated signal transmission unit 15 at a time between time t1 and time t2 (for example, time t1a). The gate drive unit 12P drives transistors Q11 to Q14 in the primary bridge circuit 112P and transistors Q31 to Q34 in the primary bridge circuit 212P based on gate pulse signals Sg11, Sg12, Sg13, Sg14 and gate pulse signals Sg31, Sg32, Sg33, Sg34, which are based on the input signals Si1ja and Si3ja output from the control device 16.

[0276] As a result, as shown in Figure 8, transistors Q11 to Q14 will have a longer conduction state (on state) at a predetermined time after time t1a. On the other hand, transistor Q12 will have a shorter conduction state (on state) at a predetermined time after time t1a. This will result in a longer primary current flowing through primary capacitor 213P and a shorter primary current flowing through primary capacitor 113P. Consequently, the DC voltage V213p generated across primary capacitor 213P will be higher than before, and the DC voltage V113p generated across primary capacitor 113P will be lower than before.

[0277] Note that the timing at which the DC voltages V113p and V213p generated in the primary capacitors 113P and 213P change actually occurs after a predetermined time has elapsed from time t1a. However, similar to the first embodiment described above, the diagram shows the DC voltages V113p and V213p changing at time t1a. Furthermore, in Figure 8, the timing at which the DC voltages V113p and V213p generated in the primary capacitors 113P and 213P change is shown at times t3a, t5a, and t7a in the same way as at time t1a.

[0278] Although a detailed explanation is omitted, the power conversion system 1D operates in the same way as at time t0 at times t2, t4, and t6. Furthermore, the power conversion system 1D operates in the same way as at time t1 at times t3, t5, and t7. In addition, the power conversion system 1D operates in the same way as at time t1a at times t3a, t5a, and t7a. As a result, as shown in Figure 8, the voltage difference between the DC voltage V113p generated at the primary capacitor 113P and the DC voltage V213p generated at the primary capacitor 213P gradually decreases.

[0279] As a result, as shown in Figure 8, after a predetermined time has elapsed from time t7a, the DC voltages V113p and V213p have the same voltage value, and at time t8, the primary DC voltage detection unit 13P detects DC voltages V113p and V213p with the same voltage value. Therefore, the pulse signal generation unit 14 calculates a capacitor DC voltage ratio Vr with a value of "1" based on the DC voltages V113p and V213p with the same detected values ​​VP1 and VP2 input from the primary DC voltage detection unit 13P. As a result, the pulse signal generation unit 14 generates a pulse signal Spls1 with a duty cycle of 50%.

[0280] Therefore, the control device 16 controls the gate drive unit 12P to output input signals Si1ja and Si3ja with the same duty cycle as the input signals Si1ja and Si3ja determined at time t7 to the isolated signal transmission unit 15, so that the DC voltages V113p and V213p generated in the primary capacitors 113P and 213P are maintained at their current voltage values. As a result, as shown in Figure 8, the DC voltages V113p and V213p generated in the primary capacitors 113P and 213P are maintained at the same voltage values ​​even after time t8.

[0281] Thus, the power conversion system 1D according to this embodiment can control the voltage balance of the DC voltages V113p and V213p generated in the primary capacitors 113P and 213P, even if the number of optical transmission units used in the isolated signal transmission unit 15 is smaller compared to conventional power conversion systems.

[0282] Furthermore, the power conversion system 1D, like the power conversion system 1A according to the first embodiment, is equipped with a secondary DC voltage detection unit 13S. Therefore, the power conversion system 1D, like the power conversion system 1A, controls the voltage balance of DC voltages V113s and V213s using the detected values ​​of DC voltages V113s and V213s generated in the secondary capacitors 113S and 213S, so that the voltage values ​​of DC voltages V113s and V213s can be controlled to be the same as the design values. Therefore, even if the absolute value deviates from the design value when the voltage balance of DC voltages V113p and V213p of the primary capacitors 113P and 213P is controlled, the power conversion system 1D can supply the design DC voltage to the secondary device 2S.

[0283] As described above, the power conversion system 1D according to the present embodiment includes an isolation transformer 111, 211, a primary side bridge circuit 112P, 212P provided on the primary side PS of the isolation transformer 111, 211 and having transistors Q11 to Q14, Q31 to Q34, and a secondary side bridge circuit 112S, 212S provided on the secondary side SS of the isolation transformer 111, 211 and having transistors Q21 to Q24, Q41 to Q44. An isolated DC / DC converter 11, 21; a control device 16 that controls the primary side bridge circuit 112P, 212P and the secondary side bridge circuit 112S, 212S; a primary side capacitor 113P, 213P connected in parallel to the primary side bridge circuit 112P, 212P; a secondary side capacitor 113S, 213S connected in parallel to the secondary side bridge circuit 112S, 212S; a primary side DC voltage detection unit 13P that individually detects DC voltages V113p, V213p generated in each of the primary side capacitors 113P, 213P; a secondary side DC voltage detection unit 13S that individually detects DC voltages V113s, V213s generated in each of the secondary side capacitors 113S, 213S; a pulse signal generation unit 14 that generates a pulse signal Spls1 with a duty ratio according to the ratio of the DC voltages V113p, V213p detected by the primary side DC voltage detection unit 13P; and an isolation signal transmission unit 15 that transmits a pulse signal Spls2 based on the pulse signal Spls1 input from the pulse signal generation unit 14 to the control device 16 in a state where the primary side PS and the secondary side SS of the isolated DC / DC converter 11, 21 are electrically isolated.

[0284] Thereby, even when the power conversion system 1D has a primary side neutral point NP (i.e., the capacitor midpoint) to which the primary side capacitor 113P and the primary side capacitor 213P are connected and has the isolation transformer 111, 211, the cost can be reduced.

[0285] 〔Third Embodiment〕 A power conversion system according to a third embodiment of the present invention will be described with reference to Figures 9 and 10. First, the schematic configuration of the power conversion system according to this embodiment will be described with reference to Figure 9. The power conversion system 1E according to this embodiment is characterized in that, in addition to the configuration of the power conversion system 1D according to the second embodiment, it is equipped with an input voltage detection unit 10, a filter unit 17, a control device 18, and an isolated signal transmission unit 19.

[0286] Figure 9 is a block diagram showing an example of the schematic configuration of the power conversion system 1E according to this embodiment. In Figure 9, for ease of understanding, the primary side device 2P and the secondary side device 2S connected to the power conversion system 1E are also shown together. Furthermore, components that perform the same operation and function as the components of the power conversion system 1D according to the second embodiment are given the same reference numerals, and detailed explanations are omitted.

[0287] As shown in Figure 9, the power conversion system 1E includes a control device 18 (an example of a second control unit) that controls a control device 16 (an example of a first control unit) while the primary side PS and secondary side SS of the isolated DC / DC converters 11 and 21 (an example of multiple DC / DC converters) are electrically isolated. The isolated DC / DC converters 11 and 21 have their input sides connected in series or parallel, and their output sides are connected in series or parallel. In this embodiment, both the input and output sides of the isolated DC / DC converters 11 and 21 are connected in parallel.

[0288] As shown in Figure 9, the power conversion system 1E includes an input voltage detection unit 10 that detects the input voltage Edc between a primary side positive electrode line P1 (an example of a positive electrode line) connected to primary side bridge circuits 112P, 212P, which are connected to primary side capacitors 113P, 213P, where DC voltages V113p, V213p are detected by a primary side DC voltage detection unit 13P (an example of one of the detection units), and a primary side negative electrode line N1 (an example of a negative electrode line) connected to primary side bridge circuits 112P, 212P, where a negative electrode potential is supplied. In other words, the power conversion system 1E includes an input voltage detection unit 10 that detects the input voltage Edc input from the primary side device 2P.

[0289] One input terminal of the input voltage detection unit 10 is connected to the primary side positive electrode line P1, and the other input terminal of the input voltage detection unit 10 is connected to the primary side negative electrode line N1. This allows the input voltage detection unit 10 to detect the input voltage Edc, which is the potential difference between the positive electrode potential supplied from the primary side device 2P to the primary side positive electrode line P1 and the negative electrode potential supplied from the primary side device 2P to the primary side negative electrode line N1. The output terminal of the input voltage detection unit 10 is connected to the control device 18. This allows the input voltage detection unit 10 to output the detected input voltage Edc to the control device 18. Specifically, the input voltage detection unit 10 can output the voltage value (i.e., the detected value) of the detected input voltage Edc to the control device 18.

[0290] As shown in Figure 9, the power conversion system 1E extracts a filter signal Sf having an amplitude corresponding to the ratio of DC voltages V113p and V213p detected by the primary DC voltage detection unit 13P, based on the duty cycle of the pulse signal Spls1 generated by the pulse signal generation unit 14, and includes a filter unit 17 provided on the output side of the isolated signal transmission unit 15. The filter unit 17 has the same configuration as the filter unit 17 in the modified example 1 of the first embodiment and performs the same function, so a description is omitted.

[0291] As shown in Figure 9, the power conversion system 1E includes an isolated signal transmission unit 19 that transmits signals while electrically isolating the control devices 16 and 18. The isolated signal transmission unit 19 includes an optical transmission unit 191 and an optical transmission unit 192. The optical transmission unit 191 transmits, for example, information (e.g., voltage value, details will be described later) about the input voltage Edc restored in the control device 18 to the control device 16. The optical transmission unit 192 transmits, for example, information (e.g., amplitude value) about the filter signal Sf input to the control device 16 to the control device 18. Although the information transmitted by each of the optical transmission units 191 and 192 is different, they have the same configuration as the optical transmission unit 151 in the first embodiment and perform the same functions, so a detailed explanation is omitted.

[0292] The control device 18 uses the input voltage Edc detected by the input voltage detection unit 10 and the filter signal Sf (an example of a signal based on a pulse signal) input from the control device 16 to reconstruct the input voltage Edc detected by the primary DC voltage detection unit 13P. The control device 18 adds or subtracts the amplitude value of the filter signal Sf input from the control device 16 to the voltage value of half the input voltage Edc input from the input voltage detection unit 10 to generate a reconstructed signal that reconstructs the DC voltages V113p and V213p. The amplitude of the filter signal Sf is, for example, a positive value when the duty cycle of the pulse signal Spls1 is greater than 50%, a negative value when the duty cycle of the pulse signal Spls1 is less than 50%, and 0 when the duty cycle of the pulse signal Spls1 is 50%. Furthermore, the absolute value of the amplitude of the filter signal Sf reflects the voltage values ​​of the DC voltages V113p and V213p. Therefore, the control device 18 can restore the DC voltages V113p and V213p by adding or subtracting the amplitude value of the filter signal Sf to a voltage value that is half the input voltage Edc.

[0293] The control device 18 outputs the generated restoration signal to, for example, the optical transmission unit 192. The restoration signal is then transmitted through the optical transmission unit 192 and input to the control device 16. The control device 16 determines the duty cycle of the input signals Si1ja and Si3ja based on the amplitude (i.e., voltage value) of the restoration signal input from the control device 18, and outputs the input signals Si1ja and Si3ja with the determined duty cycles to the isolated signal transmission unit 15.

[0294] (Operation of the power conversion system) The operation of the power conversion system 1E according to this embodiment will be explained using Figure 8 with reference to Figure 9. Since the power conversion system 1E operates in the same manner as the power conversion system 1D according to the second embodiment described above, a detailed explanation will be omitted.

[0295] Figure 10 is a timing chart showing an example of the operating waveform of the power conversion system 1E. Figure 10 illustrates the operating waveform of the power conversion system 1E related to voltage balancing control that makes the DC voltages V113p and V213p generated at the primary side capacitors 113P and 213P the same. The power conversion system 1E is configured to detect the DC voltages V113p and V213p generated at the primary side capacitors 113P and 213P each time it performs a series of operations from the first to the eighth operating mode multiple times. However, the power conversion system 1E may also be configured to detect the DC voltages V113p and V213p generated at the primary side capacitors 113P and 213P each time it performs a series of operations from the first to the eighth operating mode.

[0296] The "Primary side capacitor DC voltage," "Capacitor DC voltage ratio," and "Pulse signal" in the first to third rows of Figure 10 are the same as those in the first to third rows of Figure 8, so no explanation is provided. The fourth row of Figure 10 shows the voltage waveform of the filter signal Sf output from the filter unit 17. The fifth row of Figure 10 shows the voltage waveform of the supply signal supplied from the primary side device 2P to the power conversion system 1D between the primary side positive electrode line P1 and the primary side negative electrode line N1. The sixth row of Figure 10 shows the voltage waveform of the restored signal restored by the control device 18. The vertical axis from the fourth to sixth rows of Figure 10 represents voltage. In Figure 10, time is represented from left to right.

[0297] Furthermore, for ease of understanding, in Figure 10, the magnitudes and relative magnitudes of the DC voltages V113p generated at the primary capacitor 113P and V213p generated at the primary capacitor 213P during the passage of time from time t0 to time t9 are the same as those of the DC voltages V113p and V213p shown in Figure 6. In addition, a detailed explanation of the operation of power conversion system 1E will be omitted below, and the explanation will focus on the differences from power conversion system 1D.

[0298] As shown in Figure 10, in this embodiment, the relative magnitudes of the DC voltage V113p of the primary capacitor 113P (see Figure 9), the DC voltage V213p of the primary capacitor 213P (see Figure 9), and the voltage of half the input voltage Edc input from the primary device 2P (see Figure 9) during the period prior to time t0 are the same as the relative magnitudes of these voltage values ​​shown in Figure 6.

[0299] Therefore, as shown in Figure 10, the capacitor DC voltage ratio Vr obtained from the DC voltages V113p and V213p detected by the primary DC voltage detection unit 13P (see Figure 6) at time t0 is greater than "1". Therefore, the filter signal Sf output from the filter unit 17 (see Figure 9) to the control device 16 (see Figure 6) during the period from time t0 to time t1 is a signal with a positive amplitude value corresponding to the value of the capacitor DC voltage ratio Vr.

[0300] At time t1, the control device 16 outputs the amplitude value of the filter signal Sf input from the filter unit 17 to the control device 18 via the optical transmission unit 192 of the isolated signal transmission unit 19.

[0301] At time t0, the input voltage detection unit 10 (Figure 9) detects the voltage value of the input voltage Edc and outputs the detected voltage value to the control device 18 as the detected value. The supply signal supplied from the primary side device 2P is a DC signal of the input voltage Edc. Therefore, the input voltage detection unit 10 detects an input voltage Edc whose voltage value is constant from time t0 to time t9a.

[0302] At time t1, the control device 18 generates a restored signal S113r by adding the amplitude value of the filter signal Sf input from the control device 16 to the detected value (i.e., voltage value) of the input voltage Edc input from the input voltage detection unit 10 to restore the primary side capacitor 113P. The control device 18 also generates a restored signal S213r by subtracting the amplitude value of the filter signal Sf input from the control device 16 from the detected value (i.e., voltage value) of the input voltage Edc input from the input voltage detection unit 10 to restore the primary side capacitor 213P. The control device 18 outputs information (e.g., voltage values) related to the generated restored signals S113r and S213r to the control device 16 via the optical transmission unit 191 of the isolated signal transmission unit 19.

[0303] The control device 16 controls the gate drive unit 12P based on the voltage values ​​of the restoration signals S113r and S213r input from the control device 18, operating the primary bridge circuit 112P so that the DC voltage V113p becomes lower than the current value and the DC voltage V213p becomes higher than the current value. In other words, the control device 16 generates an input signal Si1ja to make the conduction state (on state) of the gate pulse signals Sg11 and Sg14 in the first operating mode and the gate pulse signals Sg12 and Sg13 in the third operating mode longer than the current value. The control device 16 also generates an input signal Si3ja to make the conduction state (on state) of the gate pulse signals Sg31 and Sg34 in the fifth operating mode and the gate pulse signals Sg32 and Sg33 in the seventh operating mode shorter than the current value.

[0304] As shown in Figure 10, the power conversion system 1E operates similarly to the power conversion system 1D between time t1 and time t2 (see Figure 8). As a result, as shown between time t1a and time t2 in Figure 10, the DC voltage V213p generated at the primary capacitor 213P becomes higher than the current value, and the DC voltage V113p generated at the primary capacitor 113P becomes lower than the current value.

[0305] Note that the timing at which the DC voltages V113p and V213p generated in the primary capacitors 113P and 213P change actually occurs after a predetermined time has elapsed from time t1a. However, similar to the second embodiment described above, the diagram shows the DC voltages V113p and V213p changing at time t1a. Furthermore, in Figure 10, the timing at which the DC voltages V113p and V213p generated in the primary capacitors 113P and 213P change is also shown at times t3a, t5a, t7a, and t9a in the same way as at time t1a.

[0306] Although a detailed explanation is omitted, the power conversion system 1E operates in the same way as at time t0 at times t2, t4, and t6. Furthermore, the power conversion system 1E operates in the same way as at time t1 at times t3, t5, and t7. In addition, the power conversion system 1E operates in the same way as at time t1a at times t3a, t5a, and t7a. As a result, as shown in Figure 10, the voltage difference between the DC voltage V113p generated at the primary capacitor 113P and the DC voltage V213p generated at the primary capacitor 213P gradually decreases.

[0307] As a result, as shown in Figure 10, after a predetermined time has elapsed from time t7a, the DC voltages V113p and V213p have the same voltage value, and at time t8, the primary DC voltage detection unit 13P detects that the DC voltages V113p and V213p have the same voltage value. Consequently, at time t9, the amplitude value of the filter signal Sf input to the control device 18 becomes "0". Therefore, the control device 18 generates restoration signals S113r and S213r, which have the same voltage value, and outputs them to the control device 16.

[0308] Therefore, the control device 16 controls the gate drive unit 12P based on the voltage values ​​of the restoration signals S113r and S213r input from the control device 18, and outputs input signals Si1ja and Si3ja with the same duty cycle as the determined input signals Si1ja and Si3ja to the isolated signal transmission unit 15 at time t9a so that the DC voltages V113p and V213p generated in the primary capacitors 113P and 213P are maintained at their current voltage values. As a result, as shown in Figure 10, the DC voltages V113p and V213p generated in the primary capacitors 113P and 213P are maintained at the same voltage values ​​even after time t9a.

[0309] Thus, the power conversion system 1E according to this embodiment can control the voltage balance of the DC voltages V113p and V213p generated in the primary capacitors 113P and 213P, even if the number of optical transmission units used in the isolated signal transmission unit 15 is smaller compared to conventional power conversion systems.

[0310] Furthermore, the power conversion system 1E, like the power conversion system 1D according to the first embodiment, is equipped with a secondary DC voltage detection unit 13S. Therefore, the power conversion system 1E, like the power conversion system 1D, controls the voltage balance of DC voltages V113s and V213s using the detected values ​​of DC voltages V113s and V213s generated in the secondary capacitors 113S and 213S, so that the voltage values ​​of DC voltages V113s and V213s can be controlled to be the same as the design values. Therefore, even if the absolute value deviates from the design value when the voltage balance of DC voltages V113p and V213p of the primary capacitors 113P and 213P is controlled, the power conversion system 1E can supply the design DC voltage to the secondary device 2S.

[0311] As described above, the power conversion system 1E according to this embodiment includes, in addition to the configuration of the power conversion system 1D according to the first embodiment, a control device 18 that controls the control device 16 while the primary side PS and secondary side SS of the isolated DC / DC converters 11 and 21 are electrically isolated, and an input voltage detection unit 10 that detects the input voltage Edc between a primary side positive electrode line P1 connected to primary side bridge circuits 112P and 212P to which the DC voltages V113p and V213p are detected by the primary side DC voltage detection unit 13P and which are connected to primary side capacitors 113P and 213P, and to which the positive electrode potential is supplied, and a primary side negative electrode line N1 connected to primary side bridge circuits 112P and 212P to which the negative electrode potential is supplied.

[0312] As a result, the power conversion system 1D can be made more cost-effective even if it has a primary neutral point NP (i.e., the capacitor midpoint) to which primary capacitors 113P and 213P are connected, and also has isolation transformers 111 and 211.

[0313] The present invention is not limited to the embodiments described above and can be modified in various ways. The pulse signal generation unit 14 in the first to third embodiments described above is configured to generate a pulse signal with a duty cycle corresponding to the ratio of the DC voltages of a plurality of capacitors, but the present invention is not limited thereto. For example, the pulse signal generation unit 14 may be configured to generate a pulse signal with a duty cycle corresponding to the difference in the DC voltages of a plurality of capacitors.

[0314] The power conversion system 1D according to the second embodiment described above may have a filter unit 17 on the output side of the isolated signal transmission unit 19, similar to the power conversion system 1E according to the third embodiment described above.

[0315] In the second and third embodiments described above, the isolated DC / DC converters 11 and 21 are connected in series on both the input and output sides, but the present invention is not limited thereto. For example, the isolated DC / DC converters 11 and 21 may be connected in parallel on both the input and output sides, or one of the input or output sides may be connected in series and the other in parallel.

[0316] The power conversion system 1D according to the second embodiment and the power conversion system 1E according to the third embodiment are equipped with two isolated DC / DC converters, but they may be equipped with three or more isolated DC / DC converters.

[0317] The power conversion system 1D according to the second embodiment and the power conversion system 1E according to the third embodiment may include a DC / AC converter, similar to the power conversion system 1C according to modification 2 of the first embodiment.

[0318] The technical scope of the present invention is not limited to the illustrative and described embodiments, but also includes all embodiments that produce effects equivalent to those aimed at by the present invention. Furthermore, the technical scope of the present invention is not limited to the combination of features of the invention defined by the claims, but can be defined by any desired combination of specific features from all disclosed features. [Explanation of symbols]

[0319] 1A, 1B, 1C, 1D, 1E Power Conversion System 2P primary side device 2S Secondary side device 10 Input voltage detection unit 11,21 Isolated DC / DC Converter 12P, 12S gate drive unit 13P Primary DC Voltage Detection Unit 13S Secondary DC Voltage Detection Unit 14. Pulse signal generation unit 15. Isolated signal transmission section 16,18 Control device 17 Filter section 19. Isolated signal transmission section 111,211 Isolation transformer 112P, 212P primary bridge circuit 112S, 212S secondary bridge circuit 113P, 114P, 213P primary output capacitors 113S, 114S, 213S Secondary capacitor 115P, 115S inductors 116 DC / AC Converter 131P, 131S, 132P, 132S detection unit 151, 152, 152-1~152-8, 152-i, 153, 191, 192 Optical transmission section 215P, 215S inductors a1,a2,b1,b2,c1,c2,d1,d2 connection part D1~D4, D11~D14, D21~D24, D31~D34, D41~D44 Freewheeling diodes D5, D6 diodes Edc Input Voltage N1 Primary side negative electrode line N2 secondary negative electrode line NP Primary neutral point NS Secondary neutral point P1 Primary side positive electrode line P2 Secondary side positive electrode line PS Primary side Q1-Q4, Q11-Q14, Q21-Q24, Q31-Q34, Q41-Q44 Transistors S113r, S213r Restoration signal Sf filter signal Sg11~Sg14, Sg21~Sg24, Sg31~Sg34, Sg41~Sg44 Gate pulse signals Si1ja(j=1~4),Si1jb(j=1~4),Si2ja(j=1~4),Si3ja(j=1~4),Si3jb(j=1~4),Si4ja(j=1~4) Input signal Spls1 pulse signal SPLS2 pulse signal SS secondary side V113p, V113s, V114p, V114s, V213p, V213s DC voltage Vac AC voltage VP1, VP2 detected values Vr Capacitor DC Voltage Ratio

Claims

1. An isolated DC / DC converter having an isolation transformer, a primary bridge circuit provided on the primary side of the isolation transformer and having at least two switching elements, and a secondary bridge circuit provided on the secondary side of the isolation transformer and having at least two switching elements, A control unit that controls the primary bridge circuit and the secondary bridge circuit, Multiple primary capacitors connected in series to the primary bridge circuit, Multiple secondary capacitors connected in series to the secondary bridge circuit, A primary-side DC voltage detection unit that individually detects the DC voltage generated in each of the plurality of primary-side capacitors, A secondary DC voltage detection unit that individually detects the DC voltage generated in each of the plurality of secondary capacitors, A pulse signal generation unit generates a pulse signal with a duty cycle corresponding to the ratio of the multiple DC voltages detected by either the primary DC voltage detection unit or the secondary DC voltage detection unit. An isolated signal transmission unit transmits a signal based on the pulse signal input from the pulse signal generation unit to the control unit while electrically insulating the primary and secondary sides of the isolated DC / DC converter. A power conversion system equipped with the following features.

2. At least one of the primary bridge circuit and the secondary bridge circuit has a half-bridge circuit. The power conversion system according to claim 1.

3. The control unit uses a signal based on the pulse signal output from the isolated signal transmission unit to control the bridge circuit connected to the capacitor whose DC voltage was detected by the one detection unit. The power conversion system according to claim 1 or 2.

4. A plurality of isolated DC / DC converters, each having an isolation transformer, a primary bridge circuit provided on the primary side of the isolation transformer and having at least two switching elements, and a secondary bridge circuit provided on the secondary side of the isolation transformer and having at least two switching elements, A first control unit that controls a plurality of primary bridge circuits and a plurality of secondary bridge circuits, Multiple primary side bridge circuits each have a primary side capacitor connected in parallel, A secondary capacitor connected in parallel to each of the multiple secondary bridge circuits, A primary-side DC voltage detection unit that individually detects the DC voltage generated in each of the multiple primary-side capacitors, A secondary DC voltage detection unit that individually detects the DC voltage generated in each of the multiple secondary capacitors, A pulse signal generation unit generates a pulse signal with a duty cycle corresponding to the ratio of the multiple DC voltages detected by either the primary DC voltage detection unit or the secondary DC voltage detection unit. With the primary and secondary sides of the plurality of isolated DC / DC converters electrically isolated, an isolated signal transmission unit transmits a signal based on the pulse signal input from the pulse signal generation unit to the first control unit. A power conversion system equipped with the following features.

5. Each of the multiple primary bridge circuits and the multiple secondary bridge circuits has a full bridge circuit. The power conversion system according to claim 4.

6. The system includes a second control unit that controls the first control unit while electrically insulating the primary and secondary sides of the plurality of isolated DC / DC converters, The aforementioned multiple isolated DC / DC converters have their input sides connected in series or parallel, and their output sides connected in series or parallel. The power conversion system according to claim 4 or 5.

7. The system includes an input voltage detection unit that detects the input voltage between a positive electrode line connected to a bridge circuit to which a DC voltage has been detected by the aforementioned detection unit and to which a positive electrode potential is supplied, and a negative electrode line connected to the bridge circuit and to which a negative electrode potential is supplied. The input voltage detection unit outputs the detected input voltage to the second control unit. The second control unit uses the input voltage detected by the input voltage detection unit and the signal based on the pulse signal input from the first control unit to reconstruct the DC voltage detected by the first detection unit. The power conversion system according to claim 6.

8. The first control unit uses a signal based on the pulse signal output from the isolated signal transmission unit to control the bridge circuit connected to the capacitor whose DC voltage is detected by the one detection unit. A power conversion system according to any one of claims 4 to 7.

9. Based on the duty cycle of the pulse signal generated by the pulse signal generation unit, a signal having an amplitude corresponding to the ratio of the DC voltage detected by one of the detection units is extracted, and the unit comprises a filter unit provided on the output side of the isolated signal transmission unit. A power conversion system according to any one of claims 1 to 8.

10. The isolated DC / DC converter is further equipped with a DC / AC converter connected to either the primary or secondary side. A power conversion system according to any one of claims 1 to 9.

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