sensor

Abstract

To provide a sensor capable of preventing the detection time from becoming longer.SOLUTION: A sensor comprises: a sensor array in which N sensor circuits are serial-connected; and timer circuits each provided for each sensor circuit. The sensor comprises an output circuit that receives N output logic signals outputted from the N sensor circuits and outputs a serial output signal. Each timer circuit starts a time measurement operation in response to inversion of an input logic signal of the corresponding sensor circuit. After a lapse of a predetermined time, a time constant of the corresponding sensor circuit is switched from a first time constant to a second time constant smaller than the first time constant. Each of the N sensor circuits starts a detection operation on the basis of the first time constant and executes a detection operation on the basis of the second time constant during a time period after the predetermined time has elapsed from the start of the detection operation. The serial output signal outputted from the output circuit is a signal for continuously outputting signals indicating N detection times detected by the N sensor circuits.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] The technology disclosed in this specification relates to a sensor capable of preventing an increase in detection time.

Background Art

[0002] Patent Document 1 discloses a sensor system including a sensor array having a plurality of sensors arranged in a two-dimensional array and an X-Y decoder. By scanning the sensor array with the X-Y decoder, a plurality of sensors can be read out.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] Some of the plurality of sensors constituting the sensor array may include sensors that take a long time to read out (sensors with a large time constant). Examples of such sensors include sensors with a wide dynamic range (e.g., optical sensors) and sensors in which failures or defects have occurred. Then, when all sensors are read out in order by scan reading, the detection time of the entire sensor array is limited by the reading time of the sensors that take a long time to read out (sensors with a large time constant), which is a problem.

Means for Solving the Problems

[0005] One embodiment of a sensor disclosed herein comprises a sensor array having N sensor circuits (where N is a natural number greater than or equal to 2). The sensor array has a serial connection in which the output logic signal of the preceding sensor circuit is input as the input logic signal of the next sensor circuit. The sensor comprises a timer circuit, one for each sensor circuit. There is one or more timer circuits for at least one of the N sensor circuits. The sensor comprises an output circuit that receives an input logic signal input to the first sensor circuit of the sensor array, as well as N output logic signals output from each of the N sensor circuits, and outputs a serial output signal. The timer circuit starts a time measurement operation to measure a predetermined time in response to the inversion of the input logic signal input to the corresponding sensor circuit. After a predetermined time has elapsed since the start of the time measurement operation, the timer circuit switches the time constant of the corresponding sensor circuit from a first time constant to a second time constant smaller than the first time constant. The time constant is a parameter that indicates the time required for a detection operation in which the sensor circuit detects a detection time proportional to the detected amount. Each of the N sensor circuits starts a detection operation based on a first time constant in response to the inversion of the input logic signal. Each of the N sensor circuits performs a detection operation based on a second time constant for a period after a predetermined time has elapsed since the start of the detection operation. Each of the N sensor circuits ends its detection operation by inverting the output logic signal after detecting the detection time. When the output logic signal of the K-th sensor circuit (where K is a natural number between 1 and N-1) is inverted and the detection operation of the K-th sensor circuit ends, the detection operation of the K+1-th sensor circuit begins. The serial output signal output from the output circuit is a signal that continuously outputs signals indicating the N detection times detected by the N sensor circuits.

[0006] In this sensor, the detection operation of the K+1 sensor circuit begins when the detection operation of the K-th sensor circuit is completed. Therefore, the detection operation can proceed autonomously in the order in which the serially connected sensor circuits are arranged. If a sensor circuit exceeds a predetermined time for detection, the timer circuit can switch to reducing the time constant of that sensor circuit (increasing the detection speed). This shortens the detection time of sensor circuits after a predetermined time has elapsed. When reading the detection times of all sensor circuits serially, the detection time of the entire sensor array will not be limited by the reading time of sensors that take a long time to read (sensors with large time constants). This makes it possible to suppress the lengthening of the reading time of the entire sensor array.

[0007] Each of the N sensor circuits may include a first capacitance section configured to be switchable between a first capacitance value and a second capacitance value smaller than the first capacitance value. Each of the N sensor circuits may include a current control section that variably controls the charging current to the first capacitance section according to the detected amount. Each of the N sensor circuits may include an inverting output section that inverts the output logic signal in response to the output voltage of the first capacitance section rising to a predetermined voltage. Each of the N sensor circuits may charge the first capacitance section having the first capacitance value during the period from the start of the detection operation until a predetermined time has elapsed. After the predetermined time has elapsed, the timer circuit may switch the capacitance value of the first capacitance section of the corresponding sensor circuit from the first capacitance value to the second capacitance value. Each of the N sensor circuits may charge the first capacitance section having the second capacitance value during the period after the predetermined time has elapsed.

[0008] The first capacitance section may include a first capacitance element and a second capacitance element connected in parallel to each other with respect to the inverting output section. A switch element may be placed on the charging path of the second capacitance element. The timer circuit may change the switch element from a low impedance state to a high impedance state as a predetermined time elapses.

[0009] Each of the N sensor circuits may include a variable capacitance element that controls the capacitance value variably according to the detected amount. Each of the N sensor circuits may include a current switching unit configured to switch the charging current charged to the variable capacitance element based on an input logic signal between a first current value and a second current value greater than the first current value. Each of the N sensor circuits may include an inverting output unit that inverts the output logic signal in response to the output voltage of the variable capacitance element rising to a predetermined voltage. Each of the N sensor circuits may charge the variable capacitance element with the first current value during the period from the start of detection operation until a predetermined time has elapsed. After the predetermined time has elapsed, the timer circuit may switch the current value of the current switching unit of the corresponding sensor circuit from the first current value to the second current value. Each of the N sensor circuits may charge the variable capacitance element with the second current value during the period after the predetermined time has elapsed.

[0010] The current switching section may include a first resistive element and a second resistive element connected in parallel to the variable capacitance element. A switch element may be placed on the connection path between the second resistive element and the variable capacitance element. The timer circuit may switch the switch element from a high impedance state to a low impedance state as a predetermined time elapses.

[0011] One or more timer circuits may include a second capacitance unit having a fixed capacitance value. The second capacitance unit may be charged with a predetermined current based on the input logic signal in response to the inversion of the input logic signal input to the corresponding sensor circuit. The predetermined time may be the time from when the input logic signal is inverted until the output voltage of the second capacitance unit rises to a predetermined threshold voltage.

[0012] One embodiment of a sensor disclosed herein comprises a sensor array having N sensor circuits (where N is a natural number greater than or equal to 2). The sensor array has a serial connection in which the output logic signal of the preceding sensor circuit is input as the input logic signal of the next sensor circuit. The sensor comprises a timer circuit, one for each sensor circuit. There is one or more timer circuits for at least one of the N sensor circuits. The sensor comprises an output circuit that receives an input logic signal input to the first-stage sensor circuit of the sensor array, as well as N output logic signals output from each of the N sensor circuits, and outputs a serial output signal. Each of the N sensor circuits starts a detection operation in which it detects a detection time proportional to the detected amount in response to the inversion of the input logic signal input to the corresponding sensor circuit. If each of the N sensor circuits detects a detection time proportional to the detected amount during the period from the start of the detection operation until the predetermined time has elapsed, it terminates the detection operation by inverting the output logic signal in response to the detection of the detection time. Each of the N sensor circuits terminates its detection operation by inverting its output logic signal if a predetermined time has elapsed since the start of its detection operation without detecting a detection time. When the output logic signal of the Kth sensor circuit (where K is a natural number between 1 and N-1) is inverted and the detection operation of the Kth sensor circuit ends, the detection operation of the K+1th sensor circuit begins. The serial output signal output from the output circuit is a signal that continuously outputs the N detection time signals detected by the N sensor circuits.

[0013] In this sensor, if a sensor circuit exceeds a predetermined time limit for detection operation, a timer circuit can terminate the detection operation in that sensor circuit. This makes it possible to suppress the excessive length of the overall readout time for the sensor array. [Brief explanation of the drawing]

[0014] [Figure 1]It is a block diagram showing an outline of the sensor 1 of Example 1. [Figure 2] It is a circuit configuration diagram of the sensor circuit SC(K) and the timer circuit TC(K). [Figure 3] It is a waveform diagram explaining an operation in which the detection time DT(K) is detected before the elapse of the timeout time DU. [Figure 4] It is a waveform diagram explaining an operation in which the detection time DT(K) is detected after the elapse of the timeout time DU. [Figure 5] It is a waveform diagram explaining the overall operation of the sensor 1. [Figure 6] It is a circuit configuration diagram of the sensor circuit SCa(K) according to Example 2. [Figure 7] It is a waveform diagram explaining an operation in which the detection time DT(K) is detected before the elapse of the timeout time DU. [Figure 8] It is a waveform diagram explaining an operation in which the detection time DT(K) is detected after the elapse of the timeout time DU. [Figure 9] It is a circuit configuration diagram of the sensor circuit SCb(K) according to Example 3. [Figure 10] It is a circuit configuration diagram of the sensor circuit SCc(K) according to Example 4.

BEST MODE FOR CARRYING OUT THE INVENTION

EXAMPLE

[0015] (Configuration of Sensor 1) Fig. 1 shows the sensor 1 according to Example 1. The sensor 1 is an example of an A / D conversion circuit that converts various physical quantities into digital values. The sensor 1 includes an enable circuit 10 and N (N is a natural number of 2 or more) sensor units SU(1) to SU(N).

[0016] The enable circuit 10 is a NAND logic circuit. An enable signal EN output from a control circuit (not shown) and an output signal OS(N) output from the final-stage sensor circuit SC(N) are input to the enable circuit 10. The start signal ST output from the enable circuit 10 is input to the first-stage sensor circuit SC(1). That is, the output signal OS(N) of the final-stage sensor circuit SC(N) is input as an input logic signal to the first-stage sensor circuit SC(1). The enable circuit 10 is a circuit that controls the on / off of sensor 1. During the period when the enable signal EN is at a high level, the detection operation is performed by sensor 1. During the period when the enable signal EN is at a low level, sensor 1 stops.

[0017] Each of the N sensor units SU(1) to SU(N) includes sensor circuits SC(1) to SC(N), timer circuits TC(1) to TC(N), and NAND circuits ND(1) to ND(N). The sensor circuits SC(1) to SC(N) constitute the sensor array 20. The start signal ST is input to the first-stage sensor circuit SC(1). The output signal OS(1) output from the sensor circuit SC(1) is input to the second-stage sensor circuit SC(2). Similarly, the sensor array 20 has a serial connection in which the output signal of the previous-stage sensor circuit is input as the input signal of the next-stage sensor circuit.

[0018] The timer circuit TC is a circuit provided for each one sensor circuit SC. In this embodiment, N timer circuits TC(1) to TC(N) are provided corresponding to each of the N sensor circuits SC(1) to SC(N). The start signal ST is input to the timer circuit TC(1). An output signal OT(1) is output from the timer circuit TC(1) and input to the sensor circuit SC(1). Similarly, the output signal OS(N - 1) is input to the timer circuit TC(N). The output signal OT(N) output from the timer circuit TC(N) is input to the sensor circuit SC(N).

[0019] The output circuit 30 includes NAND gates ND(1) to ND(N) and an inverter INV. The output circuit 30 receives a start signal ST and output signals OS(1) to OS(N). The NAND gate ND(1) receives the start signal ST via the inverter INV, as well as the output signal OS(1). The logic signal LS(1) is output from the NAND gate ND(1). Similarly, the logic signal LS(N-1) and the output signal OS(N) are input to the NAND gate ND(N). The serial output signal Sout is output from the NAND gate ND(N). In other words, the output circuit 30 is a logic circuit that outputs the serial output signal Sout shown in equation (2) below.

number

[0020] (Configuration of sensor circuit SC(K) and timer circuit TC(K)) The circuit configuration of the Kth sensor circuit SC(K) and timer circuit TC(K) will be explained using Figure 2. Here, K is a natural number between 1 and N-1 (inclusive).

[0021] The sensor circuit SC(K) comprises an inverter INV1, an nMOS transistor TN1, a photodiode PD, a capacitive section CN, and a Schmitt trigger inverter SI. The gate terminals of the inverter INV1 and the nMOS transistor TN1 receive the output signal OS(K-1) output from the preceding sensor circuit SC(K-1). The output terminal of the inverter INV1 is connected to the cathode terminal of the photodiode PD. The anode terminal of the photodiode PD is connected to the drain terminal of the nMOS transistor TN1, one terminal of the capacitive section CN, and the input terminal of the Schmitt trigger inverter SI. The other terminal of the capacitive section CN, and the source and back gate terminals of the nMOS transistor TN1 are connected to the reference voltage section GND. The detection current IS, which is the reverse leakage current flowing through the photodiode PD, changes according to the amount of light received. In other words, the photodiode PD functions as a current control unit that variably controls the charging current to the capacitive section CN (detection current IS) according to the amount of light received.

[0022] A voltage signal AN(K) is output from the capacitance unit CN. The capacitance unit CN comprises a first capacitance element CP1, a second capacitance element CP2, and an nMOS transistor TNg. The first capacitance element CP1 and the second capacitance element CP2 are connected in parallel to each other with respect to the photodiode PD and the Schmitt trigger inverter SI. The nMOS transistor TNg is located on the connection path (i.e., on the charging path) between the second capacitance element CP2 and the reference voltage section GND. When the nMOS transistor TNg is ON, the first capacitance element CP1 and the second capacitance element CP2 are connected in parallel. Therefore, the capacitance unit CN has a first capacitance value (CP1+CP2) determined by the combined capacitance of the first capacitance element CP1 and the second capacitance element CP2. On the other hand, when the nMOS transistor TNg is OFF, the second capacitance element CP2 is disconnected. Therefore, the capacitance unit CN has a second capacitance value (CP1) determined by the first capacitance element CP1. Consequently, the second capacitance value is smaller than the first capacitance value.

[0023] A voltage signal AN(K) is input to the input terminal of the Schmitt trigger inverter SI. The positive power supply terminal of the Schmitt trigger inverter SI is connected to the power supply voltage section VDD, and the negative power supply terminal is connected to the reference voltage section GND. The Schmitt trigger inverter SI functions as an inverting output section, inverting the output logic signal in response to the voltage signal AN(K) output from the capacitive section CN rising to the rising logic threshold voltage VT1.

[0024] The timer circuit TC(K) comprises an nMOS transistor TN2, a resistor RT, a capacitive element CT, and a Schmitt trigger inverter SI2. The output signal OS(K-1) is input to the gate terminal of the nMOS transistor TN2. The source terminal and back gate terminal of the nMOS transistor TN2 are connected to the reference voltage GND. One terminal of the resistor RT is connected to the output terminal of inverter INV1. The other terminal of the resistor RT is connected to the drain terminal of the nMOS transistor TN2, one terminal of the capacitive element CT, and the input terminal of the Schmitt trigger inverter SI2. The other terminal of the capacitive element CT is connected to the reference voltage GND. The positive power supply terminal of the Schmitt trigger inverter SI2 is connected to the power supply voltage VDD, and the negative power supply terminal is connected to the reference voltage GND. The voltage signal AT(K) output from the capacitive element CT is input to the input terminal of the Schmitt trigger inverter SI2. The output signal OT(K) output from the output terminal of the Schmitt trigger inverter SI2 is input to the gate of the nMOS transistor TNg.

[0025] (Operation of sensor circuit SC(K) and timer circuit TC(K)) The operation of the sensor circuit SC(K) and timer circuit TC(K) will be explained using the waveform diagrams in Figures 3 and 4. Time t(K-1) is the time when the sensor circuit SC(K) starts its detection operation. Specifically, time t(K-1) is the time when the output signal OS(K-1) input to the sensor circuit SC(K) falls. Time t(K) is the time when the detection time DT(K), which is the target of detection, is detected. Specifically, time t(K) is the time when the output signal OS(K) falls. Time tt is the time when it is detected that the timeout time DU has elapsed since the sensor circuit SC(K) started its detection operation. Specifically, it is the time when the output signal OT(K) falls. Time tres is the time when the sensor array 20 is reset. Specifically, it is the time when the output signal OS(k-1) falls.

[0026] Figure 3 illustrates the case where detection time DT(K) is detected before the timeout time DU has elapsed (i.e., time t(K) ≤ time tt). Figure 4 illustrates the case where detection time DT(K) is detected after the timeout time DU has elapsed (i.e., time t(K) > time tt).

[0027] Using Figure 3, we will explain the operation in which the detection time DT(K) is detected before the timeout time DU has elapsed. At a time prior to time t(K-1), the output signal OS(K-1) input to the sensor circuit SC(K) is at a high level, and inverter INV1 is in the off state. At this time, the voltage signal AN(K) is 0[V], and the output signal OS(K) output from the Schmitt trigger inverter SI is at a high level. Also, the voltage signal AT(K) is 0[V], and the output signal OT(K) output from the Schmitt trigger inverter SI2 is at a high level. Therefore, the nMOS transistor TNg is in the on state, and the second capacitance element CP2 is connected to the reference voltage section GND, just like the first capacitance element CP1. That is, the capacitance section CN has a combined capacitance (CP1+CP2) of the first capacitance element CP1 and the second capacitance element CP2 connected in parallel, and the capacitance value is large.

[0028] When the output signal OS(K-1) switches from a high level to a low level at time t(K-1), the output of inverter INV1 switches to a high level, and the nMOS transistor TN1 switches to the off state. Consequently, a reverse leakage current, the detection current IS, begins to flow through the photodiode PD (arrow Y1). Since the detection current IS changes according to the amount of light received, the charging time of the capacitive section CN changes. As the capacitive section CN is charged by the detection current IS, the voltage signal AN(K) rises with a slope of "IS / (CP1+CP2)" (see region A1). Here, IS represents the current value of the detection current IS, CP1 represents the capacitance value of the first capacitive element CP1, and CP2 represents the capacitance value of the second capacitive element CP2.

[0029] The slope of the voltage signal AN(K), "IS / (CP1+CP2)," corresponds to the time constant of the sensor circuit SC(K). The time constant is a parameter that indicates the time required for the sensor circuit SC(K) to perform a detection operation, where it detects a detection time DT(K) proportional to the detected amount (i.e., the amount of light received). A larger time constant indicates that the detection operation takes longer and the response of the sensor circuit SC(K) is slower. In this embodiment, the slope of the voltage signal AN(K) before the elapsed time tt, "IS / (CP1+CP2)," is defined as the "first time constant." That is, the sensor circuit SC(K) starts the detection operation based on the first time constant in response to the start of the detection operation.

[0030] At time t(K-1), the nMOS transistor TN2 also switches to the off state, and the timer current IT begins to flow through the resistor RT. As the capacitive section CN is charged by the timer current IT, the voltage signal AT(K) rises with a slope of "VDD / (RT×CT)" (see arrow Y2, region A2). Here, RT represents the resistance value of the resistor RT, and CT represents the capacitance value of the capacitive section CT. In other words, the timer circuit TC(K) starts a time measurement operation to measure a predetermined timeout time DU in response to the inversion of the output signal OS(K-1) input to the corresponding sensor circuit SC(K).

[0031] When the voltage signal AN(K) reaches the rising logic threshold voltage VT1 of the Schmitt trigger inverter SI at time t(K), the output signal OS(K) inverts from high level to low level (see arrow Y3). The detection time DT(K) from time t(K-1) to t(K) is proportional to "(CP1+CP2) / IS". In other words, the detection time DT(K) is an output with a time constant proportional to "CP1+CP2". Therefore, the detection time DT(K) becomes the output corresponding to the detection current IS, which is the target of detection. Subsequently, the voltage signal AN(K) rises until it reaches the power supply voltage VDD.

[0032] In other words, the sensor circuit SC(K) starts its detection operation in response to the inversion of the input logic signal, output signal OS(K-1). After the input logic signal is inverted, and a detection time DT(K) proportional to the detected amount, the detected current IS, has elapsed, the detection operation ends by inverting the output logic signal, output signal OS(K).

[0033] From time t(K) onward, while the output signal OS(K-1) remains at a low level, the voltage signals AN(K) and AT(K) rise until they reach the power supply voltage VDD. Then, at time tt, when the voltage signal AT(K) reaches the logic threshold voltage VT2 of the Schmitt trigger inverter SI2, the output signal OT(K) flips from a high level to a low level (see arrow Y4). This period from time t(K-1) to time tt is the timeout time DU that defines the timeout of the timer circuit TC(K). Since the voltage signal AT(K) rises at a constant slope regardless of the detected amount, the timeout time DU is also constant.

[0034] Then, at time tres, when the output signal OS(K-1) switches from a low level to a high level, the output of inverter INV1 inverts to a low level, and nMOS transistors TN1 and TN2 turn on. Since the on-resistance of nMOS transistor TN1 is sufficiently small, the charge stored in the first capacitive element CP1 and the second capacitive element CP2 is discharged instantaneously, and the voltage signal AN(K) changes to 0[V] (see arrow Y5). In response, the output signal OS(K) output from Schmitt trigger inverter SI inverts from a low level to a high level (see arrow Y6). Also, since the on-resistance of nMOS transistor TN2 is sufficiently small, the charge stored in the capacitive element CT is discharged instantaneously, and the voltage signal AT(K) changes to 0[V] (see arrow Y7). In response, the output signal OT(K) output from Schmitt trigger inverter SI2 inverts from a low level to a high level (see arrow Y8).

[0035] Figure 4 illustrates the operation in which the detection time DT(K) is detected after the timeout time DU has elapsed. This operation can occur when the detection current IS decreases and the upward slope of the voltage signal AN(K) decreases. The operation up to time tt is the same as in Figure 3, so the explanation is omitted. Before time tt, the voltage signal AN(K) rises with a slope of "IS / (CP1+CP2)", so the detection operation is performed based on the first time constant (see region A11).

[0036] At time tt, the voltage signal AT(K) reaches the logic threshold voltage VT2 before the voltage signal AN(K) reaches the rising logic threshold voltage VT1. Therefore, the output signal OT(K) inverts from a high level to a low level (see arrow Y11). As a result, the partial detection time DT1T(K) from time t(K-1) to time tt is detected.

[0037] When the output signal OT(K) goes low, the nMOS transistor TNg switches from a low impedance state to a high impedance state, and the second capacitive element CP2 is disconnected from the charging path. Therefore, the second capacitive element CP2 no longer contributes to the potential rise of the voltage signal AN(K). Thus, after time tt, the voltage signal AN(K) rises with a slope of "IS / CP1" (see region A12). That is, after time tt, the rising slope of the voltage signal AN(K) is increased. In this specification, the slope "IS / CP1" of the voltage signal AN(K) after time tt is defined as the "second time constant". The slope "IS / CP1" of the voltage signal AN(K) corresponding to the second time constant is greater than the slope "IS / (CP1+CP2)" of the voltage signal AN(K) corresponding to the first time constant. The second time constant reduces the time required for detection operation, thus allowing the sensor circuit SC(K) to respond faster. In other words, the second time constant is smaller than the first time constant. To put it another way, after time tt has elapsed, the timer circuit TC(K) switches the time constant of the corresponding sensor circuit SC(K) from the first time constant to a second time constant that is smaller than the first time constant.

[0038] When the voltage signal AN(K) reaches the rising logic threshold voltage VT1 of the Schmitt trigger inverter SI at time t(K), the output signal OS(K) inverts from high level to low level (see arrow Y12). The partial detection time DT2T(K) from time tt to t(K) is proportional to "CP1 / IS". Note that the operation after time t(K) is the same as the operation in Figure 3, so the explanation is omitted.

[0039] Because the time constant is switched at time tt, the partial detection times DT1T(K) and DT2T(K) are nonlinear outputs. However, as explained below, they can be converted to linear characteristics using the gains before and after the switch. Figure 4 shows the rise of the voltage signal AN(K) when the time constant is not switched at time tt, indicated by a dotted line (see region A13). In this case, the time it takes for the voltage signal AN(K) to reach the rising logic threshold voltage VT1 at time t2(K) is defined as the converted detection time DT2C(K) (see arrow Y13). The converted detection time DT2C(K) can be calculated by the following equation (1). Converted detection time DT2C(K) = (CP1 + CP2) / CP1 × Partial detection time DT2T(K) ... Equation (1) Therefore, the detection time DT(K) can be calculated by the following equation (2). Detection time DT(K) = Partial detection time DT1T + Conversion detection time DT2C(K) ... Equation (2)

[0040] The above operations are explained in summary. The sensor circuit SC(K) charges the capacitance section CN, which has a first capacitance value (CP1+CP2), during the period from the start of detection operation until the timeout period DU has elapsed. The timer circuit TC(K) switches the capacitance value of the capacitance section CN of the corresponding sensor circuit SC(K) from the first capacitance value (CP1+CP2) to the second capacitance value (CP1) as the timeout period DU elapses (see arrow Y11). During the period after the timeout period DU has elapsed, the sensor circuit SC(K) charges the capacitance section CN, which has a second capacitance value (CP1). In other words, the sensor circuit SC(K) performs detection operation based on the first time constant during the period until the timeout period DU has elapsed, and performs detection operation based on the second time constant during the period after the timeout period DU has elapsed. This makes it possible to reduce the time constant of the sensor circuit SC(K) as the timeout period DU elapses. This improves the responsiveness of the sensor circuit SC(K) after the timeout period DU has elapsed, and thus makes it possible to suppress the increase in detection time.

[0041] (Sensor 1 operation) The overall operation of sensor 1 will be explained using the waveform diagram in Figure 5. Before time t(0) in Figure 5, the enable signal EN is at a low level, and sensor 1 is in the off state. When sensor 1 is off, the start signal ST is at a high level, and the output signal OS(1) of the first stage sensor circuit SC(1) is at a high level. As shown in Figure 1, the input of each sensor circuit is the output of the preceding sensor circuit, so the output signals OS(1) to OS(N) of all sensor circuits are also at a high level.

[0042] When the enable signal EN is switched to a high level at time t(0), the start signal ST is switched from a high level to a low level, and the first detection operation of sensor 1 begins. In response to the transition of the start signal ST to a low level, charging of the capacitive section CN in the first stage sensor circuit SC(1) begins. At the same time, the logic signal LS(1) output from the NAND circuit ND(1) of the output circuit 30 is switched to a low level, so the serial output signal Sout is inverted (arrow Y21).

[0043] At time t(1), when the output signal OS(1) of the first-stage sensor circuit SC(1) switches from a high level to a low level, the logic signal LS(1) output from the NAND circuit ND(1) switches to a high level, causing the serial output signal Sout to invert from a low level to a high level (arrow Y22). The detection time DT(1) between both edges of the serial output signal Sout is inversely proportional to the detection current IS of the object being detected by the first-stage sensor circuit SC(1). Also, in response to the output signal OS(1) switching to a low level at time t(1), charging of the capacitive section CN in the second-stage sensor circuit SC(2) begins.

[0044] Similarly, when the output signal OS(2) of the second-stage sensor circuit SC(2) switches from a high level to a low level at time t(2), the serial output signal Sout inverts (arrow Y23). The detection time DT(2) between both edges of the serial output signal Sout is inversely proportional to the detection current IS of the object being detected by the second-stage sensor circuit SC(2). Also at time t(2), charging of the capacitive section CN in the third-stage sensor circuit SC(3) begins.

[0045] Similarly, when the output signal OS(K) of the preceding sensor circuit SC(K) switches from a high level to a low level, the Kth inversion occurs in the serial output signal Sout, and simultaneously, charging of the capacitive section CN in the next sensor circuit SC(K+1) begins. In this way, the detection operation is passed on in the order of serial connection.

[0046] Then, at time t(N), when the output signal OS(N) of the final, Nth stage sensor circuit SC(N) switches from a high level to a low level, the serial output signal Sout inverts (arrow Y24). This completes the detection operation of the N sensor circuits SC(1) to SC(N). The serial output signal Sout then continuously outputs signals indicating the N detection times DT(1) to DT(N) detected by the N sensor circuits SC(1) to SC(N).

[0047] As the output signal OS(N) of the final stage sensor circuit SC(N) inverts and the detection operation of the final stage sensor circuit SC(N) ends, the detection operation of the first stage sensor circuit SC(1) begins. This is explained below. The output signal OS(N) is returned to the enable circuit 10. Also, at time t(N), the enable signal EN is at a high level, and sensor 1 is in the ON state. Therefore, in accordance with the falling edge of the output signal OS(N), the start signal ST is switched to a high level (arrow Y25). The capacitive part CN in the first stage sensor circuit SC(1) is discharged instantaneously, and the output signal OS(1) inverts from a low level to a high level (arrow Y26). This change propagates to the final stage sensor circuit SC(N) in a short time (arrow Y27), and all output signals OS(1) to OS(N) return to their initial high level.

[0048] In response to the rising edge of the output signal OS(N), the start signal ST output from the enable circuit 10 is switched from a high level to a low level, and the second detection operation of sensor 1 begins (arrow Y28). Note that the content of the second detection operation is the same as the first detection operation, so the explanation is omitted.

[0049] Subsequently, at any time tdis, when the enable signal EN is switched from a high level to a low level, the start signal ST is switched to a low level (arrow Y29). Consequently, all output signals OS(1) to OS(N) are reset to their initial high level (region A21). In other words, the transition of the enable signal EN to a low level turns sensor 1 off.

[0050] In this embodiment, sensor 1 can initiate the detection operation of the (K+1)th sensor circuit when the detection operation of the Kth sensor circuit is completed. Therefore, the detection operation can proceed autonomously in the order of the serially connected sensor circuits SC(1) to SC(N). Since it is possible to read N sensor signals from N sensor circuits without the need for a scan circuit such as an XY decoder, the circuit size of sensor 1 can be reduced.

[0051] (effect) In some cases, some of the sensors constituting the sensor array 20 may include a sensor circuit SC (a sensor circuit SC with an exceptionally large time constant) that takes an order of magnitude longer to read. Examples of such sensor circuits SC include circuits with a wide dynamic range (e.g., optical sensors using photodiode elements) or circuits that are malfunctioning or defective. In such cases, when all sensor circuits SC are read sequentially by serial reading, the reading time of the sensor circuit SC with the exceptionally large time constant will limit the detection time of the entire sensor array 20. Furthermore, it may become impossible to obtain the output of all sensor circuits SC connected after the sensor circuit SC with the exceptionally large time constant.

[0052] Therefore, in the sensor 1 of Embodiment 1, if a sensor circuit SC occurs where the time taken for detection operation exceeds the timeout time DU, the timer circuit TC can switch to reducing the time constant of the sensor circuit SC (increasing the detection operation speed). This makes it possible to shorten the detection time of the sensor circuit SC after a predetermined time has elapsed. When reading the detection time DT of all sensor circuits SC serially, the detection time of the entire sensor array 20 will not be limited by the reading time of a sensor circuit SC with an order of magnitude larger time constant. In addition, it becomes possible to read the outputs of all sensor circuits SC connected after the sensor circuit SC with an order of magnitude larger time constant. [Examples]

[0053] (Configuration of sensor circuit SCa(K)) Figure 6 shows the sensor circuit SCa(K) according to Example 2. The sensor circuit SC(K) of Example 1 (Figure 2) was an example of a circuit configuration that switches the time constant of the sensor circuit according to the elapsed time of the timeout period DU. On the other hand, the sensor circuit SCa(K) of Example 2 (Figure 6) is an example of a circuit configuration that terminates the detection operation of the sensor circuit according to the elapsed time of the timeout period DU. Note that parts that are the same as those in Example 1 are denoted by the same reference numerals and their explanations are omitted.

[0054] The sensor circuit SCa(K) includes an inverting output section IO. The inverting output section IO includes a Schmitt trigger inverter SI and an AND circuit AD. A voltage signal AN(K) is input to the input terminal of the Schmitt trigger inverter SI. The output signal SS(K) output from the Schmitt trigger inverter SI and the output signal OT(K) output from the Schmitt trigger inverter SI2 are input to the input terminal of the AND circuit AD. An output signal OS(K) is output from the output terminal of the AND circuit AD.

[0055] The capacitive section CNa includes a capacitive element CP3. One end of the capacitive element CP3 is connected to the anode terminal of the photodiode PD, the drain terminal of the nMOS transistor TN1, and the input terminal of the Schmitt trigger inverter SI. The other end of the capacitive element CP3 is connected to the reference voltage section GND.

[0056] (Operation of sensor circuit SCa(K)) Using Figure 7, we will explain the operation in which the detection time DT(K) is detected before the timeout time DU has elapsed. Note that the operation that is the same as the operation example of Embodiment 1 (Figure 3) will not be explained.

[0057] Before time t(K-1), the output signal SS(K) from Schmitt trigger inverter SI and the output signal OT(K) from Schmitt trigger inverter SI2 are at a high level. Therefore, the output signal OS(K) from the AND gate AD is at a high level (arrow Y31). When the output signal OS(K-1) switches from a high level to a low level at time t(K-1), the voltage signal AN(K) rises with a slope of "IS / CP3" (see region A31). Also, the voltage signal AT(K) rises with a slope of "VDD / (RT×CT)" (see region A32).

[0058] When the voltage signal AN(K) reaches the rising logic threshold voltage VT1 of the Schmitt trigger inverter SI at time t(K), the output signal SS(K) inverts from a high level to a low level (see arrow Y32). Consequently, the output signal OS(K) also inverts to a low level (see arrow Y33). As a result, if a detection time DT(K) proportional to the detected amount is detected during the period until the timeout time DU has elapsed, the detection operation is terminated by inverting the output signal OS(K) in response to the detection of detection time DT(K). The subsequent operation is the same as the operation shown in Figure 3 of Example 1, so the explanation is omitted.

[0059] Using Figure 8, we will explain the operation in which the detection time DT(K) is detected after the timeout time DU has elapsed. Note that the operation similar to the operation example in Example 1 (Figure 4) will not be explained.

[0060] At time tt, the voltage signal AT(K) reaches the logic threshold voltage VT2 before the voltage signal AN(K) reaches the rising logic threshold voltage VT1. Therefore, the output signal OT(K) inverts from a high level to a low level (see arrow Y41). Accordingly, the output signal OS(K) output from the AND circuit AD also inverts to a low level (see arrow Y42).

[0061] In other words, the inverting output section IO lowers the output signal OS(K) to a low level regardless of the state of the voltage signal AN(K) when the timer circuit TC detects the elapsed time of the timeout period DU. As a result, if the timeout period DU elapses without detecting the detection period DT(K), the detection operation ends by inverting the output signal OS(K) in accordance with the elapsed timeout period DU.

[0062] (effect) In the sensor 1 of Example 2, if a sensor circuit SCa occurs where the time taken for detection operation exceeds the timeout period DU, the timer circuit TC can forcibly terminate the detection operation at that sensor circuit SCa. This makes it possible to suppress the lengthening of the overall readout time of the sensor array 20. [Examples]

[0063] (Configuration of sensor circuit SCb(K)) Example 3 describes a modified version of the sensor circuit SC(K) (Figure 2) from Example 1. Figure 9 shows the sensor circuit SCb(K) according to Example 3. Parts identical to those in the sensor circuit SC(K) of Example 1 are denoted by the same reference numerals, and their descriptions are omitted.

[0064] Compared to the sensor circuit SC(K) of Example 1, the sensor circuit SCb(K) of Example 3 is equipped with a current switching section CS instead of a photodiode PD, and a variable capacitance element CNb(K) instead of a capacitance section CN. The variable capacitance element CNb(K) is an element that controls the capacitance value variably according to the detected amount.

[0065] The current switching section CS includes resistive elements R1 and R2. Resistive elements R1 and R2 are connected in parallel to each other with respect to the variable capacitance element CNb(K). A switch element SW is placed on the connection path between resistive element R2 and the variable capacitance element CNb(K). The switch element SW is configured to be switchable between a high-impedance state and a low-impedance state by the output signal OT(K) output from the timer circuit TC(K). That is, when the switch element SW is in the high-impedance state, the charging current IC charged to the variable capacitance element CNb(K) can be set to a first current value. When the switch element SW is in the low-impedance state, the combined resistance of the current switching section CS can be reduced, so the charging current IC can be set to a second current value which is greater than the first current value.

[0066] (Operation of sensor circuit SCb(K)) The sensor circuit SCb(K) keeps the switch element SW in a high-impedance state from the start of detection operation until the time-out period DU has elapsed. Therefore, the variable capacitance element CNb(K) is charged with a first current value. Because the first current value is small, the upward slope of the voltage signal AN(K) becomes small, resulting in low responsiveness (larger time constant). The timer circuit TC(K) switches the switch element SW to a low-impedance state as the time-out period DU elapses. Therefore, during the period after the time-out period DU has elapsed, the variable capacitance element CNb(K) is charged with a second current value. Because the second current value is larger than the first current value, the upward slope of the voltage signal AN(K) becomes larger, resulting in high responsiveness (smaller time constant).

[0067] This allows the time constant of the sensor circuit SCb(K) to be reduced as the time-out period DU elapses. Since the responsiveness of the sensor circuit SCb(K) after the time-out period DU has elapsed can be improved, it is possible to suppress the increase in detection time. [Examples]

[0068] (Configuration of sensor circuit SCc(K)) Example 4 describes a modified version of the sensor circuit SCa(K) (Figure 6) from Example 2. Figure 10 shows the sensor circuit SCc(K) according to Example 4. Note that parts identical to those in the sensor circuit SCa(K) of Example 2 and the sensor circuit SCb(K) of Example 3 (Figure 9) are denoted by the same reference numerals, and their explanations are omitted.

[0069] Compared to the sensor circuit SCa(K) of Example 2, the sensor circuit SCc(K) of Example 4 includes a resistor R1 instead of a photodiode PD, and a variable capacitance element CNb(K) instead of a capacitance element CN.

[0070] (Operation of sensor circuit SCc(K)) The sensor circuit SCc(K) continues its detection operation from the start of the detection operation until the timeout period DU has elapsed. When the timer circuit TC detects that the timeout period DU has elapsed, the output signal OT(K) inverts from a high level to a low level. Therefore, regardless of the state of the voltage signal AN(K) output from the variable capacitance element CNc(K), the output signal OS(K) is set to a low impedance state. This allows the detection operation of the sensor circuit SCc(K) to be forcibly terminated if the time taken for the detection operation exceeds the timeout period DU.

[0071] Although specific examples of the present invention have been described in detail above, these are merely illustrative and do not limit the scope of the claims. The technologies described in the claims include various modifications and changes to the specific examples illustrated above. Furthermore, the technical elements described in this specification or drawings exhibit technical usefulness individually or in various combinations, and are not limited to the combinations described in the claims at the time of filing. In addition, the technologies illustrated in this specification or drawings can achieve multiple objectives simultaneously, and achieving even one of these objectives itself constitutes technical usefulness.

[0072] (modified version) The timer circuit TC does not need to be provided in a one-to-one correspondence with all N sensor circuits SC(1) to SC(N). It may be provided for at least one of the sensor circuits SC.

[0073] In this embodiment, a configuration in which the time constant is switched in two stages has been described, but the embodiment is not limited to this. Three or more stages of switching are also possible. Furthermore, the time constant may change continuously.

[0074] In this embodiment, we have described cases where the detection target physical quantity is the detection current IS of the photodiode PD or the capacitance of the variable capacitance element CNb. However, the embodiment is not limited to this, and various physical quantities can be used as detection targets. For example, the resistance value of a variable resistor element may be used as the detection target.

[0075] The configuration of the inverting output IO in Example 2 is just one example. The inverting output IO can be configured using various logic elements.

[0076] The timeout time DU is an example of a predetermined time. The photodiode PD is an example of a current control unit. The Schmitt trigger inverter SI is an example of an inverting output unit. The nMOS transistor TNg is an example of a switching element. [Explanation of symbols]

[0077] 1: Sensor 10: Enable circuit 20: Sensor array 30: Output circuit TC(1)~TC(N): Timer circuit ND(1)~ND(N): NAND circuit OS(1)~OS(N): Output signal OT(1)~OT(N): Output signal LS(1)~LS(N): Logic signal Sout: Serial output signal CN: Capacitance section PD: Photodiode SI: Schmitt trigger inverter

Claims

1. A sensor array comprising N sensor circuits (where N is a natural number greater than or equal to 2), wherein the sensor array has a serial connection in which the output logic signal of the preceding sensor circuit is input as the input logic signal of the next sensor circuit, A timer circuit is provided for each of the aforementioned com circuits, The output circuit receives the input logic signal input to the first stage sensor circuit of the sensor array, as well as the N output logic signals output from each of the N sensor circuits, and outputs a serial output signal, wherein the output circuit inverts the serial output signal in accordance with the inversion of each of the N output logic signals. Equipped with, The timer circuit starts a time measurement operation to measure a predetermined time in response to the inversion of the input logic signal input to the corresponding sensor circuit. The timer circuit, after a predetermined time has elapsed since the start of the time measurement operation, switches the time constant of the corresponding sensor circuit from a first time constant to a second time constant that is smaller than the first time constant. The aforementioned time constant is a parameter that indicates the time required for the detection operation in which the sensor circuit detects a detection time proportional to the detected amount. Each of the N sensor circuits starts the detection operation based on the first time constant in response to the inversion of the input logic signal. Each of the N sensor circuits performs the detection operation based on the second time constant during the period after the predetermined time has elapsed from the start of the detection operation. Each of the N sensor circuits terminates the detection operation by inverting the output logic signal after detecting the detection time. In response to the inversion of the output logic signal of the K-th sensor circuit (where K is a natural number between 1 and N-1), and the termination of the detection operation of the K-th sensor circuit, the detection operation of the K+1-th sensor circuit is initiated. The serial output signal output from the output circuit is configured such that the time interval between consecutive inverted edges corresponds to the detection time detected by the corresponding sensor circuit. The serial output signal is a signal in which N time intervals corresponding to N sensor circuits appear consecutively according to the serial connection order of the N sensor circuits. Sensor.

2. Each of the N sensor circuits is A first capacity unit configured to be switchable between a first capacity value and a second capacity value smaller than the first capacity value, A current control unit that variably controls the charging current to the first capacitance unit according to the detected amount, In response to the output voltage of the first capacitance unit rising to a predetermined voltage, an inverting output unit inverts the output logic signal, It is equipped with, Each of the N sensor circuits charges the first capacitance unit having the first capacitance value during the period from the start of the detection operation until the predetermined time has elapsed. The timer circuit, after the predetermined time has elapsed, switches the capacitance value of the first capacitance section of the corresponding sensor circuit from the first capacitance value to the second capacitance value. Each of the N sensor circuits charges the first capacitance unit having the second capacitance value during the period after the predetermined time has elapsed. The sensor according to claim 1.

3. The first capacitance unit comprises a first capacitance element and a second capacitance element connected in parallel to each other with respect to the inverting output unit. A switch element is placed on the charging path of the second capacitive element. The timer circuit changes the switch element from a low impedance state to a high impedance state as the predetermined time elapses. The sensor according to claim 2.

4. Each of the N sensor circuits is A variable capacitance element that controls the capacitance value variably according to the detected amount, A current switching unit is configured to switch the charging current charged to the variable capacitance element based on the input logic signal between a first current value and a second current value greater than the first current value. An inverting output unit that inverts the output logic signal in response to the output voltage of the variable capacitance element rising to a predetermined voltage, It is equipped with, Each of the N sensor circuits charges the variable capacitance element with the first current value during the period from the start of the detection operation until the predetermined time has elapsed. The timer circuit, after the predetermined time has elapsed, switches the current value of the current switching section of the corresponding sensor circuit from the first current value to the second current value. Each of the N sensor circuits charges the variable capacitance element with the second current value during the period after the predetermined time has elapsed. The sensor according to claim 1.

5. The current switching unit includes a first resistive element and a second resistive element connected in parallel to the variable capacitance element. A switch element is placed on the connection path between the second resistive element and the variable capacitive element. The timer circuit changes the switch element from a high impedance state to a low impedance state as the predetermined time elapses. The sensor according to claim 4.

6. One or more of the timer circuits include a second capacitance unit having a fixed capacitance value, The second capacitance unit is charged with a predetermined current based on the input logic signal in response to the inversion of the input logic signal input to the corresponding sensor circuit. The predetermined time is the time from when the input logic signal is inverted until the output voltage of the second capacitor rises to a predetermined threshold voltage. The sensor according to any one of claims 1 to 5.

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