Verification system and verification method

Abstract

To minimize a time required for verifying a resultant object of large-scale design.SOLUTION: A verification system for verifying whether or not a resultant object of design has been properly designed, includes: satisfiability problem creating means 31 for creating a satisfiability problem on the basis of design information concerning the resultant object of design; CNF creating means 32 for creating CNF by converting the satisfiability problem to a conjunctive normal form; conversion means 33 for converting the CNF to a maximum independent set problem; Hamiltonian setting means 34 for setting a Hamiltonian of an Ising model from the maximum independent set problem; optimum solution obtaining means 38; and properness / improperness determining means 35 for determining satisfiability / unsatisfiability on the basis of the number of quanta that have a spin direction of "1" as obtained.SELECTED DRAWING: Figure 2

Description

Technical Field

[0001] This invention relates to a verification system and a verification method for verifying whether a design result is properly designed or not.

Background Art

[0002] In recent years, for optimization problems including the traveling salesman problem and the design of financial portfolios, as well as design results (solutions) programs, designed programs, and designed logic circuits, there is a problem that a great deal of time is required for debugging and verification. For example, for the verification of a designed logic circuit, formal verification is generally used as a technique to complement the limitations of logic simulation. However, due to its high computational load, this formal verification requires time to prove properties and cannot be applied to large-scale circuits. In addition, special skills are required to master formal verification in order to solve the above problems.

[0003] Patent Document 1 discloses solving a combinatorial optimization problem using a quantum computer, but does not mention the verification of its solution.

[0004] In Patent Document 2, the satisfiability problem (hereinafter referred to as SAT) has come to be used in formal verification. For example, when verifying a gate-level logic circuit, it is introduced that a computer represents the logic circuit as a logical formula in conjunctive normal form (CNF) and determines whether there exists a combination of true and false values of variables that makes the entire logical formula true (“1”). This cited Document 2 discloses an improvement on a method in which, for example, a certain computer (master) divides a logical formula into a plurality of parts and assigns them to a plurality of other computers (clients) to process the divided logical formulas in parallel because the logical formula grows longer as the circuit scale increases.

[0005] Patent Document 3 discloses a solution search system capable of solving various real-world scheduling problems as SAT problems quickly and efficiently using the same circuit for different instances without complicating the algorithm, a solution search method using this solution search system, and a method for realizing this solution search method using a computer system.

[0006] The invention described in Patent Document 3 includes a plurality of data generation units, a fluctuation setting unit that supplies fluctuation probabilities to the data generation units to set the occurrence frequencies of the data generated by the data generation units to be non-uniform, and sets the occurrence frequency of a specific variable to a value different from the occurrence frequencies of other variables. It also includes a plurality of data conversion units that read the data generated by the data generation units and convert it into information, and an output adjustment unit that transmits an output adjustment signal, or an output adjustment signal and a fluctuation probability value, to the data generation units. Furthermore, it includes a feedback control unit that repeatedly controls the operation of transmitting an output adjustment signal, or an output adjustment signal and a fluctuation probability value, to the data generation units if an optimal solution has not been obtained. [Prior art documents] [Patent Documents]

[0007] [Patent Document 1] International Publication No. 2023 / 281742 [Patent Document 2] Japanese Patent Publication No. 2013-246657 [Patent Document 3] Japanese Patent Publication No. 2022-075472 [Overview of the project] [Problems that the invention aims to solve]

[0008] Embodiments of the present invention provide a verification system and verification method that, when verifying large-scale design results, require less time than conventional methods, and do not require any special skills to use these embodiments. [Means for solving the problem]

[0009] A verification system according to an embodiment of the present invention is a verification system for verifying whether a design result is properly designed, comprising: a satisfaction problem creation means for creating a satisfaction problem based on the design information of the design result; a CNF creation means for creating a CNF by converting the satisfaction problem created by the satisfaction problem creation means into a conjunctive normal form; a conversion means for converting the CNF created by the CNF creation means into a maximum independent set problem; a Hamiltonian setting means for setting the Hamiltonian of the Ising model from the maximum independent set problem obtained by the conversion means; an optimal solution acquisition means configured using a quantum computer, which determines the spin direction of quanta that make up a stable state of the set Hamiltonian; and a proper / unproper determination means for determining whether the design result is satisfyable or unsatisfyable based on the number of nodes of the CNF and the number of quanta with a spin direction of "1" obtained by the optimal solution acquisition means. The system includes a repeat execution control means that, based on the first determination result by the appropriate / inappropriate determination means, repeatedly controls the execution process of: recreating the CNF by the CNF creation means, re-converting the recreated CNF to the maximum independent set problem by the conversion means, resetting the Hamiltonian by the Hamiltonian setting means using the re-converted maximum independent set problem, obtaining the optimal solution using the reset Hamiltonian by the optimal solution acquisition means, and making a determination by the appropriate / inappropriate determination means based on the optimal solution obtained using the reset Hamiltonian, as needed. It is characterized by the following:

[0010] A verification method according to an embodiment of the present invention is a verification method for verifying whether a design result is properly designed, comprising: a satisfaction problem creation step of creating a satisfaction problem based on the design information of the design result; a CNF creation step of creating a CNF by converting the satisfaction problem created in the satisfaction problem creation step into conjunctive normal form; a conversion step of converting the CNF created in the CNF creation step into a maximum independent set problem; a Hamiltonian setting step of setting the Hamiltonian of the Ising model from the maximum independent set problem obtained in the conversion step; an optimal solution acquisition step performed using a quantum computer, wherein the optimal solution acquisition step is to find the spin direction of quanta that make up a stable state of the set Hamiltonian; and a proper / improper determination step of determining whether the design result is satisfyable or not based on the number of nodes of the CNF and the number of quanta with a spin direction of "1" obtained in the optimal solution acquisition step. The system includes a repeatable execution control step that, based on the first determination result from the appropriateness / inappropriateness determination step, repeatedly controls the execution process of: recreating the CNF in the CNF creation step, re-converting the recreated CNF to the maximum independent set problem in the conversion step, resetting the Hamiltonian in the Hamiltonian setting step using the re-converted maximum independent set problem, obtaining the optimal solution using the reset Hamiltonian in the optimal solution acquisition step, and making the determination in the appropriateness / inappropriateness determination step based on the optimal solution obtained using the reset Hamiltonian, as needed. It is characterized by the following: [Brief explanation of the drawing]

[0011] [Figure 1] Block diagram of a verification system according to an embodiment of the present invention. [Figure 2] A block diagram of the functional means realized by the arithmetic control unit 12 and the functional means realized by the quantum computer 20 in a verification system according to an embodiment of the present invention. [Figure 3] A flowchart illustrating the operation of the verification system according to an embodiment of the present invention. [Figure 4] A diagram showing AND gates, OR gates, NAND gates, inverters, and their CNF formulas. [Figure 5] This figure shows the results obtained by substituting 1 and 0 for a, b, and c in an AND gate and deriving the value of the CNF equation. [Figure 6] This flowchart shows how to create a CNF expression that combines a CNF expression representing the logic structure of a designed logic circuit with a CNF expression representing a logic structure that does not satisfy the design specifications of the said logic circuit, and then transforms it into a maximum independent set problem. [Figure 7] A diagram showing an example of a CNF formula. [Figure 8] Figure 7 shows a CNF graph created from the CNF formula. [Figure 9] Figure 8 shows a CNF graph illustrating the solution to the Maximum Independent Sets Problem (MIS). [Figure 10] This diagram illustrates how finding the optimal solution involves determining the input (combination of quantum spin directions) that minimizes (makes stable) the value of the Hamiltonian (energy function). [Figure 11] This diagram shows a block diagram of a 1-bit multiplexer, the Verilog logic description of this circuit, the created CNF, and CNFs SVA1 and SVA2 that represent the logically inverted state of the desired operation (specification) of the logic circuit (representing a state where the specification is not met). [Figure 12] This figure shows a CNF graph created from the CNF in Figure 11 according to rules 1 and 2 described above. [Figure 13]A diagram showing SVA1 and SVA2 in FIG. 11 as CNF graphs respectively. [Figure 14] A diagram in which inverted literals in the RTL and SVA1 in FIG. 11 are connected by edges to form one CNF graph, and a diagram showing the CNF graph created from the RTL and SVA1 (where violations exist). [Figure 15] A diagram of the CNF graph created from the RTL and SVA2 (where no violations exist). [Figure 16] A diagram explaining the derivation principle. [Figure 17] A diagram showing unsatisfiability among the determination of satisfiability and unsatisfiability based on the derivation principle. [Figure 18] A flowchart of a process including the derivation principle from quantum computing to the processing operation.

Embodiments for Carrying Out the Invention

[0012] Embodiments of the present invention will be described below with reference to the accompanying drawings. In each figure, the same components are denoted by the same reference numerals, and redundant descriptions are omitted. FIG. 1 shows a block diagram of a verification system according to an embodiment of the present invention. The verification system has a classical ordinary computer 10 and a quantum computer 20, and the computer 10 and the quantum computer 20 are connected by communication interfaces 11 and 21. The computer 10 is provided with an arithmetic control unit 12 composed of a CPU and a storage unit, an input unit 13 for giving data, commands, etc. to the arithmetic control unit 12, and a display unit 14 for outputting data and video.

[0013] FIG. 2 shows functional means realized by the arithmetic control unit 12 of the computer 10 and functional means realized by the quantum computer 20. That is, in the arithmetic control unit 12, there are a satisfiability problem creation means 31, a CNF creation means 32, a conversion means 33, a Hamiltonian setting means 34, a proper / improper determination means 35, a repeated execution process control means 36, and a confirmation means 37, and in the quantum computer 20, there is an optimal solution acquisition means 38.

[0014] The satisfiability problem creation means 31 creates a satisfiability problem (SAT) based on the design information of the design result. While the design result is strongly associated with the terminology related to arguments in logical verification, the present invention is not limited to this and includes the meaning of terms such as "conditions" and "constraints" in finance and logistics. Therefore, the satisfiability problem creation means 31 is intended to reduce the problem to be solved to a SAT. The CNF creation means 32 converts the satisfiability problem created by the satisfiability problem creation means 31 into conjunctive normal form (CNF) to create a CNF. The conversion means 33 converts the CNF created by the CNF creation means 32 into a maximum independent set problem (MIS), and as described later, a CNF graph is created from the CNF formula. The Hamiltonian setting means 34 sets the Hamiltonian of the Ising model from the maximum independent set problem (MIS) obtained by the conversion means 33. The appropriate / inappropriate determination means 35 determines whether the design result is satisfyable or not based on the number of nodes of the CNF and the number of quanta with a spin direction of "1" obtained by the optimal solution acquisition means 38.

[0015] The repetitive execution control means 36 controls the repetitive execution of the following processes as needed, based on the first determination result by the appropriate / inappropriate determination means 35: recreation of the CNF by the CNF creation means 32, resetting of the Hamiltonian by the Hamiltonian setting means 34 using the recreated CNF, acquisition of the optimal solution using the reset Hamiltonian by the optimal solution acquisition means 38, and determination by the appropriate / inappropriate determination means 35 based on the acquisition of the optimal solution using the reset Hamiltonian. The verification means 37, when the appropriate / inappropriate determination means 35 determines that the required CNF formula is not satisfied, repeats the operation based on the derivation principle, assuming that the required CNF formula is satisfied, to obtain a new CNF formula, and detects a logical inconsistency in the new CNF formula to confirm that the required CNF formula is not satisfied. The quantum computer 20's optimal solution acquisition means 38 is configured using the quantum computer 20 and determines the spin direction of the quanta that create a stable state of the set Hamiltonian.

[0016] The design output in this embodiment includes solutions to optimization problems, such as the Traveling Salesperson Problem and the design of a financial portfolio, as well as a designed program and a designed logic circuit. In the following explanation, however, we will use a logic circuit as the design output and verify that it meets the specifications as an example.

[0017] The problem of determining whether a logic circuit satisfies a specification is classified as an NP problem. As it is an NP problem, formal verification reduces it to an NP-complete satisfaction problem (SAT) and solves it from there. By converting it into a conjunctive normal form (CNF) that has all possible states of the logic circuit as satisfaction conditions and determining whether it is satisfiable at the same time as the specification, the validity to the specification can be comprehensively determined. Therefore, in this embodiment, as shown in the processing flowchart of Figure 3, a satisfaction problem is created based on the design information (logical structure of the DUT) of the logic circuit, which is the design result (S11). The design result can be verified using this flowchart if its design information (logical structure of the design result) can be made into a satisfaction problem, even in the case of the Traveling Salesperson Problem, solutions to optimization problems including financial portfolio design, designed programs, and even tools for debugging software such as a "theorem proving support system" and checking the correctness of theorem proofs.

[0018] Here, we will explain CNF (Conjunctive Normal Form). Conjunctional normal form is a type of standardization (normalization) of logical formulas in mathematical logic, specifically in Boolean logic, where logical formulas are represented in the form of a conjunction of disjunctive clauses. Conjunctional normal form is written in the form of a logical conjunction containing one or more logical disjunctions of one or more literals, for example, as follows:

number

[0019] A clause is formed by connecting literals (variables) using a logical OR operation, and CNF is a form where clauses are connected using a logical AND operation. It is known that in CNFs with up to two literals in a clause, the satisfiability problem can be solved in polynomial time, but when there are three or more literals, it becomes NP-complete.

[0020] Converting logic circuits to CNF (Converter-NonFractional) forms results in the format shown in Figure 4. Here, we will discuss AND gates, OR gates, NAND gates, and inverters.

[0021] Here, substituting 1 and 0 for a, b, and c in the AND gate, we obtain the value of the CNF expression as shown in Figure 5. Checking the combinations of variable values ​​for which the calculation result is 1 (satisfied), we find that the relationship is c = (a & b). In other words, the satisfaction condition of the CNF expression converted from a logic circuit is the combination of all possible states that the logic circuit can have.

[0022] The CNF generated from RTL is always satisfied, and the satisfaction condition is all circuit states. The SAT solver searches whether it is possible for this condition to be satisfied simultaneously with a CNF representing a state that does not meet the specifications, which is generated from SVA (System Verilog Assertion). If the satisfaction condition exists in this state, it means that there is a state that the circuit can take that does not meet the specifications, which indicates the existence of a bug.

[0023] As previously explained, the computational resources required for this SAT solver are enormous on classical computers (it's an NP-complete problem). The goal is to reduce the computational flow for conventional formal verification to the Ising model using the flowchart shown in Figure 3, so that it can ultimately be performed using quantum computing.

[0024] In the next step, the created satisfaction problem is converted to conjunctive normal form to create a CNF (S12). In this embodiment, as shown in Figure 6(A), a CNF of the DUT and a CNF of the "negation (NOT)" of the requirements specification are created using SVA, which is used to "reduce visual oversights" and "early detection of bugs," and these are combined with "AND" (Figure 6(B)) to form the final CNF. In other words, in this embodiment, since the design result is a designed logic circuit, in the CNF creation step S12 above, the CNF expression representing the logic structure of the designed logic circuit and the CNF expression representing a logic structure that does not satisfy the design specifications of the logic circuit are combined and then converted to a maximum independent set problem (MIS). The conjunctive normal form (CNF) converted from the logic circuit can be created by mechanically converting it to 3-CNF using Tseitin encoding. In satisfaction problems (SAT), it is known that 2-SAT is P and 3-SAT and above are NP-complete, so SAT solvers assume 3-SAT.

[0025] Next, the CNF created above is transformed into the Maximum Independent Sets Problem (MIS) (S13). Here, the satisfiability problem is reduced to the Ising model in order to solve it using quantum computing. That is, in order to reduce it to the Ising model, the satisfiability problem is first transformed into the Maximum Independent Sets Problem (MIS).

[0026] In this conversion step S13, for 3-CNFs with up to three literals in a clause, a graph is created where the three literals in the clause form a triangle, and for cases with two literals, a graph is created where the literals are connected only by edges, based on the following rules 1 and 2. This graph is then converted into an Ising model. In other words, the graph is treated as the Ising model of MIS and formalized. Rule 1: "If multiple clauses share the same literal, they are not considered vertices in the graph." Rule 2: "Positive and negative literals are also connected by edges."

[0027] According to the rules above, the graph created from the CNF equation shown in Figure 7 is as shown in Figures 8(A) and 8(B). The vertices (literals) of the graph represent quanta, and the value of the literal represents the spin direction of the quantum. The edges of the graph represent the dependencies between quanta. When a positive literal and a negative literal are connected, the edges are indicated by dashed lines.

[0028] The Hamiltonian of the Ising model is set from the maximum independent set problem obtained as described above (S14). In this maximum independent set problem (MIS), a constraint is added during the formulation that adjacent vertices cannot have "1" values ​​relative to each other, so that the ground state of energy represents the optimal solution of the MIS. Also, the more "1" values ​​there are at each vertex, the smaller and more stable the overall energy is. The Hamiltonian (energy function) is set taking these factors into consideration.

[0029] The stable state of the Hamiltonian (energy function) in this Ising model represents the solution to the maximum independent set problem (MIS) of the graph. Neighbors on the dashed edges are not connected by quanta of the same value, and "1"s do not share edges, while the state containing the most "1"s is stable. The number of "1"s at this point is the number of the largest independent set, and it is known that if the maximum number of independent sets is equivalent to the number of nodes in a 3-CNF, then this 3-CNF is satisfiable. Taking these factors into consideration, the stable state of the Hamiltonian (energy function) is obtained when the vertices shown by the white inverted letters in Figure 9 are "1".

[0030] The Hamiltonian (energy function) of the Ising model is expressed by the following equation.

number

[0031] As shown in Figure 10, in quantum computing, finding the optimal solution involves determining the input (combination of quantum spin directions) that minimizes (makes stable) the value of the Hamiltonian (energy function). This process is shown as step S15 in the flowchart in Figure 3.

[0032] If this 3-CNF is a composite of the inverted states of the logic circuit and the requirements specification (Assert Property), as shown in Figure 6(B), then satisfiability indicates that there is a common satisfaction condition among the states that do not satisfy the logic circuit and the requirements specification, i.e., there is a bug (specification violation). On the other hand, when the maximum value of the independent set does not equal the number of nodes in the 3-CNF, it becomes unsatisfiable, and the logic circuit always satisfies the specifications. This process is shown as step S16 in the flowchart of Figure 3.

[0033] Furthermore, when the condition is satisfiable (maximum number of independent sets = number of CNF nodes), the SAT solver can be fed back how the independent sets were extracted from the graph (conditions), allowing a counterexample (bug waveform) to be shown using conventional formal verification methods. When the condition is unsatisfiable, the derivation principle from the CNF equation is used to confirm that empty nodes are generated. Additionally, by deriving new nodes from literals connected by dashed lines on the graph and repeating the operation, if empty nodes are generated, it can be determined that the CNF is unsatisfiable.

[0034] Determining the quantum spin direction that creates a stable state of the Hamiltonian (energy function) of the Ising model is a strength of the quantum annealing machine, quantum computer 20, used in this embodiment. Even with millions to tens of millions of literals, it can find a solution in less time than deterministically calculating an NP problem of the same input size. By comparing the spin direction with the number of nodes in the CNF converted from the logic circuit, it is possible to determine whether the logic circuit meets the specifications.

[0035] In this embodiment, the logic circuit to be verified and the specifications (logical structure) required for that logic circuit are each converted into a 3-CNF equation. A graph is created from the 3-CNF to reduce it to the maximum independent set problem, and it is quantum computed as an Ising model. The result of this quantum computation cannot be guaranteed to be the optimal solution as is. Therefore, the calculation result (determination result) from the quantum computation and the information of the spin direction assigned to the quantum, which is the condition, are fed back to the SAT solver as a 3-CNF equation and the values ​​of each literal.

[0036] In the SAT solver, it is possible to verify the validity of the judgment result by using the result of the quantum computation as a Witness in polynomial time (realistic time). If the SAT solver obtains a result indicating that the quantum computation judgment is incorrect, the accuracy of the solution can be improved by updating the conditions of the CNF graph as a more rigorous interrelationship between quanta for the contradictory literals and re-executing the quantum computation.

[0037] In verifying this embodiment, it is important to confirm the validity of the judgment that the quantum computation result is "unsatisfiable." After confirming that the inverted literals (a pair of a positive literal and a negative literal) in the graph are correctly placed, it can be confirmed that the computation is unsatisfiable if empty nodes (nodes that do not contain any literals) are generated by repeatedly deriving new nodes from the inverted literals.

[0038] In the examples explained in Figures 7 to 10 above, specific examples of the logic circuits to be verified were not shown, but we will explain using a 1-bit multiplexer. Figure 11 shows the block diagram of this 1-bit multiplexer, the Verilog logic description of this circuit, the created CNF, and SVA1 and SVA2, which are CNFs representing the logical inversion of the content (specification) that we want to verify as the operation of the logic circuit (representing a state where the specification is not met).

[0039] When graphs are created from the above CNF according to the previously described rules 1 and 2, they are as shown in Figure 12. SVA1 and SVA2 are also converted into graphs and shown in Figures 13(A) and 13(B), respectively.

[0040] Connecting the inverted literals in RTL and SVA1 with edges to form a single CNF graph results in the graph shown in Figure 14. In other words, Figure 14 shows an attempt to derive the SAT (Maximum Independent Set Problem) – whether RTL and SVA1 can be simultaneously satisfied – by solving the MIS using a CNF graph. The black nodes represent MIS, and since their number is equivalent to the number of CNF nodes, they directly indicate the satisfaction conditions (violations within the circuit) of the CNF. Furthermore, connecting the inverted literals in RTL and SVA2 with edges to form a single CNF graph results in the graph shown in Figure 15. We then solve the MIS (Maximum Independent Sets Problem), which asks how many vertices with the value "1" (white inverted characters) can be placed while ensuring that they are not connected to each other by edges. In Figure 15, the number of CNF nodes and the number of MIS problems are different, indicating that the circuit is unsatisfiable (no violations in the circuit).

[0041] The graph in Figure 14 is created using RTL and SVA1 (where a violation exists), and it can have 7 vertices. This is equivalent to the 7-section number of the CNF created from RTL and SVA1, and it is known that the CNF is satisfiable in such cases. The vertices (variables) that are set to "1" directly indicate a malfunction (violation state) in the logic circuit. In this case, it indicates a violation of the contents of SVA1 with the circuit state S=0, A=0, B=1, C=0 (when S=0, A=C in operation).

[0042] The graph in Figure 15 is a graph created using RTL and SVA2 (no violations), and only six vertices could be placed. In this case, the number of MIS differs from the number of CNF clauses, and the CNF is determined to be unsatisfiable. The Hamiltonian representing this maximum independent set problem using the Ising model is given by the following equation.

number

[0043] SiSj is treated as a logical AND, and a penalty is set by the coefficient J when both Si and Sj are 1. On the other hand, h gives a bonus when Si is 1. In other words, the maximum number of states for each vertex that minimizes the value of this entire equation occurs when no "1"s are placed next to each other. A quantum computer, which is a quantum annealer, can find the solution to this calculation in an extremely short time. If a satisfaction determination is obtained in the graph of Figure 14, as mentioned earlier, the final state of the vertex can be fed back into the logic circuit to verify whether the obtained solution is correct. In contrast, if an unsatisfactory determination is obtained in the graph of Figure 15, it means that "there are no satisfaction conditions," so it is not possible to verify whether or not the condition is actually satisfied.

[0044] To verify the above, in this embodiment, if the appropriate / inappropriate determination means 35 determines that the required CNF formula cannot be satisfied, the verification means 37 is provided to confirm that the required CNF formula cannot be satisfied by repeating the operation based on the derivation principle, assuming that the required CNF formula is satisfied, and detecting a logical inconsistency in the new CNF formula.

[0045] First, let me explain the derivation principle. If the CNF formula is satisfyable, then each clause in the satisfaction condition must be 1. If (A|B|C) and (D|E|F) = 1, then (A|B|C) = 1 and (D|E|F) = 1. On the other hand, the fact that ((A→B)&(B→C))→(A→C) is always true. (Deductive reasoning / syllogism) If ((A→B)&(B→C))=1, then (A→C)=1 is always true. In other words, if ((!A|B)&(!B|C))=1, (!A|C)=1 always holds true.

[0046] As shown in Figure 16, ((!A|B)&(!B|C)) is of the form 2CNF, where B is an inverted literal that spans a clause. In Figure 14, it is declared that if this CNF expression is =1 (i.e., satisfied), then (!A|C)=1. Therefore, it is shown that the inverted literals B and !B can be removed, and the remaining literals can be joined by a logical OR operation to form a new clause that is also satisfied.

[0047] Using the inverted literal deletion technique described above, if a logical contradiction arises during the process of repeatedly performing operations based on the derivation principle, it is possible to prove that the CNF formula is unsatisfactory using proof by contradiction (this is called a refutation).

[0048] Returning to the CNF graph shown in Figure 12, which was created from RTL and SVA2, the following equation holds true.

number

[0049] (1) Since there is a single literal "S", if CNF is satisfied, then S=1 is confirmed. The entire clause containing S and the literal !S can be removed from the clause. The result is as follows:

number

[0050] (2) When the derivation principle is applied to C, which has the most connections among the inverted literals {B,C} connected by C6 that could not be made into independent sets, the result is as follows. (!B|C),(B|!C) [Derive a new clause from (1) and (2)] →(B|!B)=1 (!B|C),(!B|!C) [Derive a new clause from (1) and (3)] →(!B|!B) =!B (B|C),(B|!C) [Derive a new clause from (4) and (2)] →(B|B)=B (B|C),(!B|!C) [Derive a new clause from (4) and (3)] →(B|!B)=1

[0051] Delete the original clause above and create a CNF (connected by AND) with the new clauses [(B|!B)=1], [(!B|!B) =!B], [(B|B)=B], and [(B|!B)=1]. As a result, 1&!B&B&1=1, which is !B&B=1. As a result, the satisfiability / unsatisfiability result is a contradictory logical formula as shown in Figure 17, so "satisfaction is impossible".

[0052] Because the graphs generated from actual logic circuits are enormous, it is necessary to find where inverted literals that span across clauses exist in order to refute them. This is known information from when the CNF graph is constructed. Furthermore, it is known which clauses cannot have a vertex of "1" as a result of solving the MIS, and the inverted literals that these clauses share with other clauses are also known. By using this information in the refutation proof, it is possible to perform efficient derivation principle processing operations and confirm unsatisfiability. The flowchart of this process is shown in Figure 18.

[0053] Step S21 involves obtaining the optimal solution by quantum computation and determining whether the solution is satisfactory or unsatisfactory based on that solution. If it is determined to be satisfactory, a verification operation is performed by the SAT solver using feedback of the spin state (Step S22). If it is determined to be satisfactory, the derivation principle described above is processed (Step S23). The results of Step S23 are obtained, indicating whether there is a contradiction or not. If the obtained result is contradictory, a determination of unsatisfactoriness is made, and if the output is not contradictory, an inverted literal is detected by creating a CNF graph (Step S24). If the detection of an inverted literal indicates "yes", the process is repeated to Step S23. If the detection of an inverted literal indicates "no", a determination of satisfaction is made. The above processes are performed.

[0054] Even when the CNF is unsatisfiable, the MIS calculation still appears to be seeking the maximum number of independent sets that can be set. While it is uncertain whether the difficulty of the problem differs on the quantum annealer when the number of maximum independent sets is equal to the number of clauses and when it is one less, both cases still represent the optimal solution. If the difficulty level remains unchanged, it seems that the game is reaching the "unsatisfyable" judgment with the same precision as it is generating bugs. On the other hand, if the difficulty level changes (increases), there is a possibility that the game is misjudging the "unsatisfyable" state, and there is a problem in that it is difficult to distinguish this from the outside.

[0055] In this embodiment, we have listed a method using the derivation principle as a way to directly confirm unsatisfactoriness, but it is important whether the efficiency of the processing operation can be improved by using the derivation principle. If unsatisfactoriness is determined, reliability can be demonstrated if the same result is obtained by changing the initial state or conditions (parameters) and recalculating several times, so such methods can also be considered.

[0056] For the above recalculation, this embodiment includes a repeat execution control means 36 that, as necessary, repeatedly controls the execution process of the following steps based on the first determination result by the appropriate / inappropriate determination means 35: recreation of the CNF by the CNF creation means 32, re-conversion to the maximum independent set problem by the conversion means 33 using the recreated CNF, resetting of the Hamiltonian by the Hamiltonian setting means 34 using the re-converted maximum independent set problem, obtaining the optimal solution using the reset Hamiltonian by the optimal solution acquisition means 38, and determination by the appropriate / inappropriate determination means 35 based on the optimal solution acquisition using the reset Hamiltonian.

[0057] As described above, this embodiment uses the above-mentioned suitability / inappropriateness determination based on obtaining the optimal solution using the Hamiltonian to solve problems related to processing time and skill, such as the number of branches in a program or the circuit size in a logic circuit, thereby improving the performance of the verification system. Furthermore, when applied to the LSI field, it leads to a reduction in the man-hours required for product development and improves competitiveness. [Explanation of symbols]

[0058] 10 Computers 11,21 Communication Interface 12. Arithmetic Control Unit 13 Input section 14 Display section 20 Quantum Computers 31. Methods for creating satisfaction problems 32 CNF creation means 33 Conversion means 34 Hamiltonian setting means 35. Methods for determining suitability / inappropriateness 36. Repetitive execution processing control means 37. Verification methods 38. Means for obtaining the optimal solution

Claims

1. In a verification system that verifies whether the design result is properly designed, A means for creating a satisfaction problem based on the design information of the aforementioned design result, A CNF creation means that converts the satisfaction problem created by the satisfaction problem creation means into conjunctive normal form and creates a CNF, A transformation means that converts the CNF created by the CNF creation means into a maximum independent set problem, A Hamiltonian setting means for setting the Hamiltonian of the Ising model from the maximum independent set problem obtained by the conversion means, An optimal solution acquisition means configured using a quantum computer, comprising: an optimal solution acquisition means for determining the spin direction of quanta that create a stable state of the set Hamiltonian; An appropriate / inappropriate determination means for determining whether the design result is satisfyable or not based on the number of nodes of the CNF and the number of quanta with a spin direction of "1" obtained by the optimal solution acquisition means, Based on the first determination result by the appropriate / inappropriate determination means, the repetitive execution control means controls the process of repeatedly executing, as necessary, the following steps: recreation of the CNF by the CNF creation means, re-conversion to the maximum independent set problem by the conversion means using the recreated CNF, resetting of the Hamiltonian by the Hamiltonian setting means using the re-converted maximum independent set problem, acquisition of the optimal solution using the reset Hamiltonian by the optimal solution acquisition means, and determination by the appropriate / inappropriate determination means based on the optimal solution acquisition using the reset Hamiltonian. A verification system characterized by having the following features.

2. The verification system according to claim 1, characterized in that the appropriate / inappropriate determination means determines whether the design result is satisfyable or not by comparing the number of quanta with a spin direction of "1" with the number of nodes of the CNF converted from the logic circuit.

3. The verification system according to claim 1, characterized in that the conversion means creates a graph in which, for 3-CNFs with up to three literals in a clause, the three literals in the clause form triangles with vertices, and for cases with two literals, the literals are connected only by edges, based on the following rules 1 and 2, and this graph is an Ising model. Rule 1: "If multiple clauses share the same literal, they should not be overlapped as vertices in the graph." Rule 2: "Positive and negative literals are also connected by edges."

4. The verification system according to claim 1, further comprising a verification means for confirming that the required CNF formula is unsatisfactory when the appropriate / unsatisfactory determination means determines that it is unsatisfactory, by repeating the operation based on the derivation principle assuming that the required CNF formula is satisfied, and detecting a logical inconsistency in the new CNF formula.

5. The verification system according to claim 1, characterized in that the design results include the Traveling Salesperson Problem, solutions to optimization problems including the design of a financial portfolio, a designed program, and a designed logic circuit.

6. The verification system according to claim 1, wherein the design result is a designed logic circuit, and the CNF creation means creates a CNF expression by combining a CNF expression representing the logic structure of the designed logic circuit and a CNF expression representing a logic structure that does not satisfy the design specifications of the logic circuit, and then converts it into the conversion means.

7. In a verification method for verifying whether a design result is properly designed, A satisfaction problem creation step, which involves creating a satisfaction problem based on the design information of the aforementioned design result, A CNF creation step involves converting the satisfiability problem created in the satisfiability problem creation step into conjunctive normal form and creating a CNF, A transformation step to convert the CNF created by the CNF creation step into a maximum independent set problem, A Hamiltonian setting step is performed to set the Hamiltonian of the Ising model from the maximum independent set problem obtained in the above transformation step, An optimal solution acquisition step performed using a quantum computer, comprising: an optimal solution acquisition step that determines the spin direction of quanta that create a stable state of the set Hamiltonian; A suitability determination step that determines whether the design result is satisfyable or not based on the number of nodes of the CNF and the number of quanta with a spin direction of "1" obtained in the optimal solution acquisition step, Based on the first determination result from the appropriateness / inappropriateness determination step, a repetitive execution control step controls the process of repeatedly executing, as necessary, the following steps: recreating the CNF in the CNF creation step, re-converting the recreated CNF to the maximum independent set problem in the conversion step, resetting the Hamiltonian in the Hamiltonian setting step using the re-converted maximum independent set problem, obtaining the optimal solution using the reset Hamiltonian in the optimal solution acquisition step, and making the determination in the appropriateness / inappropriateness determination step based on the optimal solution obtained using the reset Hamiltonian. A verification method characterized by comprising the following features.

8. The verification method according to claim 7, characterized in that the appropriateness determination step determines whether the design result is satisfactory or not by comparing the number of quanta with a spin direction of "1" with the number of nodes of the CNF converted from the logic circuit.

9. The verification method according to claim 7, characterized in that, in the conversion step, for 3-CNFs with up to three literals in a clause, a graph is created with the three literals in the clause as vertices, and for cases with two literals, a graph is created with only edges connecting the literals, based on the following rules 1 and 2, and this graph is used as an Ising model. Rule 1: "If multiple clauses share the same literal, they should not be overlapped as vertices in the graph." Rule 2: "Positive and negative literals are also connected by edges."

10. The verification method according to claim 7, characterized in that, if it is determined that the requirements cannot be satisfied in the appropriateness determination step, the verification step further comprises a confirmation step to confirm that the requirements CNF formula cannot be satisfied by repeating the operation based on the derivation principle, assuming that the required CNF formula is satisfied, and detecting a logical inconsistency in the new CNF formula.

11. The verification method according to claim 7, characterized in that the design results include the Traveling Salesperson Problem, the solution to an optimization problem including the design of a financial portfolio, the designed program, and the designed logic circuit.

12. The verification method according to claim 7, wherein the design result is a designed logic circuit, and the CNF creation step is characterized in that a CNF expression is created by combining a CNF expression representing the logic structure of the designed logic circuit and a CNF expression representing a logic structure that does not satisfy the design specifications of the logic circuit, and then converting it to the conversion step.

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