Sequence pattern generator and sequence pattern generation method

Abstract

The present invention provides a sequence pattern generator capable of generating sequence patterns including EDS patterns. [Solution] The sequence pattern generator 7 comprises a sequence pattern generation unit 12 that generates sequence patterns consisting of data patterns and control patterns in block units, and an EDS insertion unit 14 that is set for each block of the sequence pattern and inserts an EDS pattern at the end of the data pattern of the block before scrambling.

Description

Technical Field

[0001] The present invention relates to a sequence pattern generation device and a sequence pattern generation method for generating an arbitrary sequence pattern conforming to a standard.

Background Art

[0002] In recent years, various digital communication devices have been required to have a larger transmission capacity with the increase in the number of users and the spread of multimedia communication. For this reason, higher speed and larger capacity are required for network servers and the like. Also, PCI Express (PCIe), which is a communication standard generally used in server node internal communication, is naturally required to be faster. In recent years, PCI Express 6.0 (PCIe Gen6) has been standardized, and product development has been actively promoted. Along with this, the sequence pattern generation function is also required to support the new standard PCIe6.

[0003] By the way, as an index for evaluating the quality of digital signals in digital communication devices, the bit error rate (BER), which is defined as the comparison between the number of bit errors that occur in the received data and the total number of received data, is known.

[0004] As a device for measuring the above bit error rate, for example, as disclosed in Patent Document 1 below, a test signal including fixed data is transmitted to a measurement object to be measured, and the measured signal input through the measurement object and a reference signal serving as a reference are compared bit by bit to measure the error rate of the measured signal. An error rate measurement device has been conventionally known.

[0005] And, as a sequence pattern generation device used in this type of error rate measurement device, there is known one having a function of creating, editing, and outputting an arbitrary sequence pattern conforming to the PCI Express 1.0 - 5.0 (PCIe Gen1 - 5) standard.

Prior Art Documents

Patent Documents

[0006] [Patent Document 1] Japanese Patent Publication No. 2007-274474 [Overview of the project] [Problems that the invention aims to solve]

[0007] However, conventional sequence pattern generators lacked the functionality to arbitrarily insert EDS (End of Data Stream) patterns into the sequence pattern generation. Therefore, users were unable to receive and debug sequence patterns containing EDS patterns.

[0008] Therefore, the present invention has been made in view of the above problems, and aims to provide a sequence pattern generator and a sequence pattern generator that can generate a sequence pattern including an EDS pattern. [Means for solving the problem]

[0009] To achieve the above objective, the sequence pattern generator described in claim 1 of the present invention includes a sequence pattern generation unit 12 that generates sequence patterns consisting of data patterns and control patterns in block units, An EDS pattern is set for each block of the sequence pattern, and an EDS insertion unit 14 inserts the EDS pattern at the end of each block's data pattern before scrambling, The system includes an operation unit 2 in the pattern setting screen that, when the initial value of the EDS pattern for each block of the sequence pattern is set to OFF and disabled, and when SKP OS insertion is OFF and a pattern type is set, selects the EDS pattern from the selection range of the pull-down menu and selects whether or not to reset the SKP insertion timing for each block. A sequence pattern generator , When the EDS insertion unit inserts an SKP OS at the beginning of a block and resets the SKP insertion timing, it overwrites the end of the data pattern of the block preceding the block into which the SKP OS was inserted by inserting the EDS pattern associated with the SKP OS at the beginning of the block. death, When multi-lane support is enabled, the number of sequence pattern generators corresponding to the number of lanes defined in the standard are connected to the device control unit 6 of the measuring device 1, and when the object to be measured W receives the sequence pattern, the setting patterns corresponding to the number of lanes to be recognized as the EDS pattern are distributed to the sequence pattern generators and set in a predetermined block. When one sequence pattern generator is connected to the device control unit as the sequence pattern generator, the setting pattern of the one sequence pattern generator is set to "1F 80 90 00" in a predetermined block. It is characterized by doing so.

[0010] The sequence pattern generator described in claim 2 of the present invention is A sequence pattern generation unit 12 generates sequence patterns consisting of data patterns and control patterns in block units, An EDS pattern is set for each block of the sequence pattern, and an EDS insertion unit 14 inserts the EDS pattern at the end of each block's data pattern before scrambling, A sequence pattern generator comprising: an operation unit 2 in a pattern setting screen, in which the initial value of the EDS pattern for each block of the sequence pattern is set to OFF and disabled, and when SKP OS insertion is OFF and a pattern type is set, the operation unit 2 selects and sets the EDS pattern from a selection range in a pull-down menu, and selects and sets whether or not to reset the SKP insertion timing for each block, When the EDS insertion unit inserts an SKP OS at the beginning of a block and resets the SKP insertion timing, it overwrites the end of the data pattern of the block preceding the block into which the SKP OS was inserted with the EDS pattern associated with the SKP OS at the beginning of the block. When multi-lane support is enabled, the number of sequence pattern generators corresponding to the number of lanes defined in the standard are connected to the device control unit 6 of the measuring device 1, and when the object to be measured W receives the sequence pattern, the setting patterns corresponding to the number of lanes to be recognized as the EDS pattern are distributed to the sequence pattern generators and set in a predetermined block. When two sequence pattern generators are connected to the device control unit as the sequence pattern generators, the setting pattern of one sequence pattern generator is set to "1F 90" in a predetermined block, and the setting pattern of the other sequence pattern generator is set to "80 00". It is characterized by being set in a predetermined block.

[0011] The sequence pattern generator described in claim 3 of the present invention is A sequence pattern generation unit 12 generates sequence patterns consisting of data patterns and control patterns in block units, An EDS pattern is set for each block of the sequence pattern, and an EDS insertion unit 14 inserts the EDS pattern at the end of each block's data pattern before scrambling, A sequence pattern generator comprising: an operation unit 2 in a pattern setting screen, in which the initial value of the EDS pattern for each block of the sequence pattern is set to OFF and disabled, and when SKP OS insertion is OFF and a pattern type is set, the operation unit 2 selects and sets the EDS pattern from a selection range in a pull-down menu, and selects and sets whether or not to reset the SKP insertion timing for each block, When the EDS insertion unit inserts an SKP OS at the beginning of a block and resets the SKP insertion timing, it overwrites the end of the data pattern of the block preceding the block into which the SKP OS was inserted with the EDS pattern associated with the SKP OS at the beginning of the block. When multi-lane support is enabled, the number of sequence pattern generators corresponding to the number of lanes defined in the standard are connected to the device control unit 6 of the measuring device 1, and when the object to be measured W receives the sequence pattern, the setting patterns corresponding to the number of lanes to be recognized as the EDS pattern are distributed to the sequence pattern generators and set in a predetermined block. As the sequence pattern generator The four sequence pattern generators control the device. department When connected, the first sequence pattern generator is set to "1F" in a predetermined block as its setting pattern, the second sequence pattern generator is set to "80" in a predetermined block as its setting pattern, the third sequence pattern generator is set to "90" in a predetermined block as its setting pattern, and the fourth sequence pattern generator is set to "00" in a predetermined block as its setting pattern.

[0012] Claims of the present invention 4 The sequence pattern generation method described includes the step of generating a sequence pattern consisting of a data pattern and a control pattern in block units, An EDS pattern set for each block of the sequence pattern, comprising the step of inserting the EDS pattern at the end of the data pattern for each block before scrambling; On the pattern setting screen, when the initial value of the EDS pattern for each block of the sequence pattern is set to OFF and invalid by the operation of the operation unit 2, and the insertion of SKP OS is OFF and the pattern type is set, the EDS pattern is selected and set from the selection range of the pull-down menu by the operation of the operation unit; On the pattern setting screen, the step of selectively setting for each block whether to reset the SKP insertion timing by the operation of the operation unit; When inserting SKP OS at the head of a block to reset the SKP insertion timing, the step of overwriting and inserting the EDS pattern associated with the SKP OS at the head of the block at the end of the data pattern of the block before the block into which the SKP OS is inserted; In the case of multi-lane support, the number of sequence pattern generators corresponding to the number of lanes defined in the standard is connected to the device control unit 6 of the measuring device 1, and when the object to be measured W receives the sequence pattern, the setting patterns corresponding to the number of lanes to be recognized as the EDS pattern are distributed to the sequence pattern generators and set in a predetermined block, When one sequence pattern generator is connected to the device control unit as the sequence pattern generator, the steps include setting "1F 80 90 00" as the setting pattern of the one sequence pattern generator to a predetermined block, characterized by including the above.

[0013] The sequence pattern generation method according to claim 5 of the present invention is A step of generating a sequence pattern consisting of a data pattern and a control pattern in block units, An EDS pattern set for each block of the sequence pattern, comprising the step of inserting the EDS pattern at the end of each block's data pattern before scrambling, In the pattern setting screen, the initial value of the EDS pattern for each block of the sequence pattern is set to OFF and disabled by operation of the operation unit 2, and when SKP OS insertion is OFF and a pattern type is set, the EDS pattern is selected and set from the selection range of the pull-down menu by operation of the operation unit. In the pattern setting screen, the step of selecting whether or not to reset the SKP insertion timing for each block by operating the operation unit, When an SKP OS is inserted at the beginning of a block to reset the SKP insertion timing, the EDS pattern associated with the SKP OS at the beginning of the block is overwritten and inserted at the end of the data pattern of the block preceding the block in which the SKP OS was inserted. When corresponding to multiple lanes, connecting a number of sequence pattern generators corresponding to the number of lanes defined by the standard to the device control unit 6 of the measuring device 1, and distributing a setting pattern corresponding to the number of lanes for recognizing as the EDS pattern when the object under measurement W receives the sequence pattern to the sequence pattern generator and setting it in a predetermined block and, When two sequence pattern generators are connected to the device control unit as the sequence pattern generators, the steps include setting "1F 90" as the setting pattern of one sequence pattern generator to a predetermined block, and setting "80 00" as the setting pattern of the other sequence pattern generator to a predetermined block, characterized by including the above.

[0014] Claims of the present invention 6 The sequence pattern generation method described is A step of generating a sequence pattern consisting of a data pattern and a control pattern in block units, An EDS pattern set for each block of the sequence pattern, comprising the step of inserting the EDS pattern at the end of each block's data pattern before scrambling, In the pattern setting screen, the initial value of the EDS pattern for each block of the sequence pattern is set to OFF and disabled by operation of the operation unit 2, and when SKP OS insertion is OFF and a pattern type is set, the EDS pattern is selected and set from the selection range of the pull-down menu by operation of the operation unit. In the pattern setting screen, the step of selecting whether or not to reset the SKP insertion timing for each block by operating the operation unit, When an SKP OS is inserted at the beginning of a block to reset the SKP insertion timing, the EDS pattern associated with the SKP OS at the beginning of the block is overwritten and inserted at the end of the data pattern of the block preceding the block in which the SKP OS was inserted. In the case of multi-lane support, the number of sequence pattern generators corresponding to the number of lanes defined in the standard is connected to the device control unit 6 of the measuring device 1, and when the object to be measured W receives the sequence pattern, the setting patterns corresponding to the number of lanes to be recognized as the EDS pattern are distributed to the sequence pattern generators and set in a predetermined block, As the sequence pattern generator The four sequence pattern generators control the device. department When connected, the first sequence pattern generator sets the setting pattern to "1F" in a predetermined block, the second sequence pattern generator sets the setting pattern to "80" in a predetermined block, the third sequence pattern generator sets the setting pattern to "90" in a predetermined block, and the fourth sequence pattern generator sets the setting pattern to "00" in a predetermined block. and, It is characterized by including. [Effects of the Invention]

[0015] According to the present invention, it is possible to generate a sequence pattern that includes an EDS pattern compliant with the standard. This allows for operational verification by performing a reception test to confirm whether the object under test transitions to a desired state including loopback, and to perform debugging based on the results of the reception test of the object under test. [Brief explanation of the drawing]

[0016] [Figure 1] This is a block diagram showing a schematic configuration of a measuring device including a sequence pattern generator according to the present invention. [Figure 2] This figure shows an example of a pattern setting screen. [Figure 3] This is an explanatory diagram showing the procedure for overwriting and inserting an EDS file. [Figure 4] This figure shows an example of an overwrite insertion of an EDS. [Figure 5] This figure shows an example of what happens when an EDS is overwritten and inserted during a reset setting. [Figure 6] This diagram shows the relationship between the setting values, setting patterns, and the symbols corresponding to the setting patterns when multi-lane support is enabled. [Figure 7] This is a flowchart for overwriting and inserting an EDS file. [Modes for carrying out the invention]

[0017] The embodiments for carrying out the present invention will be described in detail below with reference to the attached drawings.

[0018] As shown in Figure 1, the measuring device 1 is generally configured to include an operation unit 2, a clock module 3, a measurement module 4, a display unit 5, a device control unit 6, and a sequence pattern generator 7. Multiple modules (such as the clock module 3, measurement module 4, and modularized sequence pattern generator 7) can be freely added, removed, and rearranged in slots not shown, allowing for various measurements of the object to be measured W in accordance with standards in various configurations.

[0019] The operation unit 2 includes, for example, a pointing device such as a mouse or touchscreen for operating pointers and icons on the display screen of the display unit 5, and keys, switches, buttons, etc., provided on the main body of the measuring device 1.

[0020] The operation unit 2 includes settings related to the overwrite insertion of an EDS (End of Data Stream) pattern consisting of a specific bit sequence pattern corresponding to the SDS (Start of Data Stream) pattern (settings for "Interval with EDS" 21a, "EDS+SKP OS Insertion Type" 21b, and "EDS+SKP OS Reset" 21c in the pattern setting screen 21 of Figure 2, described later), as well as block-by-block settings for sequence patterns compliant with the standards generated by the sequence pattern generator 7 (settings for "Symbol Length" 21d, "Interval" 21e, "Block No." 21f, "Break" 21g, "Pattern Type" 21h, "Bitrate" 21i, "Pattern" 21j, "Pattern Length" 21k, "SKP OS Insertion" 21l, "SKP OS Reset" 21m, and "EIEOSQ" in the pattern setting screen of Figure 2). Insertion (21n, etc.) allows you to perform operations related to receiving tests of the object W under test and various measurements, such as issuing commands to start and stop measurements, specifying the measurement channel for setting measurement parameters, and setting / changing / referencing measurement parameters on the settings screen.

[0021] The clock module 3 consists of a clock generator and generates a reference clock signal (1 / 2 half-rate clock or full-rate clock) for input to the sequence pattern generator 7.

[0022] Furthermore, the clock module 3 is not limited to a configuration that can be attached to and detached from a slot (not shown) in the measuring device 1; an external clock generator separate from the measuring device 1 can also be used.

[0023] The measurement module 4 performs various measurements of the object under test W (such as measuring the error rate after the object under test W is transitioned to a loopback) based on the set values ​​of the measurement parameters set by the operation of the operation unit 2.

[0024] The display unit 5 is composed of, for example, a liquid crystal display provided on the main body of the measuring device 1, and displays a setting screen for initial setup performed by the operation unit 2, a pattern setting screen for generating a desired sequence pattern, a setting screen for a predetermined measurement channel, a measurement screen, etc., on the display screen.

[0025] Here, Figure 2 shows an example of the pattern setting screen 21 displayed on the display unit 5. The pattern setting screen 21 in Figure 2 displays the set sequence patterns. The sequence patterns set for each row are output from the sequence pattern generator 7 in the order of the column numbers of "Block No." 21f on the sequence pattern setting screen 21.

[0026] Furthermore, if a value is set in the "Break" column 21g on the sequence pattern setting screen 21, the sequence may pause at the row (block) where the Break setting is applied, and the output of the pattern set for that row may continue.

[0027] In the pattern setting screen 21 of Figure 2, the "Interval with EDS" (input box) 21a is used to set the SKP interval for blocks where EDS pattern overwrite insertion is enabled, as a setting related to the EDS pattern. The "Interval with EDS" (input box) 21a can be set to an initial value of, for example, 375 Blocks, and the SKP interval can be set within a setting range of 20 to 750 Blocks at 1 Block / Step.

[0028] In the example in Figure 2, the SKP interval: "Interval with EDS" (input box) 21a of the block where EDS pattern overwrite insertion is enabled is set to "20".

[0029] In the pattern setting screen shown in Figure 2, the "EDS+SKP OS Insertion Type" 21b is set by selecting the EDS pattern for each block from a pull-down menu. In "EDS+SKP OS Insertion Type" 21b, the EDS pattern for each block is initially set to OFF and disabled. When "SKP OS Insertion" 21l is OFF and "Pattern Type" 21h is 128b or 130b, the following selection range is selected from the pull-down menu: 1. OFF, 2. 1Lane (1F 80 90 00), 3. 1LaneR (00 90 80 1F), 4. 2Lane Ch0 (1F 90), 5. 2Lane Ch1 (80 00), 6. 2Lane Ch0 R (90 1F), 7. 2Lane Ch1 R (00 80), 8. 4Lane Ch0 (1F), 9. 4Lane Ch1 (80), 10. 4Lane Ch2 (90), 11. 4Lane Ch3 (00). For example, the case where "Pattern Type" 21h is 128b130b was explained, but it may be possible to change it as needed to, for example, 1b1b, 8b10b, etc.

[0030] In "EDS+SKP OS Insertion Type" 21b, when the EDS pattern for each block is enabled, the SKP interval is internally switched to EDS+SKP Interval and the EDS pattern is overwritten and inserted into the data pattern immediately before the SKP; when disabled, the existing operation is maintained.

[0031] In the example in Figure 2, in "EDS+SKP OS Insertion Type" 21b, "1Lane (1F 80 90 00)" is selected from the pull-down menu and set in block #10 of "Block No." 21f, and "2Lane Ch1 R (00 80)" is selected from the pull-down menu and set in block #11 of "Block No." 21f.

[0032] In the pattern setting screen 21 of Figure 2, "EDS+SKP OS Reset" 21c, like "SKP OS Reset" 21m, allows you to set whether to reset the SKP insertion timing for each block by selecting "ON" or "OFF" from a pull-down menu. In "EDS+SKP OS Reset" 21c, if the initial value of each block is set to OFF and disabled, and "EDS+SKP OS Insertion Type" 21b is anything other than OFF, either OFF or ON is selected.

[0033] When "EDS+SKP OS Reset" 21c is ON, it inserts an SKP at the beginning of the block (timing reset) and overwrites the last data pattern of the previous block with the EDS pattern associated with the SKP OS at the beginning of the block. Conversely, when OFF, it follows the settings of "Interval with EDS" 21a.

[0034] In the example in Figure 2, the SKP insertion timing for all blocks visible on the screen (blocks #1 to #12) is set to "OFF" in "EDS+SKP OS Reset" 21c. However, to reset the SKP insertion timing, you must select "ON" for each block.

[0035] The device control unit 6 is composed of a microcomputer equipped with, for example, a CPU, ROM, RAM, etc., and comprehensively controls the operation unit 2, clock module 3, measurement module 4, display unit 5, and sequence pattern generator 7, including setting control of each module based on the operation of the operation unit 2, variable bitrate control, output control of the reference clock signal, various measurement control of the object under test W based on the measurement signal, and display control of setting screens and measurement screens, including the pattern setting screen 21 in Figure 2.

[0036] Next, the configuration of the sequence pattern generator 7, which is the main component of the present invention, will be described.

[0037] As shown in Figure 1, the sequence pattern generator 7 is configured to include an internal clock generation unit 11, a sequence pattern generation unit 12, a data generation control unit 13, an EDS insertion unit 14, and a data multiplexing unit 15.

[0038] The sequence pattern generator 7 has the function of generating a sequence pattern that includes an EDS pattern conforming to a predetermined standard. In this embodiment, the predetermined standard is the PCI Express 3.0 (PCIe Gen3 or later standard) in which the EDS pattern is defined, but it is not limited to this. In other words, any standard that defines an EDS pattern similar to that of PCIe Gen3 or later can be applied.

[0039] The internal clock generation unit 11 generates a clock signal necessary for the generation of a sequence pattern by the sequence pattern generation unit 12 (data generation by the data generation unit 12a and control pattern generation by the control pattern generation unit 12b, which will be described later) based on the reference clock signal from the clock module 3.

[0040] To further explain, the internal clock generation unit 11 is configured with a 1 / N frequency divider (N: a positive integer of 2 or more) and a delay unit. The 1 / N frequency divider outputs a divided clock signal obtained by dividing the reference clock signal generated by the clock module or an external clock source by 1 / N. The delay unit adjusts the delay amount by varying the phase angle of the divided clock signal output from the 1 / N frequency divider so that the sequence pattern input to the data multiplexing unit 17 and the reference clock signal have an optimal phase relationship. This clock signal with the adjusted delay amount is output as a timing signal to the sequence pattern generation unit 12 (data generation unit 12a and control pattern generation unit 12b, which will be described later).

[0041] As shown enclosed by the dotted line in Figure 1, the sequence pattern generation unit 12 is configured to include a data generation unit 12a, a control pattern generation unit 12b, and a selector unit 12c, and generates sequence patterns consisting of data patterns and control patterns in block units.

[0042] The data generation unit 12a generates block-level data compliant with the standard at the timing of the clock signal from the internal clock generation unit 11, under the control of the data generation control unit 13. In the case of PCIe Gen1-6, the generated patterns differ for each Gen, so a data generation unit 12a is provided for each Gen, and block-level data is generated for each PCIe Gen1-6.

[0043] The control pattern generation unit 12b generates control patterns (SKP, EIEOS, etc.) at the timing of the clock signal from the internal clock generation unit 11, under the control of the data generation control unit 13.

[0044] The selector unit 12c, under the control of the data generation control unit 13, selects data generated by the data generation unit 12a and control patterns (SKP, EIEOS, etc.) generated by the control pattern generation unit 12b for each block, according to the setting pattern that has been set in advance in the operation unit 2 on a block-by-block basis. The block-by-block data and control patterns (SKP, EIEOS, etc.) selected by the selector unit 12c are output to the EDS insertion unit 14 as raw sequence pattern data.

[0045] The data generation control unit 13 controls the generation of sequence patterns by the sequence pattern generation unit 12, that is, the generation of data by the data generation unit 12a and the generation of control patterns (SKP, EIEOS, etc.) by the control pattern generation unit 12b, in order to generate desired data and control patterns that comply with the standard (PCIe).

[0046] The EDS insertion unit 14 overwrites and inserts the EDS pattern into the block previously set by the operation unit 2 in the raw sequence pattern data from the selector unit 12c.

[0047] The data multiplexing unit 15 is composed of, for example, a multiplexer (MUX) or a D-type flip-flop circuit, and outputs a sequence pattern in which the parallel data input from the EDS insertion unit 14 is multiplexed into serial data at the timing of the reference clock signal of the clock module 3.

[0048] Next, the operation when an EDS pattern is overwritten and inserted into the sequence pattern generated by the sequence pattern generator 7 configured as described above will be explained with reference to Figures 3(a) to (c).

[0049] Figures 3(a) to 3(c) show a portion of the sequence pattern data D1 for one block, and it is assumed that the insertion of the EDS pattern (labeled EDS in Figure 3) has been pre-configured by the operation unit 2.

[0050] As shown in Figure 3(a), when the raw sequence pattern data:D1 is selected and output by the selector unit 12c, an EDS:p1 corresponding to an SDS (not shown) is overwritten and inserted at the end of DATA:d1, as shown in Figure 3(b). Subsequently, as shown by the shaded area in Figure 3(c), scrambling is performed on DATA:d1 and EDS:p1 of the sequence pattern data:D1 into which EDS:p1 has been overwritten and inserted.

[0051] Furthermore, regarding the overwrite insertion of the EDS pattern, the insertion settings for the EDS pattern and SKP OS are performed for each block of data in the sequence pattern. For example, as shown in Figure 4, if the insertion setting for the EDS pattern is performed only for block #6 of the sequence pattern data, the EDS pattern (labeled as EDS in Figure 4) will be overwritten and inserted at the end of each data in block #6 (each DATA#6 in Figure 4).

[0052] Furthermore, like the SKP OS, the EDS pattern also requires a reset setting, and when a reset is set, it is inserted into the previous block. For example, as shown in Figure 5, if a reset is set in block #6, the SKP OS (labeled SKP in Figure 5) is inserted at the beginning of block #6, and the associated EDS pattern (labeled EDS in Figure 5) is overwritten and inserted at the end of the data in block #5 (labeled DATA#5 in Figure 5), which is the block before block #6.

[0053] By the way, Figure 1 illustrates the case where one sequence pattern generator 7 is connected to the device control unit 6 and generates a sequence pattern including an EDS pattern that conforms to the standard. However, when supporting multiple lanes, the number of sequence pattern generators 7 corresponding to the number of lanes is connected to the device control unit 6.

[0054] Furthermore, when multi-lane support is enabled, the EDS pattern used for overwriting and inserting has replacement patterns for the last 4 bytes, 2 bytes, and 1 byte, and these change depending on the settings.

[0055] Figure 6 shows the relationship between the setting values, setting patterns, and the symbols corresponding to the setting patterns when multi-lane support is enabled. Note that the setting values ​​"x1", "x2", and "x4" indicate the number of lanes.

[0056] Furthermore, the setting pattern corresponds to the number of lanes required for the device under test W to recognize the sequence pattern as an EDS. For example, the setting pattern "1F 90" for the setting value "x2 Lane0" and the setting pattern "80 00" for "x2 Lane1" in Figure 6 are patterns corresponding to the number of lanes "2". The device under test W can recognize the EDS when it receives symbols (1) and (3) corresponding to the setting pattern "1F90" and symbols (2) and (4) corresponding to the setting pattern "80 00".

[0057] In Figure 6, the settings "x1 Lane0" and "x1 Lane0 Reverse" can be addressed by connecting at least one sequence pattern generator 7 (one unit) to the device control unit 6.

[0058] For example, when one sequence pattern generator 7 is connected to the device control unit 6, the operation unit 2 selects and sets the setting value "x1 Lane0" and the setting pattern "1F 80 90 00" of the sequence pattern generator 7 from the pull-down menu of "EDS+SKP OS Insertion Type" 21b in the predetermined block of "Block No." in Figure 2. In the example in Figure 2, the setting value "x1 Lane0" and the setting pattern "1F 80 90 00" are set in "EDS+SKP OS Insertion Type" 21b of "Block No.":#10. As a result, the object under measurement W can recognize one EDS by receiving symbols (1)(2)(3)(4) corresponding to the setting pattern "1F 80 90 00" output from the sequence pattern generator 7.

[0059] Furthermore, in Figure 6, when the settings are "x2 Lane0", "x2 Lane1", "x2 Lane0 Reverse", and "x2 Lane1 Reverse", at least two (two) sequence pattern generators 7 need to be connected to the device control unit 6.

[0060] For example, when two sequence pattern generators 7 are connected to the device control unit 6, the setting patterns are distributed to the two sequence pattern generators 7 and set in predetermined blocks. That is, the operation unit 2 sets the setting pattern "1F 90" of the setting value "x2 Lane0" of one sequence pattern generator 7 in a predetermined block. The operation unit 2 also sets the setting pattern "80 00" of the setting value "x2 Lane1" of the other sequence pattern generator 7 in a predetermined block. As a result, the object under test W can recognize one EDS by receiving symbols (1)(3) corresponding to the setting pattern "1F 90" of the sequence pattern output from one sequence pattern generator 7 and symbols (2)(4) corresponding to the setting pattern "80 00" of the sequence pattern output from the other sequence pattern generator 7.

[0061] Furthermore, in Figure 6, when the settings are "x4 Lane0", "x4 Lane1", "x4 Lane2", and "x4 Lane3", at least four (four) sequence pattern generators 7 need to be connected to the device control unit 6.

[0062] For example, when four (four) sequence pattern generators 7 are connected to the device control unit 6, the setting patterns are distributed to the four (four) sequence pattern generators 7 and set in predetermined blocks. That is, the operation unit 2 sets the setting pattern "1F" of the setting value "x4 Lane0" of the first sequence pattern generator 7 in a predetermined block. The operation unit 2 also sets the setting pattern "80" of the setting value "x4 Lane1" of the second sequence pattern generator 7 in a predetermined block. Furthermore, the operation unit 2 sets the setting pattern "90" of the setting value "x4 Lane2" of the third sequence pattern generator 7 in a predetermined block. Finally, the operation unit 2 sets the setting pattern "00" of the setting value "x4 Lane3" of the fourth sequence pattern generator 7 in a predetermined block. As a result, one EDS can be recognized by receiving the symbol (1) corresponding to the sequence pattern setting pattern "1F" output from the first sequence pattern generator 7, the symbol (2) corresponding to the sequence pattern setting pattern "80" output from the second sequence pattern generator 7, the symbol (3) corresponding to the sequence pattern setting pattern "90" output from the third sequence pattern generator 7, and the symbol (4) corresponding to the sequence pattern setting pattern "00" output from the fourth sequence pattern generator 7.

[0063] Furthermore, when connecting while switching the number of lanes to support multiple lanes, the pattern setting screen 21 of one sequence pattern generator 7 may contain a mix of settings, such as "Block No.":#10 "1Lane(1F 80 90 00)" and "Block No.":#11 "2Lane Ch1 R(00 80)" in Figure 2. Also, when supporting multiple lanes, the actual output is MSB First at the byte level and LSB First at the bit level due to the constraints of the PCIe standard.

[0064] Furthermore, while Figure 6 shows support for a 4-lane multi-lane configuration, it is not limited to this; it is possible to support 1 to 16 lanes in accordance with the PCIe Gen3-6 standard.

[0065] Next, the operation when inserting an EDS pattern using the sequence pattern generator 7 described above will be explained with reference to the flowchart in Figure 7.

[0066] First, a number of sequence pattern generators 7 corresponding to the number of lanes defined in the standard are provided (ST1).

[0067] Furthermore, setting patterns corresponding to the number of lanes to be recognized as EDS patterns upon reception are distributed to each sequence pattern generator 7 and set in predetermined blocks (ST2).

[0068] Subsequently, each sequence pattern generator 7 generates a sequence pattern consisting of a data pattern and a control pattern in block units (ST3).

[0069] Then, in each sequence pattern generator 7, an EDS pattern is inserted at the end of the data pattern of the block before scrambling, which is set for each block of the sequence pattern (ST4: see Figure 4 and its explanation for a specific example).

[0070] Furthermore, when an SKP OS is inserted at the beginning of a block in each sequence pattern generator 7 to reset the SKP insertion timing, the accompanying EDS pattern is overwritten and inserted at the end of the data pattern of the block preceding the block in which the SKP OS was inserted (ST5: See Figure 5 and its explanation for a specific example).

[0071] Thus, according to this embodiment, it is possible to generate a sequence pattern that includes an EDS pattern compliant with PCIe Gen3 or later standards. This allows the sequence pattern including the EDS pattern to be input to the device under test W, and a reception test can be performed to verify whether the device under test W transitions to a desired state including loopback. Debugging can then be performed based on the results of the reception test of the device under test W.

[0072] Furthermore, multi-lane support allows for the generation of sequence patterns with EDS patterns inserted in the number of lanes corresponding to the standard (from 1 to 16 lanes for PCIe Gen3-6). As a result, debugging of the device under test W, developed using PCIe Gen3 or later standards, becomes more efficient.

[0073] The best mode of the sequence pattern generator and sequence pattern generation method according to the present invention has been described above, but the present invention is not limited by this description and drawings. That is, other modes, examples, and operating techniques made by those skilled in the art based on this mode are all included in the scope of the present invention. [Explanation of symbols]

[0074] 1. Measuring device 2 Control section 3 Clock Modules 4 Measurement Modules 5 Display section 6. Device Control Unit 7. Sequence Pattern Generator 11 Internal clock generation unit 12 Sequence pattern generation unit 12a Data generation unit 12b Control pattern generation unit 12c Selector section 13 Data Generation Control Unit 14 EDS insertion section 15. Data Multiplexing Unit 21 Pattern setting screen 21a Interval with EDS 21b EDS+SKP OS Insertion Type 21c EDS+SKP OS Reset 21d Symbol Length 21e Interval 21f Block No. 21g Break 21h Pattern Type 21i Bitrate 21j Pattern 21k Pattern Length 21L SKP OS Insertion 21m SKP OS Reset 21n EIEOSQ Insertion W Object to be measured D1 Sequence Pattern Data p1 EDS pattern d1 DATA

Claims

1. A sequence pattern generation unit (12) generates sequence patterns consisting of data patterns and control patterns in block units, An EDS pattern is set for each block of the sequence pattern, and an EDS insertion unit (14) inserts the EDS pattern at the end of each block's data pattern before scrambling, A sequence pattern generator comprising: a pattern setting screen, in which the initial value of the EDS pattern for each block of the sequence pattern is set to OFF and disabled, and when SKP OS insertion is OFF and a pattern type is set, an operation unit (2) that selects and sets the EDS pattern from the selection range of a pull-down menu and selects and sets whether or not to reset the SKP insertion timing for each block, When the EDS insertion unit inserts an SKP OS at the beginning of a block and resets the SKP insertion timing, it overwrites the end of the data pattern of the block preceding the block into which the SKP OS was inserted with the EDS pattern associated with the SKP OS at the beginning of the block. When multi-lane support is provided, the number of sequence pattern generators corresponding to the number of lanes defined in the standard is connected to the device control unit (6) of the measuring device (1), and when the object under test (W) receives the sequence pattern, the setting patterns corresponding to the number of lanes to be recognized as the EDS pattern are distributed to the sequence pattern generators and set in a predetermined block. A sequence pattern generator characterized in that, when one sequence pattern generator is connected to the device control unit, the setting pattern of the one sequence pattern generator is set to "1F 80 90 00" in a predetermined block.

2. A sequence pattern generation unit (12) that generates a sequence pattern consisting of a data pattern and a control pattern in block units, An EDS pattern is set for each block of the sequence pattern, and an EDS insertion unit (14) inserts the EDS pattern at the end of each block's data pattern before scrambling, A sequence pattern generator comprising: a pattern setting screen, in which the initial value of the EDS pattern for each block of the sequence pattern is set to OFF and disabled, and when SKP OS insertion is OFF and a pattern type is set, an operation unit (2) that selects and sets the EDS pattern from the selection range of a pull-down menu and selects and sets whether or not to reset the SKP insertion timing for each block, When the EDS insertion unit inserts an SKP OS at the beginning of a block and resets the SKP insertion timing, it overwrites the end of the data pattern of the block preceding the block into which the SKP OS was inserted with the EDS pattern associated with the SKP OS at the beginning of the block. When multi-lane support is provided, the number of sequence pattern generators corresponding to the number of lanes defined in the standard is connected to the device control unit (6) of the measuring device (1), and when the object under test (W) receives the sequence pattern, the setting patterns corresponding to the number of lanes to be recognized as the EDS pattern are distributed to the sequence pattern generators and set in a predetermined block. A sequence pattern generator characterized in that, when two sequence pattern generators are connected to the device control unit, the setting pattern of one sequence pattern generator is set to "1F 90" in a predetermined block, and the setting pattern of the other sequence pattern generator is set to "80 00" in a predetermined block.

3. A sequence pattern generation unit (12) that generates a sequence pattern consisting of a data pattern and a control pattern in block units, An EDS pattern is set for each block of the sequence pattern, and an EDS insertion unit (14) inserts the EDS pattern at the end of each block's data pattern before scrambling, A sequence pattern generator comprising: a pattern setting screen, in which the initial value of the EDS pattern for each block of the sequence pattern is set to OFF and disabled, and when SKP OS insertion is OFF and a pattern type is set, an operation unit (2) that selects and sets the EDS pattern from the selection range of a pull-down menu and selects and sets whether or not to reset the SKP insertion timing for each block, When the EDS insertion unit inserts an SKP OS at the beginning of a block and resets the SKP insertion timing, it overwrites the end of the data pattern of the block preceding the block into which the SKP OS was inserted with the EDS pattern associated with the SKP OS at the beginning of the block. When multi-lane support is provided, the number of sequence pattern generators corresponding to the number of lanes defined in the standard is connected to the device control unit (6) of the measuring device (1), and when the object under test (W) receives the sequence pattern, the setting patterns corresponding to the number of lanes to be recognized as the EDS pattern are distributed to the sequence pattern generators and set in a predetermined block. A sequence pattern generator characterized in that, when four sequence pattern generators are connected to the device control unit, the setting pattern of the first sequence pattern generator is set to "1F" in a predetermined block, the setting pattern of the second sequence pattern generator is set to "80" in a predetermined block, the setting pattern of the third sequence pattern generator is set to "90" in a predetermined block, and the setting pattern of the fourth sequence pattern generator is set to "00" in a predetermined block.

4. A step of generating a sequence pattern consisting of a data pattern and a control pattern in block units, An EDS pattern set for each block of the sequence pattern, comprising the step of inserting the EDS pattern at the end of the data pattern for each block before scrambling, In the pattern setting screen, the initial value of the EDS pattern for each block of the sequence pattern is set to OFF and disabled by operation of the operation unit (2), and when SKP OS insertion is OFF and a pattern type is set, the EDS pattern is set by selecting it from the selection range of the pull-down menu by operation of the operation unit. In the pattern setting screen, the step of selecting whether or not to reset the SKP insertion timing for each block by operating the operation unit, When an SKP OS is inserted at the beginning of a block to reset the SKP insertion timing, the EDS pattern associated with the SKP OS at the beginning of the block is overwritten and inserted at the end of the data pattern of the block preceding the block in which the SKP OS was inserted. In the case of multi-lane support, the number of sequence pattern generators corresponding to the number of lanes defined in the standard is connected to the device control unit (6) of the measuring device (1), and when the object to be measured (W) receives the sequence pattern, the setting patterns corresponding to the number of lanes to be recognized as the EDS pattern are distributed to the sequence pattern generator and set in a predetermined block, and When one sequence pattern generator is connected to the device control unit as the sequence pattern generator, the steps include setting "1F 80 90 00" as the setting pattern of the one sequence pattern generator to a predetermined block, A method for generating a sequence pattern, characterized by including the following:

5. A step of generating a sequence pattern consisting of a data pattern and a control pattern in block units, An EDS pattern set for each block of the sequence pattern, comprising the step of inserting the EDS pattern at the end of the data pattern for each block before scrambling, In the pattern setting screen, the initial value of the EDS pattern for each block of the sequence pattern is set to OFF and disabled by operation of the operation unit (2), and when SKP OS insertion is OFF and a pattern type is set, the EDS pattern is set by selecting it from the selection range of the pull-down menu by operation of the operation unit. In the pattern setting screen, the step of selecting whether or not to reset the SKP insertion timing for each block by operating the operation unit, When an SKP OS is inserted at the beginning of a block to reset the SKP insertion timing, the EDS pattern associated with the SKP OS at the beginning of the block is overwritten and inserted at the end of the data pattern of the block preceding the block in which the SKP OS was inserted. In the case of multi-lane support, the number of sequence pattern generators corresponding to the number of lanes defined in the standard is connected to the device control unit (6) of the measuring device (1), and when the object to be measured (W) receives the sequence pattern, the setting patterns corresponding to the number of lanes to be recognized as the EDS pattern are distributed to the sequence pattern generator and set in a predetermined block, and When two sequence pattern generators are connected to the device control unit as the sequence pattern generators, the steps include setting "1F 90" as the setting pattern of one sequence pattern generator to a predetermined block, and setting "80 00" as the setting pattern of the other sequence pattern generator to a predetermined block, A method for generating a sequence pattern, characterized by including the following:

6. A step of generating a sequence pattern consisting of a data pattern and a control pattern in block units, An EDS pattern set for each block of the sequence pattern, comprising the step of inserting the EDS pattern at the end of the data pattern for each block before scrambling, In the pattern setting screen, the initial value of the EDS pattern for each block of the sequence pattern is set to OFF and disabled by operation of the operation unit (2), and when SKP OS insertion is OFF and a pattern type is set, the EDS pattern is set by selecting it from the selection range of the pull-down menu by operation of the operation unit. In the pattern setting screen, the step of selecting whether or not to reset the SKP insertion timing for each block by operating the operation unit, When an SKP OS is inserted at the beginning of a block to reset the SKP insertion timing, the EDS pattern associated with the SKP OS at the beginning of the block is overwritten and inserted at the end of the data pattern of the block preceding the block in which the SKP OS was inserted. In the case of multi-lane support, the number of sequence pattern generators corresponding to the number of lanes defined in the standard is connected to the device control unit (6) of the measuring device (1), and when the object to be measured (W) receives the sequence pattern, the setting patterns corresponding to the number of lanes to be recognized as the EDS pattern are distributed to the sequence pattern generator and set in a predetermined block, and When four sequence pattern generators are connected to the device control unit as the sequence pattern generator, the steps include setting "1F" as the setting pattern of the first sequence pattern generator to a predetermined block, setting "80" as the setting pattern of the second sequence pattern generator to a predetermined block, setting "90" as the setting pattern of the third sequence pattern generator to a predetermined block, and setting "00" as the setting pattern of the fourth sequence pattern generator to a predetermined block, A method for generating a sequence pattern, characterized by including the following:

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