Indication device

Abstract

To improve display quality of a display device provided with a function of a touch panel.SOLUTION: According to one embodiment, a display device includes: a plurality of display elements each including a lower electrode, an upper electrode facing the lower electrode, and an organic layer placed between the lower electrode and the upper electrode to emit light in accordance with potential difference between the lower electrode and the upper electrode; a partition wall including a lower part of conductivity and an upper part protruding from a side face of the lower part to surround each of the plurality of display elements; and a touch panel electrode for detecting an object coming into contact with or approaching a display area including the plurality of display elements. The touch panel electrode includes a first metal wire located over the partition wall to extend along the partition wall.SELECTED DRAWING: Figure 3

Description

Technical Field

[0001] Embodiments of the present invention relate to a display device.

Background Art

[0002] In recent years, display devices applying organic light-emitting diodes (OLEDs) as display elements have been put into practical use. This display element includes a lower electrode, an organic layer covering the lower electrode, and an upper electrode covering the organic layer.

[0003] A display device may have a function of a touch panel that detects a user's operation on a display area. When an electrode for realizing such a function is disposed in the display area, it is necessary to devise the structure of the display device so as to suppress a decrease in display quality due to the electrode.

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

Patent Document 2

Patent Document 3

Patent Document 4

Patent Document 5

Patent Document 6

Patent Document 7

Summary of the Invention

Problems to be Solved by the Invention

[0005] The objective of this invention is to improve the display quality of a display device equipped with a touch panel function. [Means for solving the problem]

[0006] A display device according to one embodiment includes a plurality of display elements, each including a lower electrode, an upper electrode facing the lower electrode, and an organic layer disposed between the lower electrode and the upper electrode that emits light according to the potential difference between the lower electrode and the upper electrode; a partition wall surrounding each of the plurality of display elements, including a conductive lower part and an upper part protruding from the side of the lower part; and a touch panel electrode for detecting an object that comes into contact with or is close to the display area including the plurality of display elements. A conductive layer having the same layer as the partition wall and arranged in the peripheral region surrounding the display area, lead wires arranged in the peripheral region, and relay wiring electrically connecting the touch panel electrodes and the lead wires, The touch panel electrode includes a first metal wire located above the partition and extending along the partition. The relay wiring includes a third metal wire that electrically connects the first metal wire and the lead wire. Furthermore, the lead wire overlaps with the conductive layer. [Brief explanation of the drawing]

[0007] [Figure 1] Figure 1 shows an example of the configuration of a display device according to the first embodiment. [Figure 2] Figure 2 shows an example of a sub-pixel layout. [Figure 3] Figure 3 is a schematic cross-sectional view of the display device along the line III-III in Figure 2. [Figure 4] Figure 4 is a schematic cross-sectional view of the partition wall and its vicinity, magnified. [Figure 5] Figure 5 is a schematic diagram illustrating the sizes of the ribs, partitions, display elements, and the first metal wire. [Figure 6] Figure 6 is a schematic plan view of the display device according to the first embodiment. [Figure 7] Figure 7 is a schematic plan view showing the elements arranged in the surrounding area. [Figure 8] Figure 8 is a schematic plan view showing the elements required to realize the functions related to the touch panel. [Figure 9] Figure 9 is an enlarged view of the area enclosed by the dashed-line frame IX in Figure 6. [Figure 10]FIG. 10 is a schematic cross-sectional view of the display device along the X-X line in FIG. 9. [Figure 11] FIG. 11 is a schematic cross-sectional view near the end of the conductive layer. [Figure 12] FIG. 12 is a schematic plan view of the area surrounded by the chain line frame XII in FIG. 8. [Figure 13] FIG. 13 is a schematic plan view showing another example of a configuration applicable to the touch panel electrode and the relay wiring. [Figure 14] FIG. 14 is a schematic plan view of the area surrounded by the chain line frame XIV in FIG. 8. [Figure 15] FIG. 15 is a schematic plan view of the lead wire, the connection part, and the terminal part. [Figure 16] FIG. 16 is a schematic cross-sectional view of the peripheral area including the first pad. [Figure 17] FIG. 17 is a schematic cross-sectional view of the peripheral area including the second pad. [Figure 18] FIG. 18 is a schematic plan view of the pixel and the first metal line according to the first modification example. [Figure 19] FIG. 19 is a schematic plan view of the pixel and the first metal line according to the second modification example. [Figure 20] FIG. 20 is a schematic plan view of the pixel and the first metal line according to the third modification example. [Figure 21] FIG. 21 is a schematic plan view of the pixel and the first metal line according to the fourth modification example. [Figure 22] FIG. 22 is a schematic plan view of the pixel and the first metal line according to the fifth modification example. [Figure 23] FIG. 23 is a schematic plan view of the pixel and the first metal line according to the sixth modification example. [Figure 24] FIG. 24 is a schematic plan view of the pixel and the first metal line according to the seventh modification example. [Figure 25] FIG. 25 is a schematic plan view of the pixel and the first metal line according to the eighth modification example. [Figure 26] FIG. 26 is a schematic cross-sectional view of the peripheral area of the display device according to the second embodiment. [Figure 27] Figure 27 is another schematic cross-sectional view of the peripheral region of the display device according to the second embodiment. [Figure 28] Figure 28 is a schematic cross-sectional view of the peripheral region of the display device according to the third embodiment. [Figure 29] Figure 29 is another schematic cross-sectional view of the peripheral region of the display device according to the third embodiment. [Figure 30] Figure 30 is a schematic cross-sectional view of the display area of ​​the display device according to the fourth embodiment. [Modes for carrying out the invention]

[0008] Several embodiments will be described with reference to the drawings. The disclosure is merely an example, and any modifications that a person skilled in the art could easily conceive of while maintaining the spirit of the invention are naturally included within the scope of the present invention. Furthermore, the drawings may schematically represent the width, thickness, shape, etc., of each part in order to clarify the explanation, but these are merely examples and do not limit the interpretation of the present invention. In addition, in this specification and each drawing, the same reference numerals are used for components that perform the same or similar functions as those described above with respect to previously shown drawings, and redundant detailed explanations may be omitted as appropriate.

[0009] Furthermore, the drawings will include mutually orthogonal X, Y, and Z axes as needed to facilitate understanding. The direction along the X-axis will be referred to as the first direction X, the direction along the Y-axis as the second direction Y, and the direction along the Z-axis as the third direction Z. The third direction Z is normal to the plane containing the first direction X and the second direction Y. Viewing various elements parallel to the plane containing the first direction X and the second direction Y is called a plan view.

[0010] Each embodiment of the display device is an organic electroluminescent display device equipped with an organic light-emitting diode (OLED) as a display element, and can be mounted on various electronic devices such as televisions, personal computers, in-vehicle equipment, tablet terminals, smartphones, mobile phone terminals, and wearable terminals.

[0011] [First Embodiment] Figure 1 shows an example configuration of a display device DSP according to the first embodiment. The display device DSP has a display area DA for displaying an image and a peripheral area SA around the display area DA on an insulating substrate 10. The substrate 10 may be glass or a flexible resin film.

[0012] In this embodiment, the shape of the substrate 10 in plan view is rectangular. However, the shape of the substrate 10 in plan view is not limited to a rectangle; it may be a square, a circle, an ellipse, or other shape.

[0013] The display area DA comprises multiple pixels PX arranged in a matrix in the first direction X and the second direction Y. Each pixel PX includes multiple sub-pixels SP. In one example, pixel PX includes a red sub-pixel SP1, a green sub-pixel SP2, and a blue sub-pixel SP3. Pixel PX may also include sub-pixels SP of other colors, such as white, together with sub-pixels SP1, SP2, and SP3, or in place of any one of SP1, SP2, or SP3.

[0014] The sub-pixel SP comprises a pixel circuit 1 and a display element DE driven by the pixel circuit 1. The pixel circuit 1 comprises a pixel switch 2, a drive transistor 3, and a capacitor 4. The pixel switch 2 and the drive transistor 3 are switching elements composed of, for example, thin-film transistors.

[0015] The gate electrode of pixel switch 2 is connected to the scan line GL. One of the source and drain electrodes of pixel switch 2 is connected to the signal line SL, and the other is connected to the gate electrode of drive transistor 3 and capacitor 4. In drive transistor 3, one of the source and drain electrodes is connected to the power line PL and capacitor 4, and the other is connected to display element DE.

[0016] Note that the configuration of the pixel circuit 1 is not limited to the example shown. For example, the pixel circuit 1 may include more thin-film transistors and capacitors.

[0017] Figure 2 shows an example of the layout of sub-pixels SP1, SP2, and SP3. In the example in Figure 2, sub-pixels SP1 and SP2 are aligned in the second direction Y. Furthermore, sub-pixels SP1 and SP2 are aligned with sub-pixel SP3 in the first direction X.

[0018] When sub-pixels SP1, SP2, and SP3 are arranged in this manner, the display area DA forms columns in which sub-pixels SP1 and SP2 are alternately arranged in the second direction Y, and columns in which multiple sub-pixels SP3 are repeatedly arranged in the second direction Y. These columns are arranged alternately in the first direction X. Note that the layout of sub-pixels SP1, SP2, and SP3 is not limited to the example in Figure 2.

[0019] The display area DA has ribs 5 and partition walls 6. Ribs 5 have pixel apertures AP1, AP2, and AP3 in sub-pixels SP1, SP2, and SP3, respectively. In the example in Figure 2, pixel aperture AP2 is larger than pixel aperture AP1, and pixel aperture AP3 is larger than pixel aperture AP2.

[0020] The partition wall 6 is positioned at the boundary between adjacent subpixels SP and overlaps with the rib 5 in a plan view. The partition wall 6 has a plurality of first partition walls 6x extending in the first direction X and a plurality of second partition walls 6y extending in the second direction Y. The plurality of first partition walls 6x are positioned between adjacent pixel apertures AP1 and AP2 in the second direction Y, and between two adjacent pixel apertures AP3 in the second direction Y. The second partition walls 6y are positioned between adjacent pixel apertures AP1 and AP3 in the first direction X, and between adjacent pixel apertures AP2 and AP3 in the first direction X.

[0021] In the example shown in Figure 2, the first partition wall 6x and the second partition wall 6y are connected to each other. As a result, the partition wall 6 as a whole forms a grid surrounding the pixel apertures AP1, AP2, and AP3. It can also be said that the partition wall 6, like the rib 5, has apertures in the sub-pixels SP1, SP2, and SP3.

[0022] Sub-pixel SP1 comprises a lower electrode LE1, an upper electrode UE1, and an organic layer OR1, which overlap with the pixel aperture AP1. Sub-pixel SP2 comprises a lower electrode LE2, an upper electrode UE2, and an organic layer OR2, which overlap with the pixel aperture AP2. Sub-pixel SP3 comprises a lower electrode LE3, an upper electrode UE3, and an organic layer OR3, which overlap with the pixel aperture AP3.

[0023] The portion of the lower electrode LE1, upper electrode UE1, and organic layer OR1 that overlaps with the pixel aperture AP1 constitutes the display element DE1 of the sub-pixel SP1. The portion of the lower electrode LE2, upper electrode UE2, and organic layer OR2 that overlaps with the pixel aperture AP2 constitutes the display element DE2 of the sub-pixel SP2. The portion of the lower electrode LE3, upper electrode UE3, and organic layer OR3 that overlaps with the pixel aperture AP3 constitutes the display element DE3 of the sub-pixel SP3. The display elements DE1, DE2, and DE3 may further include a cap layer, which will be described later. The rib 5 and partition wall 6 surround each of these display elements DE1, DE2, and DE3, respectively.

[0024] The lower electrode LE1 is connected to the pixel circuit 1 of the sub-pixel SP1 (see Figure 1) through the contact hole CH1. The lower electrode LE2 is connected to the pixel circuit 1 of the sub-pixel SP2 through the contact hole CH2. The lower electrode LE3 is connected to the pixel circuit 1 of the sub-pixel SP3 through the contact hole CH3.

[0025] In the example in Figure 2, contact holes CH1 and CH2 completely overlap with the first partition wall 6x between adjacent pixel apertures AP1 and AP2 in the second direction Y. Contact hole CH3 completely overlaps with the first partition wall 6x between two adjacent pixel apertures AP3 in the second direction Y. In another example, at least a portion of contact holes CH1, CH2, and CH3 may not overlap with the first partition wall 6x.

[0026] Figure 3 is a schematic cross-sectional view of the display device DSP along the line III-III in Figure 2. A circuit layer 11 is arranged on the substrate 10 described above. The circuit layer 11 includes various circuits and wiring such as the pixel circuit 1, scan line GL, signal line SL, and power line PL shown in Figure 1.

[0027] The circuit layer 11 is covered by an organic insulating layer 12. The organic insulating layer 12 functions as a planarizing film that flattens the irregularities caused by the circuit layer 11. Although not shown in the cross-section of Figure 3, the contact holes CH1, CH2, and CH3 described above are provided in the organic insulating layer 12.

[0028] The lower electrodes LE1, LE2, and LE3 are positioned on top of the organic insulating layer 12. The ribs 5 are positioned on top of the organic insulating layer 12 and the lower electrodes LE1, LE2, and LE3. The ends of the lower electrodes LE1, LE2, and LE3 are covered by the ribs 5.

[0029] The partition wall 6 includes a conductive lower section 61 positioned on the rib 5 and an upper section 62 positioned on top of the lower section 61. The upper section 62 has a greater width than the lower section 61. As a result, in Figure 3, both ends of the upper section 62 protrude beyond the sides of the lower section 61. This shape of partition wall 6 is called an overhang.

[0030] The organic layer OR1 covers the lower electrode LE1 through the pixel aperture AP1. The upper electrode UE1 covers the organic layer OR1 and faces the lower electrode LE1. The organic layer OR2 covers the lower electrode LE2 through the pixel aperture AP2. The upper electrode UE2 covers the organic layer OR2 and faces the lower electrode LE2. The organic layer OR3 covers the lower electrode LE3 through the pixel aperture AP3. The upper electrode UE3 covers the organic layer OR3 and faces the lower electrode LE3.

[0031] In the example shown in Figure 3, cap layer CP1 is placed on top of upper electrode UE1, cap layer CP2 is placed on top of upper electrode UE2, and cap layer CP3 is placed on top of upper electrode UE3. Cap layers CP1, CP2, and CP3 adjust the optical properties of the light emitted by organic layers OR1, OR2, and OR3, respectively.

[0032] In the following explanation, the laminate containing the organic layer OR1, the upper electrode UE1, and the cap layer CP1 will be referred to as thin film FL1, the laminate containing the organic layer OR2, the upper electrode UE2, and the cap layer CP2 will be referred to as thin film FL2, and the laminate containing the organic layer OR3, the upper electrode UE3, and the cap layer CP3 will be referred to as thin film FL3.

[0033] A portion of the thin film FL1 is located above the upper part 62. This portion is separated from the portion of the thin film FL1 located below the partition wall 6 (the portion constituting the display element DE1). Similarly, a portion of the thin film FL2 is located above the upper part 62, and this portion is separated from the portion of the thin film FL2 located below the partition wall 6 (the portion constituting the display element DE2). Furthermore, a portion of the thin film FL3 is located above the upper part 62, and this portion is separated from the portion of the thin film FL3 located below the partition wall 6 (the portion constituting the display element DE3).

[0034] The sub-pixels SP1, SP2, and SP3 are each covered by the first sealing layers SE11, SE12, and SE13, respectively. The first sealing layer SE11 continuously covers the thin film FL1 and the partition wall 6 surrounding the sub-pixel SP1. The first sealing layer SE12 continuously covers the thin film FL2 and the partition wall 6 surrounding the sub-pixel SP2. The first sealing layer SE13 continuously covers the thin film FL3 and the partition wall 6 surrounding the sub-pixel SP3.

[0035] In the example shown in Figure 3, the thin film FL1 and the first sealing layer SE11 on the partition 6 between sub-pixels SP1 and SP3 are spaced apart from the thin film FL3 and the first sealing layer SE13 on the same partition 6. Similarly, the thin film FL2 and the first sealing layer SE12 on the partition 6 between sub-pixels SP2 and SP3 are spaced apart from the thin film FL3 and the first sealing layer SE13 on the same partition 6.

[0036] The first sealing layers SE11, SE12, and SE13 are covered by a resin layer RS. The resin layer RS ​​is covered by a second sealing layer SE2. The resin layer RS ​​and the second sealing layer SE2 are provided continuously over at least the entire display area DA, and a portion of them extends into the peripheral area SA.

[0037] The display device DSP further includes a cover member 20 facing the second sealing layer SE2. The cover member 20 and the second sealing layer SE2 are bonded together by a transparent adhesive layer 21. For example, OCA (Optical Clear Adhesive) can be used as the adhesive layer 21.

[0038] For example, the cover member 20 may be an optical element such as a polarizing plate, a protective film, or a cover glass. The cover member 20 may also be a laminate formed by bonding two or more elements with different functions, such as an optical element, a protective film, and a cover glass, together with an adhesive layer.

[0039] In the example shown in Figure 3, a first metal wire ML1, which constitutes the touch panel electrode TP, is placed on top of the second sealing layer SE2. The first metal wire ML1 is located above the partition wall 6 and extends along the partition wall 6. The first metal layer ML1 is covered by an adhesive layer 21.

[0040] The organic insulating layer 12 is formed of an organic insulating material. The ribs 5, the first sealing layers SE11, SE12, SE13, and the second sealing layer SE2 are formed of inorganic insulating materials such as silicon nitride (SiNx), silicon oxide (SiOx), or silicon oxynitride (SiON). The ribs 5, the first sealing layers SE11, SE12, SE13, and the second sealing layer SE2 may be laminates of different types of inorganic insulating materials. The resin layer RS ​​is formed of a resin material (organic insulating material) such as epoxy resin or acrylic resin.

[0041] The lower electrodes LE1, LE2, and LE3 each have a reflective layer formed of, for example, silver (Ag), and a pair of conductive oxide layers covering the upper and lower surfaces of this reflective layer, respectively. Each conductive oxide layer can be formed of a transparent conductive oxide such as ITO (Indium Tin Oxide), IZO (Indium Zinc Oxide), or IGZO (Indium Gallium Zinc Oxide).

[0042] The upper electrodes UE1, UE2, and UE3 are formed from a metallic material such as a magnesium-silver alloy (MgAg). For example, the lower electrodes LE1, LE2, and LE3 correspond to the anode, and the upper electrodes UE1, UE2, and UE3 correspond to the cathode.

[0043] The organic layers OR1, OR2, and OR3 have, for example, a laminated structure consisting of a hole injection layer, a hole transport layer, an electron blocking layer, an emissive layer, a hole blocking layer, an electron transport layer, and an electron injection layer. The organic layers OR1, OR2, and OR3 may also have a so-called tandem structure including multiple emissive layers.

[0044] The cap layers CP1, CP2, and CP3 are formed, for example, by a multilayer structure of multiple transparent thin films. The multilayer structure may include thin films formed from inorganic materials and thin films formed from organic materials. These multiple thin films have different refractive indices. The materials of the thin films constituting the multilayer structure are different from the materials of the upper electrodes UE1, UE2, and UE3, and also different from the materials of the first sealing layers SE11, SE12, and SE13. Note that the cap layers CP1, CP2, and CP3 may be omitted.

[0045] The first metal wire ML1 is formed of a metallic material. In one example, the first metal wire ML1 has a laminated structure of titanium (Ti), aluminum (Al), and titanium. However, the first metal wire ML1 may have a laminated structure of other metallic materials or a single-layer structure.

[0046] The lower part 61 of the partition wall 6 is formed of, for example, aluminum. The lower part 61 may be formed of an aluminum alloy such as aluminum-neodymium (AlNd), or it may have a laminated structure of an aluminum layer and an aluminum alloy layer. Furthermore, the lower part 61 may have a thin film formed of a metallic material different from aluminum or an aluminum alloy beneath the aluminum layer or aluminum alloy layer. Such a thin film can be formed of, for example, molybdenum (Mo).

[0047] The upper part 62 of the partition wall 6 has a laminated structure of a thin film made of a metallic material such as titanium and a thin film made of a conductive oxide such as ITO. The upper part 62 may also have a single-layer structure of a metallic material such as titanium. Alternatively, the upper part 62 may have a single-layer structure of an inorganic insulating material different from the first sealing layers SE11, SE12, SE13.

[0048] A common voltage is supplied to the partition wall 6. This common voltage is supplied to the upper electrodes UE1, UE2, and UE3, which are in contact with the side surface of the lower part 61. Pixel voltages are supplied to the lower electrodes LE1, LE2, and LE3 through the pixel circuits 1 of the sub-pixels SP1, SP2, and SP3, respectively.

[0049] When a potential difference is formed between the lower electrode LE1 and the upper electrode UE1, the light-emitting layer of the organic layer OR1 emits light in the red wavelength range. When a potential difference is formed between the lower electrode LE2 and the upper electrode UE2, the light-emitting layer of the organic layer OR2 emits light in the green wavelength range. When a potential difference is formed between the lower electrode LE3 and the upper electrode UE3, the light-emitting layer of the organic layer OR3 emits light in the blue wavelength range.

[0050] As another example, the light-emitting layers of organic layers OR1, OR2, and OR3 may emit light of the same color (e.g., white). In this case, the display device DSP may include a color filter that converts the light emitted by the light-emitting layers into light of the color corresponding to the sub-pixels SP1, SP2, and SP3. Alternatively, the display device DSP may include a layer containing quantum dots that are excited by the light emitted by the light-emitting layers to generate light of the color corresponding to the sub-pixels SP1, SP2, and SP3.

[0051] Figure 4 is a schematic, enlarged cross-sectional view of the partition wall 6 located at the boundary between sub-pixels SP1 and SP3 and its vicinity. In this figure, the substrate 10, circuit layer 11, cover member 20, and adhesive layer 21 are omitted.

[0052] The organic layer OR1, the upper electrode UE1, and the cap layer CP1 are formed by vapor deposition and patterned together with the first sealing layer SE11. The end FL1a of the thin film FL1, which includes the organic layer OR1, the upper electrode UE1, and the cap layer CP1, is located above the upper part 62. The end SE11a of the first sealing layer SE11 is also located above the upper part 62. The end FL1a is not covered by the first sealing layer SE11.

[0053] Similarly, the organic layer OR3, the upper electrode UE3, and the cap layer CP3 are formed by vapor deposition and patterned together with the first sealing layer SE13. The end FL3a of the thin film FL3, which includes the organic layer OR3, the upper electrode UE3, and the cap layer CP3, is located above the upper 62. The end SE13a of the first sealing layer SE13 is also located above the upper 62. The end FL3a is not covered by the first sealing layer SE13.

[0054] Ends FL1a and FL3a are separated by a gap. Ends SE11a and SE13a are separated by a gap. The resin layer RS ​​is continuously provided over the entire display area DA and covers ends FL1a, FL3a, SE11a, and SE13a. Furthermore, the resin layer RS ​​fills the gaps between ends FL1a and FL3a, and between ends SE11a and SE13a, and is in contact with the upper part 62.

[0055] The first metal wire ML1 faces the upper part 62 in the third direction Z. For example, the position of the center C1 in the width direction of the first metal wire ML1 coincides with the position of the center C2 in the width direction of the partition wall 6. However, the centers C1 and C2 may be offset from each other. The width direction refers to the direction perpendicular to the direction in which the first metal wire ML1 and the partition wall 6 extend in a plan view. For example, the width direction of the first partition wall 6x is the second direction Y, and the width direction of the second partition wall 6y is the first direction X.

[0056] The configuration of the partition 6 between sub-pixels SP1 and SP2 and its vicinity, and the configuration of the partition 6 between sub-pixels SP2 and SP3 and its vicinity, are the same as in the example in Figure 4.

[0057] Figure 5 is a schematic diagram illustrating the sizes of the rib 5, partition wall 6, display element DE1, and first metal wire ML1, showing a general cross-section of the display elements DE1, DE2 and the rib 5, partition wall 6 (second partition wall 6y), and first metal wire ML1 between them.

[0058] Here, we define Wa as the width of the display element DE1, W1 as the width of the rib 5 between the pixel apertures AP1 and AP3, W2 as the width of the upper part 62 of the partition wall 6, W3 as the width of the first metal wire ML1, D as the distance between the display element DE1 and the first metal wire ML1 in the third direction Z, and θ as the angle between the direction in which the user views the display element DE1 and the normal direction of the display element DE1.

[0059] The width W3 must be set so that the first metal wire ML1 does not obstruct the light from the display element DE1, or its influence on the light is minimal. For example, if the width W1 is 10 μm, the widths W2 and W3 are both 5 μm, the width Wa is 20 μm, and the distance D is 3.5 μm, the effect of the first metal wire ML1 is almost negligible in the angle θ range from 0° to 35°. On the other hand, when the angle θ is around 60°, the brightness of the light visible to the user decreases by about 10% compared to when the first metal wire ML1 is absent.

[0060] Furthermore, if the first metal wire ML1 is absent, the brightness decreases to about half when the angle θ is approximately 45° compared to when the angle θ is 0°. Adding the first metal wire ML1 further reduces this brightness, but it does not have any practically problematic effects.

[0061] As the width W3 increases, the influence of the first metal wire ML1 becomes apparent even in the range of small angles θ, leading to increased brightness reduction. If the width W3 is greater than the width W1, the brightness when viewing the display element DE1 from the front (angle θ is 0°) will be lower than when the first metal wire ML1 is absent, significantly reducing the display quality of the display device DSP. When the width W3 is the same as the width W1, a brightness reduction of approximately 10% occurs at an angle θ of about 30°, and a brightness reduction of approximately 30% occurs at an angle θ of about 60°.

[0062] Considering the above, it is preferable that the width W3 is less than or equal to the width W1 (W3 ≤ W1). Furthermore, it is even more preferable that the width W3 is less than or equal to the width W2 (W3 ≤ W2). In one example, the width W1 is 5 μm to 25 μm. Also, the thickness of the resin layer RS ​​is 2 μm or less, and the thickness of the second sealing layer SE2 is 1 μm or less.

[0063] When the pixel size PX is large, the area affected by the first metal wire ML1 becomes relatively smaller. For example, in the case of a 55-inch 3840 x 2160 pixel display device, the pixel size PX is approximately 315 μm. In this case, if the width Wa of the display element DE1 is 80 μm, the width W1 of the rib 5 is 5 μm, the angle θ is 60°, and the distance D is 5 μm, then if the width W3 is less than or equal to the width W1, the brightness reduction due to the first metal wire ML1 will be limited to 10% or less.

[0064] The same configuration as described in Figures 4 and 5 can be applied to the display element DE2 and the ribs 5, partition walls 6, and first metal wire ML1 arranged around it.

[0065] Next, we will explain the structures that can be applied to the surrounding SA region. Figure 6 is a schematic plan view of the display device DSP. The display device DSP includes a first gate drive circuit GD1, a second gate drive circuit GD2, a selector circuit ST, and a terminal section T as elements arranged in the peripheral region SA. The first gate drive circuit GD1, the second gate drive circuit GD2, and the selector circuit ST are examples of drive circuits that supply signals to the pixel circuit 1, and are included in the circuit layer 11 shown in Figure 3.

[0066] The first gate drive circuit GD1 and the second gate drive circuit GD2 supply scanning signals to the scanning line GL shown in Figure 1. A flexible circuit board (FPC) (see Figure 8) is connected to the terminal T. The selector circuit ST supplies the video signal input from this flexible circuit board (FPC) to the signal line SL shown in Figure 1.

[0067] The substrate 10 has ends 10a, 10b, 10c, and 10d. Ends 10a and 10b extend parallel to the second direction Y. Ends 10c and 10d extend parallel to the first direction X.

[0068] In the example shown in Figure 6, the first gate drive circuit GD1 is located between the display area DA and the end 10a, the second gate drive circuit GD2 is located between the display area DA and the end 10b, and the selector circuit ST and terminal section T are located between the display area DA and the end 10c.

[0069] Furthermore, the display device DSP includes a conductive layer CL (the part with a dot pattern) located in the peripheral region SA. In the example in Figure 6, the conductive layer CL surrounds the display region DA.

[0070] The conductive layer CL is connected to the partition wall 6 located in the display area DA. In a plan view, the conductive layer CL overlaps with the first gate drive circuit GD1, the second gate drive circuit GD2, and the selector circuit ST.

[0071] The conductive layer CL does not necessarily have to have a shape that surrounds the display area DA. For example, the conductive layer CL does not need to be placed between the display area DA and the edge 10c, or between the display area DA and the edge 10d.

[0072] The peripheral region SA contains organic layers ORs, upper electrodes UEs, cap layers CPs, and the first sealing layer SE1. The organic layers ORs are formed from the same material and using the same manufacturing process as any of the organic layers OR1, OR2, or OR3. The upper electrodes UEs are formed from the same material and using the same manufacturing process as any of the upper electrodes UE1, UE2, or UE3. The cap layers CPs are formed from the same material and using the same manufacturing process as any of the cap layers CP1, CP2, or CP3. The first sealing layer SE1 is formed from the same material and using the same manufacturing process as any of the sealing layers SE11, SE12, or SE13.

[0073] In one example, the organic layers ORs, upper electrodes UEs, cap layers CPs, and first sealing layer SE1 are formed from the same materials and using the same manufacturing process as the organic layer OR3, upper electrode UE3, cap layer CP3, and first sealing layer SE13, respectively.

[0074] In the following description, the laminate containing the organic layers ORs, upper electrodes UEs, and capping layers CPs is referred to as the thin film FL. The thin film FL and the first sealing layer SE1 overlap with the conductive layer CL in a plan view.

[0075] Figure 7 is a schematic plan view showing other elements located in the peripheral region SA. The power supply line PW is located in the peripheral region SA. The power supply line PW includes a first part P1 (the part with the diagonal pattern) and a second part P2 (the part with the dot pattern).

[0076] In the example in Figure 7, the second portion P2 encloses the display area DA. The first portion P1 extends between the display area DA and the edges 10a, 10b, and 10d, but is not located between the display area DA and the edge 10c. In another example, the first portion P1 may enclose the display area DA.

[0077] The first part P1 and the second part P2 partially overlap. The first part P1 is electrically connected to terminal T. A common voltage is supplied to the first part P1 through terminal T. Furthermore, the common voltage of the first part P1 is supplied to the second part P2.

[0078] Figure 8 is a schematic plan view showing the elements for realizing touch panel functionality. Multiple touch panel electrodes TP are arranged in the display area DA. In the example in Figure 8, 24 touch panel electrodes TP1 to TP24 (6 rows x 4 columns) are arranged in a matrix. Touch panel electrodes TP1 to TP12 are located in the left half of the display area DA, and touch panel electrodes TP13 to TP24 are located in the right half of the display area DA. Note that the number and arrangement of touch panel electrodes TP are not limited to this example.

[0079] The peripheral area SA includes a wiring area LA for connecting the touch panel electrode TP and the terminal section T. The wiring area LA contains the same number of lead wires LL (LL1 to LL24) as the touch panel electrode TP and surrounds the display area DA.

[0080] Lead wires LL1 to LL12, which are connected to touch panel electrodes TP1 to TP12 respectively, are arranged to pass through the area between the display area DA and end 10a. Lead wires LL13 to LL24, which are connected to touch panel electrodes TP13 to TP24 respectively, are arranged to pass through the area between the display area DA and end 10b.

[0081] The wiring area LA and the touch panel electrodes TP1 to TP24 are connected by relay wiring RL (RL1 to RL24). Specifically, touch panel electrodes TP1 to TP12 are connected to lead wires LL1 to LL12 via relay wiring RL1 to RL12, and touch panel electrodes TP13 to TP24 are connected to lead wires LL13 to LL24 via relay wiring RL13 to RL24.

[0082] Lead wires LL1 to LL12 are connected to terminal T via connector 81. Lead wires LL13 to LL24 are connected to terminal T via connector 82.

[0083] For example, the touch panel electrodes TP1 to TP12, lead wires LL1 to LL12, relay wiring RL1 to RL12 and connection part 81, and the touch panel electrodes TP13 to TP24, lead wires LL13 to LL24, relay wiring RL13 to RL24 and connection part 82 have a shape that is symmetrical with respect to the center line in the first direction X of the display device DSP.

[0084] One end of a flexible circuit board (FPC) is connected to terminal T, for example, via a conductive adhesive. The other end of the flexible circuit board (FPC) is connected to the circuit board of an electronic device on which a display device (DSP) is mounted. Video signals and power necessary for image display are supplied to the display device (DSP) through the flexible circuit board (FPC).

[0085] The display device DSP further comprises a display controller CT1 that performs control related to image display and a detection controller CT2 that performs control related to touch detection. These controllers CT1 and CT2 are, for example, composed of ICs and mounted on a flexible circuit board (FPC). Controllers CT1 and CT2 may be mounted on separate flexible circuit boards, and these flexible circuit boards may each be connected to a terminal section T.

[0086] In this embodiment, we assume that the touch panel electrodes TP1 to TP24 constitute a capacitive touch panel. For example, the detection controller CT2 identifies the location of contact or proximity of an object, such as a user's finger, based on the change in capacitance of the touch panel electrodes TP1 to TP24 that occurs when the object comes into contact with or near the display area DA. This type of method is called a self-capacitive method.

[0087] However, a mutual capacitance method can also be applied as an object detection method. In this case, a drive electrode is placed in the display area DA in addition to the touch panel electrodes TP1 to TP24. When an object touches or comes into close proximity to the display area DA, the electric field between the touch panel electrodes TP1 to TP24 and the drive electrode is affected by the object, and the capacitance between the touch panel electrodes TP1 to TP24 and the drive electrode changes. The detection controller CT2 identifies the location where the object touched or came into close proximity based on this change in capacitance.

[0088] Figure 9 is an enlarged view of the area enclosed by the dashed-line frame IX in Figure 6. Figure 10 is a schematic cross-sectional view of the display device DSP along line XX in Figure 9. In Figure 9, the area with the dot pattern corresponds to the conductive layer CL and the partition wall 6 (first partition wall 6x and second partition wall 6y). The conductive layer CL and the partition wall 6 are integrally formed from the same material using the same manufacturing process.

[0089] In the example shown in Figure 10, the circuit layer 11 comprises inorganic insulating layers 31, 32, and 33, an organic insulating layer 34, and metal layers 41, 42, and 43. The inorganic insulating layer 31 covers the substrate 10. The metal layer 41 is placed on top of the inorganic insulating layer 31 and covered by the inorganic insulating layer 32. The metal layer 42 is placed on top of the inorganic insulating layer 32 and covered by the inorganic insulating layer 33. The organic insulating layer 34 is placed on top of the inorganic insulating layer 33. The metal layer 43 is placed on top of the organic insulating layer 34 and covered by the organic insulating layer 12.

[0090] The inorganic insulating layers 31, 32, and 33 are formed of inorganic materials such as silicon nitride and silicon oxide. The metal layers 41, 42, and 43 have a single-layer or multi-layer structure of metallic materials such as molybdenum (Mo), tungsten (W), molybdenum-tungsten alloy (MoW), aluminum (Al), and copper (Cu).

[0091] The first gate drive circuit GD1 is formed by metal layers 41, 42, and 43 and semiconductor layers. Similarly, the second gate drive circuit GD2 and selector circuit ST shown in Figure 6, and the pixel circuit 1 shown in Figure 1, are also formed by metal layers 41, 42, and 43 and semiconductor layers. Furthermore, the scan line GL shown in Figure 1 is formed by metal layer 41, and the signal line SL shown in Figure 1 is formed by metal layer 42.

[0092] The configuration of the circuit layer 11 is not limited to that illustrated in Figure 10. For example, the circuit layer 11 may have more inorganic insulating layers and metal layers. Also, the circuit layer 11 does not have to include the organic insulating layer 34.

[0093] The conductive layer CL covers the rib 5 in the peripheral region SA. The conductive layer CL includes a lower section 61 and an upper section 62, similar to the partition wall 6 shown in Figures 3 and 4.

[0094] The second portion P2 of the power supply line PW is mostly located on top of the organic insulating layer 12 and covered by the ribs 5. For example, the second portion P2 is formed from the same material and using the same manufacturing process as the lower electrodes LE1, LE2, and LE3.

[0095] The second part P2 is connected to the first part P1 at the contact part CN1 and to the conductive layer CL at the contact part CN2. As a result, a common voltage is supplied to the conductive layer CL via the first part P1 and the second part P2. Furthermore, the common voltage of the conductive layer CL is supplied to the partition wall 6 and upper electrodes UE1, UE2, and UE3 of the display area DA.

[0096] In the contact portion CN1, the second portion P2 is in contact with the first portion P1. The contact portion CN1 corresponds to the region where the first portion P1 and the second portion P2 overlap in the plan view of Figure 7, for example. In the example of Figure 10, the first portion P1 is composed of a metal layer 43. The first portion P1 may be composed of a metal layer 41 or a metal layer 42, or of two or more of the metal layers 41, 42, and 43.

[0097] As shown in Figure 10, an opening is formed in the rib 5 in the contact portion CN2. The conductive layer CL is in contact with the second portion P2 through this opening. The opening in the rib 5 may extend over the entire area of ​​the contact portion CN2 shown in Figure 9. Alternatively, multiple openings may be provided in the rib 5 in a distributed manner within the contact portion CN2.

[0098] As shown in Figure 9, the contact portion CN2 is located between the contact portion CN1 and the display area DA in a plan view. The end portion CLa of the conductive layer CL is located between the contact portion CN1 and the contact portion CN2 in a plan view.

[0099] In Figure 9, the regions where the thin film FL and the first sealing layer SE1 are located are shown by dashed lines. In Figure 10, the thin film FL is represented as a single layer. In reality, in the thin film FL, the upper electrodes UEs cover the organic layers ORs, and the capping layers CPs cover the upper electrodes UEs. The first sealing layer SE1 covers the thin film FL.

[0100] As shown in Figure 10, the thin film FL covers the conductive layer CL. As shown in Figure 9, the positions of the edge FLa of the thin film FL and the edge SE1a of the first sealing layer SE1 are approximately coincident in a plan view. The edges FLa and SE1a are located between the edge CLa of the conductive layer CL and the contact portion CN1.

[0101] As shown in Figure 10, a resin layer RS ​​and a second sealing layer SE2 are also formed in the peripheral region SA. For example, the edge RSa of the resin layer RS ​​is located closer to the display region DA than the edge FLa of the thin film FL and the edge SE1a of the first sealing layer SE1. In the example in Figure 10, the edge RSa is located near the edge CLa of the conductive layer CL, but this is not the only example.

[0102] In the example shown in Figure 10, the second sealing layer SE2 is provided over the entire peripheral region SA. However, the second sealing layer SE2 does not necessarily have to be provided near the edges 10a, 10b, 10c, and 10d of the substrate 10. The second sealing layer SE2 completely covers the resin layer RS. Furthermore, the second sealing layer SE2 is in contact with the first sealing layer SE1, the ribs 5, and the inorganic insulating layer 33. The edge RSa of the resin layer RS ​​is covered by the first sealing layer SE1 and the second sealing layer SE2. Also, the edge FLa of the thin film FL is covered by the ribs 5 and the second sealing layer SE2.

[0103] In the example shown in Figure 9, the first metal wire ML1 constituting the touch panel electrode TP extends along the partition wall 6 and forms a grid pattern overall. Specifically, the first metal wire ML1 overlaps with the first partition wall 6x and the second partition wall 6y, and surrounds the sub-pixels SP1, SP2, and SP3 (display elements DE1, DE2, and DE3), respectively. However, the first metal wire ML1 does not necessarily need to surround each of the sub-pixels SP1, SP2, and SP3 individually.

[0104] The wiring region LA overlaps with the conductive layer CL in a plan view. Lead wires LL1 to LL12 are arranged sequentially toward the display region DA. Outside of the lead wires LL1 to LL12, at least one wiring Lx is located. These wirings Lx include, for example, ground wiring to which a reference potential is supplied. Wiring Lx may also include wiring to supply signals for touch detection.

[0105] As shown in Figure 10, the lead wires LL1 to LL12 and the wiring Lx are placed on the second sealing layer SE2. The lead wires LL1 to LL12 and the wiring Lx are covered by the adhesive layer 21. The substrate 10 has an exposed area EA near the end 10a that does not face the cover member 20. The exposed area EA is not covered by the adhesive layer 21.

[0106] Figure 11 is a schematic cross-sectional view of the conductive layer CL near its end, Cla. The conductive layer CL has a lower section 61 and an upper section 62, similar to the partition wall 6 shown in Figure 4. At the end, Cla, the upper section 62 protrudes beyond the side surface of the lower section 61. That is, the shape of the conductive layer CL at the end is overhanging, similar to that of the partition wall 6.

[0107] When a thin film FL (organic layer ORs, upper electrode UEs, and cap layer CPs) is formed on a conductive layer CL of this shape, the thin film FL is divided at the edge CLa, as shown in Figure 11. The first sealing layer SE1 covers the thin film FL located above and below the conductive layer CL, respectively, and also covers the sides of the lower part 61.

[0108] In Figures 9 and 10, we focused on the structure between the display area DA and the edge 10a of the substrate 10, but a similar structure can be applied between the display area DA and the edge 10b. Lead wires LL13 to LL24 are placed on the second sealing layer SE2, similar to lead wires LL1 to LL12, and covered by the adhesive layer 21. For example, lead wires LL1 to LL24 and wiring Lx are formed from the same material and using the same process as the first metal wire ML1.

[0109] Figure 12 is a schematic plan view of the area enclosed by the dashed-line frame XII in Figure 8, and shows an example of a configuration that can be applied to the touch panel electrodes TP15~TP18 and relay wiring RL16~RL18.

[0110] The relay wiring RL17 includes a second metal wire ML2 located in the display area DA and a third metal wire ML3 located in the peripheral area SA. The second metal wire ML2, like the first metal wire ML1 that constitutes the touch panel electrode TP17, is located above the partition wall 6 and extends along the partition wall 6. The second metal wire ML2 surrounds the sub-pixels SP1, SP2, and SP3 respectively, and as a whole forms a grid. For example, both the second metal wire ML2 and the third metal wire ML3 are formed from the same material and using the same manufacturing process as the first metal wire ML1. That is, the second metal wire ML2 and the third metal wire ML3 are located on the second sealing layer SE2 and covered by the adhesive layer 21.

[0111] For example, the width of the second metal wire ML2 is the same as the width W3 of the first metal wire ML1 as explained using Figure 5. That is, the width of the second metal wire ML2 is less than or equal to the width W1 of the rib 5, and preferably less than or equal to the width W2 of the upper part 62.

[0112] The portion of the relay wiring RL17 composed of the second metal wire ML2 passes between the touch panel electrodes TP16 and TP18 and is connected to the third metal wire ML3. The third metal wire ML3 extends linearly, for example, in the first direction X, and is connected to the lead wire LL17. In the example in Figure 12, the relay wiring RL17 includes three third metal wires ML3 aligned in the second direction Y.

[0113] The relay wirings RL16 and RL18 include the third metal wire ML3 but do not include the second metal wire ML2. In the example in Figure 12, the relay wirings RL16 and RL18 include two third metal wires ML3 aligned in the second direction Y. That is, in this example, the number of third metal wires ML3 included in the relay wirings RL16 and RL18 is less than the number of third metal wires ML3 included in the relay wiring RL17.

[0114] The wiring area LA includes several electrically floating dummy wires DM. In the example in Figure 12, the dummy wires DM are positioned between the lead wires LL16, LL17, and LL18 and the display area DA, respectively. The dummy wires DM are positioned at a similar pitch to the lead wires LL16, LL17, and LL18 and extend parallel to them.

[0115] Figure 13 is a schematic plan view showing another example of a configuration applicable to the touch panel electrodes TP15-TP18 and relay wiring RL16-RL18. In this example, the relay wiring RL17 includes two third metal wires ML3. Furthermore, compared to the example in Figure 12, the width of the portion of the relay wiring RL17 made up of the second metal wire ML2 in the second direction Y is smaller.

[0116] In addition to the examples in Figures 12 and 13, various configurations can be applied to the relay wiring RL16-RL18. For example, the relay wiring RL16-RL18 may include more third metal wires ML3.

[0117] Figure 14 is a schematic plan view of the area enclosed by the dashed-line frame XIV in Figure 8, and shows an example of a configuration that can be applied to the touch panel electrodes TP13, TP14 and the relay wiring RL13, RL14 and their vicinity.

[0118] The relay wiring RL13, like the relay wiring RL17, includes a second metal wire ML2 and a third metal wire ML3. The portion of the relay wiring RL13 composed of the second metal wire ML2 extends in the first direction X through the space between the touch panel electrode TP14 and the peripheral area SA, and is connected to the lead wire LL13.

[0119] In the example in Figure 14, the relay wiring RL13 includes three third metal wires ML3 aligned in the second direction Y, and the relay wiring RL14 includes two third metal wires ML3 aligned in the second direction Y. The number of third metal wires ML3 included in the relay wiring RL13 may be two, as in the relay wiring RL17 shown in Figure 13, or it may be four or more. The number of third metal wires ML3 included in the relay wiring RL14 is not limited to two.

[0120] In the example in Figure 14, lead wires LL13 to LL24 are bent at 90° at two locations, corners CR1 and CR2. Above corner CR1 in the figure, lead wires LL13 to LL24 extend parallel to the second direction Y. Between corners CR1 and CR2, lead wires LL13 to LL24 extend parallel to the first direction X. Below corner CR2 in the figure, lead wires LL13 to LL24 extend parallel to the second direction Y. Dummy wiring DM is also placed in the lower area of ​​the display area DA in the figure (the area between the display area DA and end 10c). These dummy wirings DM extend parallel to the first direction X.

[0121] Figures 12 to 14 show configurations applicable to touch panel electrodes TP13 to TP18 and relay wiring RL13, RL14, RL16 to RL18, but similar configurations can be applied to other touch panel electrodes TP and relay wiring RL. Specifically, in the first direction X, touch panel electrodes TP adjacent to the peripheral region SA are connected to lead wire LL by relay wiring RL composed of a third metal wire ML3. On the other hand, in the first direction X, touch panel electrodes TP that are interposed between themselves and the peripheral region SA are connected to lead wire LL by relay wiring RL composed of a second metal wire ML2 and a third metal wire ML3.

[0122] Figure 15 is a schematic plan view of the lead wires LL13 to LL24, the connection section 82, and the terminal section T. The terminal section T has a plurality of first pads PD1 arranged in the first direction X. An output wire OL is connected to each first pad PD1.

[0123] The lead wires LL13 to LL24 and each output wire OL are arranged on different layers. At connection section 82, the lead wires LL13 to LL24 and the output wire OL are connected to each other via contact holes CHs.

[0124] The terminal section T also has a second pad PD2 for supplying signals to elements related to image display, such as the selector circuit ST. The second pad PD2 is aligned with the first pad PD1 in the first direction X.

[0125] The configuration for connecting lead wires LL1 to LL12 and terminal T via connection part 81 is the same as in the example in Figure 15.

[0126] Figure 16 is a schematic cross-sectional view of the peripheral region SA including the first pad PD1 and lead wire LL. The configuration shown in this figure can be applied to the connection structure between any of the lead wires LL1 to LL24 and the first pad PD1. The first pad PD1 and the output wire OL are integrally formed by, for example, a metal layer 43. However, the first pad PD1 and the output wire OL may be formed by different metal layers.

[0127] The terminal portion T is located in the exposed region EA. That is, the first pad PD1 is exposed from the adhesive layer 21. The edge of the first pad PD1 is covered by the second sealing layer SE2. The first pad PD1 is exposed from the second sealing layer SE2 through an opening APt1 provided in the second sealing layer SE2. Although not shown in Figure 16, the first pad PD1 is connected to the flexible circuit board FPC described above.

[0128] The contact holes CHs penetrate the second sealing layer SE2. The output wire OL and the lead wire LL are connected through the contact holes CHs. In the example in Figure 16, the lead wire LL located in the contact holes CHs is exposed from the adhesive layer 21. In another example, the lead wire LL may be entirely covered by the adhesive layer 21.

[0129] Figure 17 is a schematic cross-sectional view of the peripheral region SA including the second pad PD2. The second pad PD2 is also formed by a metal layer 43, similar to the first pad PD1.

[0130] The second pad PD2 is exposed from the second sealing layer SE2 through an opening APt2 provided in the second sealing layer SE2. Although not shown in Figure 17, the second pad PD2 is connected to the flexible circuit board FPC described above.

[0131] In the example shown in Figure 17, a dummy wiring DM is placed on top of the second sealing layer SE2. The dummy wiring DM is covered by an adhesive layer 21.

[0132] In the manufacturing of a display device DSP, a circuit layer 11 including a pixel circuit 1, gate drive circuits GD1 and GD2, a selector circuit ST, a power supply line PW, and a terminal section T is first formed on a substrate 10. After the formation of the circuit layer 11, an organic insulating layer 12 is formed on top of the circuit layer 11.

[0133] Subsequently, the lower electrodes LE1, LE2, and LE3 are formed, and the ribs 5 are formed on top of them. Furthermore, the partition wall 6 and the conductive layer CL are formed.

[0134] Next, a thin film FL1 containing an organic layer OR1, an upper electrode UE1, and a cap layer CP1, and a first sealing layer SE11 are formed on sub-pixel SP1; a thin film FL2 containing an organic layer OR2, an upper electrode UE2, and a cap layer CP2, and a first sealing layer SE12 are formed on sub-pixel SP2; and a thin film FL3 containing an organic layer OR3, an upper electrode UE3, and a cap layer CP3, and a first sealing layer SE13 are formed on sub-pixel SP3. The formation order of thin films FL1, FL2, and FL3 is not particularly limited, but in one example, thin film FL3 is formed first, thin film FL2 is formed next, and thin film FL1 is formed last.

[0135] Each layer constituting the thin films FL1, FL2, and FL3 (organic layer, upper electrode, and cap layer) is formed, for example, by vapor deposition. The first sealing layers SE11, SE12, and SE13 are formed, for example, by CVD (Chemical Vapor Deposition).

[0136] The thin film FL (organic layer ORs, upper electrode UEs, cap layer CPs) and the first sealing layer SE1 of the peripheral region SA can be formed using the same material and manufacturing process as, for example, the thin film FL3 and the first sealing layer SE13. The thin films FL, FL3 and the first sealing layers SE1, SE13 are patterned using the same photolithography process. As a result, as shown in Figure 10, the edge FLa of the thin film FL and the edge SE1a of the first sealing layer SE1 are aligned.

[0137] After the formation of the thin film FL and the first sealing layer SE1, a resin layer RS ​​is formed. The resin layer RS ​​is formed, for example, by a printing method, but may also be formed by other methods such as inkjet printing. From the viewpoint of suppressing spreading to the surroundings, it is preferable to increase the viscosity of the resin layer RS ​​before curing. A printing method is suitable for forming such a high-viscosity resin layer RS.

[0138] After the formation of the resin layer RS, the second sealing layer SE2 is formed. The second sealing layer SE2 is first formed over the entire substrate 10 and then patterned by a photolithography process. This photolithography process forms the openings APt1 and APt2 and the contact holes CHs.

[0139] Subsequently, the first metal wire ML1, the second metal wire ML2, the third metal wiring ML3, the lead wire LL, and the dummy wiring DM are formed. These wirings are obtained by patterning the metal film using the same photolithography process. However, if the density of the resist formed in areas where the metal film should remain varies significantly, the etching of the metal film becomes uneven, and it may not be possible to obtain lead wires LL, etc., in the desired shape. The dummy wiring DM contributes to correcting such unevenness. That is, by placing dummy wiring DM in areas where metal wires ML1, ML2, ML3 and lead wire LL are not placed, excessive etching of metal wires ML1, ML2, ML3 and lead wire LL can be suppressed.

[0140] After the formation of the metal wires ML1, ML2, ML3, lead wire LL, and dummy wiring DM, the cover member 20 is bonded to them with an adhesive layer 21. Furthermore, a flexible circuit board (FPC) is connected to the terminal section T to complete the display device (DSP).

[0141] In this embodiment, the thin films FL1, FL2, and FL3 arranged in the display area DA are individually sealed by a partition wall 6 and first sealing layers SE11, SE12, and SE13, respectively. Furthermore, a resin layer RS ​​covers the first sealing layers SE11, SE12, and SE13, and a second sealing layer SE2 covers the resin layer RS. With this configuration, the penetration of moisture into the thin films FL1, FL2, and FL3, and further into the resin layer RS ​​above them, is suitably suppressed, making it possible to obtain a display device DSP with excellent resistance to moisture.

[0142] Furthermore, in this embodiment, the first metal wire ML1 constituting the touch panel electrode TP is located above the partition wall 6 and extends along the partition wall 6. With this configuration, the light emitted from the display elements DE1, DE2, and DE3 is less likely to be obstructed by the first metal wire ML1. This makes it possible to improve display quality while providing the display device DSP with touch detection functionality.

[0143] As explained using Figure 5, if the width W3 of the first metal wire ML1 is less than or equal to the width W1 of the rib 5, and further less than or equal to the width W2 of the upper part 62, then brightness reduction is suppressed even when the display area DA is viewed at an angle, thus further improving display quality.

[0144] As shown in Figures 12 to 13, when a portion of the relay wiring RL is composed of a second metal wire ML2 similar to the first metal wire ML1, it is possible to suppress the degradation of display quality caused by the relay wiring RL. However, if the portion of the relay wiring RL located in the display area DA is composed of metal wires with different widths or patterns than the first metal wire ML1, brightness unevenness caused by the relay wiring RL may occur. In contrast, as shown in the examples in Figures 12 to 14, if the second metal wire ML2 has a grid pattern similar to the first metal wire ML1 and also has the same width as the first metal wire ML1, the brightness can be made uniform throughout the entire display area DA.

[0145] In this embodiment, the end portion FLa of the thin film FL located in the peripheral region SA is covered by the second sealing layer SE2. This suppresses the intrusion of moisture into the peripheral circuit through the thin film FL.

[0146] Furthermore, in this embodiment, as shown in Figure 11, the thin film FL is separated by the edge CLa of the conductive layer CL. This more reliably suppresses moisture penetration through the thin film FL.

[0147] The configuration disclosed in this embodiment can be modified in various ways. Several modifications are disclosed below. Figure 18 is a schematic plan view of the pixel PX and the first metal wire ML1 according to the first modified example. The pixel PX according to the first modified example includes sub-pixels SP1, SP2, SP3 (display elements DE1, DE2, DE3) with the same layout as in Figure 2.

[0148] In the first modified example, the first metal wire ML1 is not placed between the sub-pixels SP1 and SP2 contained in each pixel PX. The first metal wire ML1 is placed between the sub-pixels SP1 and SP2 contained in different pixels PX. A similar configuration can be applied to the second metal wire ML2.

[0149] Figure 19 is a schematic plan view of the pixel PX and the first metal wire ML1 according to the second modified example. The pixel PX according to the second modified example includes sub-pixels SP1, SP2, and SP3 with the same layout as in Figure 2.

[0150] In the second modified example, the first metal wire ML1 is placed between adjacent pixels PX, and the first metal wire ML1 is not placed between sub-pixels SP1, SP2, and SP3 contained within a single pixel PX. A similar configuration can be applied to the second metal wire ML2.

[0151] Figure 20 is a schematic plan view of a pixel PX and a first metal wire ML1 according to the third modified example. In the pixel PX according to the third modified example, sub-pixels SP1, SP2, and SP3 are arranged in the first direction X. For example, the widths of sub-pixels SP1, SP2, and SP3 in the second direction Y are the same. The widths of sub-pixels SP1, SP2, and SP3 in the first direction X may be the same or different. When such pixels PX are arranged in a matrix, the display area DA is formed with columns containing multiple sub-pixels SP1 that are continuous in the second direction Y, columns containing multiple sub-pixels SP2 that are continuous in the second direction Y, and columns containing multiple sub-pixels SP3 that are continuous in the second direction Y.

[0152] In the third modified example, the sub-pixels SP1, SP2, and SP3 are all surrounded by the first metal wire ML1. A similar configuration can be applied to the second metal wire ML2.

[0153] Figure 21 is a schematic plan view of the pixel PX and the first metal wire ML1 according to the fourth modified example. The pixel PX according to the fourth modified example includes sub-pixels SP1, SP2, and SP3 with the same layout as in Figure 20.

[0154] In the fourth modified example, the first metal wire ML1 is placed between adjacent pixels PX, and the first metal wire ML1 is not placed between sub-pixels SP1, SP2, and SP3 contained within a single pixel PX. A similar configuration can be applied to the second metal wire ML2.

[0155] Figure 22 is a schematic plan view of a pixel PX and a first metal wire ML1 according to the fifth modified example. The pixel PX according to the fifth modified example includes sub-pixels SP1, SP2, SP3, and a white sub-pixel SP4. Sub-pixel SP4 has a display element DE4 that emits white light. In each pixel PX, sub-pixels SP1 and SP4 are aligned in the first direction X, and sub-pixels SP2 and SP3 are aligned in the first direction X. Also, sub-pixels SP1 and SP2 are aligned in the second direction Y, and sub-pixels SP3 and SP4 are aligned in the second direction Y.

[0156] In the fifth modified example, the sub-pixels SP1, SP2, SP3, and SP4 are all surrounded by the first metal wire ML1. A similar configuration can be applied to the second metal wire ML2.

[0157] Figure 23 is a schematic plan view of the pixel PX and the first metal wire ML1 according to the sixth modified example. The pixel PX according to the sixth modified example includes sub-pixels SP1, SP2, SP3, and SP4 with the same layout as in Figure 22.

[0158] In the sixth modified example, the first metal wire ML1 is placed between adjacent pixels PX. Furthermore, the first metal wire ML1 is also placed between sub-pixels SP1 and SP4 contained within one pixel PX, and between sub-pixels SP2 and SP3 contained within one pixel PX. On the other hand, the first metal wire ML1 is not placed between sub-pixels SP1 and SP2 contained within one pixel PX, and between sub-pixels SP3 and SP4 contained within one pixel PX. A similar configuration can be applied to the second metal wire ML2.

[0159] Figure 24 is a schematic plan view of the pixel PX and the first metal wire ML1 according to the seventh modified example. The pixel PX according to the seventh modified example includes sub-pixels SP1, SP2, SP3, and SP4 with the same layout as in Figure 22.

[0160] In the seventh modified example, the first metal wire ML1 is placed between adjacent pixels PX. Furthermore, the first metal wire ML1 is also placed between sub-pixels SP1 and SP2 contained within one pixel PX, and between sub-pixels SP3 and SP4 contained within one pixel PX. On the other hand, the first metal wire ML1 is not placed between sub-pixels SP1 and SP4 contained within one pixel PX, and between sub-pixels SP2 and SP3 contained within one pixel PX. A similar configuration can be applied to the second metal wire ML2.

[0161] Figure 25 is a schematic plan view of the pixel PX and the first metal wire ML1 according to the eighth modified example. The pixel PX according to the eighth modified example includes sub-pixels SP1, SP2, SP3, and SP4 with the same layout as in Figure 22.

[0162] In the eighth modified example, the first metal wire ML1 is placed between adjacent pixels PX, and the first metal wire ML1 is not placed between sub-pixels SP1, SP2, SP3, and SP4 contained within a single pixel PX. A similar configuration can be applied to the second metal wire ML2.

[0163] The first to eighth modifications described above can also be applied to the embodiments described later. Furthermore, the configurations of the pixel PX, the first metal wire ML1, and the second metal wire ML2 can be modified in ways other than those shown in the first to eighth modifications.

[0164] [Second Embodiment] A second embodiment will now be described. Unless otherwise specified, the configuration is the same as in the first embodiment. Figures 26 and 27 are schematic cross-sectional views of the peripheral region SA of the display device DSP according to the second embodiment. Figure 26 shows a cross-section of the peripheral region SA including the first pad PD1, similar to Figure 16, and Figure 27 shows a cross-section of the peripheral region SA including the second pad PD2, similar to Figure 17.

[0165] In the examples shown in Figures 16 and 17, the organic insulating layer 12 was not formed near the terminal portion T. On the other hand, in the examples shown in Figures 26 and 27, the organic insulating layer 12 was formed around the terminal portion T.

[0166] As shown in Figure 26, the organic insulating layer 12 covers the edge of the first pad PD1 and the output wire OL. The organic insulating layer 12 has an opening that overlaps with the opening APt1. Furthermore, the contact holes CHs penetrate not only the second sealing layer SE2 but also the organic insulating layer 12. The lead wire LL is connected to the output wire OL through the contact holes CHs.

[0167] Furthermore, as shown in Figure 27, the organic insulating layer 12 covers the edge of the second pad PD2. The organic insulating layer 12 has an opening that overlaps with the opening APt2.

[0168] Even with the configuration of this embodiment, the same effects as in the first embodiment can be obtained. Furthermore, in the configuration of this embodiment, protrusions made of the organic insulating layer 12 are formed around the first pad PD1 and the second pad PD2. This prevents the conductive adhesive connecting the flexible circuit board (FPC) and the pads PD1 and PD2 from flowing, making it possible to achieve good connection and conductivity between the flexible circuit board (FPC) and the pads PD1 and PD2.

[0169] [Third Embodiment] A third embodiment will now be described. Unless otherwise specified, the configuration is the same as in the embodiments described above. Figures 28 and 29 are schematic cross-sectional views of the peripheral region SA of the display device DSP according to the third embodiment. Figure 28 shows a cross-section of the peripheral region SA including the first pad PD1, similar to Figure 26, and Figure 29 shows a cross-section of the peripheral region SA including the second pad PD2, similar to Figure 27.

[0170] In this embodiment, as in the second embodiment, an organic insulating layer 12 is formed around the terminal portion T. Furthermore, in this embodiment, the organic insulating layer 12 has a slit SLT. The slit SLT penetrates the organic insulating layer 12.

[0171] For example, the slit SLT surrounds the display area DA. That is, in a plan view, the slit SLT is located between the pads PD1 and PD2 and the display area DA. More specifically, in a plan view, the slit SLT is located between the contact holes CHs and the display area DA. In the cross-section of Figure 28, the slit SLT is located between the contact holes CHs and the conductive layer CL.

[0172] In the examples shown in Figures 28 and 29, the slit SLT is covered by the second sealing layer SE2. The lead wire LL crosses the slit SLT. Furthermore, the cover member 20 and the adhesive layer 21 are located above the slit SLT.

[0173] As in this embodiment, by providing the slit SLT, it is possible to suppress the intrusion of moisture into the interior of the display device DSP through the organic insulating layer 12 from the vicinity of pads PD1 and PD2. In particular, by providing the slit SLT inside the contact holes CHs, it is possible to effectively suppress the intrusion of moisture from the vicinity of the contact holes CHs.

[0174] [Fourth Embodiment] A fourth embodiment will now be described. Configurations not specifically mentioned are the same as those in the embodiments described above. Figure 30 is a schematic cross-sectional view of the display area DA of the display device DSP according to the fourth embodiment. Similar to the example in Figure 3, the first metal wire ML1 is arranged on the second sealing layer SE2. In this embodiment, the first metal wire ML1 is covered by the third sealing layer SE3. The third sealing layer SE3 is covered by the adhesive layer 21.

[0175] The third sealing layer SE3, like the second sealing layer SE2, is formed of an inorganic insulating material such as silicon nitride, silicon oxide, or silicon oxynitride.

[0176] The third sealing layer SE3 is provided over, for example, the entire display area DA and the peripheral area SA. The third sealing layer SE3 has openings in the terminal portion T that are the same shape as the openings APt1 and APt2 of the second sealing layer SE2. The third sealing layer SE3 covers not only the first metal wire ML1, but also the second metal wire ML2, the lead wire LL, and the dummy wiring DM.

[0177] As in this embodiment, by providing a third sealing layer SE3, the first metal wire ML1, the second metal wire ML2, the lead wire LL, and the dummy wiring DM can be protected from moisture. Other effects are the same as in the embodiments described above.

[0178] All display devices that a person skilled in the art can implement by appropriately modifying the design based on the display devices described above as embodiments of the present invention also fall within the scope of the present invention insofar as they encompass the gist of the present invention.

[0179] Within the scope of the concept of the present invention, a person skilled in the art can conceive of various modifications, and such modifications are also understood to fall within the scope of the present invention. For example, any modifications made by a person skilled in the art to add, delete, or change the design of any of the above-described embodiments, or to add, omit, or change the conditions of any process, are also included within the scope of the present invention, as long as they retain the essence of the present invention.

[0180] Furthermore, any other effects and advantages brought about by the embodiments described above that are obvious from the description herein or that can be appropriately conceived by those skilled in the art are naturally considered to be brought about by the present invention. [Explanation of Symbols]

[0181] DSP...Display device, DA...Display area, SA...Peripheral area, PX...Pixel, SP1, SP2, SP3...Sub-pixel, SE11, SE12, SE13, SE1...First sealing layer, SE2...Second sealing layer, RS...Resin layer, CL...Conductive layer, PW...Power supply line, T...Terminal section, PD1, PD2...Pads, TP...Touch panel electrode, ML1...First metal wire, ML2...Second metal wire, LL...Lead wire, RL...Relay wiring, 1...Pixel circuit, 5...Rib, 6...Partition wall, 10...Substrate, 20...Cover member, 21...Adhesive layer, 61...Lower part of partition wall, 62...Upper part of partition wall.

Claims

1. A plurality of display elements each include a lower electrode, an upper electrode facing the lower electrode, and an organic layer positioned between the lower electrode and the upper electrode that emits light according to the potential difference between the lower electrode and the upper electrode, A partition wall enclosing each of the plurality of display elements, including a conductive lower part and an upper part protruding from the side of the lower part, A touch panel electrode for detecting an object that comes into contact with or is close to a display area including the plurality of display elements, A conductive layer is arranged in the peripheral region surrounding the display area and has the same layer as the partition wall, Lead wires arranged in the aforementioned peripheral region, A relay wiring that electrically connects the touch panel electrode and the lead wire, Equipped with, The touch panel electrode includes a first metal wire located above the partition wall and extending along the partition wall. The relay wiring includes a third metal wire that electrically connects the first metal wire and the lead wire. The lead wire overlaps with the conductive layer. Display device.

2. The system further comprises ribs having multiple pixel apertures that overlap with each of the aforementioned multiple display elements, The partition wall is positioned on the rib, The width of the first metal wire is less than or equal to the width of the rib between two adjacent pixel apertures. The display device according to claim 1.

3. The width of the first metal wire is less than or equal to the width of the upper part. The display device according to claim 1.

4. A plurality of first sealing layers covering each of the plurality of display elements, A resin layer covering the plurality of first sealing layers, A second sealing layer covering the aforementioned resin layer, Furthermore, The first metal wire is placed on the second sealing layer. The display device according to claim 1.

5. A cover member facing the second sealing layer, An adhesive layer for bonding the cover member to the second sealing layer, Furthermore, The first metal wire is covered by the adhesive layer. The display device according to claim 4.

6. Further comprising a terminal portion arranged in the peripheral region and connected to the lead wire, The display device according to claim 1.

7. The relay wiring includes a second metal wire located above the partition wall and extending along the partition wall. The display device according to claim 6.

8. The system further comprises dummy wiring arranged in the peripheral region and extending parallel to the lead wires, The display device according to claim 1.

9. The touch panel electrode includes a first touch panel electrode and a second touch panel electrode, The aforementioned lead wires include a first lead wire and a second lead wire, The relay wiring includes a first relay wiring that electrically connects the first touch panel electrode and the first lead wire, and a second relay wiring that electrically connects the second touch panel electrode and the second lead wire. The dummy wiring is positioned to extend parallel to the first lead wire or the second lead wire between the third metal wire of the first relay wiring and the third metal wire of the second relay wiring. The display device according to claim 8.

10. An organic insulating layer located below the lead wire, The output wire located below the aforementioned organic insulating layer, Furthermore, The terminal portion is located below the organic insulating layer and includes a conductive pad connected to the output line. The lead wire and the output wire are connected through a contact hole that penetrates the organic insulating layer. The display device according to claim 6.

11. The organic insulating layer has a slit located between the pad and the display area. The display device according to claim 10.

12. In a plan view, the first metal wire surrounds at least one of the plurality of display elements. The display device according to any one of claims 1 to 11.

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