Encoding configuration method and apparatus

Abstract

The present application provides an encoding configuration method and apparatus. The method includes: an optical network unit receives first information, the first information indicating a change amount of forward error correction codeword information compared with a first forward error correction mother code; the optical network unit determines forward error correction codeword information based on the first information; according to the technical solution provided in the present application, the change amount of forward error correction codeword information compared with the first forward error correction mother code is indicated to help implement a flexible configuration of forward error correction codeword information.

Description

Technical Field

[0001] This application claims the priority of Chinese Patent Application No. 202210015997.2, titled "Encoding Composition Method and Apparatus", filed with the China National Intellectual Property Administration on January 7, 2022, the entire content of which is incorporated herein by reference.

[0002] This application relates to the field of optical communication, and more particularly, to an encoding composition method and apparatus.

Background Art

[0003] In a passive optical network (PON) system, different optical network units (ONUs) have different transmission distances to an optical line termination (OLT), or different optical network units pass through different optical splitters to the optical line termination, resulting in different link losses between different ONUs and the OLT. Forward error correction (FEC) is used to solve the problems of link loss and transmission penalty caused by optical splitters and optical fiber transmission. In this technology, redundant error correction codes may be added to the transmitted code sequence to significantly narrow the allowable range of the optical signal-to-noise ratio (OSNR) at the receiving end and reduce the bit error rate and transmission power.

[0004] Currently, to guarantee transmission performance, FEC coding methods are defined between the OLT and ONU based on the maximum possible link loss, and a unified FEC coding method is used. Generally, in a PON system, the link loss from one ONU to the OLT is high, and the link loss from another ONU to the OLT is low. An ONU with low link loss does not require FEC coding with strong error correction capabilities, but it must use the same FEC coding method as the ONU with high link loss. However, such FEC coding generally has a large overhead or is complex, resulting in wasted effort.

[0005] Therefore, there is an urgent need for an encoding configuration method that enables flexible configuration of forward error correction FEC codeword information. [Overview of the project] [Means for solving the problem]

[0006] This application provides an encoding configuration method and apparatus to help implement a flexible configuration of forward error correction codeword information.

[0007] According to a first aspect, an encoding configuration method is provided. The method includes: an optical network unit receives first information, the first information indicating the amount of change in forward error correction codeword information compared to a first forward error correction mother code; and the optical network unit determines forward error correction codeword information based on the first information.

[0008] According to the technical solution provided in this application, the amount of change in the forward error correction codeword information compared to a first forward error correction parent code is shown in order to help implement a flexible configuration of forward error correction codeword information.

[0009] In relation to the first aspect, in a partial implementation of the first aspect, prior to receiving the first information, the method further includes: the optical network unit transmits capability report information, the capability report information indicates forward error correction master codes supported by the optical network unit, and the forward error correction master codes supported by the optical network unit include a first forward error correction master code.

[0010] According to the technical solution provided in this application, an optical line termination device can determine a first forward error correction marker from forward error correction markers supported by an optical network unit, process the first forward error correction marker, and determine forward error correction codeword information suitable for the optical network unit. Furthermore, standard-defined codeword information is not required. This helps to implement a flexible configuration of forward error correction codeword information.

[0011] In relation to the first embodiment, in some implementations of the first embodiment, before transmitting capability reporting information, the method further includes: the optical network unit receives capability query information, which is used to query forward error correction parent codes supported by the optical network unit.

[0012] In relation to the first embodiment, in other implementations of a part of the first embodiment, the first information includes second information. The second information indicates, by using a bit sequence, the amount of change in the payload information of the forward error correction codeword information compared to the payload information of the first forward error correction parent code.

[0013] In relation to the first aspect, in other implementations of a part of the first aspect, the bit sequence of the second information includes the first sequence, the value of which is 0, representing that 256 bits or 128 bits of the first forward error correction marker corresponding to the first sequence are shortened. In this case, the bit sequence of the second information may further include the second sequence, the value of which is 1, representing that 256 bits or 128 bits of the first forward error correction marker corresponding to the second sequence are not shortened. Alternatively, the bit sequence of the second information includes the first sequence, the value of which is 1, representing that 256 bits or 128 bits of the first forward error correction marker corresponding to the first sequence are shortened. In this case, the bit sequence of the second information may further include the second sequence, the value of which is 0, representing that 256 bits or 128 bits of the first forward error correction marker corresponding to the second sequence are not shortened.

[0014] Each bit in a bit sequence corresponds to one column (or half a column) of the parent code matrix, corresponding to 256 (or 128) bits of parent code information.

[0015] In relation to the first aspect, in other implementations of a part of the first aspect, the first information further includes third information. The third information indicates, by using a bit sequence, the change in the parity bit information of the forward error correction codeword information compared to the parity bit information of the first forward error correction parent code.

[0016] In relation to the first aspect, in other implementations of a part of the first aspect, the bit sequence of the third information includes a third sequence, the value corresponding to the third sequence being 0, which indicates that 256 bits or 128 bits of the first forward error correction marker corresponding to the third sequence are punctured. In this case, the bit sequence of the third information may further include a fourth sequence, the value corresponding to the fourth sequence being 1, which indicates that 256 bits or 128 bits of the first forward error correction marker corresponding to the fourth sequence are not punctured. Alternatively, the bit sequence of the third information includes a third sequence, the value corresponding to the third sequence being 1, which indicates that 256 bits or 128 bits of the first forward error correction marker corresponding to the third sequence are punctured. In this case, the bit sequence of the third information may further include a fourth sequence, the value corresponding to the fourth sequence being 0, which indicates that 256 bits or 128 bits of the first forward error correction marker corresponding to the fourth sequence are not punctured.

[0017] In the technical solution of this application, specific forward error correction codeword information is represented by a bit sequence. To help implement a flexible configuration of forward error correction codeword information, the first forward error correction parent code may be processed in units of one or half columns of the encoded matrix to obtain the forward error correction codeword information.

[0018] In relation to the first aspect, in further implementations of the first aspect, the first information includes a first value indicating that M bits of the payload information of a first forward error correction parent code are shortened based on a first order in order to obtain the payload information of the forward error correction codeword information, where M is obtained by multiplying the first value by 256 or 128.

[0019] In relation to the first aspect, in further implementations of the first aspect, the first information includes a second value indicating that N bits of the parity bit information of a first forward error correction parent code are punctured based on a second order in order to obtain the parity bit information of the forward error correction codeword information, where N is obtained by multiplying the second value by 256 or 128.

[0020] In the technical solution of this application, in order to help implement a flexible configuration of forward error correction codeword information, the value represents that the parent code matrix corresponding to the first forward error correction parent code is processed to obtain specific forward error correction codeword information.

[0021] The first and / or second order is back to front or front to back.

[0022] In relation to the first aspect, in a partial implementation of the first aspect, the first information further includes a fourth piece of information, the fourth piece of information indicating that the first information is valid.

[0023] The first information is carried within the first message. The first message includes at least one of the following: a physical layer operations, administration and maintenance (PLOAM) message, an optical network terminal management and control interface (OMCI) message, and an operations, administration and maintenance (OAM) message.

[0024] According to a second aspect, an encoding configuration method is provided. The method includes the following. An optical line terminal device determines first information, and the first information indicates a change amount of forward error correction codeword information compared with a first forward error correction mother code. The optical line terminal device transmits the first information to an optical network unit, and the first information is used by the optical network unit to determine forward error correction codeword information.

[0025] According to the technical solution provided in this application, in order to help implement a flexible configuration of forward error correction codeword information, a change amount of forward error correction codeword information compared with a first forward error correction mother code is shown.

[0026] In connection with the second aspect, in some implementations of the second aspect, before transmitting the first information, the method further includes the following. The optical line terminal device receives capability report information, and the capability report information indicates a forward error correction mother code supported by the optical network unit, and the forward error correction mother code supported by the optical network unit includes the first forward error correction mother code.

[0027] According to the technical solution provided in this application, the optical line terminal device can determine the first forward error correction mother code from the forward error correction mother code supported by the optical network unit, process the first forward error correction mother code, and determine forward error correction codeword information suitable for the optical network unit. Furthermore, codeword information defined by the standard is not required. This helps implement a flexible configuration of forward error correction codeword information.

[0028] In connection with the second aspect, in some implementations of the second aspect, before receiving the capability report information, the method further includes the following. The optical line terminal device transmits capability query information, and the capability query information is used to query the forward error correction mother code supported by the optical network unit.

[0029] In connection with the second aspect, in some other implementations of the second aspect, the first information includes the second information. The second information indicates, by using a bit sequence, the amount of change in the payload information of the forward error correction codeword information compared to the payload information of the first forward error correction mother codeword.

[0030] In connection with the second aspect, in some other implementations of the second aspect, the bit sequence of the second information includes the first sequence, and the value of the first sequence is 0 indicating that 256 bits or 128 bits of the first forward error correction mother codeword corresponding to the first sequence are shortened. In this case, the bit sequence of the second information may further include the second sequence, and the value of the second sequence is 1 indicating that 256 bits or 128 bits of the first forward error correction mother codeword corresponding to the second sequence are not shortened. Alternatively, the bit sequence of the second information includes the first sequence, and the value corresponding to the first sequence is 1 indicating that 256 bits or 128 bits of the first forward error correction mother codeword corresponding to the first sequence are shortened. In this case, the bit sequence of the second information may further include the second sequence, and the value of the second sequence is 0 indicating that 256 bits or 128 bits of the first forward error correction mother codeword corresponding to the second sequence are not shortened.

[0031] The bits in the bit sequence correspond to one column (or half column) of the mother code matrix and correspond to 256 (or 128) bits of the mother code information.

[0032] In connection with the second aspect, in some other implementations of the second aspect, the first information further includes the third information. The third information indicates, by using a bit sequence, the amount of change in the parity bit information of the forward error correction codeword information compared to the parity bit information of the first forward error correction mother codeword.

[0033] In relation to the second aspect, in other implementations of a part of the second aspect, the bit sequence of the third information includes a third sequence, the value corresponding to the third sequence being 0, which indicates that 256 bits or 128 bits of the first forward error correction marker corresponding to the third sequence are punctured. In this case, the bit sequence of the third information may further include a fourth sequence, the value corresponding to the fourth sequence being 1, which indicates that 256 bits or 128 bits of the first forward error correction marker corresponding to the fourth sequence are not punctured. Alternatively, the bit sequence of the third information includes a third sequence, the value corresponding to the third sequence being 1, which indicates that 256 bits or 128 bits of the first forward error correction marker corresponding to the third sequence are punctured. In this case, the bit sequence of the third information may further include a third sequence, the value corresponding to the third sequence being 0, which indicates that 256 bits or 128 bits of the first forward error correction marker corresponding to the third sequence are not punctured.

[0034] In the technical solution of this application, specific forward error correction codeword information is represented by a bit sequence. To help implement a flexible configuration of forward error correction codeword information, the first forward error correction parent code may be processed in units of one or half columns of the encoded matrix to obtain the forward error correction codeword information.

[0035] In relation to the second aspect, in further implementations of the second aspect, the first information includes a first value indicating that M bits of the payload information of a first forward error correction parent code are shortened based on a first order in order to obtain the payload information of the forward error correction codeword information, where M is obtained by multiplying the first value by 256 or 128.

[0036] In relation to the second aspect, in further implementations of the second aspect, the first information includes a second value indicating that N bits of the parity bit information of a first forward error correction parent code are punctured based on a second order in order to obtain the parity bit information of the forward error correction codeword information, where N is obtained by multiplying the second value by 256 or 128.

[0037] In the technical solution of this application, in order to help implement a flexible configuration of forward error correction codeword information, the value represents that the parent code matrix corresponding to the first forward error correction parent code is processed to obtain specific forward error correction codeword information.

[0038] The first and / or second order is back to front or front to back.

[0039] In relation to the second aspect, in some implementations of the second aspect, the first information further includes a fourth piece of information, the fourth piece of information indicating that the first information is valid.

[0040] The first information is carried within the first message. The first message includes at least one of the following: a physical layer operation, management, and maintenance PLOAM message, an optical network terminal management and control interface OMCI message, and an operation, management, and maintenance OAM message.

[0041] According to a third aspect, an encoding configuration device is provided. The device includes a transceiver unit configured to receive first information, wherein the first information indicates the amount of change in forward error correction codeword information compared to a first forward error correction parent code, and a processing unit configured to determine forward error correction codeword information based on the first information.

[0042] In relation to a third aspect, in a partial implementation of the third aspect, the transceiver unit is further configured to transmit capability reporting information, the capability reporting information indicating a forward error correction master code supported by an optical network unit, the forward error correction master code supported by the optical network unit includes a first forward error correction master code.

[0043] In relation to the third aspect, in some implementations of the third aspect, the transceiver unit is further configured to receive capability query information, which is used to query a forward error correction parent code supported by the optical network unit.

[0044] According to a fourth aspect, an encoding configuration device is provided. The device includes a processing unit configured to determine first information, wherein the first information indicates the amount of change in forward error correction codeword information compared to a first forward error correction master code, and a transceiver unit configured to transmit the first information to an optical network unit.

[0045] In relation to the fourth aspect, in some implementations of the fourth aspect, the transceiver unit is further configured to receive capability reporting information, the capability reporting information indicating forward error correction master codes supported by the optical network unit, the forward error correction master codes supported by the optical network unit include a first forward error correction master code.

[0046] In relation to the fourth aspect, in some implementations of the fourth aspect, the transceiver unit is further configured to transmit capability query information, which is used to query a forward error correction parent code supported by the optical network unit.

[0047] According to a fifth aspect, a communication device including a processor is provided. The processor is coupled to memory and configured to read instructions in memory and then execute a method according to any one of the preceding aspects based on the instructions. The communication device may be an optical network unit entity in the first aspect, or a device including an optical network unit entity, or the communication device may be an optical line termination device entity in the second aspect, or a device including an optical line termination device entity.

[0048] In relation to the fifth aspect, in possible implementations, the communication device further includes a memory, which is configured to store necessary program instructions and data.

[0049] In relation to the fifth aspect, in possible implementations, the communication device is a chip or a chip system. Optionally, when the communication device is a chip system, the communication device may include a chip, or it may include a chip and other discrete devices.

[0050] According to a sixth aspect, a communication device is provided which includes a processor and an interface circuit. The interface circuit is configured to receive a computer program or instruction and to transmit a computer program or instruction to the processor. The processor is configured to execute a computer program or instruction so that the communication device performs the method according to the first or second aspect.

[0051] In relation to the sixth aspect, in possible implementations, the communication device is a chip or a chip system. Optionally, when the device used for charging is a chip system, the device may include a chip, or a chip and another discrete device.

[0052] According to the seventh aspect, a communication system is provided which includes an optical network unit and an optical line termination device according to the first and second aspects.

[0053] The optical network unit is configured to perform the method according to the first embodiment. The optical line termination device is configured to perform the method according to the second embodiment.

[0054] According to the eighth aspect, a computer program product is provided. The computer program product includes computer program code. When the computer program code is executed on a computer, the computer is enabled to perform the method according to the preceding aspects.

[0055] It should be noted that all or part of the computer program code may be stored in a first storage medium. The first storage medium may be encapsulated together with the processor or separately from the processor. This is not particularly limited to this embodiment of the present application.

[0056] According to the ninth aspect, a computer-readable medium is provided. The computer-readable medium stores program code. When the computer program code is executed in a computer, the computer is enabled to perform the method according to the preceding aspect.

[0057] According to a tenth aspect, a chip system including memory and a processor is provided. The memory is configured to store computer programs. The processor is configured to call and execute computer programs from memory in order to enable a communication device on which the chip system is installed to perform a method according to any one of the first and second aspects and their possible implementations.

[0058] The chip system may include an input chip or interface configured to transmit information or data, and an output chip or interface configured to receive information or data. [Brief explanation of the drawing]

[0059] [Figure 1] This is a schematic diagram of uplink and downlink transmission in a PON system. [Figure 2] This is a schematic diagram of the encoding configuration method according to an embodiment of the present application. [Figure 3] This is a schematic diagram of a specific example of an encoding configuration method according to an embodiment of the present application. [Figure 4] This is a schematic diagram showing forward error correction codeword information using a bit sequence according to an embodiment of the present application. [Figure 5] This is a schematic diagram showing forward error correction codeword information by using values ​​according to an embodiment of the present application. [Figure 6] This is a schematic diagram of an encoding device according to an embodiment of the present application. [Figure 7] This is a schematic diagram of an encoding configuration device according to an embodiment of the present application. [Modes for carrying out the invention]

[0060] The technical solution of this application will be described below with reference to the attached drawings.

[0061] As telecommunications services become increasingly sophisticated, user demand for bandwidth is also growing. Telecommunications operators in China and around the world have considered fiber-to-the-home (FTTH) to be the inevitable choice for access networks. FTTH using PON systems has become the mainstream option. In a PON network, this access technology allows only optical fibers and passive optical devices such as optical splitters to be used between the local end (OLT) and the user (ONU) of the access network, without the need to rent equipment rooms or provide power. Thus, a PON network is called a passive optical network. During data transmission and reception, broadcast format is used for downstream traffic in a PON network, and unicast format is used for upstream traffic in a PON network.

[0062] Figure 1 is a schematic diagram of uplink and downlink transmission in a PON system.

[0063] As shown in Figure 1, during downlink transmission, the data delivered from the OLT One channel The signal is split into N parts using an optical splitter. Channel The signal is divided into N parts. Channel Faith The number , all Major U They are transmitted simultaneously. The ONU selectively receives downlink data with the same ID as the ONU and discards other data.

[0064] Upward direction In N pieces from the ONU ChannelOptical signals are combined into a single optical signal group using time division multiplexing (TDM) technology. The principle is to divide the uplink transmission time into several time slots Ti (i=1, 2, 3, ..., 32, ...). In each time slot, only one ONU is arranged to transmit grouping information to the OLT in a grouping scheme, and each ONU transmits the grouping information sequentially based on the order specified by the OLT. TDM requires the OLT to measure the distance between the OLT and each ONU and then perform strict transmission timing for each ONU. Each ONU obtains timing information from the downlink signal transmitted by the OLT and transmits the uplink grouping signal in the time slot specified by the OLT to avoid competition between ONUs. A PON based on this principle is called a time division multiplexing passive optical network (TDM-PON).

[0065] In PON systems, different ONUs have different transmission distances to the OLT, or different ONUs pass through different optical splitters to the OLT, resulting in different link losses between different ONUs and OLTs. FEC technology is used to solve the link loss and transmission penalty caused by optical splitters and optical fiber transmission. In this technology, redundant error correction codes may be added to the transmitted code sequence to significantly narrow the acceptable range of OSNR at the receiving end and reduce bit error rate and transmit power. Furthermore, this technology can effectively improve the channels used for optical fiber signal transmission. Various types of distortion and uneven latency are always present during signal transmission in the medium. The final result of the signal's bit error rate and jitter may be reflected in the system's bit error rate. FEC technology can solve the problems of fiber dispersion, signal attenuation, channel noise, and interference between multiple optical fibers in long-distance, ultra-long-distance, and high-capacity high-density wavelength division multiplexing (DWDM) optical fiber communication systems. This significantly degrades the performance between systems.

[0066] In 10G PON, Reed-Solomon (RS) encoded FEC is used. However, in 50G PON, low-density parity check (LDPC) encoding is selected. Different FEC encoding methods have different performance and implementation costs. More complex FEC encoding methods can usually provide more encoding advantages. For the same encoding method, it is also possible to introduce more overhead to provide more encoding advantages.

[0067] Currently, to guarantee transmission performance, FEC coding methods are defined between the OLT and ONU based on the maximum possible link loss, and a unified FEC coding method is used. Generally, in a PON system, the link loss from one ONU to the OLT is high, and the link loss from another ONU to the OLT is low. An ONU with low link loss does not require FEC coding with strong error correction capabilities, but it must use the same FEC coding method as the ONU with high link loss. However, such FEC coding generally has a large overhead or is complex, resulting in wasted effort.

[0068] Based on this, the present application provides an encoding configuration method and apparatus for implementing a flexible configuration of forward error correction FEC codeword information. The technical solution of the present application will be described in detail below by using an example of interaction between an optical line termination device 110 and an optical network unit 120.

[0069] Figure 2 is a schematic diagram of the encoding configuration method according to an embodiment of this application.

[0070] S210: The optical network unit 120 receives the first information, which indicates the amount of change in the forward error correction codeword information compared with the first forward error correction master code.

[0071] The first information is determined by the optical line termination device 110. The optical line termination device 110 may determine forward error correction codeword information suitable for the optical network unit 120 based on the signal quality, transmission power, etc. of the optical network unit 120. In addition, the amount of change in the forward error correction codeword information compared to the first forward error correction master code is shown in the form of the first information, and therefore the optical network unit 120 knows the forward error correction codeword information accurately.

[0072] Before receiving the first information, the optical network unit 120 may transmit capability report information to the optical line termination device 110, the capability report information indicating forward error correction master codes supported by the optical network unit 120, and the forward error correction master codes supported by the optical network unit 120 include a first forward error correction master code.

[0073] In this way, the optical line termination device 110 can determine a first forward error correction marker from the forward error correction markers supported by the optical network unit 120, process the first forward error correction marker, and determine forward error correction codeword information suitable for the optical network unit 120. Furthermore, codeword information defined by standards is not required. This helps to implement a flexible configuration of forward error correction codeword information.

[0074] Optionally, before transmitting capability report information, the optical network unit 120 may receive capability query information transmitted by the optical line termination device 110, which is used to query forward error correction parent codes supported by the optical network unit 120.

[0075] The first information is carried within the first message. The first message includes at least one of the following: a physical layer operation, management, and maintenance PLOAM message, an optical network terminal management and control interface OMCI message, and an operation, management, and maintenance OAM message.

[0076] S220: The optical network unit 120 determines forward error correction codeword information based on the first information.

[0077] In possible implementations, the first information may include the second information, which indicates, using a bit sequence, the change in the payload information of the forward error correction codeword information compared to the payload information of the first forward error correction parent code.

[0078] The bit sequence of the second information includes the first sequence, the value of which is 0, representing that 256 bits or 128 bits of the first forward error correction master code corresponding to the first sequence are shortened. In this case, the bit sequence of the second information may further include a second sequence, the value of which is 1, representing that 256 bits or 128 bits of the first forward error correction master code corresponding to the second sequence are not shortened.

[0079] Alternatively, the bit sequence of the second information may include the first sequence, the value of which is 1, representing that 256 or 128 bits of the first forward error correction master code corresponding to the first sequence are abbreviated. In this case, the bit sequence of the second information may further include a second sequence, the value of which is 0, representing that 256 or 128 bits of the first forward error correction master code corresponding to the second sequence are not abbreviated.

[0080] Each bit in a bit sequence corresponds to one column (or half a column) of the parent code matrix, corresponding to 256 (or 128) bits of parent code information.

[0081] Optionally, the first information may further include a third piece of information. The third piece of information indicates, using a bit sequence, the change in the parity bit information of the forward error correction codeword information compared to the parity bit information of the first forward error correction parent code.

[0082] The bit sequence of the third information includes a third sequence, the value corresponding to the third sequence being 0, which indicates that 256 bits or 128 bits of the first forward error correction marker corresponding to the third sequence are punctured. In this case, the bit sequence of the third information may further include a fourth sequence, the value corresponding to the fourth sequence being 1, which indicates that 256 bits or 128 bits of the first forward error correction marker corresponding to the fourth sequence are not punctured.

[0083] Alternatively, the bit sequence of the third information may include a third sequence, the value corresponding to the third sequence being 1, which indicates that 256 or 128 bits of the first forward error correction marker corresponding to the third sequence are punctured. In this case, the bit sequence of the third information may further include a fourth sequence, the value corresponding to the fourth sequence being 0, which indicates that 256 or 128 bits of the first forward error correction marker corresponding to the fourth sequence are not punctured.

[0084] In the technical solution of this application, specific forward error correction codeword information is represented by a bit sequence. To help implement a flexible configuration of forward error correction codeword information, the first forward error correction parent code may be processed in units of one or half columns of the encoded matrix to obtain the forward error correction codeword information.

[0085] In another possible implementation, the first information may include a first value indicating that M bits of the payload information of a first forward error correction parent code are abbreviated based on a first order in order to obtain the payload information of the forward error correction codeword information, where M is obtained by multiplying the first value by 256 or 128.

[0086] Optionally, the first information may further include a second value indicating that N bits of the parity bit information of the first forward error correction parent code are punctured based on a second order in order to obtain the parity bit information of the forward error correction codeword information, where N is obtained by multiplying the second value by 256 or 128.

[0087] The first and / or second order is back to front or front to back.

[0088] In the technical solution of this application, in order to help implement a flexible configuration of forward error correction codeword information, the value represents that the parent code matrix corresponding to the first forward error correction parent code is processed to obtain specific forward error correction codeword information.

[0089] Optionally, the first piece of information may further include a fourth piece of information. The fourth piece of information indicates that the first piece of information is valid.

[0090] According to the technical solution provided in this application, the amount of change in the forward error correction codeword information compared to a first forward error correction parent code is shown in order to help implement a flexible configuration of forward error correction codeword information.

[0091] Figure 3 is a schematic diagram of a specific example of the encoding configuration method according to the embodiment of this application.

[0092] S310: The optical network unit 120 receives capability inquiry information transmitted by the optical line termination device 110.

[0093] Capability query information is used to query forward error correction parent codes supported by the optical network unit 120. Capability query information may be carried in a first message. The first message includes at least one of the following: a physical layer operation, management, and maintenance PLOAM message, an optical network terminal management and control interface OMCI message, and an operation, management, and maintenance OAM message.

[0094] As an example, and not an exhaustive one, when capability query information is carried within a PLOAM message, the specific format and content of the capability query information may be shown in Table 1 below. The bolded "FEC capability query" represents the type of forward error correction parent code supported by the optical network unit 120 and queried or requested by the optical line termination device 110.

[0095] [Table 1]

[0096] S320: The optical network unit 120 transmits capability report information.

[0097] As an example, and not an exhaustive one, when capability reporting information is carried within a PLOAM message, the specific format of the capability reporting information may be shown in Tables 2 and 3 below. "FEC code Capability" in bold represents the type of forward error correction matrix supported by the optical network unit 120. In Table 2, the forward error correction matrix supported by the optical network unit 120 includes LDPC. In Table 3, the optical network unit 120 supports shortening and puncturing of forward error correction FEC matrix codes.

[0098] [Table 2]

[0099] [Table 3]

[0100] S330: The optical network terminal 110 determines the first information, which indicates the amount of change in the forward error correction codeword information compared with the first forward error correction master code.

[0101] The forward error correction codeword information includes payload information and parity bit information. In this embodiment of the present application, the first information may indicate the change in the forward error correction codeword information compared to a first forward error correction parent code by using bit sequences and / or values. In a 50G PON, a 12*69 encoding matrix is ​​used. When a new codeword structure is generated based on the encoding matrix, the columns of the matrix are generally pruned in units of one or half columns. As shown in Figure 4, the default codeword LDPC(17280, 14592) uses the first 57 and 12 columns of the matrix during encoding. Based on the different contents of the first information, there may be four possible cases:

[0102] Case 1: The payload portion and parity bit portion of the forward error correction codeword information are indicated by using a bit sequence.

[0103] Specifically, the first piece of information mentioned above may include both the second and third pieces of information. The second piece of information indicates, using a bit sequence, the change in the payload information of the forward error correction codeword information compared to the payload information of the first forward error correction master code. The third piece of information indicates, using a bit sequence, the change in the parity bit information of the forward error correction codeword information compared to the parity bit information of the first forward error correction master code. In this way, the forward error correction codeword information configured for the optical network unit 120 is represented by a bit sequence.

[0104] As an example, and not an limitation, when the first information is carried within a PLOAM message, the specific format of the first information may be shown in Table 4 below. The bolded "FEC capability set" indicates that the message is forward error correction codeword information configured for the optical network unit 120. The bolded "FEC code selection" indicates that the message contains a bit sequence.

[0105] Table 4

[0106] As shown in Figure 4, the 12*69 parent code matrix has a total of 69 columns, 57 of which are payload information and 12 of which are parity bit information. For example, forward error correction codeword information is represented by bit sequence A. One column of the parent code matrix corresponds to 256 bits of codeword information and one bit of bit sequence A. Bit sequence A includes bit sequence A1 and bit sequence A2. Bit sequence A contains 69 bits, bit sequence A1 contains 57 bits, and bit sequence A2 contains 12 bits. Bit sequence A1 represents the change in payload information of the forward error correction codeword information compared to the payload information of the first forward error correction parent code. Bit sequence A2 represents the change in parity bit information of the forward error correction codeword information compared to the parity bit information of the first forward error correction parent code. In other words, the first information is bit sequence A, the second information is bit sequence A1, and the third information is bit sequence A2. Bit sequence A1 includes a first sequence (for example, the first and second columns), the value of which is 0, representing that 256 bits of the first forward error correction master code corresponding to the first sequence are shortened. In this case, bit sequence A1 further includes a second sequence (for example, the third through 57th columns), the value of which is 0, representing that 256 bits of the first forward error correction master code corresponding to the second sequence are not shortened. In this way, the amount of change in the payload information of the forward error correction codeword information compared to the payload information of the first forward error correction master code is indicated by using bit sequence A1. After receiving the second information (i.e., bit sequence A1), the optical network unit 120 may shorten the payload information of the first forward error correction master code based on the representation of the bit sequence in order to obtain the payload information of the forward error correction codeword information configured for the optical network unit 120.In this case, bit sequence A2 includes a third sequence (for example, from the last column to the third-to-last column), where the value corresponding to the third sequence is 0, indicating that 256 bits of the first forward error correction master code corresponding to the third sequence are punctured. In this case, bit sequence A2 further includes a fourth sequence (for example, from the fourth-to-last column to the twelfth-to-last column), where the value corresponding to the fourth sequence is 1, indicating that 256 bits of the first forward error correction master code corresponding to the fourth sequence are not punctured. In this way, the change in the parity bit information of the forward error correction codeword information compared to the parity bit information of the first forward error correction master code is shown by using bit sequence A2. After receiving the third information (i.e., bit sequence A2), the optical network unit 120 may puncture the parity bit information of the first forward error correction master code based on the bit sequence representation in order to obtain the parity bit information of the forward error correction codeword information configured for the optical network unit 120.

[0107] Correspondingly, for example, forward error correction codeword information is represented by bit sequence B. Half a column of the parent code matrix corresponds to 128 bits of codeword information and corresponds to 1 bit of bit sequence B. Bit sequence B includes bit sequence B1 and bit sequence B2. Unlike bit sequence A described above, bit sequence B contains 69 * 2 = 138 bits, bit sequence B1 contains 57 * 2 = 114 bits, and bit sequence B2 contains 12 * 2 = 24 bits. For further explanation, see the above description of bit sequence A. Details are not described again in this specification.

[0108] In this embodiment of the present application, it should be understood that setting the value corresponding to a sequence to 0 may indicate that 256 bits or 128 bits of the first forward error correction master code corresponding to the sequence are shortened or punctured, or setting the value corresponding to a sequence to 1 may indicate that 256 bits or 128 bits of the first forward error correction master code corresponding to the sequence are shortened or punctured. This is not limited to the present application.

[0109] In this case, when a half-sequence is used as the unit, the bit sequence can contain up to 69*2 = 138 bits, meaning that 18 bytes (144 bits) may be used to complete the display. When a full sequence is used as the unit, the bit sequence can contain up to 69 bits, meaning that 9 bytes (72 bits) may be used to complete the display. This helps reduce signaling overhead and conserve transmission resources.

[0110] Optionally, to ensure the validity of the codeword, not all columns are generally punctured and shortened; only a portion of a column may be punctured and shortened. For example, up to 32 columns can be shortened, and 8 columns can be punctured. When a half-column is used as a unit, the bit sequence may contain a maximum of (32+8)*2=80 bits, meaning that 10 bytes (80 bits) may be used to complete the representation. When a column is used as a unit, the bit sequence may contain a maximum of 32+8=40 bits, meaning that 5 bytes (40 bits) may be used to complete the representation, which can result in further reductions in signaling overhead and savings in transmission resources.

[0111] Optionally, the priority of the punctures may be that the punctures begin with the last column. For example, if three columns are to be punctured, the punctures begin with the 57th column. Specifically, the 57th, 56th, and 55th columns are punctured consecutively. During puncture, the punctures may be performed based on the priority of the 59th, 60th, 61st, 62nd, and 67th columns, and so on.

[0112] According to the technical solution described in Case 1, the specific forward error correction codeword information is represented by a bit sequence. To help implement a flexible configuration of the forward error correction codeword information, the first forward error correction parent code may be processed in units of one or half columns of the encoded matrix to obtain the forward error correction codeword information.

[0113] Case 2: The payload portion and parity bit portion of the forward error correction codeword information are indicated by using values.

[0114] Specifically, the first information mentioned above may include both a first and a second value, where the first value indicates that M bits of the payload information of the first forward error correction master code are truncated based on a first order in order to obtain the payload information of the forward error correction codeword information. The second value indicates that N bits of the parity bit information of the first forward error correction master code are punctured based on a second order in order to obtain the parity bit information of the forward error correction codeword information. M is obtained by multiplying the first value by 256 or 128, and N is obtained by multiplying the second value by 256 or 128.

[0115] As an example, and not an limitation, when the first information is carried within a PLOAM message, the specific format of the first information may be shown in Table 5 below. The bolded "FEC capability set" indicates that the message is forward error correction codeword information configured for the optical network unit 120. The bolded "Shortened columns number" represents the first value. The bolded "Punctured columns number" represents the second value.

[0116] [Table 5]

[0117] As shown in Figure 5, the 12*69 parent code matrix has a total of 69 columns, 57 of which are payload information and 12 of which are parity bit information.

[0118] In a possible implementation, one column of the parent code matrix corresponds to 256 bits of codeword information and one bit of the first value. When the first value is 3 and the first order is back-to-front, it means that M bits of the payload information of the first forward error correction parent code are shortened back-to-front in order to obtain the payload information of the forward error correction codeword information. M is obtained by multiplying the first value by 256, i.e., M = 3 * 256 = 768. In this way, after receiving the first value, the optical network unit 120 may process the payload information of the first forward error correction parent code in order to obtain the payload information of the forward error correction codeword information.

[0119] When the second value is 2 and the second order is back-to-front, it means that N bits of the parity bit information of the first forward error correction mother code are punctured back-to-front in order to obtain the parity bit information of the forward error correction codeword information. N is obtained by multiplying the second value by 256, i.e., N = 2 * 256 = 512. In this way, after receiving the second value, the optical network unit 120 may process the parity bit information of the first forward error correction mother code in order to obtain the parity bit information of the forward error correction codeword information.

[0120] In another possible implementation, half a column of the parent code matrix corresponds to 128 bits of codeword information and one bit of the first value. When the first value is 3 and the first order is back-to-front, it represents that M bits of the payload information of the first forward error correction parent code are punctured back-to-front in order to obtain the payload information of the forward error correction codeword information. M is obtained by multiplying the first value by 128, i.e., M = 3 * 128 = 384. In this way, after receiving the first value, the optical network unit 120 may process the payload information of the first forward error correction parent code in order to obtain the payload information of the forward error correction codeword information. When the second value is 2 and the second order is back-to-front, it represents that N bits of the parity bit information of the first forward error correction parent code are punctured back-to-front in order to obtain the parity bit information of the forward error correction codeword information. N is obtained by multiplying the second value by 128, i.e., N = 2 * 128 = 256. In this way, after receiving the second value, the optical network unit 120 may process the parity bit information of the first forward error correction parent code in order to obtain the parity bit information of the forward error correction codeword information.

[0121] In this embodiment of the present application, it should be understood that the first order and / or the second order may be back-to-front or front-to-back. The first order may be the same as or different from the second order. Optionally, the first order and / or the second order may alternatively be multiple orders / single sequences specified by negotiation or according to a protocol, for example, starting from the middle column. This is not limited to the present application. The first order and / or the second order may be consecutive. For example, when the first value is 3, three consecutive columns (or half-columns) are processed. Optionally, the first order and / or the second order may alternatively be discontinuous. For example, when the first value is 3, the columns may be processed based on an order specified by negotiation or according to a protocol, for example, an order of odd-numbered or even-numbered columns. This is not limited to the present application.

[0122] Optionally, the priority of the punctures may be that the punctures begin with the last column. For example, if three columns are to be punctured, the punctures begin with the 57th column. Specifically, the 57th, 56th, and 55th columns are punctured consecutively. During puncture, the punctures may be performed based on the priority of the 59th, 60th, 61st, 62nd, and 67th columns, and so on.

[0123] In this case, when half-segments are used as units, the payload portion has a total of 57*2 possibilities, and the parity bits have a total of 12*2 possibilities. The payload portion is represented by using at least 7 bits, and the parity bits are represented by using 5 bits. This helps reduce signaling overhead and conserve transmission resources.

[0124] Optionally, to ensure the validity of the codeword, not all columns may be punctured and shortened; rather, only a portion of the columns may be punctured and shortened. For example, up to 32 columns can be shortened, and 8 columns can be punctured. When half columns are used as units, only 6 bits are needed to represent the payload portion and 4 bits are needed to represent the parity portion, which can result in further reductions in signaling overhead and savings in transmission resources.

[0125] According to the technical solution described in Case 2, in order to help implement a flexible configuration of forward error correction codeword information, the value represents that the parent code matrix corresponding to the first forward error correction parent code is processed to obtain specific forward error correction codeword information.

[0126] Case 3: The payload portion of the forward error correction codeword information is indicated by using a bit sequence. The parity bit portion of the forward error correction codeword information is indicated by using a value.

[0127] Specifically, the first piece of information mentioned above may include both the second piece of information and the second value. The second piece of information indicates, using a bit sequence, the change in the payload information of the forward error correction codeword information compared to the payload information of the first forward error correction parent code. The second value indicates that N bits of the parity bit information of the first forward error correction parent code are punctured based on the second order in order to obtain the parity bit information of the forward error correction codeword information. N is obtained by multiplying the second value by 256 or 128. For example, the second piece of information includes bit sequence A1. When half a sequence is used as the unit, bit sequence A1 contains 57 * 2 = 114 bits. In this case, the parity bit portion may be indicated by using 5 bits in the value representation method.

[0128] For specific methods of expressing the second piece of information and the second value, and for their beneficial effects, please refer to the descriptions of Case 1 and Case 2 above. Further details will not be explained again herein.

[0129] According to the technical solution described in Case 3, the payload information of the forward error correction codeword information is represented by a bit sequence, and the parity bit information of the forward error correction codeword information is represented by a value. To help implement a flexible configuration of the forward error correction codeword information, the first forward error correction parent code may be processed in units of one or half columns of the encoded matrix to obtain the forward error correction codeword information.

[0130] Case 4: The payload portion of the forward error correction codeword information is indicated by using a value. The parity bit portion of the forward error correction codeword information is indicated by using a bit sequence.

[0131] Specifically, the first information may include both the third information and the first value. The first value indicates that M bits of the payload information of the first forward error correction parent code are abbreviated based on a first order in order to obtain the payload information of the forward error correction codeword information. M is obtained by multiplying the first value by 256 or 128. The third information indicates the change in the parity bit information of the forward error correction codeword information compared to the parity bit information of the first forward error correction parent code, by using a bit sequence. For example, when a column is used as a unit, the payload portion is represented by using 7 bits, and the third information includes bit sequence A2, which contains 12 bits.

[0132] For specific representations of the third piece of information and the first value, as well as their beneficial effects, please refer to the descriptions of Case 1 and Case 2 above. Further details will not be provided again herein.

[0133] According to the technical solution described in Case 4, the payload information of the forward error correction codeword information is represented by a value, and the parity bit information of the forward error correction codeword information is represented by a bit sequence. To help implement a flexible configuration of the forward error correction codeword information, the first forward error correction parent code may be processed in units of one or half columns of the encoded matrix to obtain the forward error correction codeword information.

[0134] S340: The optical line termination device 110 transmits the first information to the optical network unit 120.

[0135] The first information is carried within the first message. The first message includes at least one of the following: a physical layer operation, management, and maintenance PLOAM message, an optical network terminal management and control interface OMCI message, and an operation, management, and maintenance OAM message.

[0136] S350: The optical network unit 120 determines forward error correction codeword information based on the first information.

[0137] Specifically, corresponding to the description in S330, the optical network unit 120 processes the first forward error correction parent code in units of one or half columns of the encoded matrix based on the content of the first information as well as the bit sequence and / or values, in order to obtain forward error correction codeword information.

[0138] According to the technical solution provided in this application, the amount of change in the forward error correction codeword information compared to a first forward error correction parent code is shown in order to help implement a flexible configuration of forward error correction codeword information.

[0139] It should be understood that the sequence numbers of the aforementioned processes do not indicate the order of execution. The order of execution of processes should be determined based on the function and internal logic of the processes and should not be considered as any limitation to the implementation processes of the embodiments of this application.

[0140] In the embodiments of this application, unless otherwise specified or a logical inconsistency arises, the terminology and / or descriptions in different embodiments are consistent and may be mutually referenced, and the technical features of different embodiments may be combined on the basis of their internal logical relationships to form a new embodiment.

[0141] It will be understood that the methods implemented by the communication device in the aforementioned embodiments of this application may, alternatively, be implemented by a component (e.g., a chip or circuit) that can be configured inside the communication device.

[0142] An encoding configuration method provided in embodiments of this application is described in detail with reference to Figures 2, 3, 4, and 5. The aforementioned encoding configuration method is described primarily in terms of interaction between network elements. It will be understood that in order to implement the aforementioned functions, each device includes a corresponding hardware structure and / or software module for performing each function. Those skilled in the art will notice, in combination with the example units and algorithmic steps described in the embodiments disclosed herein, that this application can be implemented in hardware or in combination of hardware and computer software. Whether the functions are performed by hardware or by hardware driven by computer software will depend on the specific application and design constraints of the technical solution. Those skilled in the art may implement the functions described for their respective specific applications using different methods, but such implementations should not be considered to deviate from the scope of this application.

[0143] The encoding configuration apparatus provided in the embodiments of this application will be described in detail below with reference to Figures 6 and 7. It should be understood that the description of the apparatus embodiments corresponds to the description of the method embodiments. Therefore, for matters not described in detail, please refer to the method embodiments described above. For brevity, some of the content will not be described again in this specification.

[0144] In embodiments of this application, a transmitting end device or a receiving end device may be divided into functional modules based on the examples of the methods described above. For example, each functional module may be obtained by a division based on its corresponding function, or two or more functions may be integrated into a single processing module. The integrated module may be implemented in hardware form or in the form of a software functional module. Note that in embodiments of this application, the module division is illustrative and merely a logical division of function. Actual implementation During Alternatively, a different partitioning method may be used. An example where each functional module is obtained through partitioning based on its corresponding function is used for the explanation below.

[0145] Figure 6 is a schematic diagram of the structure of an example encoding configuration device according to this application. Any device involved in any one of the above methods 200 to 400, such as an optical line termination device and an optical network unit, may be implemented by the encoding configuration device shown in Figure 6.

[0146] It should be understood that the encoding configuration device 600 may be an entity device, a component of an entity device (for example, an integrated circuit or chip), or a functional module within an entity device.

[0147] As shown in Figure 6, the encoding configuration device 600 includes one or more processors 610. The processors 610 may store execution instructions for performing the methods of the embodiments of this application. Optionally, the processors 610 may invoke interfaces for implementing receiving and transmitting functions. The interfaces may be, but are not limited to, logical interfaces or physical interfaces. For example, the interfaces may be transceiver circuits or interface circuits. Transceiver circuits or interface circuits configured to implement receiving and transmitting functions may be separate or integrated together. The transceiver circuits or interface circuits may be configured to read and write codes / data, or the transceiver circuits or interface circuits may be configured to transmit or transfer signals.

[0148] Optionally, the interface may be implemented by a transceiver. Optionally, the encoding configuration device 600 may further include a transceiver 630. The transceiver 630 may be referred to as a transceiver unit, transceiver machine, transceiver circuit, or transceiver, and is configured to provide receiving and transmitting functions.

[0149] Optionally, the encoding configuration device 600 may further include memory 620. The specific location of the memory 620 is not particularly limited in this embodiment of the present application. The memory may be integrated into the processor or independent of the processor. If the encoding configuration device 600 does not include memory, it is sufficient that the encoding configuration device 600 has processing capabilities, and the memory may be located elsewhere (for example, in a cloud system).

[0150] The processor 610, memory 620, and transceiver 630 communicate with each other through internal connection paths to transfer control signals and / or data signals.

[0151] Although not shown, it will be understood that the encoding configuration device 600 may further include other devices such as an input device, an output device, or a battery.

[0152] Optionally, in some embodiments, memory 620 may store execution instructions for performing the method of the embodiments of this application. The processor 610 may execute the instructions stored in memory 620 and, in combination with other hardware (e.g., transceiver 630), complete the steps performed in the following manner. For specific operating processes and beneficial effects, please refer to the description in the embodiments of the method described above.

[0153] The methods disclosed in embodiments of this application may be applied to or implemented by a processor 610. The processor 610 may be an integrated circuit chip having signal processing capabilities. In the implementation process, the steps of the method may be completed by using instructions in the form of integrated logic circuits or software of the processor's hardware. The processor may be a general-purpose processor, a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field programmable gate array (FPGA), or another programmable logic device, discrete gate or transistor logic device, or discrete hardware component. The methods, steps, and logic block diagrams disclosed in embodiments of this application may be implemented or executed. The general-purpose processor may be a microprocessor, or the processor may be any ordinary processor, etc. The steps of the methods disclosed in relation to embodiments of this application may be performed and completed directly by a hardware decoding processor, or by using a combination of hardware and software modules within the decoding processor. The software module may be placed in a mature storage medium in the art, such as random access memory (RAM), flash memory, read-only memory (ROM), programmable read-only memory, electrically erasable programmable memory, or registers. The storage medium is placed in memory, and the processor reads the instructions in memory and, in combination with the processor hardware, completes the steps of the method described above.

[0154] It will be understood that memory 620 may be volatile memory or non-volatile memory, or may contain both volatile and non-volatile memory. Non-volatile memory may be read-only memory (ROM), programmable read-only memory (programmable ROM, PROM), erasable programmable read-only memory (erasable PROM, EPROM), electrically erasable programmable read-only memory (electrically EPROM, EEPROM), or flash memory. Volatile memory may be random-access memory (RAM) and may function as an external cache. For illustrative purposes only, rather than limiting, many forms of RAM are available, such as static random access memory (static RAM, SRAM), dynamic random access memory (dynamic RAM, DRAM), synchronous dynamic random access memory (synchronous DRAM, SDRAM), double data rate synchronous dynamic random access memory (double data rate SDRAM, DDR SDRAM), enhanced synchronous dynamic random access memory (enhanced SDRAM, ESDRAM), synchlink dynamic random access memory (synchlink DRAM, SLDRAM), and direct rambus random access memory (direct rambus RAM, DR RAM). It should be noted that the memory of the systems and methods described herein includes, but is not limited to, these memories and any other suitable type of memory.

[0155] Figure 7 is a schematic diagram of the structure of an example encoding device according to this application.

[0156] Optionally, the specific form of the encoding configuration device 700 may be a general-purpose computer device or a chip within a general-purpose computer device. This is not limited to this embodiment of the present application. As shown in Figure 7, the encoding configuration device includes a processing unit 710 and a transceiver unit 720.

[0157] Specifically, the encoding configuration device 700 may be any device in this application and may implement functions that can be performed by the device. It should be understood that the encoding configuration device 700 may be an entity device, a component of an entity device (e.g., an integrated circuit or chip), or a functional module within an entity device.

[0158] In possible designs, the encoding configuration device 700 may be an optical line termination device in the embodiments of the method described above, or a chip configured to perform the functions of an optical line termination device in the embodiments of the method described above.

[0159] For example, the processing unit 710 is configured to determine a first piece of information, which indicates the amount of change in the forward error correction codeword information compared to a first forward error correction master code, and the transceiver unit 720 is configured to transmit the first piece of information to the optical network unit.

[0160] Optionally, the transceiver unit 720 is further configured to receive capability report information, which indicates forward error correction master codes supported by the optical network unit, and the forward error correction master codes supported by the optical network unit include a first forward error correction master code.

[0161] Optionally, the transceiver unit 720 may be further configured to transmit capability query information, which is used to query forward error correction master codes supported by the optical network unit.

[0162] When the encoding configuration device 700 is an optical line termination device, the transceiver unit 720 of the encoding configuration device 700 may be implemented by using a communication interface (e.g., a transceiver or an input / output interface), and the processing unit 710 of the encoding configuration device 700 may be implemented by using at least one processor, which may correspond to, for example, the processor 610 shown in Figure 6.

[0163] Optionally, the encoding configuration device 700 may further include a storage unit. The storage unit may be configured to store instructions or data. The processing unit may retrieve the instructions or data stored in the storage unit and perform the corresponding operation.

[0164] It should be understood that the specific process by which the unit performs the corresponding steps described above is detailed in the embodiments of the method described above. For the sake of brevity, the details are not described herein.

[0165] In another possible design, the encoding configuration device 700 may be an optical network unit device in the embodiment of the method described above, or a chip configured to implement the functions of the optical network unit in the embodiment of the method described above.

[0166] For example, the transceiver unit 720 is configured to receive first information, which indicates the amount of change in forward error correction codeword information compared to a first forward error correction master code, and the processing unit 710 is configured to determine the forward error correction codeword information based on the first information.

[0167] Optionally, the transceiver unit 720 is further configured to transmit capability reporting information, which indicates forward error correction master codes supported by the optical network unit, and the forward error correction master codes supported by the optical network unit include a first forward error correction master code.

[0168] Optionally, the transceiver unit 720 may be further configured to receive capability query information, which is used to query forward error correction master codes supported by the optical network unit.

[0169] When the encoding configuration device 700 is an optical network unit device, the transceiver unit 720 of the encoding configuration device 700 may be implemented using a communication interface (e.g., a transceiver or an input / output interface), which may correspond to, for example, the transceiver 630 shown in Figure 6, and the processing unit 710 of the encoding configuration device 700 may be implemented using at least one processor, which may correspond to, for example, the processor 610 shown in Figure 6.

[0170] Optionally, the encoding configuration device 700 may further include a storage unit. The storage unit may be configured to store instructions or data. The processing unit may retrieve the instructions or data stored in the storage unit and perform the corresponding operation.

[0171] It should be understood that the specific process by which the unit performs the corresponding steps described above is described in detail in the embodiments of the method described above. For the sake of brevity, the details are not described herein.

[0172] It should be further understood that the device 700 may be further configured to implement the functions of the optical line termination device and optical network unit in the embodiments of the method described above. The transceiver unit 720 may be configured to perform receiving and transmitting operations, and the processing unit 710 may be configured to perform operations other than receiving and transmitting. For further details, refer to the description of the embodiments of the method described above, which are not re-listed herein.

[0173] Furthermore, in this application, the encoding configuration device 700 is presented in the form of a functional module. The term “module” as used herein may be an application-specific integrated circuit (ASIC), a circuit, a processor and memory for executing one or more software or firmware programs, an integrated logic circuit, and / or another device capable of providing the aforementioned functions. In a simple embodiment, those skilled in the art will understand that the device 700 may be in the form shown in Figure 7. The processing unit 710 may be implemented using the processor 610 shown in Figure 6. Optionally, if the encoding configuration device shown in Figure 6 includes memory 620, the processing unit 710 may be implemented using the processor 610 and memory 620. The transceiver unit 720 may be implemented using the transceiver 630 shown in Figure 6. The transceiver 630 includes receiving and transmitting functions. Specifically, the processor is implemented by executing a computer program stored in memory. Optionally, if device 700 is a chip, the functions and / or processes of the transceiver unit 720 may be performed by alternatively using pins, circuits, etc. Optionally, memory may be an in-chip storage unit such as a register or cache. The storage unit may be a storage unit located within the computer device but outside the chip, for example, memory 620 shown in Figure 6, or a storage unit deployed in another system or device but not located within the computer device.

[0174] Aspects or features of this application may be implemented as methods, apparatus, or products using standard programming and / or engineering technologies. The term “product” as used in this application refers to a product accessible from any computer-readable device, carrier, or medium. It is possible to It includes a computer program. For example, computer-readable media may include, but are not limited to, magnetic storage components (e.g., hard disks, floppy disks, or magnetic tapes), optical discs (e.g., compact discs (CDs) and digital versatile discs (DVDs)), smart cards, and flash memory components (e.g., erasable programmable read-only memory (EPROM), cards, sticks, or key drives). Furthermore, the various storage media described herein may represent one or more devices and / or other machine-readable media configured to store information. The term “machine-readable media” may include, but are not limited to, wireless channels and various other media capable of storing, containing, and / or carrying instructions and / or data.

[0175] According to the methods provided in embodiments of this application, this application further provides a computer program product, which includes computer program code. When the computer program code is executed on a computer, the computer is enabled to perform the methods according to either embodiment shown in Figure 2 or Figure 3.

[0176] According to the methods provided in embodiments of this application, the application further provides a computer-readable medium for storing program code. When the program code is executed on a computer, the computer is enabled to perform the method according to either embodiment shown in Figure 2 or Figure 3.

[0177] According to the method provided in the embodiments of this application, this application further provides a system including the aforementioned apparatus or device.

[0178] All or part of the embodiments described above may be implemented using software, hardware, firmware, or any combination thereof. When software is used to implement an embodiment, all or part of the embodiment may be implemented in the form of a computer program product. A computer program product includes one or more computer instructions. When the computer instructions are loaded into a computer and executed, all or part of the procedures or functions according to the embodiments of this application are generated. The computer may be a general-purpose computer, a dedicated computer, a computer network, or another programmable device. The computer instructions may be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another. For example, computer instructions may be transmitted from one website, computer, server, or data center to another website, computer, server, or data center by a wired method (e.g., coaxial cable, fiber optic cable, or digital subscriber line (DSL)) or wireless method (e.g., infrared, radio, or microwave). Computer-readable storage media may be any available medium that can be accessed by a computer, or a data storage device that incorporates one or more available media, such as a server or data center. Available media may be magnetic media (e.g., floppy disks, hard disks, or magnetic tapes), optical media (e.g., high-density digital video discs (DVDs)), semiconductor media (e.g., solid-state discs (SSDs)), etc.

[0179] As used herein, terms such as “component,” “module,” and “system” are used to describe computer-related entities, hardware, firmware, combinations of hardware and software, software, or software being run. For example, a component may be, but is not limited to, a process running on a processor, a processor, an object, an executable file, an execution thread, a program, and / or a computer. As illustrated by the use of diagrams, both an application running on a computing device and the computing device itself may be components. One or more components may reside in a process and / or an execution thread, and components may reside on one computer and / or be distributed across two or more computers. In addition, these components may run from various computer-readable media that store various data structures. Components may communicate by using local and / or remote processes based on signals having one or more data packets (for example, data from two components interacting with another component on the other side of a network such as the Internet, interacting with another system by using signals).

[0180] It should be further understood that the terms "and / or" in this specification indicate only the relationship of association between related subjects, and that three relationships may exist. For example, A and / or B may represent the following three cases: that only A exists, that both A and B exist, and that only B exists. In addition, the letter " / " in this specification generally indicates an "or" relationship between related subjects.

[0181] Furthermore, it should be understood that the numbers “first,” “second,” etc., introduced in the embodiments of this application are merely intended to distinguish different objects, for example, different “information,” “devices,” or “units.” Understanding specific objects and correspondences between different objects should be determined based on the function and internal logic of the objects and should not be considered as any limitation on the implementation process of the embodiments of this application.

[0182] For the purpose of providing a convenient and concise explanation, it will be readily apparent to those skilled in the art that, for the detailed operating processes of the aforementioned systems, apparatus, and units, refer to the corresponding processes of the embodiments of the methods described above. Further details are not described again herein.

[0183] It should be understood that in some embodiments provided in this application, the systems, devices, and methods disclosed may be implemented in different ways. For example, the embodiments of the devices described are merely examples. For example, the division of units is merely a logical division of functions, and the actual implementation During Other divisions may exist. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not performed. In addition, the mutual coupling or direct coupling or communication connection shown or considered may be implemented by using several interfaces. Indirect coupling or communication connection between devices or units may be implemented electronically, mechanically, or in other forms.

[0184] Units described as separate components may or may not be physically separate, and components shown as units may or may not be physical units, may be located in one location, or may be distributed across multiple network units. Some or all of the units may be selected based on actual requirements to achieve the objectives of the solutions of the embodiments.

[0185] In addition, the functional units of the embodiments of this application may be integrated into a single processing unit, each unit may exist physically independently, or two or more units may be integrated into a single unit.

[0186] When a function is implemented in the form of a software function unit and sold or used as an independent product, the function may be stored on a computer-readable storage medium. Based on such understanding, the technical solutions of this application may be implemented in the form of a software product, or a portion of the technical solution that contributes to ordinary technology may be implemented in the form of a software product. A computer software product is stored on a storage medium and includes several instructions for instructing a computer device (which may be a personal computer, server, network device, etc.) to perform all or part of the steps of the method described in the embodiments of this application. The aforementioned storage medium includes any medium capable of storing program code, such as a USB flash drive, a removable hard disk, read-only memory (ROM), random access memory (RAM), a magnetic disk, or an optical disk.

[0187] The foregoing description is merely a specific implementation of the present application and is not intended to limit the scope of protection of this application. All modifications or substitutions that are readily conceivable to a person skilled in the art within the scope of the technical scope disclosed herein fall within the scope of protection of this application. Accordingly, the scope of protection of this application is subject to the scope of protection of the claims. [Explanation of symbols]

[0188] 110 Optical network termination equipment 120 Optical Network Units 200~400 methods 600 Encoding Configuration Device 610 Processor 620 memory 630 transceiver 700 Encoding Configuration Device 710 Processing Unit 720 Transceiver Unit

Claims

1. An encoding configuration method, A step of receiving capability query information by an optical network unit, wherein the capability query information is used to query the forward error correction capability supported by the optical network unit; The optical network unit transmits capability report information, the capability report information indicating whether the optical network unit supports shortening of the forward error correction parent code matrix, Includes, The capability reporting information indicates that the optical network unit supports shortening of the forward error correction parent code matrix, and the method is The optical network unit receives first information, wherein the first information indicates the amount of change in forward error correction codeword information compared to a first forward error correction generator matrix, the first information includes a first value indicating that M bits of the payload information of the forward error correction generator matrix are shortened based on a first order in order to obtain the payload information of the forward error correction codeword information, where M is obtained by multiplying the first value by 256 or 128, and the first order is back to front or front to back. Methods that further include this.

2. The optical network unit determines the forward error correction codeword information based on the first information. The method according to claim 1, further comprising:

3. The method according to claim 1, wherein the first value is the number of shortened columns in the forward error correction generator matrix.

4. The method according to claim 1, wherein the first information further includes a fourth piece of information, the fourth piece of information indicating that the first information is valid.

5. The first information is conveyed within the first message, and the first message is as follows: The method according to claim 1, comprising at least one of the following: a physical layer operation, management, and maintenance PLOAM message, an optical network terminal management and control interface OMCI message, and an operation, management, and maintenance OAM message.

6. An encoding configuration method, A step of transmitting capability query information by an optical line termination device, wherein the capability query information is used to query the forward error correction capability supported by the optical network unit, The optical line termination device receives capability report information, the capability report information indicating whether the optical network unit supports forward error correction matrix shortening. Includes, The capability reporting information indicates that the optical network unit supports shortening of the forward error correction parent code matrix, and the method is The optical line termination device determines first information, wherein the first information indicates the amount of change in forward error correction codeword information compared to a first forward error correction parent code matrix. The optical network terminal further includes the step of transmitting the first information to the optical network unit, The first information includes a first value indicating that M bits of the payload information of the first forward error correction parent code matrix are shortened based on a first order in order to obtain the payload information of the forward error correction codeword information, wherein M is obtained by multiplying the first value by 256 or 128, and the first order is back to front or front to back.

7. The method according to claim 6, wherein the first value is the number of shortened columns in the forward error correction generator matrix.

8. The method according to claim 6, wherein the first information further includes a fourth piece of information, the fourth piece of information indicating that the first information is valid.

9. The first information is conveyed within the first message, and the first message is as follows: The method according to claim 6, comprising at least one of the following: a physical layer operation, management, and maintenance PLOAM message, an optical network terminal management and control interface OMCI message, and an operation, management, and maintenance OAM message.

10. A communication device including a processor, wherein the processor is It is configured to receive capability query information, and the capability query information is used to query the forward error correction capability supported by the optical network unit. The processor is configured to transmit capability reporting information, which indicates whether the optical network unit supports shortening of the forward error correction parent code matrix. The capability reporting information indicates that the optical network unit supports shortening of the forward error correction parent code matrix, and the processor, A communication device further configured to receive first information, wherein the first information indicates the amount of change in forward error correction codeword information compared to a first forward error correction parent code matrix, and the first information includes a first value indicating that M bits of the payload information of the forward error correction parent code matrix are shortened based on a first order in order to obtain payload information of the forward error correction codeword information, where M is obtained by multiplying the first value by 256 or 128, and the first order is back to front or front to back.

11. The communication device according to claim 10, wherein the processor is further configured to determine the forward error correction codeword information based on the first information.

12. The communication device according to claim 10, wherein the first value is the number of shortened columns in the forward error correction parent code matrix.

13. A communication device including a processor, wherein the processor is It is configured to transmit capability query information, which is used to query the forward error correction capability supported by the optical network unit. The processor is configured to receive capability report information, which indicates whether the optical network unit supports shortening of the forward error correction parent code matrix. The capability reporting information indicates that the optical network unit supports shortening of the forward error correction parent code matrix, and the processor, Further configured to determine a first piece of information, wherein the first piece of information indicates the change in forward error correction codeword information compared to a first forward error correction parent code matrix, The processor is further configured to transmit the first information to the optical network unit. The first information includes a first value indicating that M bits of the payload information of the first forward error correction parent code matrix are shortened based on a first order in order to obtain the payload information of the forward error correction codeword information, where M is obtained by multiplying the first value by 256 or 128, and the first order is back to front or front to back, in a communication device.

14. The communication device according to claim 13, wherein the first value is the number of shortened columns in the forward error correction parent code matrix.

15. The communication device according to claim 13, wherein the first information further includes a fourth piece of information, the fourth piece of information indicating that the first information is valid.

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