Multi-channel BTL drive circuit, multi-channel BTL drive method, and multi-channel BTL drive program

Abstract

In multi-channel BTL drive circuits, the number of components is reduced and wiring is simplified. [Solution] The multi-channel BTL drive circuit comprises a signal processing circuit and a common return line. The signal processing circuit time-divides each period of the sampling rate into a plurality of slots, including a first slot and a second slot, assigns the first PWM signal to the first slot and the second PWM signal to the second slot, outputs a waveform to the first individual line that is in phase with the common return line in the second slot, and outputs a waveform to the second individual line that is in phase with the common return line in the first slot.

Description

Technical Field

[0005] , , ,

[0001] The present disclosure relates to a multi-channel BTL drive circuit, a multi-channel BTL drive method, and a multi-channel BTL drive program.

Background Art

[0002] Patent Document 1 discloses an audio playback device that drives a speaker according to an audio signal output from a microcomputer to play back audio. In this audio playback device, a plurality of signals generated by the microcomputer are differentially output as one output signal, thereby removing noise superimposed on the plurality of signals.

[0003] By the way, in the field of audio playback devices such as digital audio equipment, as one of the methods for driving a load such as a speaker, a BTL (Bridge-Tied Load) drive method is known. In the BTL drive method, independent amplifier circuits are connected to both ends of the load, and the load is driven by applying signals having opposite phases to each other. This method can theoretically obtain an output four times that of a single-ended drive method in which one terminal of the load is grounded (GND) under the same power supply voltage, and is used in fields such as mobile devices and in-vehicle audio that require low-voltage drive. In addition, in order to improve power efficiency, digital amplification technologies such as class D amplifiers using PWM (pulse width modulation) signals are often used in BTL configurations. A PWM amplifier converts an audio signal into the density of pulse widths and realizes high-efficiency amplification with suppressed heat loss by causing a power element in the output stage to perform a high-speed switching operation.

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0005] However, when applying the conventional BTL drive method to a multi-channel environment such as stereo, it is necessary to provide two independent drive lines (Hot and Cold) for each channel. Therefore, when performing stereo playback, a total of four wires are required, leading to an increase in the number of components and complexity of the wiring.

[0006] The purpose of this disclosure is to reduce the number of components and simplify wiring in a multi-channel BTL drive circuit. [Means for solving the problem]

[0007] To solve the above problems, a multi-channel BTL drive circuit according to one aspect of the present disclosure is a multi-channel BTL drive circuit that supplies power to a plurality of loads, including a first load and a second load, by PWM control synchronized with the sampling rate of the input signals based on input signals of a plurality of channels, including a first channel and a second channel, comprising: a signal processing circuit that generates a pair of first PWM signals which are a first individual signal and a first return signal based on the input signal of the first channel, and generates a pair of second PWM signals which are a second individual signal and a second return signal based on the input signal of the second channel, and the first individual signal The signal processing circuit comprises: a first power conversion circuit that supplies power to the first load in accordance with a number; a second power conversion circuit that supplies power to the second load in accordance with the second individual signal; a common power conversion circuit that supplies power to the first load in accordance with the first return signal and also supplies power to the second load in accordance with the second return signal; a first individual line connected to the first power conversion circuit through which the first individual signal flows; a second individual line connected to the second power conversion circuit through which the second individual signal flows; and a common return line connected to the common power conversion circuit through which the first return signal and the second return signal flow alternately. The signal processing circuit time-divides each period of the sampling rate into a plurality of slots, including a first slot and a second slot, assigns the first PWM signal to the first slot and the second PWM signal to the second slot, outputs a waveform to the first individual line that is in phase with the common return line in the second slot, and outputs a waveform to the second individual line that is in phase with the common return line in the first slot. [Effects of the Invention]

[0008] According to this disclosure, the number of components in a multi-channel BTL drive circuit can be reduced and wiring can be simplified. [Brief explanation of the drawing]

[0009] [Figure 1] Figure 1 is a block diagram showing a multi-channel BTL drive circuit according to an embodiment. [Figure 2] Figure 2 is a timing chart showing the operation of the multi-channel BTL drive circuit in Figure 1. [Figure 3] Figure 3 is a block view of the comparative example. [Figure 4] Figure 4 is a timing chart showing the operation of a comparative example multi-channel BTL drive circuit. [Figure 5] Figure 5 is a timing chart illustrating the secondary modulation of the multi-channel BTL drive circuit shown in Figure 1. [Figure 6] Figure 6 shows the configuration when the multi-channel BTL drive circuit from Figure 1 is applied to a 3-pole headphone plug. [Figure 7] Figure 7 is a diagram showing the configuration of a multi-channel BTL drive circuit of the first modified example. [Figure 8] Figure 8 is a diagram showing a multi-channel BTL drive circuit of the second modified example. [Modes for carrying out the invention]

[0010] Embodiments of this disclosure will be described below with reference to the drawings. In all drawings illustrating the embodiments, common components are denoted by the same reference numerals, and repeated descriptions are omitted. The following embodiments are not intended to unduly limit the content of this disclosure as described in the claims. Not all components shown in the embodiments are necessarily essential components of this disclosure. Also, each drawing is a schematic diagram and is not necessarily a strict illustration. In the following description, when similar elements are described without distinction, reference numerals (or common reference numerals) are used, and when similar elements are described separately, element identification numbers (or reference numerals) may be used. Also, in the following description, control lines and information lines are shown only if deemed necessary for the explanation, and not all control lines and information lines in the product are necessarily shown. All components may be interconnected.

[0011] <Overview> The multi-channel BTL drive circuit 1 according to this embodiment supplies power to the first load, the first speaker 3L, and the second load, the second speaker 3R, by PWM control based on the audio signal from the PCM sound source 2L as the input signal for the first speaker 3L, and the audio signal from the PCM sound source 2R as the input signal for the second speaker 3R. The return line through which the return signal of the first speaker 3L flows and the return line through which the return signal of the second speaker 3R flows are combined into a common return line CC, thus reducing the number of components and simplifying the wiring.

[0012] The signal processing circuit 10 time-divides each period of the audio signal sampling rate between the first slot SL1 and the second slot SL2, assigning the first PWM signal (first individual signal and first return signal) for the first speaker 3L to the first slot SL1, and the second PWM signal (second individual signal and second return signal) for the second speaker 3R to the second slot SL2. The first individual line LH for the first speaker 3L outputs a waveform in phase with the common return line CC in the second slot SL, and the second individual line RH for the second speaker 3R outputs a waveform in phase with the common return line CC in the first slot SL. As a result, the first speaker 3L and the second speaker 3R output audio that matches the sound source.

[0013] <Overall Structure> Figure 1 is a block diagram showing a multi-channel BTL drive circuit 1 according to an embodiment. As shown in Figure 1, the multi-channel BTL drive circuit 1 supplies power to the first speaker 3L of the first channel and the second speaker 3R of the second channel by PWM control based on the audio signal from the first PCM sound source 2L for the first channel and the audio signal from the second PCM sound source 2R for the second channel. The multi-channel BTL drive circuit 1 includes a signal processing circuit 10, a first half-bridge circuit 11L, a second half-bridge circuit 11R, and a common half-bridge circuit 11C.

[0014] The first speaker 3L is an example of a first load. The second speaker 3R is an example of a second load. As an example, the first speaker 3L is a left speaker, and the second speaker 3R is a right speaker. The audio signal from the first PCM sound source 2L is an input signal of the first channel in the signal processing circuit 10. The audio signal from the second PCM sound source 2R is an input signal of the second channel in the signal processing circuit 10. The first half-bridge circuit 11L is an example of a first power conversion circuit. The second half-bridge circuit 11R is an example of a second power conversion circuit. The common half-bridge circuit 11C is an example of a common power conversion circuit. The half-bridge circuit can also be said to be a specific example of a switching circuit as an example of a power conversion circuit.

[0015] The signal processing circuit 10 synchronously samples the audio signals of the first PCM sound source 2L and the second PCM sound source 2R, and generates a PWM signal synchronized with the sampling rate. As a result, oversampling processing during PWM signal generation becomes unnecessary, and the switching frequency is reduced. Specifically, the signal processing circuit 10 generates a pair of first PWM signals, which is a pair of a first individual signal (Hot side) and a first return signal (Cold side), based on the audio signal from the first PCM sound source 2L. The signal processing circuit 10 generates a pair of second PWM signals, which is a pair of a second individual signal (Hot side) and a second return signal (Cold side), based on the audio signal from the second PCM sound source 2R.

[0016] The signal processing circuit 10 calculates the duty ratio of the pair of first PWM signals based on the amplitude level of the audio signal from the first PCM sound source 2L and determines the pulse width. The signal processing circuit 10 calculates the duty ratio of the pair of second PWM signals based on the amplitude level of the audio signal from the second PCM sound source 2R and determines the pulse width.

[0017] The first half-bridge circuit 11L is connected to the signal processing circuit 10 via the first individual line LH. The signal processing circuit 10 sends the first individual signal of the first PWM signal to the first individual line LH. The first half-bridge circuit 11L supplies power Vdd to the first speaker 3L according to the first individual signal of the first PWM signal.

[0018] The second half-bridge circuit 11R is connected to the signal processing circuit 10 via the second individual line RH. The signal processing circuit 10 sends the second individual signal of the second PWM signal to the second individual line RH. The second half-bridge circuit 11R supplies power Vdd to the second speaker 3R according to the second individual signal of the second PWM signal.

[0019] The common half-bridge circuit 11C is connected to the signal processing circuit 10 via the common return line CC. Therefore, the common return line CC is not an earthed line. The signal processing circuit 10 alternately sends the first return signal of the first PWM signal and the second return signal of the second PWM signal to the common return line CC. The common half-bridge circuit 11C has a timing to supply power Vdd to the first speaker 3L according to the first return signal of the first PWM signal and a timing to supply power Vdd to the second speaker 3R according to the second return signal of the second PWM signal. That is, the common half-bridge circuit 11C serves as both the half-bridge circuit for the first speaker 3L and the half-bridge circuit for the second speaker 3R, and the common return line CC serves as both the return line for the first speaker 3L and the return line for the second speaker 3R.

[0020] <Operation> FIG. 2 is a timing chart showing the operation of the multi-channel BTL drive circuit 1 of FIG. 1. Hereinafter, the operation of the multi-channel BTL drive circuit 1 will be mainly described with reference to FIG. 2 while appropriately referring to the configuration of FIG. 1.

[0021] The signal processing circuit 10 time-divides each period of the sampling rate into a first slot SL1 and a second slot SL2, assigning a pair of first PWM signals for the first speaker 3L to the first slot SL1 and a pair of second PWM signals for the second speaker 3R to the second slot SL2. That is, the signal processing circuit 10 assigns the signals of each channel to multiple slots SL1 and SL2 that do not overlap with each other in the signal frame P corresponding to each period of the sampling rate. As a channel configuration setting, the signal processing circuit 10 has a setting where, for example, the first half region of the signal frame P corresponding to each period of the sampling rate is set to the first slot SL1, the second half region to the second slot SL2, and the time width of the first slot SL1 and the time width of the second slot SL2 are the same.

[0022] The signal processing circuit 10 assigns the first individual signal (Hot side) of the pair of first PWM signals for the first speaker 3L to the first slot SL1 of the first individual line LH, and assigns the first return signal (Cold side) of the pair of first PWM signals for the first speaker 3L to the first slot SL1 of the common return line CC.

[0023] The signal processing circuit 10 assigns the second individual signal (Hot side) of the pair of second PWM signals for the second speaker 3R to the second slot SL2 of the second individual line RH, and assigns the second return signal (Cold side) of the pair of second PWM signals for the second speaker 3R to the second slot SL2 of the common return line CC.

[0024] The signal processing circuit 10 outputs a waveform to the first individual line LH that is in phase with the common return line CC in the second slot SL. For example, the signal processing circuit 10 outputs a waveform to the first individual line LH that is substantially the same potential as the common return line CC in the second slot SL. As a result, the differential signal (LH-CC) that drives the first speaker 3L is turned off in the second slot SL2. This reduces power consumption.

[0025] The signal processing circuit 10 outputs a waveform to the second individual line RH that is in phase with the common return line CC in the first slot SL. For example, the signal processing circuit 10 outputs a waveform to the second individual line RH that is substantially the same potential as the common return line CC in the first slot SL. As a result, the differential signal (RH-CC) that drives the second speaker 3R is turned off in the first slot SL1. This reduces power consumption.

[0026] Thus, in a signal frame P corresponding to one period, the signal processing circuit 10 drives the first channel in the first slot SL1 and the second channel in the second slot SL2. In this case, in order to suppress interference between adjacent slots SL1 and SL2, the maximum modulation width of each channel can be limited to within half of the signal frame P (i.e., 1 / number of channels). Furthermore, the signal processing circuit 10 can dynamically change the slot length, assignment order, carrier frequency, and phase based on the load state, sound source attributes, and whether sound quality or power saving is the priority, through programmable control.

[0027] <Comparative Example> Figure 3 is a block diagram showing a comparative example of a multi-channel BTL drive circuit 1001. As shown in Figure 3, the comparative example of a multi-channel BTL drive circuit 1001 comprises a signal processing circuit 1010, a pair of first half-bridge circuits 11LH, 11LC, and a pair of second half-bridge circuits 11RH, 11RC.

[0028] The signal processing circuit 1010 generates a pair of first PWM signals, which are a first individual signal (Hot side) and a first return signal (Cold side), based on the audio signal from the first PCM sound source 2L. The signal processing circuit 1010 inputs the first individual signal to the first half-bridge circuit 11LH via the first individual line LP, and inputs the first return signal to the first half-bridge circuit 11LC via the first return line LM.

[0029] The signal processing circuit 1010 generates a pair of second PWM signals, which are a second individual signal (Hot side) and a second return signal (Cold side), based on the audio signal from the second PCM sound source 2R. The signal processing circuit 1010 inputs the second individual signal to the second half-bridge circuit 11RH via the second individual line RH, and inputs the second return signal to the second half-bridge circuit 11RC via the second return line RC.

[0030] Thus, in the comparative example multi-channel BTL drive circuit 1001, a first return line LC for the first speaker 3L and a second return line RC for the second speaker 3R are provided separately, and a first half-bridge circuit 11LC for the first speaker 3L and a second half-bridge circuit 11Rc for the second speaker 3R are provided separately.

[0031] Figure 4 is a timing chart showing the operation of the comparative example multi-channel BTL drive circuit 1001. As shown in Figure 4, the signal processing circuit 1010 assigns the first individual signal (Hot side) of the pair of first PWM signals for the first speaker 3L to the entire first individual line LH, and assigns the first return signal (Cold side) of the pair of first PWM signals for the first speaker 3L to the entire first return line LC.

[0032] The signal processing circuit 1010 assigns the second individual signal (Hot side) of the pair of second PWM signals for the second speaker 3R to the entire second individual line RH, and assigns the second return signal (Cold side) of the pair of second PWM signals for the second speaker 3R to the entire second return line RC.

[0033] Thus, in the comparative example multi-channel BTL drive circuit 1001, the first return line LC for the first speaker 3L and the second return line RC for the second speaker 3R are provided separately, resulting in a large number of components. In the multi-channel BTL drive circuit 1 of this embodiment shown in Figure 2, while achieving audio reproduction similar to the multi-channel BTL drive circuit 1001, the number of components can be reduced and wiring can be simplified.

[0034] <Secondary Modulation> Figure 5 is a timing chart illustrating the secondary modulation of the multi-channel BTL drive circuit 1 in Figure 1. As shown in Figure 5, the signal processing circuit 10 generates a spreading code S synchronized with multiple slots obtained by time-dividing one period of the sampling rate of the audio signal, and a pair of PWM signals according to the value of the spreading code S. two Next, perform modulation. In this secondary modulation, while maintaining the differential component between the first individual line LH and the common return line CC (LH-CC), and the differential component between the second individual line RH and the common return line CC (RH-CC), the signal waveform of the target slot, which is either the first slot SL1 or the second slot SL2, is inverted in the time axis direction with reference to the center time of the target slot for each of the first individual line LH, the second individual line RH, and the common return line CC. Secondary modulation disrupts the periodicity of the PWM signal on the transmission line, reducing noise peaks. this Secondary modulation by The differential components of the pair of PWM signals are not affected by secondary modulation, thus preventing degradation of sound quality.

[0035] Specifically, the spreading code S is a sequence of random or pseudorandom numbers that takes the logical values ​​of 0 (primary value) or 1 (secondary value). A linear feedback shift register that generates M-sequence random numbers can be used as the spreading code generator.

[0036] The signal processing circuit 10 does not modulate the first individual signal of the first individual line LH, the second individual signal of the second individual line RH, and the common return signal of the common return line CC when the spreading code S is "0". On the other hand, the signal processing circuit 10 modulates the first individual signal of the first individual line LH, the second individual signal of the second individual line RH, and the common return signal of the common return line CC when the spreading code S is "1". Modulation is performed on each line of the first individual line LH, the second individual line RH, and the common return line CC. In this case, the signal waveform of the target slot among multiple slots SL1 and SL2, where the spreading code S is "1", is measured in the time axis direction with respect to the center time of the target slot. This is achieved by reversing the process.

[0037] Here, the radiated principal components (LH+CC) of the first PWM signal and the radiated principal components (RH+CC) of the second PWM signal are sources of EMI (electromagnetic interference). The radiated principal components (LH+CC) of the first PWM signal and the radiated principal components (RH+CC) of the second PWM signal have a periodicity in which harmonic components that are integer multiples of the carrier frequency of the PWM signal are strongly present, regardless of the presence or absence of an audio signal. This periodicity is the cause of noise in which energy is concentrated at a specific frequency.

[0038] In the multi-channel BTL drive circuit 1 of this embodiment, a random spreading code S(0,1,1,0,···) is generated in synchronization with the PWM period. The drive voltage across the speaker 3L is proportional to the differential component (LH-CC) of the modulated first individual signal and the first return signal. This differential component (LH-CC) is equal to the differential component (LH-CC) before modulation, regardless of the value of the spreading code S. Therefore, As mentioned above Secondary modulation due to inversion does not affect the quality of the sound reproduced from speaker 3L. The same applies to speaker 3R.

[0039] On the other hand, the radiated components (LH+CC) of the modulated first individual signal and common return signal have their periodicity disrupted by the influence of a random spreading code S. Similarly, the radiated components (LH+CC) of the modulated second individual signal and common return signal also have their periodicity disrupted by the influence of a random spreading code S. Therefore, in the harmonic components of the PWM signal that are integer multiples of the carrier frequency, energy is spread to nearby frequency bands, significantly reducing the peak energy level and thus reducing EMI.

[0040] <Compatible with 3-prong plugs> Figure 6 shows the configuration when the multi-channel BTL drive circuit 1 of Figure 1 is applied to the 3-pole plug 51 of the headphones 50. As shown in Figure 6, the multi-channel BTL drive circuit 1 may also include a terminal circuit 40 for electrically connecting to the 3-pole plug 51 of the headphones 50 (or earphones). Here, the 3-pole plug 51 is based on a general standard such as a 3.5 mm diameter stereo mini plug as specified in JIS-C-C6560 (Coaxial connectors for microphones and earphones).

[0041] The terminal circuit 40 includes a first terminal TL, a second terminal TR, and a common terminal TC. The first terminal TL is a terminal for electrical connection to the first individual terminal 51a of the 3-pole plug 51 and is conductive to line LH which connects the first half-bridge circuit 11L to the first speaker 3L. The second terminal TR is a terminal for electrical connection to the second individual terminal 51b of the 3-pole plug 51 and is conductive to line RH which connects the second half-bridge circuit 11R to the second speaker 3R. The common terminal TC is a terminal for electrical connection to the ground terminal 51c of the 3-pole plug 51 and is conductive to line CC which connects the common half-bridge circuit 11C to the first speaker 3L and the second speaker 3R.

[0042] In the comparative example shown in Figure 3, since the return lines LC and RC of each channel are independent, in order to output them as is, it is necessary to use a so-called balanced 4-pole plug that transmits four signal lines, such as L+, L-, R+, and R-, independently. In the comparative example, although a minor 4-pole plug could be used, a sophisticated conversion circuit was required to use a major 3-pole plug. In contrast, in the embodiment shown in Figure 6, a 3-pole plug can be used with a simple terminal circuit 40 without requiring a sophisticated conversion circuit. Note that although Figure 6 illustrates a configuration in which speakers 3L and 3R and headphones 50 are shared, a configuration without speakers 3L and 3R is also possible.

[0043] <Summary> As described above, with the multi-channel BTL drive circuit 1 of this embodiment, the return line through which the return signal of the first speaker 3L flows and the return line through which the return signal of the second speaker 3R flows are combined into a common return line CC, thus reducing the number of components and simplifying the wiring.

[0044] The signal processing circuit 10 then assigns the first PWM signal (first individual signal and first return signal) for the first speaker 3L and the second PWM signal (second individual signal and second return signal) for the second speaker 3R to the first slot SL1 and second slot SL2, which are formed by time-dividing each period of the sampling rate, respectively. The first individual line LH for the first speaker 3L outputs a waveform in phase with the common return line CC in the second slot SL, and the second individual line RH for the second speaker 3R outputs a waveform in phase with the common return line CC in the first slot SL. Thus, a BTL drive system can be suitably realized while using the common return line CC.

[0045] (modified version) The multi-channel BTL drive circuit of this disclosure is not limited to the embodiments described above. For example, the configuration shown in Figure 7 or Figure 8 may be used.

[0046] Figure 7 is a configuration diagram showing the multi-channel BTL drive circuit 101 of the first modified example. As shown in Figure 7, the multi-channel BTL drive circuit 101 of the first modified example includes a configuration for a third speaker 3W for low-frequency reproduction (LFE) in addition to the first speaker 3L and the second speaker 3R.

[0047] The multi-channel BTL drive circuit 101 includes a signal processing circuit 110, a first half-bridge circuit 11L, a second half-bridge circuit 11R, and a common half-bridge circuit 11C. The multi-channel BTL drive circuit 101 also supplies power to a third speaker 3W for low-frequency reproduction by PWM control based on the audio signals of the first PCM sound source 2L and the second PCM sound source 2R. Therefore, the multi-channel BTL drive circuit 101 also includes a third half-bridge circuit 11W for the third speaker 3W.

[0048] The signal processing circuit 110 includes PCM-PWM data converters 21L, 21R, 21W, PCM-PWM data width converters 22L, 22R, 22W, a multiplexer 23, a channel configuration setting 24, PWM sequencers 25L, 25R, 25W, 25C, and PWM waveform generators 26L, 26R, 26W, 26C.

[0049] The PCM-PWM data converter 21L and the PCM-PWM width converter 22L sample the audio signal input from the PCM sound source 2L at a predetermined sampling rate and convert it into a pair of first PWM signals, which are a first individual signal (Hot side) and a first return signal (Cold side) for the first speaker 3L of the first channel. They then calculate the duty cycle based on the amplitude level of the audio signal from the first PCM sound source 2L and determine the pulse width.

[0050] The PCM-PWM data converter 21R and the PCM-PWM width converter 22R sample the audio signal input from the PCM sound source 2R at the same sampling rate and convert it into a pair of second PWM signals, which are a second individual signal (Hot side) and a second return signal (Cold side) for the second speaker 3R of the second channel. They then calculate the duty cycle based on the amplitude level of the audio signal from the second PCM sound source 2R to determine the pulse width.

[0051] The mixing processor 20 combines the audio signal of the first PCM sound source 2L and the audio signal of the second PCM sound source 2R to generate an LFE signal, which is output to the PCM-PWM data converter 21W. The PCM-PWM data converter 21W and the PCM-PWM width converter 22W convert the LFE signal input from the mixing processor 20 into a pair of third PWM signals, which are a third individual signal (Hot side) and a third return signal (Cold side) for the third speaker 3W, and calculate the duty cycle based on the amplitude level of the audio signal from the mixing processor 20 to determine the pulse width.

[0052] Based on the information in the channel configuration setting 24, the multiplexer 23 time-divides each period of the sampling rate to the first slot SL1, the second slot SL2, and the third slot SL3, assigning a pair of first PWM signals to the first slot SL1, a pair of second PWM signals to the second slot SL2, and a pair of third PWM signals to the third slot SL3.

[0053] The first PWM sequencer 25L and the first PWM waveform generator 26L, in accordance with a command from the multiplexer 23, assign the first individual signal of the first PWM signal to the first slot SL1 of the signal frame P of the PWM signal to be input to the first half-bridge circuit 11L.

[0054] The second PWM sequencer 25R and the second PWM waveform generator 26R, in accordance with the command from the multiplexer 23, assign the second individual signal of the second PWM signal to the second slot SL2 of the signal frame P of the PWM signal to be input to the second half-bridge circuit 11R.

[0055] The third PWM sequencer 25W and the third PWM waveform generator 26W, in accordance with a command from the multiplexer 23, assign the third individual signal of the third PWM signal to the third slot SL3 of the signal frame P of the PWM signal to be input to the third half-bridge circuit 11W.

[0056] The common PWM sequencer 25C and the common PWM waveform generator 26C, in accordance with a command from the multiplexer 23, assign the first return signal of the first PWM signal to the first slot SL1 of the signal frame P of the PWM signal to be input to the common half-bridge circuit 11C. The common PWM sequencer 25C and the common PWM waveform generator 26C, in accordance with a command from the multiplexer 23, assign the second return signal of the second PWM signal to the second slot SL2 of the signal frame P of the PWM signal to be input to the common half-bridge circuit 11C. The common PWM sequencer 25C and the common PWM waveform generator 26C, in accordance with a command from the multiplexer 23, assign the third return signal of the third PWM signal to the third slot SL3 of the signal frame P of the PWM signal to be input to the common half-bridge circuit 11C.

[0057] In the above configuration, the third half-bridge circuit 11C is shared for the return signals of the first speaker 3L, the second speaker 3R, and the third speaker 3W, reducing the number of components and simplifying the wiring.

[0058] Figure 8 is a configuration diagram showing the second modified multi-channel BTL drive circuit 201. As shown in Figure 8, the second modified multi-channel BTL drive circuit 201 includes a configuration for a third speaker 3W for low-frequency reproduction (LFE) in addition to the first speaker 3L and the second speaker 3R, but the third speaker 3W is connected to the hot terminal of the first speaker 3L and the hot terminal of the second speaker 3R. With this configuration, the mixing processor 20 shown in Figure 7 can be eliminated.

[0059] In the power conversion circuit, a half-bridge circuit, which is an example of a switching circuit, was used. However, any circuit that converts power to the load by PWM control, even one that is not for amplification, may be used.

[0060] Although a speaker was given as an example of a load, a DC motor may also be used as a load. In that case, the first half-bridge circuit 11L and the common half-bridge circuit 11C may be connected to each terminal of the first motor, and the second half-bridge circuit 11R and the common half-bridge circuit 11C may be connected to each terminal of the second motor. When the motor is stopped, the first individual line LH and the second individual line RH may be set to a high impedance state. In this way, similar to the multi-channel BTL drive of a speaker, the number of components in motor control and wiring can be simplified in multi-axis control using multiple motors.

[0061] Furthermore, each functional block in the above-described embodiment may be implemented as a hardware circuit, or it may be a processing circuit realized by a processor executing a software program. For example, in the configuration of Figure 1, all or at least part of the signal processing circuit 10 may be realized by a processor that executes a program.

[0062] The functions realized by the components described herein may be implemented in a circuitry or processing circuitry, including general-purpose processors, application-specific processors, integrated circuits, ASICs (Application Specific Integrated Circuits), CPUs (a Central Processing Unit), FPGAs (Field-Programmable Gate Arrays), conventional circuits, and / or combinations thereof, programmed to realize the described functions. A processor, including transistors and other circuits, is considered a circuitry or processing circuitry. A processor may be a programmed processor that executes a program stored in memory. In this specification, circuitry, unit, and means are hardware programmed to realize or perform the described functions. Such hardware may be any hardware disclosed herein, or any hardware known to be programmed to realize or perform the described functions. If such hardware is a processor that is considered a type of circuitry, then such circuitry, means, or unit is a combination of hardware and software used to constitute such hardware and / or processor.

[0063] Although several embodiments of this disclosure have been described above, these embodiments can be implemented in a variety of other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. For example, configurations and processes in one embodiment may be combined with configurations and processes in another embodiment, or a modification of one embodiment may be applied to another embodiment. These embodiments and their variations are included in the scope and spirit of the invention, as well as in the claims and their equivalents.

[0064] (Note) The details described in each of the above embodiments are noted below.

[0065] (Note 1) A multi-channel BTL drive circuit that supplies power to multiple loads, including a first load and a second load, by PWM control synchronized with the sampling rate of the input signals based on input signals from multiple channels, including a first channel and a second channel, comprising: a signal processing circuit that generates a pair of first PWM signals, which are a first individual signal and a first return signal, based on the input signal of the first channel, and generates a pair of second PWM signals, which are a second individual signal and a second return signal, based on the input signal of the second channel; a first power conversion circuit that supplies power to the first load in accordance with the first individual signal; a second power conversion circuit that supplies power to the second load in accordance with the second individual signal; and a circuit that supplies power to the first load in accordance with the first return signal and supplies power to the second load in accordance with the second return signal. A multi-channel BTL drive circuit comprising a common power conversion circuit that supplies power, a first individual line connected to the first power conversion circuit through which a first individual signal flows, a second individual line connected to the second power conversion circuit through which a second individual signal flows, and a common return line connected to the common power conversion circuit through which a first return signal and a second return signal flow alternately, wherein the signal processing circuit time-divides each period of the sampling rate into a plurality of slots including a first slot and a second slot, assigns a first PWM signal to the first slot and a second PWM signal to the second slot, outputs a waveform in phase with the common return line in the second slot to the first individual line and outputs a waveform in phase with the common return line in the first slot to the second individual line.

[0066] (Note 2) The multi-channel BTL drive circuit described in Appendix 1 is characterized in that the first power conversion circuit is a first half-bridge circuit, the second power conversion circuit is a second half-bridge circuit, and the common power conversion circuit is a common half-bridge circuit.

[0067] (Note 3) The signal processing circuit generates a spreading code representing a first or second logical value in synchronization with multiple slots. When the spreading code is the first value, the first PWM signal and the second PWM signal are not modulated, and the first slot... Or the target slot which is the second slot. When the spreading code in is second value, the first PWM signal and the second PWM signal are modulated, and the modulation is, While maintaining the differential component between the first individual line and the common return line, and the differential component between the second individual line and the common return line, Each line: the first individual line, the second individual line, and the common return line. Regarding this, the signal waveform of the target slot is measured in the time axis direction with respect to the center time of the target slot. A multi-channel BTL drive circuit as described in Appendix 1 or 2, including inversion.

[0068] (Note 4) A multi-channel BTL drive circuit as described in any of Appendix 1 to 3, wherein the first load and the second load are a first speaker and a second speaker, respectively, the first PWM signal is a signal generated based on an audio signal to the first speaker, and the second PWM signal is a signal generated based on an audio signal to the second speaker.

[0069] (Note 5) A multi-channel BTL drive circuit according to any one of the appendices 1 to 4, further comprising a terminal circuit for electrically connecting to a 3-pole plug of headphones or earphones, the terminal circuit including a first terminal which is electrically connected to a line connecting a first power conversion circuit to a first speaker for electrically connecting to a first individual terminal of the 3-pole plug, a second terminal which is electrically connected to a line connecting a second power conversion circuit to a second speaker for electrically connecting to a second individual terminal of the 3-pole plug, and a common terminal which is electrically connected to a line connecting a common power conversion circuit to a first speaker and a second speaker for electrically connecting to the ground terminal of the 3-pole plug.

[0070] (Note 6) A multi-channel BTL drive method for supplying power to multiple loads, including a first load and a second load, by PWM control synchronized with the sampling rate of the input signals based on input signals from multiple channels, including a first channel and a second channel, comprising the steps of: generating a pair of first PWM signals, which are a first individual signal and a first return signal, based on the input signal of the first channel, and generating a pair of second PWM signals, which are a second individual signal and a second return signal, based on the input signal of the second channel; and time-dividing each period of the sampling rate into multiple slots, including a first slot and a second slot, and assigning the first PWM signal to the first slot and the second PWM signal A multi-channel BTL driving method comprising the steps of: assigning a signal to a second slot; flowing a first individual signal through a first individual line connected to a first power conversion circuit that supplies power to a first load; flowing a second individual signal through a second individual line connected to a second power conversion circuit that supplies power to a second load; and alternately flowing a first return signal and a second return signal through a common return line connected to a common power conversion circuit that supplies power to the first and second loads; and outputting a waveform in phase with the common return line in the second slot through the first individual line; and outputting a waveform in phase with the common return line in the first slot through the second individual line.

[0071] (Note 7) A multi-channel BTL drive program that operates a processor to supply power to multiple loads, including a first load and a second load, by PWM control synchronized with the sampling rate of the input signals based on input signals from multiple channels, including a first channel and a second channel, comprising the steps of: generating a pair of first PWM signals, which are a first individual signal and a first return signal, based on the input signal of the first channel, and generating a pair of second PWM signals, which are a second individual signal and a second return signal, based on the input signal of the second channel; and time-dividing each period of the sampling rate into multiple slots, including a first slot and a second slot, to assign the first PWM signal to the first slot, and the second A multi-channel BTL drive program that causes the processor to perform the following steps: assign a PWM signal to the second slot; send a first individual signal to a first individual line connected to a first power conversion circuit that supplies power to the first load; send a second individual signal to a second individual line connected to a second power conversion circuit that supplies power to the second load; and alternately send a first return signal and a second return signal to a common return line connected to a common power conversion circuit that supplies power to the first and second loads; and output a waveform in phase with the common return line in the second slot to the first individual line, and output a waveform in phase with the common return line in the first slot to the second individual line. [Explanation of Symbols]

[0072] 1. Multi-channel BTL drive circuit 3L 1st speaker (1st load) 3R Second speaker (second load) 10 Signal Processing Circuits 11C Common Half-Bridge Circuit (Common Power Conversion Circuit) 11L First Half-Bridge Circuit (First Power Conversion Circuit) 11R Second Half-Bridge Circuit (Second Power Conversion Circuit) 40 terminal circuit 50 headphones 51 3-pin plug 51a 1st individual terminal 51b 2nd individual terminal 51c Ground terminal CC Common Return Line LH 1st Individual Line RH 2nd Individual Line P: Signal frame (each period of the sampling rate) S Diffusion Code SL1 1st slot SL2 2nd slot TC Common Terminal TL Terminal 1 TR 2nd terminal

Claims

1. A multi-channel BTL drive circuit that supplies power to a plurality of loads, including a first load and a second load, by PWM control synchronized with the sampling rate of the input signals based on input signals from a plurality of channels, including a first channel and a second channel, A signal processing circuit that generates a pair of first PWM signals, which are a first individual signal and a first return signal, based on the input signal of the first channel, and generates a pair of second PWM signals, which are a second individual signal and a second return signal, based on the input signal of the second channel, A first power conversion circuit that supplies power to the first load in accordance with the first individual signal, A second power conversion circuit that supplies power to the second load in accordance with the second individual signal, A common power conversion circuit that supplies power to the first load in response to the first return signal and supplies power to the second load in response to the second return signal, A first individual line connected to the first power conversion circuit, through which the first individual signal flows, A second individual line connected to the second power conversion circuit, through which the second individual signal flows, The common return line is connected to the common power conversion circuit and through which the first return signal and the second return signal alternately flow, The aforementioned signal processing circuit is Each period of the sampling rate is time-divided into a plurality of slots, including the first slot and the second slot, and the first PWM signal is assigned to the first slot, and the second PWM signal is assigned to the second slot. The first individual line outputs a waveform in phase with the common return line in the second slot, and the second individual line outputs a waveform in phase with the common return line in the first slot. The aforementioned signal processing circuit is A spreading code representing a first or second logical value is generated synchronously in the plurality of slots. When the spreading code is the first value, the first PWM signal and the second PWM signal are not modulated. When the spreading code in the target slot, which is the first slot or the second slot, is the second value, the first PWM signal and the second PWM signal are modulated. The modulation includes a multi-channel BTL drive circuit that maintains the differential component between the first individual line and the common return line, and the differential component between the second individual line and the common return line, while inverting the signal waveform of the target slot in the time axis direction with respect to the center time of the target slot for each of the first individual line, the second individual line, and the common return line.

2. The first power conversion circuit is a first half-bridge circuit, The aforementioned second power conversion circuit is a second half-bridge circuit, The multi-channel BTL drive circuit according to claim 1, wherein the common power conversion circuit is a common half-bridge circuit.

3. The first load and the second load are the first speaker and the second speaker, respectively. The first PWM signal is a signal generated based on the audio signal to the first speaker. The multi-channel BTL drive circuit according to claim 1, wherein the second PWM signal is a signal generated based on the audio signal to the second speaker.

4. It further comprises a terminal circuit for electrically connecting to a 3-pole plug of headphones or earphones, The aforementioned terminal circuit is A terminal for electrically connecting to the first individual terminal of the three-pole plug, the first terminal being in conductivity with the line connecting the first power conversion circuit to the first speaker, A terminal for electrically connecting to the second individual terminal of the three-pole plug, the second terminal being in conductivity with the line connecting the second power conversion circuit to the second speaker, The multi-channel BTL drive circuit according to claim 3, comprising a terminal for electrically connecting to the ground terminal of the three-pole plug, and a common terminal that conducts with the lines connecting the common power conversion circuit to the first speaker and the second speaker.

5. A multi-channel BTL drive method that supplies power to a plurality of loads, including a first load and a second load, by PWM control synchronized with the sampling rate of the input signals based on input signals of a plurality of channels, including a first channel and a second channel, wherein The steps of generating a pair of first PWM signals, which are a first individual signal and a first return signal, based on the input signal of the first channel, and generating a pair of second PWM signals, which are a second individual signal and a second return signal, based on the input signal of the second channel, The steps include dividing each period of the sampling rate into a plurality of slots, including a first slot and a second slot, assigning the first PWM signal to the first slot, and assigning the second PWM signal to the second slot, The steps include: passing the first individual signal through a first individual line connected to a first power conversion circuit that supplies power to the first load; passing the second individual signal through a second individual line connected to a second power conversion circuit that supplies power to the second load; and alternately passing the first return signal and the second return signal through a common return line connected to a common power conversion circuit that supplies power to the first and second loads; The first individual line outputs a waveform in phase with the common return line in the second slot, and the second individual line outputs a waveform in phase with the common return line in the first slot, A step of generating a spreading code representing a first or second logical value in synchronization with the plurality of slots, A multi-channel BTL driving method comprising the steps of: not modulating the first PWM signal and the second PWM signal when the spreading code is the first value; and modulating the first PWM signal and the second PWM signal when the spreading code in the target slot, which is the first or second slot, is the second value, wherein the modulation includes inverting the signal waveform of the target slot in the time axis direction with respect to the center time of the target slot for each line of the first individual line, the second individual line, and the common return line, while maintaining the differential component between the first individual line and the common return line, and the differential component between the second individual line and the common return line.

6. A multi-channel BTL drive program that operates a processor to supply power to a plurality of loads, including a first load and a second load, by PWM control synchronized with the sampling rate of the input signals based on input signals from a plurality of channels, including a first channel and a second channel, wherein the processor operates to supply power to a plurality of loads, including a first load and a second load, The steps of generating a pair of first PWM signals, which are a first individual signal and a first return signal, based on the input signal of the first channel, and generating a pair of second PWM signals, which are a second individual signal and a second return signal, based on the input signal of the second channel, The steps include dividing each period of the sampling rate into a plurality of slots, including a first slot and a second slot, assigning the first PWM signal to the first slot, and assigning the second PWM signal to the second slot, The steps include: passing the first individual signal through a first individual line connected to a first power conversion circuit that supplies power to the first load; passing the second individual signal through a second individual line connected to a second power conversion circuit that supplies power to the second load; and alternately passing the first return signal and the second return signal through a common return line connected to a common power conversion circuit that supplies power to the first and second loads; The first individual line outputs a waveform in phase with the common return line in the second slot, and the second individual line outputs a waveform in phase with the common return line in the first slot, A step of generating a spreading code representing a first or second logical value in synchronization with the plurality of slots, A multi-channel BTL drive program that causes the processor to perform the following steps: when the spreading code is the first value, the first PWM signal and the second PWM signal are not modulated; when the spreading code in the target slot, which is the first slot or the second slot, is the second value, the first PWM signal and the second PWM signal are modulated, wherein the modulation includes maintaining the differential component between the first individual line and the common return line, and the differential component between the second individual line and the common return line, while inverting the signal waveform of the target slot in the time axis direction with respect to the center time of the target slot for each line of the first individual line, the second individual line, and the common return line.

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