Isolator

Abstract

To provide an isolator capable of suppressing complication of a manufacturing process and an increase in a size.SOLUTION: An isolator package includes: an isolator module 40 including an insulating layer (first substrate) 414, an insulating layer 415 in contact with a top surface of the insulating layer 414, an insulating layer 413 in contact with a bottom surface of the insulating layer 414, a coil CU arranged at a same height as the insulating layer 415, and a coil CL arranged at a same height as the insulating layer 413 and facing the coil CU; a conductor BP arranged below the isolator module 40 and electrically connected to a bottom surface of the coil CL; and a semiconductor chip. The coil CL and a top surface of the semiconductor chip are electrically connected to each other with the conductor BP and a conductive pad PLb interposed therebetween.SELECTED DRAWING: Figure 6

Description

Technical Field

[0004] , ,

[0001] Embodiments of the present invention relate to isolators.

Background Art

[0002] An isolator that transmits a signal from a transmission-side circuit to a reception-side circuit in an insulated state between the transmission-side circuit and the reception-side circuit is known.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Patent Document 2

Patent Document 3

Patent Document 4

Patent Document 5

Summary of the Invention

Problems to be Solved by the Invention

[0004] Suppress the complication of the manufacturing process and the increase in size.

Means for Solving the Problems

[0005] The isolator according to the embodiment includes an isolator module including a first substrate, a first insulating layer in contact with the upper surface of the first substrate, a second insulating layer in contact with the lower surface of the first substrate, a first coil included in the same layer as the first insulating layer, and a second coil provided opposite to the first coil and included in the same layer as the second insulating layer; a first conductor portion provided below the isolator module and electrically connected to the lower surface of the second coil; and a first chip, wherein the second coil and the upper surface of the first chip are electrically connected via the first conductor portion. [Brief explanation of the drawing]

[0006] [Figure 1] A plan view showing an example of a planar layout of an isolator according to the embodiment. [Figure 2] A cross-sectional view along line II-II in Figure 1, showing an example of the cross-sectional structure of the isolator according to the embodiment. [Figure 3] A perspective view showing an example of the structure of an isolator module according to the embodiment. [Figure 4] A perspective view showing an example of the structure of the primary circuit of an isolator module according to the embodiment. [Figure 5] A perspective view showing an example of the structure of the secondary circuit of an isolator module according to the embodiment. [Figure 6] A cross-sectional view along the line VI-VI in Figure 3, showing an example of the cross-sectional structure of an isolator module according to the embodiment. [Figure 7] A plan view showing an example of the planar layout of an isolator according to the first modified example. [Figure 8] A cross-sectional view along line VIII-VIII in Figure 7 shows an example of the cross-sectional structure of the isolator according to the first modified example. [Figure 9] A plan view showing an example of the planar layout of an isolator according to the second modified example. [Figure 10] A cross-sectional view along line XX in Figure 9, showing an example of the cross-sectional structure of the isolator according to the second modified example. [Figure 11] A plan view showing an example of the planar layout of an isolator according to the third modified example. [Figure 12] Perspective view showing an example of the structure of the isolator module according to the third modification. [Figure 13] Perspective view showing an example of the structure of the primary circuit of the isolator module according to the third modification. [Figure 14] Perspective view showing an example of the structure of the secondary circuit of the isolator module according to the third modification. [Figure 15] Perspective view showing an example of the structure of the isolator module according to the fourth modification. [Figure 16] Perspective view showing an example of the structure of the primary circuit of the isolator module according to the fourth modification. [Figure 17] Perspective view showing an example of the structure of the secondary circuit of the isolator module according to the fourth modification.

Embodiments for Carrying Out the Invention

[0007] Hereinafter, embodiments will be described with reference to the drawings. The dimensions and ratios in the drawings are not necessarily the same as those in reality.

[0008] In the following description, components having substantially the same functions and configurations are denoted by the same reference numerals. When particularly distinguishing between elements having similar configurations, different characters or numbers may be added to the end of the same reference numeral.

[0009] 1. Embodiment The isolator according to the embodiment will be described.

[0010] FIG. 1 is a plan view showing an example of the planar layout of the isolator according to the embodiment. FIG. 2 is a cross-sectional view taken along line II-II of FIG. 1 showing an example of the cross-sectional structure of the isolator according to the embodiment. As shown in FIGS. 1 and 2, the isolator package 1 is a package including a digital isolator. The isolator package 1 includes a frame 10, semiconductor chips 20 and 30, an isolator module 40, and an insulating member 50. In FIG. 1, the insulating member 50 is shown omitted.

[0011] The frame 10 is, for example, a plate-shaped metal member. On the surface of the frame 10, semiconductor chips 20 and 30 are provided via insulating adhesive members 11 and 12, respectively. The frame 10 functions as a substrate for supporting the semiconductor chips 20 and 30.

[0012] Hereinafter, a plane parallel to the surface of the frame 10 is defined as the XY plane. Directions intersecting perpendicularly to each other within the XY plane are defined as the X direction and the Y direction. A direction intersecting the XY plane is defined as the Z direction. Among the Z directions, the direction from the frame 10 toward the semiconductor chips 20 and 30 is also referred to as the upward direction.

[0013] The isolator module 40 is provided on the upper surface of the semiconductor chip 20 via an insulating adhesive member 13. Thereby, the isolator module 40 is provided at a position overlapping, for example, the semiconductor chip 20 when viewed in the Z direction.

[0014] A circuit 21 is formed in the semiconductor chip 20. The circuit 21 includes a signal transmission / reception circuit and a modulation / demodulation circuit. The circuit 21 is electrically connected to the isolator module 40 via a conductor portion BP connected to the upper surface of the semiconductor chip 20. That is, the semiconductor chip 20 and the isolator module 40 are electrically connected, for example, by flip chip bonding. The conductor portion BP is, for example, a bump. Also, the conductor portion BP may be formed, for example, by soldering. The semiconductor chip 20 is electrically connected to the pin 23 via a bonding wire Wc.

[0015] The semiconductor chip 30 is arranged in parallel with the semiconductor chip 20 in the X direction. A circuit 31 is formed in the semiconductor chip 30. The circuit 31 includes a signal transmission / reception circuit and a modulation / demodulation circuit. The circuit 31 is electrically connected to the isolator module 40 via bonding wires Wa and Wb. The semiconductor chip 30 is electrically connected to the pin 33 via a bonding wire Wd.

[0016] The isolator module 40 is a module that functions as a digital isolator. A transformer is mounted in the isolator module 40. The isolator module 40 is configured to transmit signals while isolating the transmitting circuit (primary circuit) and the receiving circuit (secondary circuit) using the transformer. Details of the configuration of the isolator module 40 will be described later.

[0017] The insulating member 50 includes, for example, an insulating resin. The frame 10, semiconductor chips 20 and 30, isolator module 40, and bonding wires Wa and Wb are sealed by the insulating member 50. The pins 23 and 33 are fixed by the insulating member 50, while having portions exposed to the outside of the insulating member 50.

[0018] With the above configuration, the isolator package 1 can transmit signals between pins 23 and 33 via the isolator module 40.

[0019] Figure 3 is a perspective view showing an example of the structure of an isolator module according to the embodiment. Figure 4 is a perspective view showing an example of the structure of the primary circuit of the isolator module according to the embodiment. Figure 5 is a perspective view showing an example of the structure of the secondary circuit of the isolator module according to the embodiment. Figure 6 is a cross-sectional view along line VI-VI in Figure 3, showing an example of the cross-sectional structure of the isolator module according to the embodiment. As shown in Figures 3, 4, 5, and 6, the isolator module 40 includes, for example, a wiring board 41. In Figures 3, 4, and 5, conductive members within the wiring board 41 are shown through an insulating member covering the conductive members. Also, in Figure 6, the adhesive member 13 is not shown.

[0020] The wiring board 41 is a printed circuit board that includes a primary circuit and a secondary circuit. As the printed circuit board, for example, a flexible printed circuit board (FPC) can be used. The shape of the wiring board 41 can be, for example, rectangular, but is not limited to rectangular, and any shape can be used.

[0021] The wiring board 41 contains conductive pads PUa, PUb, PLa, and PLb, a dummy pad Pdm, and coils CU and CL. The outer shape of the wiring board 41 is formed by laminating insulating layers 411, 412, 413, 414, 415, 416, and 417 in that order.

[0022] Pads PLa and PLb are provided within the insulating layer 412. The portion of the insulating layer 411 below the insulating layer 412 that overlaps with pads PLa and PLb when viewed in the Z direction is removed. The lower surface of each pad PLa and PLb is electrically connected to the circuit 21 of the semiconductor chip 20 via the corresponding conductor portion BP. Each of pads PLa and PLb has, for example, a circular shape. However, it is not limited to this. Each of pads PLa and PLb may have, for example, a rectangular shape.

[0023] Furthermore, the dummy pad Pdm is provided within the insulating layer 412, similar to pads PLa and PLb. The dummy pad Pdm is provided such that, for example, the dummy pad Pdm and pad PLa are positioned point-symmetrically with respect to PLb when viewed in the Z direction. The size of the dummy pad Pdm, as well as pads PLa and PLb, are, for example, equivalent. Note that the arrangement and size of the dummy pad Pdm are not limited to those shown in Figure 4. The position and size of the dummy pad Pdm can be determined, for example, based on the center of gravity of the isolator module 40, in order to make it easier to keep the isolator module 40 horizontal with respect to the XY plane when mounting the isolator module 40. Also, although the case in which the wiring board 41 includes one dummy pad Pdm is shown, it is not limited to this. The dummy pad Pdm may not be included, or two or more may be included within the insulating layer 412.

[0024] The coil CL is provided within the insulating layer 413. The coil CL contains, for example, copper. The upper surface of the coil CL is located below, for example, the upper surface of the insulating layer 413. The lower surface of the coil CL is flush with, for example, the lower surface of the insulating layer 413. Viewed in the Z direction, the coil CL has a spiral winding shape and a predetermined inductance. The coil CL has a central end and an outer peripheral end. The outer peripheral end of the coil CL is electrically connected to the pad PLa. The central end of the coil CL is electrically connected to the pad PLb. With this configuration, a current path is formed between the conductor BP connected to the pad PLa and the conductor BP connected to the pad PLb. The coil CL is also called the primary coil.

[0025] Furthermore, the lower part of the coil CL may be plated. Also, the coil CL may be composed of, for example, two or more layers of copper foil.

[0026] Pads PUa and PUb are provided within the insulating layer 416. The portion of the insulating layer 417 above the insulating layer 416 that overlaps with pads PUa and PUb when viewed in the Z direction is removed. Bonding wires Wa and Wb are electrically connected to pads PUa and PUb, respectively. Each of pads PUa and PUb may have a different shape and size from, for example, pads PLa and PLb. More specifically, if each of pads PLa and PLb is circular, each of pads PUa and PUb may be rectangular, for example, or may be larger than each of pads PLa and PLb.

[0027] Furthermore, pad PUa is positioned so that, when viewed in the Z direction, it overlaps with, for example, pad PLa. Similarly, pad PUb is positioned so that, when viewed in the Z direction, it overlaps with, for example, pad PLb.

[0028] The coil CU is provided within the insulating layer 415. The coil CU contains, for example, copper. The upper surface of the coil CU is flush with, for example, the upper surface of the insulating layer 415. The lower surface of the coil CU is located above, for example, the lower surface of the insulating layer 415. Viewed in the Z direction, the coil CU has a spiral winding shape and a predetermined inductance. The coil CU has a central end and an outer peripheral end. The outer peripheral end of the coil CU is electrically connected to pad PUa. The central end of the coil CU is electrically connected to pad PUb. With this configuration, a current path is formed between bonding wire Wa and bonding wire Wb. The coil CU is also called a secondary coil.

[0029] Furthermore, the upper part of the coil CU may be plated. Also, the coil CU may be composed of, for example, two or more layers of copper foil.

[0030] With the above configuration, above the conductor section BP, the pads PLa and PLb, coil CL, coil CU, and pads PUa and PUb are arranged, for example, in this order facing upwards. Furthermore, the primary and secondary coils are arranged opposite each other, separated from each other in the Z direction. As a result, the primary and secondary coils function as a transformer.

[0031] According to this embodiment, in the isolator module 40, coils CL and CU are arranged on the same wiring board 41. This configuration makes it possible to suppress the complexity of the manufacturing process compared to the case in which an isolator module is formed by bonding a wiring board containing a primary coil and a wiring board containing a secondary coil. More specifically, when an isolator module is formed by bonding a wiring board containing a primary coil and a wiring board containing a secondary coil, the characteristics of the isolator module may deteriorate due to misalignment of the primary and secondary coils during the bonding process. Therefore, the manufacturing process may become complicated in order to suppress the occurrence of misalignment of the primary and secondary coils. According to this embodiment, since both the primary and secondary coils are provided within the same wiring board 41, the occurrence of misalignment can be easily suppressed compared to the case in which an isolator module is formed by bonding a wiring board containing a primary coil and a wiring board containing a secondary coil. Therefore, it is possible to suppress the complexity of the manufacturing process while suppressing the deterioration of the characteristics of the isolator module.

[0032] Furthermore, according to this embodiment, pads PLa and PLb are positioned below coil CL. In this configuration, pads PLa and PLb are directly connected to coil CL on their upper surfaces. Also, pads PUa and PUb are positioned above coil CU. In this configuration, pads PUa and PUb are directly connected to coil CU on their lower surfaces. With these configurations, according to this embodiment, for example, a pad connected to the primary coil does not need to be positioned outside the secondary coil and the pads connected to the secondary coil when viewed in the Z direction. This makes it possible to suppress an increase in the size of the isolator module 40 and the isolator package 1.

[0033] To elaborate, for example, if the pads connected to the primary coil and the pads connected to the secondary coil, which are positioned opposite the primary coil, are both located at the top of the isolator module, then, viewed in the Z direction, the pads connected to the outer periphery and the central end of the primary coil will both be positioned outside the portion including the secondary coil and the pads connected to it. As a result, the size of the isolator module 40 and the isolator package 1 will increase in proportion to the area of ​​the pads connected to the primary coil. Similarly, if the pads connected to the primary coil and the pads connected to the secondary coil are both located at the bottom of the isolator module, the size of the isolator module 40 and the isolator package 1 will increase for the same reason. According to this embodiment, since pads PLa and PLb and pads PUa and PUb are located below the primary coil and above the secondary coil, respectively, the increase in the size of the isolator module 40 and the isolator package 1 can be suppressed.

[0034] Furthermore, according to the embodiment, for example, the shapes of pads PUa and PUb can be different from the shapes of pads PLa and PLb. This allows pads PUa and PUb to have the same shape as the alignment pattern used when mounting the isolator module 40 in the manufacturing process of the isolator package 1. Therefore, when mounting the isolator module 40, the position of the isolator module 40 can be adjusted without providing a different alignment pattern on the upper part of the isolator module than the pads. In other words, pads PUa and PUb can also be used as an alignment pattern. Thus, even with such a configuration, it is possible to suppress an increase in the size of the isolator module 40 and the isolator package 1.

[0035] Furthermore, according to this embodiment, the isolator module 40 is electrically connected to the semiconductor chip 20 by flip-chip bonding. As a result, the isolator module 40 is positioned to overlap with the semiconductor chip 20 when viewed in the Z direction. This configuration also helps to suppress an increase in the size of the isolator package 1.

[0036] Furthermore, according to this embodiment, it is possible to suppress an increase in the number of windings of coils CL and CU. This also helps to suppress an increase in the size of the isolator module 40 and the isolator package 1. More specifically, when an isolator module is formed by bonding a wiring board containing a primary coil and a wiring board containing a secondary coil, the two wiring boards are bonded together, for example, by an adhesive. As a result, the coil formed on one wiring board and the coil formed on the other wiring board are separated by the thickness of the adhesive. However, according to this embodiment, since coils CL and CU are positioned below and above one wiring board 41, respectively, an adhesive is not required to bond the two wiring boards together. This suppresses an increase in the distance between coils CL and CU. Therefore, it is possible to suppress a decrease in the coupling coefficient of the transformer due to an increase in the distance between the primary coil and the secondary coil. Consequently, it is possible to suppress an increase in the number of windings of each coil CL and CU due to a decrease in the coupling coefficient of the transformer.

[0037] Furthermore, according to the embodiment, the positions of pads PLa and PUa, and pads PLb and PUb, can be set to overlap when viewed in the Z direction. This suppresses a decrease in the rigidity of the portion where bonding wires Wa and Wb are formed. As a result, bonding wires Wa and Wb can be formed with high precision. This improves the reliability of the isolator package 1.

[0038] Furthermore, according to the embodiment, the isolator module 40 includes a dummy pad Pdm in the same layer as the pads PLa and PLb. This configuration allows, for example, adjustment of the center of gravity of the isolator module. This makes it easier to position the isolator module 40 horizontally with respect to the XY plane during the manufacturing process of the isolator package 1. With this configuration, the bonding wires Wa and Wb can be formed with high precision. Therefore, the reliability of the isolator package 1 can also be improved with this configuration.

[0039] Furthermore, as in the embodiment, if the isolator module 40 is electrically connected to the semiconductor chip 20 by flip-chip bonding, it is possible to suppress the difficulty in manufacturing the isolator package 1 compared to, for example, the case where pads provided on the upper and lower surfaces of the isolator module are connected to the semiconductor chip by bonding wires above and below the isolator module, respectively. Reliability can also be improved with such a configuration.

[0040] To elaborate, when pads provided on the upper and lower surfaces of the isolator module are connected to a semiconductor chip by bonding wires above and below the isolator module, respectively, wire bonding is performed to the upper and lower surfaces of the isolator module, which may make manufacturing difficult. Furthermore, in such cases, the isolator module may become unstable, potentially reducing the reliability of the product. According to this embodiment, the isolator module 40 is electrically connected to the semiconductor chip 20 by flip-chip bonding, making manufacturing easier. Therefore, reliability can be improved.

[0041] Furthermore, according to the embodiment, as described above, pads PLa and PLb are directly connected to coil CL, respectively. Also, pads PUa and PUb are directly connected to coil CU, respectively. With these configurations, the deterioration of the insulation withstand voltage characteristics due to vias and wiring can be suppressed.

[0042] To elaborate, if both the pad connected to the primary coil and the pad connected to the secondary coil are located at the top of the isolator module, then, as described above, the pad connected to the primary coil is positioned outside the portion containing the secondary coil and the pad connected to the secondary coil. Furthermore, for example, in a layer below the layer in which the primary coil is formed, wiring is formed extending from the central end and outer edge of the primary coil to the position of the pad. Vias are also provided to electrically connect this extending wiring to the pad located at the top of the isolator module. In such cases, the proximity of the vias and extending wiring to the coil may degrade the dielectric strength characteristics of the element. Similarly, if both the pad connected to the primary coil and the pad connected to the secondary coil are located at the bottom of the isolator module, the dielectric strength characteristics of the element may also degrade for the same reason. According to this embodiment, since vias and extending wiring are not provided, the degradation of dielectric strength characteristics can be suppressed.

[0043] 2. Variations Next, we will describe an isolator relating to a modified example. In the following, we will omit the explanation of configurations equivalent to those in the embodiment and mainly describe configurations that differ from the embodiment.

[0044] 2.1. First Variation First, the isolator according to the first modified example will be described. The first modified example differs from the embodiment in that the isolator module 40 is provided at a different position from the semiconductor chips 20 and 30 when viewed in the Z direction. The following will mainly describe the configuration that differs from the embodiment. Configurations equivalent to those in the embodiment will be omitted.

[0045] Figure 7 is a plan view showing an example of the planar layout of the isolator according to the first modified example. Figure 8 is a cross-sectional view along line VIII-VIII in Figure 7, showing an example of the cross-sectional structure of the isolator according to the first modified example. Figures 7 and 8 correspond to Figures 1 and 2 in the embodiment, respectively.

[0046] The isolator package 1 comprises frames 101, 102, 103a, and 103b, semiconductor chips 20 and 30, an isolator module 40, and an insulating member 50. Frames 101, 102, 103a, and 103b may, for example, be provided as a single integrated structure insulated from each other, although this is not shown in the figure. Note that in Figure 7, the insulating member 50 is omitted.

[0047] Frames 101, 102, 103a, and 103b are, for example, plate-shaped metal members. A semiconductor chip 20 is provided on the upper surface of frame 101 via an insulating adhesive member 11. A semiconductor chip 30 is provided on the upper surface of frame 102 via an insulating adhesive member 12. An isolator module 40 is provided on the upper surface of part 103a and part 103b via a conductive part BP. Frames 101 and 102 function as substrates supporting the semiconductor chips 20 and 30, respectively. Frames 103a and 103b function as wiring for electrically connecting the semiconductor chip 20 and the isolator module 40.

[0048] The circuit 21 of the semiconductor chip 20 is electrically connected to frames 103a and 103b via bonding wires We and Wf, respectively. In this configuration, the semiconductor chip 20 and the isolator module 40 are electrically connected by bonding wires We and Wf, and frames 103a and 103b.

[0049] Similar to the embodiment, the first modification also suppresses the complexity of the manufacturing process. Furthermore, similar to the embodiment, the increase in size can be suppressed by providing pads PLa and PLb and pads PUa and PUb below coil CL and above coil CU, respectively, configuring pads PUa and PUb to be usable as alignment patterns, and suppressing the increase in the number of windings of coils CL and CU. Also, similar to the embodiment, reliability can be improved. Furthermore, similar to the embodiment, the deterioration of dielectric strength characteristics can be suppressed.

[0050] Furthermore, according to the first modified example, the isolator module 40 is mounted on frames 103a and 103b at positions different from those of the semiconductor chips 20 and 30 when viewed in the Z direction. This allows the semiconductor chips 20 and 30 and the isolator module 40 to be mounted spaced apart from each other. This facilitates the mounting of each element during the manufacturing process. It also improves the reliability of the isolator package 1.

[0051] 2.2. Second Variation Next, the isolator relating to the second modified example will be described. The second modified example differs from the first modified example in that the semiconductor chips 20 and 30, and the isolator module 40 are provided above the semiconductor substrate. The following description will mainly focus on the configurations that differ from the first modified example. Configurations equivalent to those of the first modified example will be omitted.

[0052] Figure 9 is a plan view showing an example of the planar layout of the isolator according to the second modified example. Figure 10 is a cross-sectional view along line XX in Figure 9, showing an example of the cross-sectional structure of the isolator according to the second modified example. Figures 9 and 10 correspond to Figures 1 and 2 in the embodiment, respectively.

[0053] The isolator package 1 includes a semiconductor substrate S. The semiconductor substrate S is provided with, for example, pins 23 and 33, and wirings 60 and 61. On the semiconductor substrate S, each of the pins 23 and 33, and the wirings 60 and 61 is provided such that at least a portion of it is exposed on the upper surface of the semiconductor substrate S. The wirings 60 and 61 are for electrically connecting the semiconductor chip 20 and the isolator module 40. Each of the wirings 60 and 61 has, for example, a first portion exposed on the upper surface of the semiconductor substrate S and electrically connected to the isolator module 40, and a second portion exposed on the upper surface of the semiconductor substrate S and electrically connected to the semiconductor chip 20. Figure 10 shows the first portion 60a of the wiring 60 and the second portion 60b of the wiring 60.

[0054] On the upper surface of the semiconductor substrate S, semiconductor chips 20 and 30 and an isolator module 40 are provided via insulating adhesive members 11, 12, and 14, respectively. The isolator module 40 is electrically connected to wirings 60 and 61 via bumps BP provided between the semiconductor substrate S and the isolator module 40. The bumps BP are provided, for example, on the upper surface of the first portion 60a of wiring 60 and on the upper surface of the first portion of wiring 61. The semiconductor substrate S functions as a substrate supporting the semiconductor chips 20 and 30 and the isolator module 40.

[0055] The circuit 21 of the semiconductor chip 20 is electrically connected to the wirings 60 and 61 via bonding wires We and Wf, respectively. The bonding wires We and Wf are electrically connected to the second portion 60b of the wiring 60 and the second portion of the wiring 61, respectively. With this configuration, the semiconductor chip 20 and the isolator module 40 are electrically connected by the bonding wires We and Wf, and the wirings 60 and 61.

[0056] This configuration, like the embodiment and the first modification, can suppress the complexity of the manufacturing process. It can also suppress an increase in size, similar to the first modification. Furthermore, reliability can be improved, similar to the embodiment and the first modification. Finally, degradation of dielectric strength characteristics can be suppressed, similar to the embodiment and the first modification.

[0057] Furthermore, according to the second modification, similar to the first modification, the implementation of each element becomes easier, and reliability can be improved.

[0058] 2.3. Third Variation Next, we will describe the isolator according to the third modified example. The third modified example differs from the embodiment in that the isolator package includes two paths for transmitting signals. Below, we will mainly describe the configuration that differs from the embodiment. Configurations equivalent to those in the embodiment will be omitted as appropriate.

[0059] Figure 11 is a cross-sectional view showing an example of the cross-sectional structure of the isolator according to the third modified example. Figure 11 corresponds to Figure 1 in the embodiment. In the third modified example, the cross-sectional structure in the XZ plane can be the same as the cross-sectional structure shown in Figure 2 of the embodiment, so its explanation is omitted.

[0060] As shown in Figure 11, the isolator package 1 comprises a frame 10, semiconductor chips 20 and 30, an isolator module 40, and an insulating member 50.

[0061] Circuits 121 and 221 are formed on the semiconductor chip 20. Circuits 121 and 221 are aligned, for example, in the Y direction. Each of circuits 121 and 221 includes a signal transmission / reception circuit and a modulation / demodulation circuit. Circuits 121 and 221 are each electrically connected to the isolator module 40 via a conductive portion BP connected to the upper surface of the semiconductor chip 20. The semiconductor chip 20 is electrically connected to pin 123 via a bonding wire Wc1. This means that circuit 121 is electrically connected to pin 123 by the bonding wire Wc1. The semiconductor chip 20 is electrically connected to pin 223 via a bonding wire Wc2. This means that circuit 221 is electrically connected to pin 223 by the bonding wire Wc2.

[0062] Circuits 131 and 231 are formed on the semiconductor chip 30. Circuits 131 and 231 are aligned, for example, in the Y direction. Circuits 131 and 231 include signal transmission / reception circuits and modulation / demodulation circuits. Circuit 131 is electrically connected to the isolator module 40 via bonding wires Wa1 and Wb1. Circuit 231 is electrically connected to the isolator module 40 via bonding wires Wa2 and Wb2. The semiconductor chip 30 is electrically connected to pin 133 via bonding wire Wd1. This means that circuit 131 is electrically connected to pin 133 by bonding wire Wd1. The semiconductor chip 30 is electrically connected to pin 233 via bonding wire Wd2. This means that circuit 231 is electrically connected to pin 233 by bonding wire Wd2.

[0063] The isolator module 40 comprises isolator sections 140 and 240. The isolator sections 140 and 240 are, for example, aligned in the Y direction. The isolator module 40 is configured to transmit signals using the isolator section 140 while isolating the circuit that functions as the transmitting circuit from among circuits 121 and 131 and the circuit that functions as the receiving circuit from among circuits 121 and 131. The isolator module 40 is also configured to transmit signals using the isolator section 240 while isolating the circuit that functions as the transmitting circuit from among circuits 221 and 231 and the circuit that functions as the receiving circuit from among circuits 221 and 231. Details of the configuration of the isolator module 40 will be described later.

[0064] In the configuration described above, the circuit 121 of semiconductor chip 20, the circuit 131 of semiconductor chip 30, and the isolator portion 140 of isolator module 40 constitute channel Ch1 within the isolator package 1. In addition, the circuit 221 of semiconductor chip 20, the circuit 231 of semiconductor chip 30, and the isolator portion 240 of isolator module 40 constitute channel Ch2 within the isolator package 1.

[0065] In the above explanation, the cases in which circuits 121, 131, 221, and 231 all include transmitting and receiving circuits have been shown, but the explanation is not limited to this. For example, one of circuits 121 and 131 may be a circuit that includes a transmitting or receiving circuit, and the other of circuits 121 and 131 may be a circuit that includes a receiving or transmitting circuit. Also, for example, one of circuits 221 and 231 may be a circuit that includes a transmitting or receiving circuit, and the other of circuits 221 and 231 may be a circuit that includes a receiving or transmitting circuit. In other words, channels Ch1 and Ch2 may each be channels that transmit signals in only one direction.

[0066] Next, the configuration of the isolator module 40 will be described. Figure 12 is a perspective view showing an example of the structure of the isolator module according to the third modified example. Figure 13 is a perspective view showing an example of the structure of the primary circuit of the isolator module according to the third modified example. Figure 14 is a perspective view showing an example of the structure of the secondary circuit of the isolator module according to the third modified example. Note that in Figures 12, 13, and 14, the conductive members within the wiring board 41 are shown as being seen through the insulating members covering the conductive members.

[0067] The wiring board 41 is provided with conductive pads PLa1, PLb1, PUa1, PUb1, PLa2, PLb2, PUa2, and PUb2, dummy pads Pdm1 and Pdm2, and coils CL1, CU1, CL2, and CU2. Pads PLa1, PLb1, PUa1, and PUb1, and dummy pad Pdm1 are included in the isolator portion 140. Pads PLa2, PLb2, PUa2, and PUb2, and dummy pad Pdm2 are included in the isolator portion 240.

[0068] The cross-sectional structure in the XZ section including pad PUb1 and the cross-sectional structure in the XZ section including pad PUb2 can be the same as the cross-sectional structure of the wiring board 41 shown in Figure 6 of the embodiment.

[0069] In the isolator portion 140, pads PLa1 and PLb1 are provided within the insulating layer 412, similar to pads PLa and PLb in the embodiment. Of the insulating layer 411 below the insulating layer 412, the portion that overlaps with pads PLa1 and PLb1 when viewed in the Z direction is removed. The lower surface of each pad PLa1 and PLb1 is electrically connected to the circuit 121 of the semiconductor chip 20 via the conductor portion BP corresponding to the pad. The shape of each pad PLa1 and PLb1 is similar to, for example, the shape of pads PLa and PLb in the embodiment.

[0070] Furthermore, the dummy pad Pdm1 is provided within the insulating layer 412, similar to the dummy pad Pdm in the embodiment. The dummy pad Pdm1 and pad PLa1 are positioned point-symmetrically with respect to PLb1, for example, when viewed in the Z direction. The sizes of the dummy pad Pdm1 and pads PLa1 and PLb1 are, for example, equivalent. In the example shown in Figure 12, the isolator portion 140 is shown to include one dummy pad Pdm1, but it is not limited to this. The dummy pad Pdm1 may not be included, or two or more may be included within the insulating layer 412.

[0071] Coil CL1 is provided such that its upper and lower surfaces are at the same height as the upper and lower surfaces of coil CL in the embodiment. Coil CL1 is made of copper, for example. The outer peripheral end of coil CL1 is electrically connected to pad PLa1. The central end of coil CL1 is electrically connected to pad PLb1. With this configuration, a current path is formed between the conductive portion BP connected to pad PLa1 and the conductive portion BP connected to pad PLb1. In the isolator portion 140, coil CL1 is also called the primary coil.

[0072] Pads PUa1 and PUb1 are provided within the insulating layer 416, similar to pads PUa and PUb in the embodiment. The portion of the insulating layer 417 above the insulating layer 416 that overlaps with pads PUa1 and PUb1 when viewed in the Z direction is removed. Bonding wires Wa1 and Wb1 are electrically connected to pads PUa1 and PUb1, respectively. The shapes of pads PUa1 and PUb1 are similar to, for example, the shapes of pads PUa and PUb in the embodiment.

[0073] Furthermore, pad PUa1 is positioned so that, when viewed in the Z direction, it overlaps with, for example, pad PLa1. Similarly, pad PUb1 is positioned so that, when viewed in the Z direction, it overlaps with, for example, pad PLb1.

[0074] Coil CU1 is provided such that its upper and lower surfaces are at the same height as the upper and lower surfaces of coil CU in the embodiment. Coil CU1 is made of, for example, copper. The outer peripheral end of coil CU1 is electrically connected to pad PUa1. The central end of coil CU1 is electrically connected to pad PUb1. With this configuration, a current path is formed between bonding wire Wa1 and bonding wire Wb1. In the isolator portion 140, coil CU1 is also called a secondary coil.

[0075] Coils CL1 and CU1 are arranged opposite each other, separated in the Z direction. This allows coils CL1 and CU1 to function as a transformer.

[0076] The isolator section 240 can have a structure substantially equivalent to that of the isolator section 140. That is, in the isolator section 240, the pads PUa2, PUb2, PLa2, and PLb2, the dummy pad Pdm2, and the coils CU2 and CL2 are provided in the same way as the pads PUa1, PUb1, PLa1, and PLb1, the dummy pad Pdm1, and the coils CU1 and CL1 in the isolator section 140, except that their positions in the XY plane are different. Bonding wires Wa2 and Wb2 are electrically connected to pads PUa2 and PUb2, respectively.

[0077] In the examples shown in Figures 12, 13, and 14, the structures of the isolator portion 140 and the isolator portion 240 are shown to be similar, but this is not the only case. For example, the isolator portion 140 and the isolator portion 240 may be arranged symmetrically with respect to the XZ plane.

[0078] Furthermore, while the third modification shows a case where the isolator package 1 includes two channels, Ch1 and Ch2, it is not limited to this. The number of channels included in the isolator package 1 may be more than two.

[0079] This configuration, like the embodiment, the first modification, and the second modification, can suppress the complexity of the manufacturing process. Furthermore, the third modification, like the embodiment, can suppress an increase in size. Also, like the embodiment, the first modification, and the second modification, reliability can be improved. Furthermore, like the embodiment, the first modification, and the second modification, deterioration of the dielectric strength characteristics can be suppressed.

[0080] Furthermore, according to the third modification, the isolator package 1 includes multiple channels. This makes it possible to suppress the increase in size compared to the case where multiple channels are configured using multiple isolator packages, each having a single channel.

[0081] 2.4. Fourth Variation Next, the isolator according to the fourth modified example will be described. The fourth modified example differs from the embodiment in that, when viewed in the Z direction, the pad PUa and the dummy pad Pdm of the isolator module 40 are located at overlapping positions. Below, the configurations that differ from the embodiment will be mainly described. Configurations equivalent to those in the embodiment will be omitted as appropriate.

[0082] Figure 15 is a perspective view showing an example of the structure of an isolator module according to the fourth modified example. Figure 16 is a perspective view showing an example of the structure of the primary circuit of the isolator module according to the fourth modified example. Figure 17 is a perspective view showing an example of the structure of the secondary circuit of the isolator module according to the fourth modified example. Note that in Figures 15, 16, and 17, the conductive members within the wiring board 41 are shown as being seen through the insulating members covering the conductive members.

[0083] In the fourth modified example, pads PLa and PUa are positioned at different locations relative to each other when viewed in the Z direction. As a result, pads PUa and PLa do not overlap, for example, when viewed in the Z direction.

[0084] The dummy pad Pdm is positioned so that it overlaps with pad PUa when viewed in the Z direction.

[0085] This configuration, like the embodiment, the first modification, the second modification, and the third modification, can suppress the complexity of the manufacturing process. Furthermore, like the embodiment and the third modification, it can suppress an increase in size. Also, like the embodiment, the first modification, the second modification, and the third modification, it can improve reliability. Furthermore, like the embodiment, the first modification, the second modification, and the third modification, it can suppress the deterioration of the dielectric strength characteristics.

[0086] Furthermore, according to the fourth modification, even if the positions of pads PLa and PUa are different, by positioning the dummy pad Pdm in a position that overlaps with pad PUa when viewed in the Z direction, a decrease in the rigidity of the portion forming the bonding wire Wa can be suppressed. As a result, the bonding wire Wa can be formed with high precision. In addition, the reliability of the isolator package 1 can be improved.

[0087] 3. Others While several embodiments of the present invention have been described, these embodiments are presented as examples only and are not intended to limit the scope of the invention. These embodiments can be carried out in a variety of other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included in the scope and spirit of the invention, as well as in the claims and their equivalents. [Explanation of Symbols]

[0088] 1…Isolator package 10, 101, 102, 103a, 103b…frames 11, 12, 13, 14… Adhesive components 20, 30... Semiconductor chips 21, 31, 121, 131, 221, 231… circuits Wa, Wb, Wc, Wd, We, Wf, Wa1, Wb1, Wa2, Wb2… Bonding wires 23, 33, 123, 133, 223, 233… pin 40…Isolator Module 41...Wiring board 50…Insulating material PLa, PLb, PUa, PUb, PLa1, PLb1, PUa1, PUb1, PLa2, PLb2, PUa2, PUb2... pads Pdm, Pdm1, Pdm2… Dummy pads 411, 412, 413, 414, 415, 416, 417… Insulating layer BP...Conductor part S... Semiconductor substrate

Claims

1. An isolator module comprising a first substrate, a first insulating layer in contact with the upper surface of the first substrate, a second insulating layer in contact with the lower surface of the first substrate, a first coil included in the same layer as the first insulating layer, and a second coil provided opposite the first coil and included in the same layer as the second insulating layer, A first conductor portion is provided below the isolator module and electrically connected to the lower surface of the second coil, The first chip and, Equipped with, The second coil and the upper surface of the first chip are electrically connected via the first conductor portion. Isolator.

2. The first chip is provided below the first conductor portion, The first conductor portion is in contact with the upper surface of the first chip, The isolator according to claim 1.

3. The first wiring provided below the first conductor portion, Furthermore, The first conductor portion is in contact with the upper surface of the first wiring, The isolator according to claim 1.

4. The first chip and the first wiring are electrically connected via a wire. The isolator according to claim 3.

5. Furthermore, equipped with a second chip, The first coil and the second chip are electrically connected via a wire. The isolator according to claim 1.

6. At one end of the second coil, a first pad is in contact with the lower surface of the second coil. Furthermore, The first conductor portion is in contact with the lower surface of the first pad, The isolator according to claim 1.

7. A dummy pad, which is contained in the same layer as the first pad and electrically insulated from the second coil, Furthermore, The isolator according to claim 6.

8. Within the first insulating layer, a third coil is provided spaced apart from the first coil, Within the second insulating layer, a fourth coil is provided so as to face the third coil and spaced apart from the second coil, A second conductor portion is provided below the isolator module and electrically connected to the lower surface of the fourth coil, Equipped with, The fourth coil and the upper surface of the first chip are electrically connected via the second conductor portion. The isolator according to claim 1.

9. The first conductor portion is formed by bumps or soldering. The isolator according to claim 1.

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