Packaging structure and method for memory systems

Abstract

The present disclosure provides a packaging structure and a manufacturing method for a memory system. The packaging structure for the memory system includes a memory module, a memory controller, a redistribution layer electrically connected to the memory controller, a plastic encapsulation layer that encapsulates the memory module and the memory controller, and one or more connection pillars extending vertically and configured to supply power to the memory module. Each memory module includes vertically stacked memory dies. Each connection pillar includes a first portion in physical contact with one of the memory dies and a second portion in physical contact with the redistribution layer.

Description

Technical Field

[0001] [Cross - Reference to Related Applications] This application claims the benefit of priority of Chinese Application No. 202111630406.4, filed on December 28, 2021, the content of which is hereby incorporated by reference in its entirety into this specification.

[0002] The present disclosure relates to semiconductor storage, and more particularly, to a packaging structure of a memory system and a method for manufacturing the same.

Background Art

[0003] A memory system mainly includes a memory die and a memory controller. In some examples, the memory system can include a solid - state drive (SSD), etc. The packaging structure of the memory system is to enclose the memory die and the memory controller with a housing, which not only serves to mount, fix, seal, and protect the memory die and the memory controller, but also enhances the electrical and thermal performance. Through the bond pads on the memory die and the lead - out pads of the memory controller, the memory die and the memory controller are wired to the pins of the packaging housing. These pins are connected to other devices via wires on a circuit board, thereby connecting the memory system to an external circuit. The packaging quality of the memory system directly affects the performance of the memory system and also affects the design and manufacture of the circuit board to which the memory system is connected. Therefore, the packaging of the memory system is very important.

[0004] However, there are many problems in the conventional packaging of memory systems. It is urgent to develop a new packaging structure and manufacturing method for memory systems.

Summary of the Invention

[0005] In one embodiment, the packaging structure of the memory system includes a memory module having memory dies stacked vertically, a memory controller, a redistribution layer having a first surface electrically connected to the memory controller, a plastic encapsulation layer sealing the memory module, the memory controller, and the redistribution layer, and one or more connection pillars extending vertically and configured to supply power to the memory module, each connection pillar including a first portion that is in physical contact with one of the memory dies and a second portion that is in physical contact with the redistribution layer.

[0006] In some implementations, the memory module includes a first memory module and a second memory module, with the first and second memory modules positioned on either side of the memory controller, respectively.

[0007] In some implementations, the first memory module has a first distance from the memory controller, the second memory module has a second distance from the memory controller, and the first distance is the same as the second distance.

[0008] In some implementations, the first memory module, the second memory module, and the memory controller are arranged in a straight line such that the memory controller is located between the first and second memory modules.

[0009] In some implementation configurations, the edges of two adjacent dies in a stacked die are offset such that the upper die of two adjacent dies has an extension that extends beyond the lower die of the two adjacent dies, the lower die of the two adjacent dies has an uncoated portion that extends beyond the upper die of the two adjacent dies, and the uncoated portion of the lower die of the two adjacent dies includes a bonding pad.

[0010] In some implementations, the first memory module includes a first memory die that is offset by a third distance in the first direction, and the second memory module includes a second memory die that is offset by a fourth distance in the second direction, where the third distance is equal to the fourth distance.

[0011] In some implementations, both the first and second memory dies are stacked vertically, with both the first and second directions being perpendicular to the vertical, and the first direction being opposite to the second direction.

[0012] In some implementations, the first number on the first memory die is equal to the second number on the second memory die.

[0013] In some implementations, one connection pillar in the first memory module is physically attached to one bonding pad of a first subset of the first memory die, a second subset of the memory die of the first memory die is connected by bonding wires to a first portion of the connection pillar in the first memory module, one connection pillar in the second memory module is physically attached to one bonding pad of a second subset of the second memory die, and a second subset of the memory die of the second memory die is connected by bonding wires to a first portion of the connection pillar in the second memory module.

[0014] In some implementations, each connection pillar in the first memory module is physically attached to each bonding pad of the first memory die, and each connection pillar in the second memory module is physically attached to each bonding pad of the second memory die.

[0015] In some implementations, one or more connecting pillars include one or more copper pillars.

[0016] In some implementations, the packaging structure of the memory system includes metal solder balls located on the second surface of a redistribution layer, which are electrically connected to one or more memory modules and memory controllers via the redistribution layer, with the second and first surfaces facing opposite each other.

[0017] In some implementations, the packaging structure of the memory system includes at least one passive device sealed in a plastic encapsulation layer. The at least one passive device is located on a first surface of a redistribution layer and is electrically connected to the redistribution layer.

[0018] In some implementations, the first and second memory dies include 3D NAND flash memory dies.

[0019] In another embodiment, the packaging structure of the memory system includes a memory module having vertically stacked memory dies, a memory controller, a redistribution layer having a first surface electrically connected to the memory controller, a plastic encapsulation layer sealing the memory module, memory controller, and redistribution, and one or more connection pillars extending vertically and configured to supply power to the memory module. Each connection pillar includes a first portion that is in physical contact with one of the memory dies and a second portion that is in physical contact with the redistribution layer.

[0020] In some implementation configurations, the edges of two adjacent dies in a stacked die are offset such that the upper die of two adjacent dies has an extension that extends beyond the lower die of the two adjacent dies, the lower die of the two adjacent dies has an uncoated portion that extends beyond the upper die of the two adjacent dies, and the uncoated portion of the lower die of the two adjacent dies includes a bonding pad.

[0021] In some implementations, one connection pillar within the memory module is physically attached to one bonding pad among a first subset of memory dies, and a second subset of the memory dies is connected by bonding wires to a first portion of one connection pillar within the memory module.

[0022] In some implementations, at least two connection pillars within the memory module are physically attached to two bonding pads among two of a first subset of memory dies respectively, and a second subset of the memory dies is connected by bonding wires to a first portion of two connection pillars within the memory module.

[0023] In some implementations, each connection pillar within the memory module is physically attached to the bonding pad of each memory die respectively.

[0024] In some implementations, one or more connection pillars comprise one or more copper pillars.

[0025] In some implementations, the packaging structure of the memory system includes metal solder balls located on a second surface of the redistribution layer. The metal solder balls are electrically connected to the memory module and the memory controller via redistribution, and the second surface and the first surface are on opposite sides of each other.

[0026] In some implementations, the packaging structure of the memory system includes at least one passive device encapsulated by a plastic encapsulation layer. The at least one passive device is disposed on a first surface of the redistribution layer and is electrically connected to the redistribution layer.

[0027] In some implementations, the memory die includes a 3D NAND flash memory die.

[0028] In yet another aspect, a method for packaging a memory system includes the following operations. A step of providing one or more memory modules, each memory module having memory dies stacked vertically and one or more connection pillars configured to supply power to the one or more memory modules, the step including providing a memory controller having lead-out pads, and a step of mounting the one or more memory modules and the memory controller on a first surface of a redistribution layer, the redistribution layer being configured to electrically connect the one or more connection pillars of the one or more memory modules to the lead-out pads of the memory controller, and a step of forming a plastic encapsulation layer to encapsulate the one or more memory modules, the memory controller, the redistribution layer, and the one or more connection pillars.

[0029] In some implementations, the step of mounting the one or more memory modules and the memory controller on the redistribution layer includes physically connecting a first portion of each connection pillar to one of the memory dies and physically connecting a second portion of each connection pillar to the redistribution layer.

[0030] In some implementations, the step of providing one or more modules includes providing a first carrier, sequentially stacking the memory dies on the first carrier with a misalignment such that the bonding pads of each memory die are not covered, forming one or more connection pillars on one or more bonding pads of the memory dies, a first portion of the one or more connection pillars being in physical contact with the corresponding one or more bonding pads, forming a molding layer to encapsulate the memory dies and the connection pillars, removing the first carrier, and removing a portion of the molding layer to expose a second portion of the one or more connection pillars.

[0031] In some implementations, providing one or more modules involves the steps of: providing a first carrier; sequentially stacking a first memory die and a second memory die on the first carrier, wherein the first memory die and the second memory die are arranged in parallel on the first carrier; forming one or more first connection pillars on one or more bonding pads of the first memory die, wherein a first portion of one or more first connection pillars is in physical contact with one or more corresponding bonding pads of the first memory die; and forming one or more second connection pillars on one or more bonding pads of the second memory die, wherein a first portion of one or more second connection pillars is in physical contact with one or more second connection pillars. The process includes the steps of: a portion of a first memory die being in physical contact with one or more corresponding bonding pads of a second memory die; forming a molded layer that seals the first memory die, the second memory die, one or more first connecting pillars, and one or more second connecting pillars; removing the first carrier; removing a portion of the molded layer to expose the second portions of one or more first and second connecting pillars; and cutting the molded layer to obtain a first memory module and a second memory module, wherein the first memory module comprises a first memory die and one or more first connecting pillars, and the second memory module comprises a second memory die and one or more second connecting pillars.

[0032] In some implementation configurations, the step of providing one or more memory modules includes having an extension portion that extends beyond the lower die of two adjacent dies, the lower die of two adjacent dies having an uncovered portion that extends beyond the upper die of two adjacent dies, and the upper die of two adjacent dies being offset from the edges of two adjacent dies of the memory die such that the bonding pads of each die are located on the uncovered portion of the lower die of two adjacent dies.

[0033] In some implementations, the method further includes the steps of shifting the edges of two adjacent dies by a third distance in a first direction, and shifting a second memory die by a fourth distance in a second direction. The first and second directions are opposite directions, both are perpendicular to the vertical direction, and the third distance is equal to the fourth distance.

[0034] In some implementation configurations, the step of forming a plastic encapsulation layer includes the steps of providing a second carrier, mounting one or more memory modules and a memory controller on the second carrier, wherein the second portion of one or more connection pillars in one or more memory modules is on the same surface as the pull-out pad of the memory controller and the second carrier, forming a plastic encapsulation layer to encapsulate the one or more memory modules and the memory controller, and removing the second carrier.

[0035] In some implementations, the step of installing one or more memory modules and memory controllers includes aligning the first memory module, the second memory module, and the memory controller in a straight line such that the memory controller is positioned between the first memory module and the second memory module.

[0036] In some implementations, the method further includes the step of forming metal solder balls on a second surface of the redistribution layer. The metal solder balls are electrically connected via the redistribution layer to one or more memory modules and memory controllers located on a first surface of the redistribution layer, with the second surface and the first surface being opposite to each other.

[0037] The accompanying drawings incorporated herein and forming part thereof illustrate aspects of the disclosure and, together with the description, further illustrate the disclosure and enable those skilled in the art to prepare and use the disclosure. [Brief explanation of the drawing]

[0038] [Figure 1A] This is a schematic diagram of the packaging structure of a memory system using a wire bonding process. [Figure 1B] This is a schematic diagram of the packaging structure of a memory system using the TSV process. [Figure 1C] This is a schematic diagram of the fan-out packaging structure of a memory system provided by one implementation of this disclosure. [Figure 1D] This is a schematic diagram of each layer of the fan-out packaging structure of a memory system according to one implementation of this disclosure. [Figure 2] This is a schematic flowchart of a method for manufacturing a packaging structure for a memory system according to one implementation of the present disclosure. [Figure 3A] This is a schematic diagram illustrating the operation of a method for manufacturing a packaging structure for a memory system according to one implementation of the present disclosure. [Figure 3B] This is a schematic diagram illustrating the operation of a method for manufacturing a packaging structure for a memory system according to one implementation of the present disclosure. [Figure 3C] This is a schematic diagram illustrating the operation of a method for manufacturing a packaging structure for a memory system according to one implementation of the present disclosure. [Figure 3D] This is a schematic diagram illustrating the operation of a method for manufacturing a packaging structure for a memory system according to one implementation of the present disclosure. [Figure 3E] This is a schematic diagram illustrating the operation of a method for manufacturing a packaging structure for a memory system according to one implementation of the present disclosure. [Figure 3F] This is a schematic diagram illustrating the operation of a method for manufacturing a packaging structure for a memory system according to one implementation of the present disclosure. [Figure 3G] This is a schematic diagram illustrating the operation of a method for manufacturing a packaging structure for a memory system according to one implementation of the present disclosure. [Figure 3H] This is a schematic diagram illustrating the operation of a method for manufacturing a packaging structure for a memory system according to one implementation of the present disclosure. [Figure 3I]This is a schematic diagram illustrating the operation of a method for manufacturing a packaging structure for a memory system according to one implementation of the present disclosure. [Figure 3J] This is a schematic diagram illustrating the operation of a method for manufacturing a packaging structure for a memory system according to one implementation of the present disclosure. [Figure 3K] This is a schematic diagram illustrating the operation of a method for manufacturing a packaging structure for a memory system according to one implementation of the present disclosure. [Figure 3L] This is a schematic diagram illustrating the operation of a method for manufacturing a packaging structure for a memory system according to one implementation of the present disclosure. [Figure 4A] This is a schematic cross-sectional view of the packaging structure of a memory system according to one implementation of the present disclosure. [Figure 4B] This is a schematic top view of the packaging structure of a memory system according to one implementation of the present disclosure. [Figure 5A] This is a schematic cross-sectional view of the packaging structure of a memory system according to one implementation of the present disclosure. [Figure 5B] This is a schematic cross-sectional view of the packaging structure of a memory system according to one implementation of the present disclosure. [Figure 6A] This is a schematic cross-sectional view of the packaging structure of another memory system according to one implementation of the present disclosure. [Figure 6B] This is a schematic cross-sectional view of a packaging structure of yet another memory system according to one implementation of the present disclosure. [Figure 6C] This is a schematic cross-sectional view of a packaging structure of yet another memory system according to one implementation of the present disclosure. [Modes for carrying out the invention]

[0039] While specific configurations and arrangements are described, it should be understood that these are for illustrative purposes only. Therefore, other configurations and arrangements may be used without departing from the scope of this disclosure. Furthermore, this disclosure can be used for a variety of other applications. The functional and structural features described in this disclosure may be combined, adjusted, and modified with respect to each other and in ways not specifically shown in the drawings, so that these combinations, adjustments, and modifications remain within the scope of this disclosure.

[0040] In general, technical terms can be understood at least partially from their use in context. For example, the term “one or more” as used herein may, at least partially depending on the context, be used to describe any feature, structure, or characteristic in a singular sense, or to describe a combination of features, structures, or characteristics in a plural sense. Similarly, terms such as “a,” “an,” or “the” may, at least partially depending on the context, be understood to convey either a singular or plural usage. Furthermore, the term “based on” may be understood not necessarily to convey an exclusive set of factors, but rather, at least partially depending on the context, may allow for the presence of additional factors that are not necessarily explicitly stated.

[0041] The meanings of “on,” “above,” and “over” in this disclosure should be interpreted in the broadest sense, so that it should be easily understood that “on” means not only “directly on” something, but also “on” something with an intermediate feature or layer between them, and that “above” or “over” means not only “above” or “over” something, but can also mean “above” or “over” something (i.e., directly on something) without an intermediate feature or layer between them.

[0042] Furthermore, spatially relative terms such as “beneath,” “below,” “lower,” “above,” and “upper” may be used herein to facilitate the description of the relative relationship between one element or feature and another, as shown in the figures. These spatially relative terms are intended to encompass different orientations of the device in use or operation, in addition to the orientation shown in the figures. The device may be oriented in other directions (it may be rotated 90 degrees or in other directions), and the spatially relative descriptors used herein may be interpreted accordingly.

[0043] As used herein, “bond pad” is a general term referring to an electrical bonding pad associated with a test point or external electrical connection in an integrated electronic device such as an integrated circuit (IC) or micro-electro-mechanical system (Micro-Electro-Mechanical System) device. Related industry terms are “bonding pad” and “bump.” As used herein, “solder bump” or “solder ball” is a general term referring to a solder ball bonded to a bond pad for further assembly of a die into a package using surface mount technology or wire bonding.

[0044] As used herein, the term “die” generally refers to a small piece of semiconductor wafer that has been diced and processed into a portion containing an integrated circuit or other device. The term “die stack” generally refers to a vertical assembly of two or more dies containing an integrated circuit interconnected to function as a unit.

[0045] As used herein, the term “substrate” refers to the material upon which subsequent material layers are added. The substrate itself may be patterned. The material added to the top of the substrate may be patterned or left unpatterned. Furthermore, the substrate may include a wide range of semiconductor materials such as silicon, germanium, gallium arsenide, and indium phosphide. Alternatively, the substrate may be made from non-conductive materials such as glass, plastic, or sapphire wafers.

[0046] As used herein, the term “layer” refers to a portion of a material that includes a region having thickness. A layer may extend over the entire substructure or superstructure, or it may have a smaller extent than the substructure or superstructure. Furthermore, a layer may be a region of a uniform continuous structure, or a region of a non-uniform continuous structure having a thickness less than the thickness of the continuous structure. For example, a layer may be located in any pair of horizontal planes between continuous structures, on the top and bottom surfaces of a continuous structure. A layer may extend horizontally, vertically, and / or along a tapered surface. A substrate may be a single layer, which may contain one or more layers, and / or have one or more layers on top of, above, and / or below it. A layer may include multiple layers. For example, an interconnection layer may include one or more conductor and contact layers (on which interconnection lines and / or via contacts are formed) and one or more dielectric layers.

[0047] As used herein, the term “nominal / nominally” refers to a desired or target value of a component or process behavior characteristic or parameter, set during the design phase of a product or process, along with a range of values ​​above and / or below the desired value. The range of values ​​may be due to slight variations in the manufacturing process or tolerances. As used herein, the term “about” indicates a value of a given quantity that may vary based on a specific technology node related to the semiconductor device in question. Based on a specific technology node, the term “about” may indicate a value of a given quantity that varies, for example, within a range of 10 to 30% of the value (e.g., ±10%, ±20%, or ±30% of the value).

[0048] As used herein, the term "connected" refers to a direct connection, such as an electrical or mechanical connection, between connected things without an intermediate device.

[0049] As used herein, the term “circuit” can refer to one or more passive and / or active components configured to work together to provide a desired function. The term “IC” is a microelectronic circuit monolithically fabricated on a semiconductor wafer substrate by a microfabrication method.

[0050] As used herein, the term “edge misaligned” generally refers to a stack of dies having one or more edges that are misaligned horizontally or laterally from one another.

[0051] As used herein, the term “top surface” refers to the surface of the structure furthest from the substrate on which the structure is formed on top / inside, and the term “bottom surface” refers to the surface of the structure closest to the substrate on which the structure is formed on top / inside. In this disclosure, the relative positions of the top surface and bottom surface do not change even if the orientation of the object changes.

[0052] In this disclosure, the height of an object's surface is defined as the distance between the surface on which the object is formed and the substrate. In this disclosure, the relative position of two surfaces is defined based on the heights of the two surfaces and does not change as the orientation of the object changes.

[0053] As used herein, the terms “stair,” “step,” and “level” are interchangeable. As used herein, a staircase structure refers to a set of surfaces comprising at least two horizontal planes and at least two vertical planes such that each horizontal plane is adjacent to a first vertical plane extending upward from a first edge of the horizontal plane and to a second vertical plane extending downward from a second edge of the horizontal plane. “Stair” refers to a vertical shift in height of a set of adjacent surfaces. “Staircase structure” refers to a structure having multiple steps extending vertically.

[0054] As used herein, terms such as “first,” “second,” etc., are used to distinguish similar subjects and are not necessarily used to describe a specific order or sequence.

[0055] It should be noted that the technical solutions described in the implementations of this disclosure can be combined in any way, provided they do not conflict.

[0056] Conventionally, memory die packaging generally uses wire bonding (WB) and through-silicon via (TSV) processes. As shown in Figure 1A, the wire bonding process includes the steps of joining memory dies 101 using an adhesive layer 102 and forming wire loops 103 on the surface of the memory dies. The TSV process shown in Figure 1B includes forming multiple through-silicon vias within a stack of multiple memory dies. However, conventional memory system packaging has the following problems: 1) The wire bonding process increases the overall area of ​​the package structure by more than 20% due to the presence of bent wires between the pads and the substrate. 2) The wire bonding process has long conductive paths, which limits the high-frequency performance of the memory die. 3) During the wire bonding process, the curved portion of the wire occupies a certain height in the package, which affects the design of the package structure. 4) The wire bonding process is time-consuming (also called manufacturing time) and requires a wire bonding machine. 5) Semiconductor substrates (SBTs) require ultra-small line / space manufacturing, and costs increase exponentially with decreasing line / space size. 6) Holes must be drilled during the SBT manufacturing process, and these holes are not filled with metal in subsequent manufacturing processes, which increases resistance and affects the high-frequency performance of the product. 7) The TSV process requires coordination between chip design and chip packaging, which is technically difficult and costly.

[0057] In recent years, the emergence of fan-out packaging structures for memory dies and the development of packaging materials have accelerated the development of memory die packaging. Figure 1C is a schematic diagram of a fan-out package structure for memory dies. Figure 1D is a schematic diagram of each layer of the fan-out package structure for memory dies. As shown in Figures 1C and 1D, the manufacturing method of a fan-out package structure for memory dies generally includes the following steps: providing a substrate 110; forming an adhesive layer 111 on the substrate; photolithography and electroplating the adhesive layer 111 to form a redistribution layer (RDL) 113; mounting a memory die 112 on the RDL 113 by a bonding process; sealing the memory die in a layer of plastic encapsulating material by an injection molding process; removing the substrate and adhesive layer; photolithography and electroplating the RDL to form an underbump metal layer (UBM) 114; and forming metal solder balls on the UBM.

[0058] Fan-out packaging structures for memory dies can effectively save packaging space. At the same time, fan-out packaging structures allow for packaging with better heat dissipation and higher performance, such as higher frequencies. However, current fan-out packaging structures generally do not support System-in-a-Package (SIP) packaging of stacked memory dies, i.e., the packaging of memory systems. Conventional memory system packaging is complex.

[0059] The packaging structure of the memory system provided by the implementation of this disclosure uses a memory module to obtain a SIP fan-out structure. The memory module is electrically connected to the RDL by physically contacting it via connecting pillars, and the memory controller is located on the first face of the RDL and electrically connected to the RDL. Because both the memory module and the memory controller are located on the first face of the RDL and electrically connected to the RDL, the overall line distance can be reduced by more than 40%, thereby shortening the signal transmission path between the memory module, memory controller and external devices, and thus the resulting memory system packaging structure has better high-frequency performance. The memory controller does not require wire bonding, which simplifies the packaging process of the memory system and saves costs. By using Cu pillars instead of gold wires, costs can be further reduced and parasitic resistance and inductance can be reduced. Processing copper pillars is much easier than wire bonding, which can shorten the manufacturing cycle.

[0060] The implementation of this disclosure provides a method for manufacturing a memory system packaging structure. Figure 2 is a schematic flowchart of the method for manufacturing a memory system packaging structure. As shown in Figure 2, the method includes the following operations.

[0061] Operation 201: A step of providing one or more memory modules and a memory controller, each of the one or more memory modules comprising a plurality of stacked memory dies, and the memory controller having a pull-out pad. A step of forming one or more connection pillars, each of the one or more connection pillars having a first portion positioned on a bonding pad of one of the stacked memory dies and electrically in contact with the bonding pad of one of the stacked memory dies. A step of forming a molded layer that seals the plurality of memory dies and connection pillars.

[0062] Operation 202: A step of sealing one or more memory modules and memory controllers within a plastic encapsulation layer, wherein the first portion of each connecting pillar extends through the molded layer such that the second portion of each connecting pillar and the pull-out pad of the memory controller are exposed on the same surface of the plastic encapsulation layer.

[0063] Operation 203: A step of forming an RDL on the same surface of a plastic encapsulation layer, wherein the second portion of each connecting pillar and the pull-out pad of the memory controller are both positioned on the first surface of the RDL and electrically connected to the RDL.

[0064] Figures 3A to 3L are schematic cross-sectional views of the operation of a method for manufacturing a packaging structure for a memory system according to one implementation of the present disclosure. It should be understood that the operation shown in Figure 2 is not exclusive, and other operations may be performed before, after, or between any of the operations. Next, the method for manufacturing a packaging structure for a memory system will be described with reference to Figures 2 and 3A to 3L.

[0065] As shown in Figure 3F, one or more memory modules 30 are provided. Each of the one or more memory modules 30 includes a plurality of stacked memory dies 302, a molding layer 304 that seals the plurality of stacked memory dies 302, and at least one connecting pillar 303 that extends from one of the plurality of stacked memory dies 302 through the molding layer 304. The surface of each stacked memory die 302 is provided with at least one bonding pad 305 that is not covered by an adjacent memory die 302. A first portion 303-1 of each connecting pillar 303 is positioned in electrical contact with at least one bonding pad 305 of the stacked memory die 302, and a second portion 303-2 is exposed on the surface of the molding layer 304.

[0066] In some implementation configurations, the multiple stacked memory dies 302 may include, but are not limited to, NAND flash memory dies. The sides and bottom of each stacked memory die 302 include an insulating layer to insulate the memory dies 302 from each other. The material of the molding layer 304 may include an epoxy molding compound (EMC). The connecting pillars 303 are perpendicular to the surface of the stacked memory die 302 and may include at least one conductive material such as copper, gold, aluminum, silver, and / or other suitable metallic materials.

[0067] In some implementation configurations, each of the memory modules 30 includes multiple stacked memory dies 302, and the electrical connections differ between the multiple stacked memory dies 302 and the connection pillars 303.

[0068] In some implementation configurations, each memory module 30 includes one connection pillar 303 connected to a bonding pad 305 of one of the stacked memory dies 302, and the other stacked memory dies 302 are electrically connected to the connection pillar 303 via bonding wires.

[0069] In some implementation configurations, if each of the memory modules 30 includes multiple connection pillars 303, the electrical connections differ between the multiple stacked memory dies 302 and the multiple connection pillars 303.

[0070] In some implementation configurations, each memory module 30 includes a plurality of connection pillars 303, each of which is bonded to a plurality of bonding pads on a stacked memory die 302, and the other stacked memory die 302 is electrically connected to the plurality of connection pillars 303 via bonding wires.

[0071] In some implementation configurations, each of the memory modules 30 includes a plurality of connection pillars 303. For each die of the stacked memory die 302, each of the plurality of connection pillars 303 is electrically in contact with a corresponding bonding pad of the stacked memory die 302.

[0072] In some implementation configurations, the step of providing one or more memory modules includes the steps of providing a first carrier 301, sequentially stacking a plurality of memory dies 302 in an offset state so that the bonding pads of each memory die are not covered on the first carrier 301, forming one or more connection pillars 303 having a first portion electrically connected to a bonding pad 305 on at least one of the plurality of memory dies 302, forming a molded layer 304 that seals the plurality of stacked memory dies 302 and the connection pillars 303, removing the first carrier 301, and removing the partial molded layer 304, thereby exposing a second portion 303-2 of one or more connection pillars 303.

[0073] In some implementations, a first carrier 301 is provided, as shown in Figure 3A. In some implementations, the first carrier 301 further includes a temporary bonding film.

[0074] As shown in Figure 3B, a plurality of memory dies 302 are sequentially stacked vertically on the first carrier 301, and one or more bonding pads 305 are provided on the surface of each memory die 302 that are not covered by adjacent memory dies 302.

[0075] In some implementation configurations, the front surfaces of multiple stacked memory dies 302 are bonded to a temporary bonding film of the first carrier 301. The front surface of each memory die 302 is the surface on which one or more bonding pads 305 are located.

[0076] In some implementation configurations, the multiple stacked memory dies 302 may be offset in any direction parallel to the surfaces of the multiple stacked memory dies 302. Two adjacent stacked memory dies 302 may be offset so that a bonding pad 305 on one surface of the memory die 302 is exposed.

[0077] As shown in Figure 3C, one or more connecting pillars 303 having a first portion 303-1 that is electrically connected to the bonding pad 305 are formed on one or more of the bonding pads 305 among a plurality of memory dies 302.

[0078] In some implementations, the connecting pillar 303 is perpendicular to the surface of the stacked memory die 302 and is in electrical contact with at least one bonding pad 305 of the stacked memory die 302. The electrical contact can be understood as two structures that are in contact and electrically connected.

[0079] As shown in Figure 3D, a molded layer 304 is formed that seals the multiple stacked memory dies 302 and one or more connecting pillars 303. In some mounting configurations, the molded layer 304 can completely seal the multiple stacked memory dies 302 and one or more connecting pillars 303. The molded layer 304 protects the multiple stacked memory dies 302 and can reduce physical and / or chemical damage to the multiple stacked memory dies 302 (such as oxidation and damage from moisture).

[0080] In some implementation configurations, the material of the molded layer 304 includes, but is not limited to, EMC.

[0081] As shown in Figure 3E, the first carrier 301 is removed.

[0082] As shown in Figure 3F, by removing a portion of the molded layer 304, a second portion 303-2 of one or more connecting pillars 303 is exposed. In some configurations, a portion of the molded layer 304 is removed first, followed by the removal of one carrier 301.

[0083] In some implementations, a portion of the molded layer 304 can be removed by grinding to expose a second portion 303-2 of at least one connecting pillar 303. In some implementations, when the molded layer 304 simultaneously seals multiple memory modules 30, the molded layer 304 may also be divided into multiple molded portions, each of which seals each of the multiple memory modules 30 individually according to subsequent processing requirements. For example, the molded layer 304 may be cut into two portions 304-1 and 304-2 as shown in Figure 3F, with each portion sealing one memory module 30 (30A and 30B). Note that the number of memory modules 30 shown in Figures 3B to 3L is illustrative and does not limit the number of memory modules 30 in the implementations of this disclosure.

[0084] In some implementations, a first carrier 301 is provided, and a plurality of first memory dies and a plurality of second memory dies are sequentially stacked on the first carrier 301, and the plurality of first memory dies and the plurality of second memory dies are arranged in parallel on the first carrier 301, and one or more connecting pillars 303 are formed, and the connecting pillars electrically connect to at least one bonding pad 305 of the plurality of first memory dies and at least one bonding pad 305 of the plurality of second memory dies. The molded layer 304 has a first connected portion 303-1 and is formed to seal a plurality of first memory dies, a plurality of second memory dies, and one or more connecting pillars 303. The first carrier 301 is removed, a portion of the molded layer 304 is removed to expose the second portion 303-2 of one or more connecting pillars 303, and the molded layer 304 is cut to obtain a first memory module 30A containing a plurality of first memory dies and a second memory module 30B containing a plurality of second memory dies.

[0085] In the above implementation configuration, multiple memory modules 30 can be formed using the same molding layer 304. That is, since multiple memory modules 30 can be formed simultaneously in the same process, production efficiency is greatly improved and production costs can be reduced.

[0086] Since multiple memory dies 302 are stacked on top of each other, the footprint of the memory module 30 can be reduced. The memory module 30 uses connecting pillars 303 instead of conventional wire bonding (e.g., bent wires bonded between bonding pads and bonding substrates), which further reduces the offset size between memory dies within the memory module 30 (the distance between the ends of conventional bent wires should not be too close) and shortens the signal transmission path between the memory module 30 and external devices. Furthermore, the use of connecting pillars avoids the bonding substrate used in conventional wire bonding techniques, saving time and cost. In addition, conventional wire bonding techniques are more complex during the manufacturing of the memory module 30 than connecting pillar techniques. Connecting pillars are also more reliable than conventional wire bonding.

[0087] In operation 201, a memory controller is also provided for controlling multiple memory modules, and a pull-out pad is provided on the surface of the memory controller.

[0088] In some implementations, as shown in Figures 3H and 3I, the memory system packaging structure further includes one or more passive devices 312 sealed within a plastic encapsulation layer 32. The one or more passive devices 312 are arranged on the first surface 331 of the RDL 33 and electrically connected to the RDL 33 (shown in Figure 3K). In some implementations, the one or more passive devices 312 include capacitors, resistors, inductors, and the like. The specific number, location, and type of the one or more passive devices 312 may vary depending on the actual requirements of the memory system packaging structure.

[0089] Operation 202. Referring to Figure 3J, the multiple memory modules 30 and the memory controller 31 are sealed within a plastic encapsulation layer 32. The second portion 303-2 of one or more connection pillars 303 in the multiple memory modules 30, and the lead pad 310 on the surface 311 of the memory controller 31 are both exposed on the same surface 321 of the plastic encapsulation layer 32. As shown in Figure 3K, if the second portion 303-2 of one or more connection pillars 303 in the multiple memory modules 30 is in electrical contact with the RDL 33, the lead pad 310 of the memory controller 31 can be directly electrically connected to the RDL 33, thereby shortening the signal transmission path of the memory controller 31.

[0090] In some implementation configurations, the step of sealing a plurality of memory modules 30 and memory controllers 31 in a plastic sealing layer 32 includes the steps of providing a second carrier 301', mounting the plurality of memory modules 30 and memory controllers 31 on the surface of the second carrier 301' such that the second portion 303-2 of one or more connecting pillars 303 of the plurality of memory modules 30 and the pull-out pad 310 of the memory controller 31 are located on the same surface of the second carrier 301', forming a plastic sealing layer 32 that seals the plurality of memory modules 30 and memory controllers 31, and removing the second carrier 301'.

[0091] In some implementation configurations, a second carrier 301' is provided, as shown in Figure 3G. The second carrier 301' may have a temporary bonding film. The temporary bonding film includes an adhesive layer used to attach multiple memory modules 30 and memory controllers 31 in a subsequent process.

[0092] In some implementation configurations, multiple memory modules 30 and memory controllers 31 are mounted on the surface of a second carrier 301', and as a result, the second portion of one or more connection pillars 303 of the multiple memory modules 30, and the pull-out pads 310 of the memory controllers 31 are all located on the same surface of the second carrier 301'.

[0093] In some implementation configurations, the front surfaces of multiple memory modules 30 and the front surface of the memory controller 31 are attached to a temporary bonding film on the second carrier 301'. The front surfaces of the multiple memory modules 30 are the surfaces on which the second portion of one or more connection pillars 303 is located, and the front surface of the memory controller is the surface on which the pull-out pad 310 is located. In a subsequent process, when the second carrier 301' and the temporary bonding film on the second carrier 301' are removed, the second portion of one or more connection pillars 303 in the multiple memory modules 30 and the pull-out pad 310 of the memory controller 31 are all exposed to facilitate electrical connection with the RDL 33.

[0094] In some implementations, the arrangement of memory modules 30 and memory controllers 31 on the surface of the second carrier 301' may vary. The packaging structure of the memory system may include two memory modules 30 or one memory module 30, as described below.

[0095] As shown in Figure 3H, in some implementation configurations, the memory modules include a first memory module 30A and a second memory module 30B. The front surfaces of the first memory module 30A, the second memory module 30B, and the memory controller 31 are attached to a temporary bonding film of the second carrier 301'. The memory controller 31 is located between the first memory module 30A and the second memory module 30B.

[0096] In some implementations, the distance between the memory controller 31 and the first memory module 30A is the first distance D1, the distance between the memory controller 31 and the second memory module 30B is the second distance D2, and the first distance D1 is equal to the second distance D2.

[0097] In some implementations, the memory controller 31 is positioned between the first memory module 30A and the second memory module 30B. The first memory module 30A and the second memory module 30B are arranged symmetrically with respect to the memory controller 31. That is, the signal path from the first memory module 30A to the memory controller 31 and the signal path from the second memory module 30B to the memory controller 31 are symmetrical and consistent, which improves the high-frequency performance of the memory system's packaging structure.

[0098] The symmetrical arrangement of the first memory module 30A and the second memory module 30B with respect to the memory controller 31 can be understood as the main components in the first memory module 30A and the main components in the second memory module 30B being symmetrically arranged with respect to the memory controller 31, except that, for manufacturing purposes, some components are not perfectly symmetrically arranged. If a component in the first memory module 30A or a component in the second memory module 30B has a specific offset, the signal paths between the first memory module 30A and the memory controller 31 and between the second memory module 30B and the memory controller 31 remain unaffected and are still symmetrically distributed with respect to the memory controller 31.

[0099] The first distance D1 is equal to the second distance D2. The first memory module 30A, the second memory module 30B, and the memory controller 31 are aligned in a straight line on the first plane 331 (shown in Figure 3K). Compared to the case where the first memory module 30A, the second memory module 30B, and the memory controller 31 are not aligned in a straight line, the signal paths between the first memory module 30A and the memory controller 31, and between the second memory module 30B and the memory controller 31 are shorter when they are aligned in a straight line.

[0100] In some implementations, as shown in Figure 3H, the first memory module 30A includes a plurality of first memory dies 302A offset in a first direction with a third distance D3, and the second memory module 30B includes a plurality of second memory dies 302B offset in a second direction with a fourth distance D4. Both the first and second directions are perpendicular to the stacking direction of the plurality of memory dies 302, and the first direction is opposite to the second direction.

[0101] In some implementations, the first memory module 30A and the second memory module 30B are not only arranged symmetrically with respect to the memory controller 31, but the multiple first memory dies 302A within the first memory module 30A and the multiple second memory dies 302B within the second memory module 30B are also arranged symmetrically with respect to the center line AA (shown in Figure 3H) of the memory controller 31. As a result, the signal paths from the first memory module 30A to the memory controller 31 and from the second memory module 30B to the memory controller 31 are symmetrical and consistent, thereby further improving the signal integrity and high-frequency performance of the memory system's packaging structure.

[0102] As shown in Figure 3H, in some implementations, the number of first memory dies 302A is the same as the number of second memory dies 302B. The third distance D3 is equal to the fourth distance D4. Here, the number of memory dies contained in the first memory module 30A and the second memory module 30B is the same, and the distance by which multiple first memory dies 302A in the first memory module 30A shift in the first direction is equal to the distance by which multiple second memory dies 302B in the second memory module 30B shift in the second direction. The first memory module 30A and the second memory module 30B may have the same internal structure. Multiple memory dies 302 in the first memory module 30A and the second memory module 30B are arranged symmetrically with respect to the center line AA of the memory controller 31. As a result, the signal path from each memory die in the first memory module 30A to the memory controller 31 is symmetrical and consistent with respect to the signal path from each memory die in the second memory module 30B to the memory controller 31, thus promoting the signal integrity of the memory system.

[0103] In some implementations, the first memory module 30A and the second memory module 30B may have the same internal structure and the same memory die, and are arranged on both sides of the memory controller 31, respectively. In some implementations, the first memory module 30A and the second memory module 30B are arranged symmetrically with respect to the center line AA of the memory controller 31, to which the corresponding pull-out pads 310 are provided.

[0104] Figure 3H shows an exemplary implementation for an array of packaging structures for a memory system containing two memory modules 30. Next, an array of packaging structures for a memory system containing one memory module 30 will be described.

[0105] In some implementations, the memory system packaging structure includes one memory module 30. The front surfaces of the one memory module 30 and the memory controller 31 are attached to a temporary bonding film of a second carrier 301'. The memory controller 31 is located to the side of the one memory module 30.

[0106] As shown in Figure 3I, in some implementation configurations, a plastic sealing layer 32 is formed to seal a single memory module 30 and memory controller 31.

[0107] In some implementation configurations, the plastic encapsulation layer 32 completely seals the memory module 30 and memory controller 31, reducing their physical and / or chemical damage (such as damage from oxidation or moisture). The material of the plastic encapsulation layer 32 includes, but is not limited to, EMC.

[0108] The materials of the plastic encapsulation layer 32 and the molded layer 304 may be the same or different. In some implementations, the materials of the plastic encapsulation layer 32 and the molded layer 304 may include EMC or Ajinomoto Build-up Film (ABF).

[0109] As shown in Figure 3J, the second carrier 301' is removed, and as a result, the second portion 303-2 of the connecting pillar 303 in the memory module 30 and the pull-out pad 310 of the memory controller 31 are both exposed to the same surface 321 of the plastic encapsulation layer 32, where the same surface 321 of the plastic encapsulation layer 32 is the surface of the plastic encapsulation layer 32 that was in contact with the second carrier 301'.

[0110] Operation 203. Referring to Figures 3K and 3J, the RDL 33 is formed on the same surface 321 of the plastic encapsulation layer. The memory module 30 is electrically connected to the RDL by physical contact between the second portion of the connecting pillar 303 and the RDL. The memory controller 31 is located on the first surface 331 of the RDL 33 and is electrically connected to the RDL 33 via the pull-out pad 310.

[0111] In some implementations, the RDL33 may include at least one conductive layer and at least one insulating layer. The conductive layer may be electrically connected to the second portion 303-2 of the connecting pillar 303. The conductive layer may include a metal or other suitable conductive material, or a combination thereof. The insulating layer may include an organic or inorganic material such as silicon oxide, silicon nitride, silicon oxynitride, or other suitable insulating material, or a combination thereof.

[0112] The second portion 303-2 of the connecting pillar 303 within the memory module 30, and the pull-out pad 310 of the memory controller 31 are both exposed on the same surface 321 of the plastic sealing layer 32. As a result, when the RDL 33 is formed in operation 203, the memory controller 31 can be electrically connected to the RDL 33 by soldering, thereby shortening the signal transmission path of the memory controller 31 and improving the high-frequency performance of the memory system's packaging structure.

[0113] Referring to Figures 3L and 3K, a metal solder ball 34 is formed on the second surface 332 of the RDL 33. The metal solder ball 34 is electrically connected via the RDL 33 to the memory module 30 and memory controller 31 located on the first surface 331 of the RDL 33. The second surface 332 and the first surface 331 are on opposite sides of each other.

[0114] In some implementations, the insulating layer of the RDL33 may have multiple openings to expose a portion of the conductive layer, with the multiple openings corresponding to metal solder balls 34. In this case, the metal solder balls 34 may function as signal input / output terminals. Signals from an external device can be input to the memory system packaging structure and / or signals from the memory system packaging structure can be output to an external device via the metal solder balls 34. In some implementations, the metal solder balls 34 may be electrically connected to at least one of the connecting pillars 303 and the memory controller 31.

[0115] While exemplary implementations for forming the packaging structure of a memory system are described herein, it should be noted that one or more operations may be omitted from the formation of the packaging structure of the memory system.

[0116] Figure 4A is a schematic cross-sectional view of the packaging structure of a memory system according to several implementations of the present disclosure, and Figure 4B is a schematic top view of the packaging structure of a memory system according to several implementations of the present disclosure. As shown in Figures 4A and 4B, the packaging structure of the memory system includes at least one of a memory module 40, a memory controller 41, a plastic sealing layer 42 that seals the memory module 40 and the memory controller 41, and an RDL 43. Each memory module 40 includes a plurality of vertically stacked memory dies 402, a molded layer 404 that seals the plurality of memory dies 402, and one or more connecting pillars 403. A first portion 403-1 of one or more connecting pillars 403 is electrically contacted and positioned on a bonding pad 405 of at least one memory die 402, and the one or more connecting pillars 403 extend from the first portion 403-1 through the molded layer 404 such that a second portion 403-2 of the connecting pillar 403 is positioned on the first surface 431 of the RDL 43 and electrically connected to the RDL 43. The packaging structure of the memory system may include metal solder balls 44 formed on the second surface 432 of the RDL 43. The metal solder balls 44 are electrically connected via the RDL 43 to a memory module 40 and a memory controller 41 located on the first surface 431 of the RDL 43. The second surface 432 and the first surface 431 are opposite each other. The packaging structure of the memory system may further include one or more passive devices 412 arranged on the first surface 431 of the RDL 43 and electrically connected to the RDL 43.

[0117] A pull-out pad 410 is provided on the surface 411 of the memory controller 41. The memory controller 41 is located on the first surface 431 of the RDL 43 and is electrically connected to the RDL 43 via the pull-out pad 410.

[0118] In some implementation configurations, the sides and bottom surfaces of each memory die 402 within a plurality of stacked memory dies 402 include an insulating layer, which insulates and protects the memory die 402, increases the mechanical strength of the memory die 402, and thus improves the reliability of the memory system's packaging structure.

[0119] In some implementation configurations, the multiple stacked memory dies 402 may be offset in any direction parallel to the surfaces of the multiple stacked memory dies 402. Two adjacent stacked memory dies 402 may be offset so that the bonding pads 405 on the surface of the memory die 402 are exposed.

[0120] In some implementation configurations, multiple stacked memory dies 402 are stacked in a stepped manner, and the exposed stepped surface of each memory die 402 of the multiple stacked memory dies 402 has multiple bonding pads 405. Except for the bottommost memory die 402, all other memory dies 402 of the multiple stacked memory dies 402 are offset in a first direction such that all bonding pads 405 on the surface of the multiple stacked memory dies 402 are exposed. The first direction is perpendicular to the stacking direction of the multiple stacked memory dies 402.

[0121] As shown in Figure 5A, the memory system packaging structure includes a first memory module 50A, a second memory module 50B, a memory controller 51, a plastic sealing layer 52 that seals the memory modules and the memory controller 51, and an RDL 53. The memory controller 51 is located between the first memory module 50A and the second memory module 50B. In some implementations, the memory system packaging structure may include metal solder balls 54 formed on the second surface 532 of the RDL 53. The memory system packaging structure may further include one or more passive devices 512 arranged on the first surface 531 of the RDL 53 and electrically connected to the RDL 53.

[0122] In some implementations, the distance between the memory controller 51 and the first memory module 50A is the first distance D1 (shown in Figure 3H), and the distance between the memory controller 51 and the second memory module 50B is the second distance D2 (shown in Figure 3H). The first distance D1 is equal to the second distance D2.

[0123] A pull-out pad 510 is provided on the surface 511 of the memory controller 51. The memory controller 51 is located on the first surface 531 of the RDL 53 and is electrically connected to the RDL 43 via the pull-out pad 410.

[0124] In Figure 5A, the memory controller 51 is located between the first memory module 50A and the second memory module 50B. The first memory module 50A and the second memory module 50B are arranged symmetrically with respect to the memory controller 51. That is, the signal path from the first memory module 50A to the memory controller 51 and the signal path from the second memory module 50B to the memory controller 51 are symmetrical and consistent, which improves the high-frequency performance of the memory system's packaging structure.

[0125] As shown in Figure 5A, the first memory module 50A, the second memory module 50B, and the memory controller 51 are aligned in a straight line on the first surface 531. Compared to the case where the first memory module 50A, the second memory module 50B, and the memory controller 51 are not aligned in a straight line, the signal paths between the first memory module 50A and the memory controller 51, and between the second memory module 50B and the memory controller 51 are shorter when they are aligned in a straight line.

[0126] In some implementations, as shown in Figure 5A, the first memory module 50A includes a plurality of first memory dies 502A stacked vertically and offset in the first direction by a third distance D3 (shown in Figure 3H), and the second memory module 50B includes a plurality of second memory dies 502B offset in the second direction by a fourth distance D4 (shown in Figure 3H). Both the first and second directions are perpendicular to the stacking direction of the plurality of memory dies 502, and the first direction is opposite to the second direction.

[0127] In some implementations, the first memory module 50A and the second memory module 50B are not only arranged symmetrically with respect to the memory controller 51, but the multiple first memory dies 502A within the first memory module 50A and the multiple second memory dies 502B within the second memory module 50B are also arranged symmetrically with respect to the center line AA of the memory controller 51. As a result, the signal paths from the first memory module 50A to the memory controller 51 and from the second memory module 50B to the memory controller 51 are symmetrical and consistent, thereby further improving the signal integrity and high-frequency performance of the memory system's packaging structure.

[0128] As shown in Figure 5A, in some implementations, the number of first memory dies 502A is the same as the number of second memory dies 502B, and the displacement distance of multiple first memory dies 502A in the first direction within the first memory module 50A is equal to the displacement distance of multiple second memory dies 502B in the second memory module 50B in the second direction. The first memory module 50A and the second memory module 50B may have the same internal structure. Multiple memory dies 502 in the first memory module 50A and the second memory module 50B are arranged symmetrically with respect to the center line AA of the memory controller 51. As a result, the signal path from each memory die in the first memory module 50A to the memory controller 51 is symmetric and consistent with respect to the signal path from each memory die in the second memory module 50B to the memory controller 51, thus promoting signal integrity of the memory system.

[0129] In some implementations, as shown in Figure 5B, the packaging structure of the memory system includes one memory module 50, and the memory controller 51 is located on one side of the memory module 50.

[0130] In some implementations, as shown in Figure 5B, each memory module 50 includes multiple memory dies 502, and the electrical connections differ between the multiple memory dies 502 and the connection pillars 503.

[0131] In some implementations, each memory module 50 includes one connection pillar 503, which is connected to a bonding pad 505 of one of the memory dies 502. The other memory dies 502 are electrically connected to the connection pillar 503 via bonding wires.

[0132] In some implementations, when each of the memory modules 50 includes one connection pillar 503, the packaging structure of the memory system may include at least one bonding wire, and other memory dies within the multiple memory dies 502 can be electrically connected to the one connection pillar 503 via the bonding wire in various ways. Two methods for achieving electrical connection between the multiple memory dies 502 and the one connection pillar 503 are described below.

[0133] Method 1: As shown in Figure 6A, any two adjacent memory dies 602 of the multiple memory dies 602 are electrically connected by bonding wires 607, and one connecting pillar 603 is connected to the bonding pad 605 of one of the memory dies 602. In this way, each memory die 602 in the memory module 60 is electrically connected to the RDL 63 via one connecting pillar 603.

[0134] Method 2: One connection pillar 603 makes electrical contact with the bonding pad 605 of one of the multiple memory dies 602, and the other memory dies are directly connected to the connection pillar via bonding wires 607.

[0135] In some implementations, when each memory module 60 includes multiple connection pillars 603, the electrical connections vary between the multiple memory dies 602 and the multiple connection pillars 603. Two methods for achieving electrical connections between the multiple memory dies 602 and the multiple connection pillars 603 are described below.

[0136] Method 1: As shown in Figure 6B, each of the memory modules 60 includes a plurality of connection pillars 603, each of which is connected to a bonding pad 605 of a portion of the memory die within a plurality of memory dies 602. The other memory dies of the plurality of memory dies 602 are electrically connected to the plurality of connection pillars 603 via bonding wires 607.

[0137] Method 2: As shown in Figure 6C, each of the memory modules 60 includes a plurality of connection pillars 603, each of which is connected to a corresponding bonding pad 605 of the memory die 602.

[0138] In some implementations, the connection pillar 603 is formed on each of the multiple memory dies 602. Each memory die 602 is electrically connected to the RDL 63 via the connection pillar 603. Each memory die 602 does not require additional bonding wires 607 for signal transmission to external devices, thereby improving the reliability of the memory system packaging structure during manufacturing.

[0139] In some implementations, a pull-out pad 610 is provided on the surface 611 of the memory controller 61. The memory controller 61 is located on the first surface 631 of the RDL 63 and is electrically connected to the RDL 63 via the pull-out pad 610.

[0140] In some implementations, the memory system packaging structure includes metal solder balls 64 on the second surface 632 of the RDL 63. The metal solder balls 64 are electrically connected via the RDL 63 to the memory module 60 and memory controller 61 located on the first surface 631 of the RDL 63. The second surface 632 and the first surface 631 are on opposite sides of each other.

[0141] In some implementations, the memory system packaging structure further includes one or more passive devices 612 sealed in a plastic encapsulation layer 62. The one or more passive devices 612 are located on a first surface 631 of the RDL 63 and are electrically connected to the RDL 63. The one or more passive devices 612 include capacitors, resistors, inductors, and the like. The specific number, location, and type of the one or more passive devices 612 may vary depending on the actual requirements of the memory system packaging structure.

[0142] In some implementations, the memory die 602 may be a 3D NAND flash memory die.

[0143] The exemplary memory system packaging structure described above can be used to form various memory system products such as Universal Flash Memory (UFS), Embedded Multimedia Card (eMMC), Personal Computer Memory (PC) Card, CF Card, SmartMedia (SM) Card, Memory Stick, Multimedia Card (MMC), SD Card, and SSD. A memory controller within the memory system package structure can control the operation of one or more memory dies of the memory module, including reading, erasing, and programming. The memory controller can also be configured to manage various functions, including but not limited to bad block management, garbage collection, and wear leveling. Any other appropriate functions, such as formatting the memory die, can also be performed by the memory controller. The memory controller can communicate with external devices according to specific communication protocols. For example, a memory controller can communicate with external devices via at least one of various interface protocols, such as the USB protocol, MMC protocol, PCI protocol, serial bus protocol, Advanced Technology Attachment (ATA) protocol, serial-ATA protocol, parallel-ATA20 protocol, Small Computer Small Interface (SCSI) protocol, Expansion Small Disk Interface (ESDI) protocol, and Integrated Drive Electronics (IDE) protocol.

[0144] The foregoing descriptions of specific implementations can be readily modified and / or adapted to various applications. Therefore, such adaptations and modifications are intended to fall within the meaning and scope of equivalents of the disclosed implementations, based on the teachings and guidance presented herein.

[0145] The scope and width of this disclosure should not be limited by any of the exemplary implementations described above, but should be defined solely in accordance with the following claims and their equivalents.

Claims

1. A packaging structure for a memory system, A memory module having vertically stacked memory dies, The memory controller, A redistribution layer having a first surface electrically connected to the memory controller, A plastic sealing layer that seals the memory module and the memory controller, One or more connection pillars extending vertically and configured to supply power to the memory module, each connection pillar comprising a first portion that is in physical contact with one of the memory dies and a second portion that is in physical contact with the redistribution layer, Equipped with, In a top view, the memory controller and all of the memory dies provided in the memory module do not overlap. The memory controller has a pull-out pad on its surface, The second portion of each of the one or more connecting pillars and the surface of the drawer pad are flush. The packaging structure of a memory system.

2. The memory module comprises a first memory module and a second memory module, the first memory module and the second memory module being positioned on either side of the memory controller, respectively, in the packaging structure for the memory system according to claim 1.

3. The packaging structure for a memory system according to claim 2, wherein the first memory module has a first distance from the memory controller, the second memory module has a second distance from the memory controller, and the first distance is the same as the second distance.

4. The packaging structure for a memory system according to claim 3, wherein the first memory module, the second memory module, and the memory controller are arranged in a straight line such that the memory controller is located between the first memory module and the second memory module.

5. The edges of two adjacent dies among the stacked memory dies are offset such that the upper die of the two adjacent dies has an extended portion that extends beyond the lower die of the two adjacent dies, and the lower die of the two adjacent dies has an uncovered portion that extends beyond the upper die of the two adjacent dies. The uncoated portion of the lower die of the two adjacent dies includes a bonding pad. The packaging structure for the memory system according to claim 4.

6. The packaging structure for a memory system according to claim 5, wherein the first memory module comprises a first memory die that is offset by a third distance in a first direction, and the second memory module comprises a second memory die that is offset by a fourth distance in a second direction, the third distance being equal to the fourth distance.

7. The packaging structure for a memory system according to claim 6, wherein both the first memory die and the second memory die are stacked in the vertical direction, both the first direction and the second direction are perpendicular to the vertical direction, and the first direction is opposite to the second direction.

8. The packaging structure for the memory system according to claim 7, wherein the first number of the first memory dies is equal to the second number of the second memory dies.

9. One connection pillar in the first memory module is physically attached to one of the bonding pads of a first subset of the first memory die, and a second subset of the first memory die is connected to the first portion of the connection pillar in the first memory module by bonding wires. One connection pillar in the second memory module is physically attached to one of the bonding pads of the first subset of the second memory die, and the second subset of the second memory die is connected to the first portion of the connection pillar in the second memory module by bonding wires. The packaging structure for the memory system according to claim 8.

10. Each connection pillar in the first memory module is physically attached to each of the bonding pads of the first memory die. Each connection pillar in the second memory module is physically attached to each of the bonding pads of the second memory die. The packaging structure for the memory system according to claim 8.

11. The packaging structure for the memory system according to claim 9, wherein the one or more connecting pillars comprises one or more copper pillars.

12. The redistribution layer further comprises a metal solder ball located on the second surface of the redistribution layer, The metal solder ball is electrically connected to the memory module and the memory controller via the redistribution layer, and the second surface and the first surface are on opposite sides of each other. The packaging structure for the memory system according to claim 11.

13. The plastic sealing layer further comprises at least one passive device sealed within it. The at least one passive device is positioned on the first surface of the redistribution layer and is electrically connected to the redistribution layer. The packaging structure for the memory system according to claim 12.

14. The packaging structure for the memory system according to claim 13, wherein the first memory die and the second memory die comprise three-dimensional NAND flash memory dies.

15. A packaging structure for a memory system, A memory module having vertically stacked memory dies, The memory controller, A redistribution layer having a first surface electrically connected to the memory controller, A plastic sealing layer that seals the memory module and the memory controller, The system comprises one or more connecting pillars that extend vertically and are configured to supply power to the memory module, Each connecting pillar is A first portion that is in physical contact with one of the memory dies, It comprises a second portion that is in physical contact with the redistribution layer, In a top view, the memory controller and all of the memory dies provided in the memory module do not overlap. The memory controller has a pull-out pad on its surface, The second portion of each of the one or more connecting pillars and the surface of the drawer pad are flush. The packaging structure of a memory system.

16. The edges of two adjacent dies among the stacked memory dies are offset such that the upper die of the two adjacent dies has an extended portion that extends beyond the lower die of the two adjacent dies, and the lower die of the two adjacent dies has an uncovered portion that extends beyond the upper die of the two adjacent dies. The uncoated portion of the lower die of the two adjacent dies includes a bonding pad. The packaging structure for the memory system according to claim 15.

17. The packaging structure for a memory system according to claim 16, wherein one connection pillar in the memory module is physically attached to one of the bonding pads of a first subset of the memory die, and a second subset of the memory die is connected to the first portion of the connection pillar in the memory module by bonding wires.

18. The packaging structure for a memory system according to claim 16, wherein at least two connection pillars in the memory module are physically attached to two of two bonding pads of a first subset of the memory die, and a second subset of the memory die is connected to the first portion of the two connection pillars in the memory module by bonding wires.

19. The packaging structure for the memory system according to claim 16, wherein each connection pillar in the memory module is physically attached to each of the bonding pads of the memory die.

20. A method for packaging a memory system, A step of providing one or more memory modules, each memory module comprising vertically stacked memory dies and one or more connecting pillars configured to supply power to the one or more memory modules, The steps include providing a memory controller having a pull-out pad, A step of mounting the one or more memory modules and the memory controller on a first surface of a redistribution layer, wherein the redistribution layer is configured to electrically connect the one or more connection pillars of the one or more memory modules to the pull-out pads of the memory controller, The process includes the step of forming a plastic sealing layer that seals one or more memory modules, the memory controller, and one or more connection pillars, In the step of providing the memory controller, the memory controller is provided such that, in a top view, the memory controller and all of the memory dies provided by each of the one or more memory modules do not overlap. In the step of providing the memory controller, the memory controller is provided such that the pull-out pad is located on the surface of the memory controller. The step of mounting the one or more memory modules and the memory controller on the first surface of the redistribution layer comprises the step of physically connecting the second portion of each of the one or more connection pillars to the redistribution layer. A method wherein, in the step of forming the plastic sealing layer, the second portion of each of the one or more connecting pillars and the pull-out pad are exposed on the same surface of the plastic sealing layer.

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