Controller, image forming apparatus, and access arbitration method

Abstract

To prevent an increase in read latency on a plurality of devices connected with communication interfaces.SOLUTION: A controller has: a plurality of communication interfaces; a first arbiter that arbitrates access to a memory; and a second arbiter that is provided between the plurality of communication interfaces and the first arbiter, and when receiving unprocessed read requests from the communication interfaces to the memory, limits the number of the unprocessed read requests to be passed through the first arbiter.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] The present invention relates to a controller, an image forming apparatus, and an access arbitration method.

Background Art

[0002] There is known an image processing apparatus that transfers image data line by line using a high-speed serial interface such as PCI Express (registered trademark) for transferring image data between a scanner or a plotter and a controller.

[0003] There is also known a data transfer apparatus that accumulates read requests to a memory and interrupts the issuance of write requests to the memory until the next read request is issued when the number of read requests for which data transfer has not been completed reaches a first value or more (see, for example, Patent Document 1).

Summary of the Invention

Problems to be Solved by the Invention

[0004] According to the technique disclosed in Patent Document 1, the read latency with respect to the memory can be reduced.

[0005] However, in this method, when a plurality of devices are connected to a communication interface (such as PCI Express), the read latency of the devices connected to the communication interface may become longer due to access to the memory by other devices.

[0006] One embodiment of the present invention has been made in view of the above problems, and suppresses an increase in the read latency of devices connected to a communication interface when a plurality of devices are connected to the communication interface.

Means for Solving the Problems

[0007] To solve the above problems, a controller according to one embodiment of the present invention includes a plurality of communication interfaces, a first arbiter for mediating access to memory, and a second arbiter provided between the plurality of communication interfaces and the first arbiter, which, when it receives an unprocessed read request from the communication interface to the memory, limits the number of unprocessed read requests that it passes to the first arbiter. The communication interface communicates with the device connected to the communication interface in accordance with the PCI Express standard, and the second arbiter limits the number of pending read requests to pass to the first arbiter to a value smaller than the number of outstanding requests from the device. [Effects of the Invention]

[0008] According to one embodiment of the present invention, when multiple devices are connected to a communication interface, it is possible to suppress the increase in read latency of devices connected to the communication interface. [Brief explanation of the drawing]

[0009] [Figure 1] This figure shows an example of the hardware configuration of an image forming apparatus according to one embodiment. [Figure 2] This is a sequence diagram showing an example of processing when a read request occurs according to the first embodiment. [Figure 3] This is a sequence diagram showing an example of processing when a read request occurs according to the second embodiment. [Figure 4] This figure shows an example of the hardware configuration of an image forming apparatus. [Figure 5] This is a sequence diagram showing an example of processing when a read request occurs. [Modes for carrying out the invention]

[0010] Embodiments of the present invention will be described in detail below with reference to the drawings.

[0011] <Image Processing Device> Before describing this embodiment, we will first describe an image forming apparatus, which is an example of an electronic device that serves as the premise for this embodiment.

[0012] Figure 4 shows an example of the hardware configuration of an image forming apparatus. The image forming apparatus 1 is an electronic device having image forming functions, such as an MFP (Multifunction Peripheral) or a copier, which has scanning, copying, printing, and facsimile functions mounted in a single housing.

[0013] In the example shown in Figure 4, the image forming apparatus 1 includes an overall control unit 10, an image processing unit 20, a storage device 30, a scanner unit 40, and a printer unit 50, etc.

[0014] The overall control unit (controller) 10 is a controller that controls the entire image forming apparatus 1. In the example shown in Figure 4, the overall control unit 10 is a control board having a memory 11, a memory controller 110, an arbiter 120, a CPU (Central Processing Unit), and multiple communication interfaces 140a, 140b, etc. In the following description, when referring to any of the multiple communication interfaces 140a, 140b, "communication interface 140" will be used. The number of multiple communication interfaces 140 may be two or more other numbers.

[0015] In the example shown in Figure 4, the memory controller 110, arbiter 120, CPU (Central Processing Unit) 130, and multiple communication interfaces 140a and 140b are composed of an SoC (System on a Chip) 100. The SoC 100 is a semiconductor device designed to function as a system by integrating a processor such as the CPU 130, peripheral circuits, and application circuits on a single integrated circuit chip. Note that the SoC is another example of the controller according to this embodiment. In other words, the controller according to this embodiment may be a control board such as the overall control unit 10, or a semiconductor device such as the SoC 100.

[0016] Memory 11 is a non-volatile storage device such as DRAM (Dynamic Random Access Memory). Note that memory 11 may be a type of memory other than DRAM. The memory controller 110 is a circuit that performs data writing to and reading from memory 11, as well as DRAM refresh.

[0017] The arbiter 120 is a circuit that mediates access to the memory 11 and the memory controller 110 by the CPU 130 and multiple communication I / F 140a and 140b, and is also called a bus arbiter. The CPU 130 is a processor (arithmetic unit) that controls various functions of the image forming apparatus 1 by executing a predetermined program.

[0018] The communication interface 140 is a communication interface for communicating with the image processing ASIC 21 and the storage device 30, etc., in accordance with standards such as PCI Express®. PCI Express is a standard for an extended interface using a serial transfer method for high-speed data communication. In the example in Figure 4, the communication interface 140 includes a FIFO (First In First Out) 141 and a PCIe PHY 142. The FIFO 141 is a first-in, first-out buffer. The PCIe PHY 142 is a circuit that implements the physical layer of PCI Express and sends and receives data with the device connected to the communication interface 140.

[0019] The image processing unit 20 is connected to the communication interface 140a of the overall control unit 10 and controls the scanner unit 40 and the printer unit 50 to perform image processing such as copying, printing, or scanning. In the example in Figure 4, the image processing unit 20 has an image processing ASIC (Application Specific Integrated Circuit) 21. The image processing ASIC is an image processing device that controls image processing such as copying, printing, or scanning.

[0020] The scanner unit 40 is a reading device that reads documents and the like according to the control from the image processing ASIC 21. The printer unit 50 is a printing device that prints print data on a printing medium according to the control from the image processing ASIC 21.

[0021] The storage device 30 is a large-capacity storage device such as an SSD (Solid State Drive) or an HDD (Hard Disk Drive), for example.

[0022] For example, when the image forming apparatus 1 executes copy processing, the image processing ASIC 21 reads a document with the scanner unit 40, performs image processing on the read data, and temporarily stores it in the memory 11 of the overall control unit 10 or the like. Also, when the printer unit 50 is ready, the image processing ASIC 21 acquires data from the memory 11 of the overall control unit 10, performs image processing for printing, and then prints the data using the printer unit 50. Such image processing has different specifications for each company, and the processing is complicated and requires real-time performance, so it is often realized by an ASIC.

[0023] Also, it is desirable that the image processing ASIC 21 and the overall control unit 10 be connected by a high-speed communication I / F 140 such as PCI Express so that large-capacity image data can be transmitted and received with low latency.

[0024] (Example of processing of image forming apparatus) The image processing ASIC 21 of the image processing unit 20 writes the image data acquired by the scanner unit 40 into the memory 11 in the overall control unit 10 by transmitting a write request to the SoC 100 via a PCI Express (hereinafter referred to as PCIe) interface. Also, the image processing ASIC 21 reads out the image data stored in the memory 11 by transmitting a read request to the SoC 100 via the PCIe interface.

[0025] The communication interface 140a of the overall control unit 10 temporarily stores read and write requests received from the image processing ASIC 21 in the FIFO 141 and outputs them to the arbiter 120 in the order in which the stored commands were received.

[0026] The arbiter 120 mediates access requests to memory 11 from the CPU 130, which shares memory 11, and from multiple communication I / F modules such as 140a and 140b. Normally, when the arbiter 120 receives multiple access requests to memory 11, it grants access rights in a round-robin manner, but is not limited to this, and can also grant access rights preferentially to modules with higher priority based on priority settings.

[0027] PCIe, by definition, has a feature called Outstanding Requet. Normally, when the CPU 130 and multiple communication I / F modules such as 140a and 140b send an access request to the arbiter 120, they cannot send the next access request to the arbiter 120 until a response to the previous access request is received. The PCIe Outstanding Requet feature allows a module to send the next access request to the arbiter 120 after sending the previous access request, but before a response to the previous access request is received. In particular, read requests require time for the SoC 100 to prepare the read data, so sending read requests continuously using the Outstanding Requet feature can improve system performance.

[0028] (Example of processing when a read request occurs) Figure 5 shows an example of processing when the image processing ASIC 21 sends eight read requests to the SoC 100's communication I / F 140a in the image forming apparatus 1 shown in Figure 4. Here, it is assumed that the communication I / F 140a can accept up to four unprocessed read requests from the image processing ASIC 21 using the Outstanding request function. Note that an unprocessed read request (Outstanding read request) is a state in which the communication I / F 140a has received a read request from the image processing ASIC 21, etc., but has not yet returned a response to that read request.

[0029] In step S1 of Figure 5, the image processing ASIC 21 sequentially sends four read requests (Read cmd0 to Read cmd3) to the SoC 100's communication I / F 140a. Note that the SoC 100 can only accept up to four unprocessed read requests, so at this point, the image processing ASIC 21 withholds sending the next four read requests (Read cmd4 to Read cmd7).

[0030] The communication interface 140a sequentially notifies the arbiter 120 of the four received read requests (Read cmd0 to Read cmd3), and the arbiter 120 sequentially notifies the memory 11 of the four received read requests (Read cmd0 to Read cmd3). For the sake of simplicity, the following explanation assumes that the memory controller 110 is included in the memory 11.

[0031] In step S2, the memory 11 (and memory controller 110) reads the read data (Read data0 to Read data3) for the four read requests it has received, and sequentially outputs the read data to the arbiter 120. The arbiter 120 outputs the four read data (Read data0 to Read data3) received from the memory 11 to the communication interface 140a, and the communication interface 140a sequentially transmits the four read data to the image processing ASIC 21.

[0032] In step S3, after receiving read data (Read data0) from communication I / F140a, the image processing ASIC21 sends the next read request (Read cmd4) to communication I / F140. Similarly, after receiving read data (Read data1) from communication I / F140a, the image processing ASIC21 sends the next read request (Read cmd5) to communication I / F140. In the same manner, after receiving read data (Read data2), the image processing ASIC21 sends a read request (Read cmd6) to communication I / F140, and after receiving read data (Read data3), it sends a read request (Read cmd7) to communication I / F140. Communication I / F140a sequentially notifies the arbiter 120 of the four read requests (Read cmd4 to Read cmd7) it has received.

[0033] Here, during the period T2 between when the arbiter 120 sends read data (Read Data3) to the communication interface 140a and when it receives a read request (Read cmd4) from the communication interface 140a, the storage device 30 or the like may issue an access request. If, for example, the storage device 30 issues a large number of write requests during this period T2, then in step S3, a period T3 occurs until the arbiter 120 outputs read requests (Read cmd4 to Read cmd7) to the memory 11.

[0034] In this case, for example, in step S4, there is a delay in the timing when the memory 11 sends the read data (Read data4 to Read data7) and when the image processing ASIC 21 sends the read data (Read data4 to Read data7). This results in a problem where, for example, the read latency T4 of the read request (Read cmd4) becomes longer than the read latency T1 of the read request (Read cmd0).

[0035] The image processing ASIC 21, for example, when printing using the printer unit 50, needs to send data in time with the rotation of the photosensitive drum in the printer unit 50. This time is called the line period. If the read latency T4 of the aforementioned read request (Read cmd4) becomes longer than the line period, the print data will not be able to keep up with the rotation of the photosensitive drum, resulting in an abnormal image.

[0036] Therefore, the image forming apparatus 1 according to this embodiment has the hardware configuration shown in Figure 1 in order to suppress the increase in read latency of devices connected to the communication I / F 140 when multiple devices are connected to the communication I / F 140.

[0037] <Hardware Configuration> Figure 1 shows an example of the hardware configuration of an image forming apparatus according to one embodiment. In addition to the hardware configuration of the image forming apparatus 1 described in Figure 4, the image forming apparatus 1 according to this embodiment has a second arbiter 150 provided between an arbiter (first arbiter) 120 and a communication I / F 140.

[0038] The second arbiter 150 arbitrates access requests from multiple communication interfaces 140a and 140b, and has the function of limiting the number of unprocessed read requests that it passes to the arbiter 120 when it receives an unprocessed read request from the communication interface 140a. For example, the second arbiter 150 limits the number of unprocessed read requests that it passes to the first arbiter to a value smaller than the number of outstanding requests from the image processing ASIC 21. Here, the number of outstanding requests is the number of unprocessed read requests that the SoC 100 can accept from the image processing ASIC.

[0039] As a specific example, the second arbiter 150 limits the number of unprocessed read requests received from the communication I / F 140a to one, which is then output to the first arbiter.

[0040] <Processing flow> Next, the processing flow of the access arbitration method according to this embodiment will be described.

[0041] [First Embodiment] Figure 2 is a sequence diagram showing an example of processing when a read request occurs according to the second embodiment. This process shows an example of processing when the image processing ASIC 21 in the image forming apparatus 1 shown in Figure 1 sends eight read requests to the communication I / F 140a of the SoC 100. Here, the communication I / F 140a is capable of receiving up to four unprocessed read requests from the image processing ASIC 21 using the Outstanding requet function. The second arbiter 150 limits the number of unprocessed read requests received from the communication I / F 140a to one and outputs it to the first arbiter.

[0042] In step S1, the image processing ASIC 21 sequentially sends four read requests (Read cmd0 to Read cmd3) to the SoC 100's communication I / F 140a, similar to the process described in Figure 5. Note that the SoC 100 can only accept up to four unprocessed read requests, so at this point, the image processing ASIC 21 withholds sending the next four read requests (Read cmd4 to Read cmd7).

[0043] The communication interface 140a sequentially outputs the four received read requests (Read cmd0 to Read cmd3) to the second arbiter 150.

[0044] At timing t1 in Figure 2, the second arbiter 150 outputs the read request (Read cmd0) received from the communication interface 140a to the arbiter (first arbiter) 120. Note that the second arbiter 150 limits the number of unprocessed read requests output to the arbiter (first arbiter) 120 to one, and therefore holds the output of other received read requests (Read cmd1 to Read cmd3).

[0045] The arbiter (first arbiter) 120 notifies the memory 11 of the read request (Read cmd0) received from the second arbiter 150. For the sake of simplicity, the following explanation assumes that the memory 11 includes a memory controller 110.

[0046] At timing t2 in Figure 2, memory 11 reads the read data (Read data0) in response to the received read request (Read cmd0), and outputs the read data to the second arbiter 150 via the arbiter (first arbiter) 120.

[0047] As a result, at timing t3 in Figure 2, the second arbiter 150 can output the next read request (Read cmd1) to the arbiter (first arbiter) 120. At timing t3, the second arbiter 150 transmits the read data (Read data0) received from the arbiter (first arbiter) 120 to the image processing ASIC 21 via the communication I / F 140a. The second arbiter 150 also outputs the next read request (Read cmd1) to the memory 11 via the arbiter (first arbiter) 120.

[0048] At timing t4 in Figure 2, memory 11 reads the read data (Read data1) in response to the received read request (Read cmd1), and outputs the read data to the second arbiter 150 via the arbiter (first arbiter) 120. Also at timing t4, the image processing ASIC 21 becomes ready to output the next read request (Read cmd4), and sends the read request (Read cmd4) to the second arbiter 150 via the communication I / F 140a.

[0049] At timing t5 in Figure 2, the second arbiter 150 becomes ready to output the next read request (Read cmd2) to the arbiter (first arbiter) 120. At timing t5, the second arbiter 150 transmits the read data (Read data1) received from the arbiter (first arbiter) 120 to the image processing ASIC 21 via the communication I / F 140a. The second arbiter 150 also outputs the next read request (Read cmd2) to the memory 11 via the arbiter (first arbiter) 120.

[0050] At timing t6 in Figure 2, memory 11 reads the read data (Read data2) in response to the received read request (Read cmd2), and outputs the read data to the second arbiter 150 via the arbiter (first arbiter) 120. Also at timing t6, the image processing ASIC 21 becomes ready to output the next read request (Read cmd5), and sends the read request (Read cmd5) to the second arbiter 150 via the communication I / F 140a.

[0051] At timing t7 in Figure 2, the second arbiter 150 becomes ready to output the next read request (Read cmd3) to the arbiter (first arbiter) 120. At timing t7, the second arbiter 150 transmits the read data (Read data2) received from the arbiter (first arbiter) 120 to the image processing ASIC 21 via the communication I / F 140a. The second arbiter 150 also outputs the next read request (Read cmd3) to the memory 11 via the arbiter (first arbiter) 120.

[0052] At timing t8 in Figure 2, memory 11 reads the read data (Read data3) in response to the received read request (Read cmd3), and outputs the read data to the second arbiter 150 via the arbiter (first arbiter) 120. Also at timing t8, the image processing ASIC 21 becomes ready to output the next read request (Read cmd6), and sends the read request (Read cmd6) to the second arbiter 150 via the communication I / F 140a.

[0053] At timing t9 in Figure 2, the second arbiter 150 becomes ready to output the next read request (Read cmd4) to the arbiter (first arbiter) 120. At timing t9, the second arbiter 150 transmits the read data (Read data3) received from the arbiter (first arbiter) 120 to the image processing ASIC 21 via the communication I / F 140a. The second arbiter 150 also outputs the next read request (Read cmd4) to the memory 11 via the arbiter (first arbiter) 120.

[0054] At timing t10 ​​in Figure 2, memory 11 reads the read data (Read data4) in response to the received read request (Read cmd4), and outputs the read data to the second arbiter 150 via the arbiter (first arbiter) 120. Also at timing t10, the image processing ASIC 21 becomes ready to output the next read request (Read cmd7), and sends the read request (Read cmd7) to the second arbiter 150 via the communication I / F 140a.

[0055] At timing t11 in Figure 2, the second arbiter 150 becomes ready to output the next read request (Read cmd5) to the arbiter (first arbiter) 120. At timing t11, the second arbiter 150 transmits the read data (Read data4) received from the arbiter (first arbiter) 120 to the image processing ASIC 21 via the communication I / F 140a. The second arbiter 150 also outputs the next read request (Read cmd5) to the memory 11 via the arbiter (first arbiter) 120.

[0056] At timing t12 in Figure 2, memory 11 reads the read data (Read data5) in response to the received read request (Read cmd5), and outputs the read data to the second arbiter 150 via the arbiter (first arbiter) 120.

[0057] At timing t13 in Figure 2, the second arbiter 150 becomes ready to output the next read request (Read cmd6) to the arbiter (first arbiter) 120. At timing t13, the second arbiter 150 transmits the read data (Read data5) received from the arbiter (first arbiter) 120 to the image processing ASIC 21 via the communication I / F 140a. The second arbiter 150 also outputs the next read request (Read cmd6) to the memory 11 via the arbiter (first arbiter) 120. Note that the processing from t14 onward is a repetition of the same process, so the explanation is omitted here.

[0058] As a result of the process shown in Figure 2, read requests from communication I / F 140a are continuously sent to the arbiter (first arbiter) 120. Furthermore, while read requests from communication I / F 140a are being continuously sent to the arbiter (first arbiter) 120, it holds off on accepting access requests from other communication I / F 140b. This makes it possible to suppress the lengthening of the read latency of read requests (Read cmd1 to Read cmd7) according to this embodiment. For example, in the example in Figure 2, it can be seen that the read latency Ta for read request (Read cmd1) and the read latency Tb for read request (Read cmd5) are similar values.

[0059] Note that the timings t1 to t14 shown in Figure 2 are illustrative and do not represent the actual hardware operating timings. It is desirable for designers to set the number of unprocessed read requests that the second arbiter 150 passes to the arbiter (first arbiter) 120 in accordance with the actual hardware operating timings.

[0060] [Second Embodiment] The second arbiter 150 may limit the number of unprocessed read requests it accepts from the communication interface 140a when it receives an unprocessed read request from the communication interface 140a to the memory 11.

[0061] Figure 3 is a sequence diagram showing an example of processing when a read request occurs according to the second embodiment. This process shows another example of the processing when the image processing ASIC 21 in the image forming apparatus 1 shown in Figure 1 sends eight read requests to the communication I / F 140a of the SoC 100. Here, the communication I / F 140a is capable of receiving up to four unprocessed read requests from the image processing ASIC 21 using the Outstanding requet function. The second arbiter 150 is also designed to limit the number of unprocessed read requests it receives from the communication I / F 140a to two.

[0062] In step S1, the image processing ASIC 21 sequentially sends four read requests (Read cmd0 to Read cmd3) to the SoC 100's communication I / F 140a, similar to the process described in Figures 1 and 5. Since the SoC 100 can only accept up to four unprocessed read requests, the image processing ASIC 21 suspends sending the next four read requests (Read cmd4 to Read cmd7) at this point.

[0063] At timing t1 in Figure 3, the communication interface 140a outputs the read request (Read cmd0) received from the image processing ASIC 21 to the second arbiter 150. At timing t2, the communication interface 140a also outputs the read request (Read cmd1) received from the image processing ASIC 21 to the second arbiter 150. Since the second arbiter 150 limits the number of unprocessed read requests it accepts to two, the remaining two read requests (Read cmd2 and Read cmd3) are stored in the FIFO 141 of the communication interface 140a.

[0064] The second arbiter 150 outputs the read requests (Read cmd0, Read cmd1) received from the communication I / F 140a to the memory controller 110 via the arbiter (first arbiter) 120. In the second embodiment, the memory 11 and the memory controller 110 are described separately.

[0065] Around the time t3 in Figure 3, the memory controller 110 reads the requested data from the memory 11 and outputs the read data (Read Data0) to the second arbiter 150 via the arbiter (first arbiter) 120. The second arbiter 150 outputs the received read data (Read Data0) to the communication interface 140a. As a result, at the time t5, the communication interface 140a can output a read request (Read cmd2) to the second arbiter 150.

[0066] Around the time t4 in Figure 3, the memory controller 110 reads the requested data from the memory 11 and outputs the read data (Read Data1) to the second arbiter 150 via the arbiter (first arbiter) 120. The second arbiter 150 outputs the received read data (Read Data1) to the communication interface 140a. As a result, at the time t6, the communication interface 140a can output a read request (Read cmd3) to the second arbiter 150.

[0067] At timing t5 in Figure 3, the communication interface 140a outputs the read request (Read cmd2) received from the image processing ASIC 21 to the second arbiter 150. As a result, the second arbiter 150 outputs the read request (Read cmd2) received from the communication interface 140a to the memory controller 110 via the arbiter (first arbiter) 120.

[0068] Furthermore, at timing t5, the communication interface 140a transmits the read data (Read data0) received from the second arbiter 150 to the image processing ASIC 21. This allows the image processing ASIC 21 to send the next read request (Read cmd4), and it then sends the read request (Read cmd4) to the communication interface 140a.

[0069] At timing t6 in Figure 3, the communication interface 140a outputs a read request (Read cmd3) received from the image processing ASIC 21 to the second arbiter 150. As a result, the second arbiter 150 outputs the read request (Read cmd3) received from the communication interface 140a to the memory controller 110 via the arbiter (first arbiter) 120.

[0070] Furthermore, at timing t6, the communication interface 140a transmits the read data (Read data1) received from the second arbiter 150 to the image processing ASIC 21. This allows the image processing ASIC 21 to send the next read request (Read cmd5), and it then sends the read request (Read cmd5) to the communication interface 140a.

[0071] Around the time t7 in Figure 3, the memory controller 110 reads the requested data from the memory 11 and outputs the read data (Read Data2) to the second arbiter 150 via the arbiter (first arbiter) 120. The second arbiter 150 outputs the received read data (Read Data2) to the communication interface 140a. As a result, at the time t9, the communication interface 140a can output a read request (Read cmd4) to the second arbiter 150.

[0072] Around the time t8 in Figure 3, the memory controller 110 reads the requested data from the memory 11 and outputs the read data (Read Data 3) to the second arbiter 150 via the arbiter (first arbiter) 120. The second arbiter 150 outputs the received read data (Read Data 3) to the communication interface 140a. As a result, at the time t10, the communication interface 140a can output a read request (Read cmd 5) to the second arbiter 150.

[0073] At timing t9 in Figure 3, the communication interface 140a outputs the read request (Read cmd4) received from the image processing ASIC 21 to the second arbiter 150. As a result, the second arbiter 150 outputs the read request (Read cmd4) received from the communication interface 140a to the memory controller 110 via the arbiter (first arbiter) 120.

[0074] Furthermore, at timing t9, the communication interface 140a transmits the read data (Read data2) received from the second arbiter 150 to the image processing ASIC 21. This allows the image processing ASIC 21 to send the next read request (Read cmd6), and it then sends the read request (Read cmd6) to the communication interface 140a.

[0075] At timing t10 ​​in Figure 3, the communication interface 140a outputs a read request (Read cmd5) received from the image processing ASIC 21 to the second arbiter 150. As a result, the second arbiter 150 outputs the read request (Read cmd5) received from the communication interface 140a to the memory controller 110 via the arbiter (first arbiter) 120.

[0076] Furthermore, at timing t10, the communication interface 140a transmits the read data (Read data3) received from the second arbiter 150 to the image processing ASIC 21. This allows the image processing ASIC 21 to send the next read request (Read cmd7), and it then sends the read request (Read cmd7) to the communication interface 140a.

[0077] At timing t11 in Figure 3, the memory controller 110 reads the requested data from memory 11 and outputs the read data (Read Data 4) to the second arbiter 150 via the arbiter (first arbiter) 120. The second arbiter 150 outputs the received read data (Read Data 4) to the communication interface 140a. As a result, at timing t13, the communication interface 140a can output a read request (Read cmd 6) to the second arbiter 150.

[0078] At timing t12 in Figure 3, the memory controller 110 reads the requested data from the memory 11 and outputs the read data (Read Data 5) to the second arbiter 150 via the arbiter (first arbiter) 120. The second arbiter 150 outputs the received read data (Read Data 5) to the communication interface 140a. As a result, at timing t14, the communication interface 140a can output a read request (Read cmd 7) to the second arbiter 150.

[0079] At timing t13 in Figure 3, the communication interface 140a outputs the read request (Read cmd6) received from the image processing ASIC 21 to the second arbiter 150. As a result, the second arbiter 150 outputs the read request (Read cmd6) received from the communication interface 140a to the memory controller 110 via the arbiter (first arbiter) 120.

[0080] Also, at timing t13, the communication interface 140a transmits the read data (Read data 4) received from the second arbiter 150 to the image processing ASIC 21.

[0081] At timing t14 in Figure 3, the communication interface 140a outputs a read request (Read cmd7) received from the image processing ASIC 21 to the second arbiter 150. Also at timing t14, the communication interface 140a transmits the read data (Read data5) received from the second arbiter 150 to the image processing ASIC 21. The processing after t14 is a repetition of the same process, so the explanation is omitted here.

[0082] As shown in Figure 3, the arbiter (first arbiter) 120 will continuously receive read requests and perform read operations from the communication interface 140a. Furthermore, while the arbiter (first arbiter) 120 is continuously receiving read requests and performing read operations from the communication interface 140a, it will hold off on accepting access requests from other communication interfaces 140b. This makes it possible to suppress the lengthening of the read latency of read requests (Read cmd1 to Read cmd7) in the second embodiment as well.

[0083] Note that the timings t1 to t14 shown in Figure 3 are illustrative and do not represent the actual hardware operating timings. It is desirable for designers to set the number of unprocessed read requests that the second arbiter 150 passes to the arbiter (first arbiter) 120 in accordance with the actual hardware operating timings.

[0084] As described above, according to each embodiment of the present invention, when multiple devices are connected to a communication interface, it is possible to suppress the increase in read latency of devices connected to the communication interface.

[0085] In the above embodiments, the electronic device equipped with a controller (overall control unit 10, or SoC 100) was described as the image forming apparatus 1. However, the controller may be located in an electronic device other than the image forming apparatus 1. [Explanation of symbols]

[0086] 1. Image forming apparatus 10. Overall control unit (an example of a controller) 11 memory 21. Image Processing ASIC (Device, Image Processing Device) 100 SoCs (another example of a controller) 120 Arbiter (First Arbiter) 140, 140a, 140b communication interfaces 150 Second Arbiter [Prior art documents] [Patent Documents]

[0087] [Patent Document 1] Japanese Patent Publication No. 2019-003384

Claims

1. Multiple communication interfaces, The first arbiter mediates access to memory, A second arbiter is provided between the plurality of communication interfaces and the first arbiter, and when it receives an unprocessed read request from the communication interface to the memory, it limits the number of unprocessed read requests that are passed to the first arbiter. It has, The aforementioned communication interface communicates with the device connected to the communication interface in accordance with the PCI Express® standard. The second arbiter limits the number of pending read requests to pass to the first arbiter to a value smaller than the number of Outstanding requests from the device. controller.

2. The controller according to claim 1, wherein the second arbiter limits the number of pending read requests to be sent to the first arbiter to one.

3. The controller according to claim 1, wherein the second arbiter limits the number of unprocessed read requests received from the communication interface to two.

4. Multiple communication interfaces, The first arbiter mediates access to memory, A second arbiter is provided between the plurality of communication interfaces and the first arbiter, and when it receives an unprocessed read request from the communication interface to the memory, it limits the number of unprocessed read requests that are passed to the first arbiter. A group controller, The aforementioned unprocessed read requests are read requests to the memory that the controller receives from a device connected to the communication interface, but before returning a response to the read request to the device.

5. Multiple communication interfaces, The first arbiter that mediates access to memory, and A second arbiter is provided between the plurality of communication interfaces and the first arbiter, and when it receives an unprocessed read request from the communication interface to the memory, it limits the number of unprocessed read requests that are passed to the first arbiter. A controller having, An image processing device connected to the aforementioned communication interface, Having, Image forming apparatus.

6. A controller according to any one of claims 1 to 4, An image processing device connected to the aforementioned communication interface, Having, Image forming apparatus.

7. The controller Communication processing that uses multiple communication interfaces, A first arbitration process that arbitrates access to memory, When an unprocessed read request to the memory is received from the communication interface, a second arbitration process limits the number of such unprocessed read requests that are passed to the first arbitration process, Execute, The aforementioned communication interface communicates with the device connected to the communication interface in accordance with the PCI Express standard. The second arbitration process limits the number of unprocessed read requests to pass to the first arbitration process to a value smaller than the number of Outstanding requests from the device. Access mediation methods.

8. The controller Communication processing that uses multiple communication interfaces, A first arbitration process that arbitrates access to memory, When an unprocessed read request to the memory is received from the communication interface, a second arbitration process limits the number of such unprocessed read requests that are passed to the first arbitration process, Execute, The aforementioned unprocessed read requests are read requests to the memory received by the controller from a device connected to the communication interface, but before the controller returns a response to the read request to the device. Access mediation methods.

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