Video signal processing device and video signal processing method

Abstract

A video signal processing device (100) addresses failure of wiring (101) for transmitting video signals, the video signal processing device (100) comprising: a signal collection circuit (103) that collects signals transmitted by the wiring (101); a failure diagnosis circuit (104) that creates failure diagnosis information relating to failure of the wiring (101) from the signals collected by the signal collection circuit (103); a switch control circuit (105) that generates, from the failure diagnosis information, switch information for shifting upper bits constituting the video signals to lower bits or for bypassing the upper bits; and a transmission-side switch circuit (106) that is disposed prior to the wiring (101) and switches the path of the bits constituting the video signals in accordance with the switch information.

Description

Video signal processing device and video signal processing method

[0001] The present disclosure relates to a video signal processing device and a video signal processing method, and more particularly to a video signal processing device and the like that can deal with failures in wiring for transmitting video signals.

[0002] Patent Document 1 points out that in a conventional video display device, when a cascade-connected driver IC fails, data cannot be passed to the driver IC and subsequent drivers, and depending on the location of the failed driver IC, the area of ​​abnormal display may become larger. Therefore, Patent Document 1 discloses that, in the event of a failure, failure information that can identify the location of the failed driver IC is used to bypass the failed driver IC and display reduced or other types of video data on the screen.

[0003] JP 2012-230168 A

[0004] However, while the technology in Patent Document 1 is based on the idea of ​​using failure information to bypass the failed part when a failure occurs, there is a problem in that the video display device cannot respond if the wiring connecting the video source and the video controller fails and the video signal does not reach the video controller. Note that "wiring failure" refers to an abnormal state such as a broken wire, short circuit, or level fixation (fixed at 0, fixed at 1, etc.) in the wiring.

[0005] Therefore, the present disclosure aims to provide a video signal processing device and a video signal processing method that can transmit a video signal in a manner that suppresses the impact of a failure even if the wiring that transmits the video signal fails.

[0006] In order to achieve the above object, a video signal processing device according to one embodiment of the present disclosure is a video signal processing device that deals with failures in wiring for transmitting video signals, and includes: a signal collection circuit that collects signals transmitted through the wiring; a fault diagnosis circuit that creates fault diagnosis information regarding a failure in the wiring from the signals collected by the signal collection circuit; a switch control circuit that generates, from the fault diagnosis information created by the fault diagnosis circuit, switch information for shifting or bypassing higher-order bits that constitute the video signal to lower-order bits; and a transmitting-side switch circuit that is arranged in a stage before the wiring and switches the path of the bits that constitute the video signal in accordance with the switch information generated by the switch control circuit.

[0007] In order to achieve the above object, a video signal processing method according to one embodiment of the present disclosure is a video signal processing method for dealing with a fault in a wiring for transmitting a video signal, and includes: a signal collection step of collecting signals transmitted over the wiring for transmitting the video signal; a fault diagnosis step of creating fault diagnosis information related to a fault in the wiring from the signals collected in the signal collection step; a switch control step of generating, from the fault diagnosis information created in the fault diagnosis step, switch information for shifting or bypassing higher-order bits constituting the video signal to lower-order bits; and a transmission-side switching step of switching the path of the bits constituting the video signal in accordance with the switch information generated in the switch control step, prior to transmission of the video signal over the wiring.

[0008] The present disclosure provides a video signal processing device and a video signal processing method that can transmit a video signal in a manner that suppresses the effects of a failure even if the wiring that transmits the video signal fails.

[0009] 7A . FIG. 7B is a circuit diagram showing the configuration of a video signal processing device according to embodiment 1. FIG. 7C is a flowchart showing the operation of the video signal processing device according to embodiment 1. FIG. 7D is a diagram showing an example of a test pattern transmitted by a test signal generation circuit when a video signal is composed of RGB color components. FIG. 7E is a diagram showing an example of an inspection result expected under normal conditions on the receiving side. FIG. 7F is a diagram showing an example of an inspection result when a fault occurs for only the R component. FIG. 7G is a flowchart showing a fault diagnosis flow by a fault diagnosis circuit. FIG. 7H is a diagram showing an example of an inspection result when a fault occurs in embodiment 1. FIG. 7I is a diagram showing an example of a fault diagnosis result corresponding to the inspection result when a fault occurs in FIG. 7A . FIG. 7IH is a flowchart showing the flow of creating switch information by a switch control circuit. FIG. 7IH is a diagram showing an example of the circuit configuration of a transmitting-side switch circuit in embodiment 1. FIG. 7IH is a circuit diagram showing the configuration of a video signal processing device according to embodiment 2. FIG. 7IH is a flowchart showing the operation of a video signal processing device according to embodiment 2. FIG. 7IH is a diagram showing detailed circuit configurations of a transmitting-side switch circuit and a receiving-side switch circuit. FIG. 7IH is a circuit diagram showing the configuration of a video signal processing device according to embodiment 2 in the case where the output of the transmitting-side switch circuit is controlled to be fixed during testing. FIG. 7IH is a flowchart showing control when a test signal is generated by a switch control circuit. FIG. 7IH is a flowchart showing the operation of switch control on the transmitting side by the switch control circuit. FIG. 7IH is a flowchart showing the operation of switch control on the receiving side by the switch control circuit. 17A is a diagram showing an example of a fault diagnosis result corresponding to the inspection result at the time of a fault in FIG. 17A . FIG. 17B is a diagram showing an example of values ​​before and after a switch of a priority selection register in which video signals are rearranged in order of priority. FIG. 17C is a circuit diagram showing a configuration of a video signal processing device according to embodiment 3. FIG. 17D is a diagram showing an example of inspection results at the time of a fault in embodiment 3. FIG. 17E is a diagram showing an example of values ​​before and after a switch of a priority selection register in which video signals are rearranged in order of priority. FIG. 17F is a diagram showing an example of a fault diagnosis result corresponding to the inspection result at the time of a fault in FIG. 17A . FIG. 17G is a diagram showing an example of values ​​before and after a switch of a priority selection register in which video signals are rearranged in order of priority in embodiment 4. FIG. 17H is a diagram showing an example of a fault diagnosis result corresponding to the inspection result at the time of a fault in FIG. 17A . FIG. 17H is a diagram showing an example of values ​​before and after a switch of a priority selection register in which video signals are rearranged in order of priority in embodiment 4.28A is a circuit diagram showing the configuration of a video signal processing device according to embodiment 5. FIG. 28B is a diagram showing an example of mapping of data on LVDS lanes. FIG. 28C is a diagram showing a change in mapping of data on LVDS lanes due to a failure in embodiment 5. FIG. 28D is a diagram showing an example of an inspection result at the time of a failure in embodiment 5. FIG. 28E is a diagram showing an example of a fault diagnosis result corresponding to the inspection result at the time of the failure of FIG. 28A. FIG. 28F is a diagram showing an example of values ​​before and after a switch of a priority selection register in which video signals are rearranged in order of priority. FIG. 28F is a circuit diagram showing the configuration of a video signal processing device according to embodiment 6. FIG. 28G is a flowchart showing a fault diagnosis method compatible with a plurality of video interfaces. FIG. 28H is a flowchart showing a switch control method for a plurality of video interfaces. FIG. 28I is a circuit diagram showing the configuration of a video signal processing device according to embodiment 7.

[0010] Embodiments of the present disclosure will be described in detail below with reference to the drawings. Each embodiment described below represents a specific example of the present disclosure. The numerical values, video signal bit configurations, failure examples, test pattern examples, circuit elements, circuit element layout and connection configurations, steps, and step sequences shown in the following embodiments are merely examples and are not intended to limit the present disclosure. Furthermore, each figure is not necessarily an exact representation. In each figure, substantially identical components are designated by the same reference numerals, and redundant descriptions are omitted or simplified. Furthermore, "connection" refers to an electrical connection, and includes not only a direct connection between two circuit elements but also an indirect connection between two circuit elements with another circuit element inserted between them. Furthermore, "wiring failure" includes not only a failure caused by the wiring itself but also a failure caused by a circuit element along the wiring path.

[0011] Conventionally, various devices have been designed to be fault-tolerant, with fail-safe functions to prevent the device from ceasing operation even in the event of a failure, allowing the device to safely shut down or safely maintain operation. In recent years, there has been an increasing demand for functional safety mechanisms in in-vehicle image processing devices, such as designs that take into account safe function shutdown and degradation of video display functionality in the event of a failure. The present disclosure proposes a video signal processing device that, in the event of a wiring failure, enables video display to continue without stopping the video display, while suppressing degradation of video functionality due to the failure. Hereinafter, first to seventh embodiments of a video signal processing device according to the present disclosure will be described with reference to the drawings.

[0012] (Embodiment 1) (Device Configuration) Fig. 1 is a circuit diagram showing the configuration of a video signal processing device 100 according to embodiment 1. In this embodiment, as an example, a video signal is composed of 8 bits for each of the RGB components (in order from the most significant bit, R[7] to R[0], G[7] to G[0], and B[7] to B[0], respectively) and a 3-bit video control signal (simply referred to as "control signal" in the figure). Fig. 1 shows that the most significant bits (R[7], G[7], B[7]) of the wiring for each of the RGB components are disconnected.

[0013] 1, video signal processing device 100 is a device that deals with failures in wiring 101 for transmitting and receiving video signals, and includes test signal generation circuit 102 that transmits test signals (i.e., test patterns) to wiring 101, signal collection circuit 103 that collects inspection results for failures in wiring 101 (i.e., signals transmitted through wiring 101), fault diagnosis circuit 104 that creates fault diagnosis results from the inspection results (i.e., fault diagnosis information regarding faults in wiring 101), switch control circuit 105 that generates switch information for shifting higher-order bits to lower-order bits or bypassing them from the fault diagnosis results, and transmission-side switch circuit 106 that is arranged upstream of wiring 101 and switches the path of video signal bits in accordance with the switch information. Here, "shifting higher-order bits to lower-order bits" means shifting a bit diagnosed as having a failure to a lower-order bit.

[0014] The test signal generation circuit 102 is not necessarily required, because the video signal transmitted through the wiring 101 can be used as a test pattern instead. Furthermore, the arrangement of the test signal generation circuit 102, signal collection circuit 103, fault diagnosis circuit 104, and switch control circuit 105 is not limited to either the transmission side or the reception side of the video signal.

[0015] (Operation Flowchart) Fig. 2 is a flowchart showing the operation of the video signal processing device 100 according to embodiment 1. An overview of how each component circuit operates will be described using the flowchart in Fig. 2.

[0016] In S201, the test signal generation circuit 102 transmits a test signal onto the wiring 101.

[0017] In S202, the signal collecting circuit 103 collects the test results (signal collecting step).

[0018] In S203, fault diagnosis circuit 104 diagnoses a fault in wiring 101 based on the inspection results (fault diagnosis step).

[0019] In S204, if the diagnosis by the fault diagnosis circuit 104 shows that there is no fault (No in S204), the process returns to sending the test signal again (S201). On the other hand, if there is a fault (Yes in S204), in S205 the test signal generation circuit 102 creates switch information to shift the bits of the video signal (switch control step).

[0020] In S206, the transmission side switch circuit 106 switches the wiring path of the video signal in accordance with the switch information (transmission side switching step).

[0021] The wiring and each component circuit will be described in detail below.

[0022] (Wiring 101) The wiring 101 is used to connect the transmitting side and receiving side of a video signal. This wiring 101 can be replaced with wiring within an LSI (i.e., integrated circuit), wiring on a board (i.e., circuit board), or a cable connecting devices. Furthermore, the wiring 101 is characterized by including a parallel cable or a cable for a high-speed interface such as LVDS (Low Voltage Differential Signaling) or MIPI (Mobile Industry Processor Interface). Although not shown, the wiring 101 may also include various circuit elements, such as electronic components and connectors, arranged along its path.

[0023] The video signal is a multi-bit video data signal expressed in a color information format such as RGB or YUV, and further includes video control signals such as a clock signal and vertical and horizontal synchronization signals required for video display.

[0024] (Test Signal Generation Circuit 102) When testing for a fault in the wiring 101, the test signal generation circuit 102 switches the transmission path so that a test pattern can be sent onto the wiring 101, and transmits the test pattern to the receiving side via the wiring 101. FIG. 3 is a diagram showing an example of a test pattern transmitted by the test signal generation circuit 102 when the video signal is composed of RGB color components. A sequence of 27 test patterns indicated by test pattern numbers (1 to 27) is shown here. In this test pattern, each bit of the video data signal and the video control signal is tested, pattern by pattern, with the tested bit set to 1 and the untested bit set to 0. This is performed for all bits, and by toggling each bit in turn (i.e., shifting the tested bit one bit at a time), it is confirmed that the signal can be transferred correctly.

[0025] (Signal Collection Circuit 103) The signal collection circuit 103 receives the test pattern transmitted to the wiring 101 and collects the test results. The signal collection circuit 103 may be a simple memory element (register) that stores the data on the wiring 101 in order at the timing when the test pattern is transmitted. FIG. 4 is a diagram showing an example of the test results expected on the receiving side under normal conditions. Twenty-seven test results corresponding to the test patterns in FIG. 3 are shown. A normal test result will be the same data as the test pattern, with the test target bits of each pattern being 1 and the other bits being 0.

[0026] 5 shows an example of various test results when a fault occurs for only the R component. The R component has 8 bits, and the test is performed using 8 patterns to toggle the 8 test target bits in order (i.e., shift the test target bits one bit at a time).

[0027] The upper diagrams (i.e., (a1) and (a2) in Figure 5) show an example of a broken wire, and in the third test result, R[5] is expected to be 1, but since it is 0 ((a1) in Figure 5), the diagnosis result is that R[5] is broken or stuck at 0 ((a2) in Figure 5).

[0028] The middle diagram (i.e., (b1) and (b2) of Figure 5) shows an example of a short circuit, where in the third test result, only R[5] is expected to be 1, but at the same time R[4] is also 1, and in the fourth test result, only R[4] is expected to be 1, but at the same time R[5] is also 1 ((b1) of Figure 5), so the diagnosis result is that R[5] and R[4] are short-circuited ((b2) of Figure 5).

[0029] The lower diagram (i.e., (c1) and (c2) in Figure 5) shows an example of a stuck-at-1 condition, where a 0 is transmitted when not being tested, but because R[5] is always 1 ((c1) in Figure 5), the diagnosis result is that the device is stuck at 1 ((c2) in Figure 5).

[0030] (Fault diagnosis circuit 104) Fault diagnosis circuit 104 diagnoses faults in bits of wiring 101 based on the inspection results of signal collection circuit 103. FIG.

[0031] First, in S601, fault diagnosis circuit 104 receives the test results from signal collection circuit 103. Then, the test circuit 104 repeatedly diagnoses whether or not the test target bit is faulty for the number of bits of the video signal (S601a to S601b).

[0032] In the repetition, first, if the test target bit is 1 in S602 (Yes in S602) and all non-test target bits are 0 in S603 (Yes in S603), then in S605 the fault diagnosis circuit 104 determines that the test target bit is operating normally.

[0033] Furthermore, if the test target bit is 1 in S602 (Yes in S602) and there is a non-test target bit that is 1 in S603 (No in S603), the non-test target bit that is not originally set to 1 has been set to 1, and therefore in S606 the fault diagnosis circuit 104 determines that there is a short circuit with the test target bit or that the non-test target bit is stuck at 1.

[0034] Furthermore, if the test target bit is not set to 1 in S602 but is set to 0 (No in S602) and all bits not to be tested are set to 0 (Yes in S604), the test target bit, which should normally transmit 1, is set to 0, and therefore the fault diagnosis circuit 104 determines in S607 that the test target bit is broken or stuck at 0.

[0035] Furthermore, if the test target bit is not set to 1 in S602 but is set to 0 (No in S602), and there is a bit not being tested that is set to 1 in S604 (No in S604), then in S608 the fault diagnosis circuit 104 determines that the test target bit is either disconnected or stuck at 0. In addition, because the not-test target bit that is not originally set to 1 is set to 1, the fault diagnosis circuit 104 determines that the not-test target bit is short-circuited with the test target bit or stuck at 1.

[0036] In S609, fault diagnosis circuit 104 notifies switch control circuit 105 of the fault diagnosis result.

[0037] Faults may involve either a break or a short circuit, or a mixture of both. The fault diagnosis flow of FIG. 6 allows for rough fault diagnosis.

[0038] In addition, in the fault diagnosis flow of FIG. 6, a judgment is made for each test pattern, but this is not limited to this. It is also considered effective to check whether the bit is fixed to 0 or 1 across multiple patterns, causing the signal to be stuck.

[0039] 7A is a diagram showing an example of the test results at the time of a failure in the first embodiment. RGB components as video signal bits and each bit of the video control signal are arranged vertically, and the test results of each test pattern are arranged horizontally. In the first embodiment, as shown in FIG. 1, as an example, a case is assumed in which the most significant bit of each RGB component (i.e., R[7], G[7], and B[7]) is broken, and the first, ninth, and seventeenth test patterns are detected as 0, even though they should be 1.

[0040] 7B is a diagram showing an example of a fault diagnosis result corresponding to the inspection result at the time of the fault in FIG. 7A. Each column shows the fault diagnosis result, priority (priority number), and name of the video signal after the transmitting switch, corresponding to the video signal bit. The fault diagnosis circuit 104 determines that there is a break or that the most significant bit of each RGB component being tested is 0, even though it should be 1. On the other hand, since all bits not being tested are 0, it can be determined that there is no short circuit with the bit being tested or that the bit is not fixed at 1.

[0041] The fault diagnosis results are shown as an example, and can also be presented as a table that shows the details of the fault condition, such as a break in the wiring 101, a short circuit, a stuck at 0, or a stuck at 1, and are not limited to the format shown in FIG. 7B.

[0042] Furthermore, the upper bits of the color components have a large effect on the structure and color of the image. In this embodiment, the priority of the upper bits is assumed to be higher, and the priority numbers of the video signals are also shown in Figure 7B. Note that the smaller the priority number, the higher the priority.

[0043] (Switch Control Circuit 105) The switch control circuit 105 generates switch information for switching the transmitting side switch circuit 106 based on the failure diagnosis result.

[0044] Normally, if there is a failure on the upper bit side, the upper bits cannot be transmitted, resulting in significant image distortion and color abnormalities. To suppress such abnormalities, in this embodiment, the switch control circuit 105 creates switch information for shifting the upper bits of each component to the lower bits based on the failure diagnosis results shown in Figure 7B.

[0045] In the first embodiment, the switch control circuit 105 calculates the number of shifts (that is, the number of bits to shift) for shifting the transmission side switch circuit 106 as the switch information.

[0046] FIG. 8 is a flowchart showing a flow of creating switch information by the switch control circuit 105.

[0047] First, in S801, switch control circuit 105 receives the fault diagnosis result from fault diagnosis circuit 104.

[0048] In "calculating the R component" in S802, the switch control circuit 105 checks the fault diagnosis result, looping from the lower-order bits with lower priority to the higher-order bits to check whether a fault exists. If no fault is found (No in S802), the switch control circuit 105 checks whether a fault exists on the next higher-order bit side (S801a to S801b).

[0049] In S803, if there is a fault (Yes in S802), the switch control circuit 105 determines the priority number of the faulty bit. The priority number of each component ranges from 0 to 7, and since it is checked from the lowest bit, the lowest priority number among the faulty bits is determined. In the first embodiment, since the highest bit is faulty, the priority number is 0.

[0050] In steps S804 and S805, the switch control circuit 105 calculates priority numbers for the other color components in the same manner as in the "calculation of the R component."

[0051] In step S806, the switch control circuit 105 calculates the maximum priority number among the three color components. In the first embodiment, the most significant bits of the three color components are disconnected, so the maximum priority number is 0 in common.

[0052] In S807, the switch control circuit 105 adds 1 to the maximum priority number to calculate the shift number. In the first embodiment, the maximum priority number 0 is added by 1, and the shift number is 1.

[0053] In S808, the switch control circuit 105 generates switch information for shifting the bits of the three color components to the right (i.e., shifting them downwards) by the shift number (here, 1).

[0054] 7B shows the result of switching after the transmission side switch by shifting, in which the most significant bits of each color component are shifted to the least significant bits by one bit. Furthermore, the switch control circuit 105 performs a fixing control of the fault signal, and more specifically, fixes the potential so that the most significant bit of each RGB color component does not become unstable and the voltage of the bit of the faulty wiring 101 does not become unstable (i.e., float) due to a break in the wiring.

[0055] In the flow of switch control by shifting shown in Fig. 8, the RGB components are shifted by the same number of bits, but switch information may be created so that components without faults are not shifted and only faulty video signal components are shifted. In this case, the number of shifts may differ for each color component depending on the faulty bit.

[0056] Alternatively, for each color component, only the bits lower than the faulty bit may be shifted to lower bits. For example, if only bit R[5] among bits R[7] to R[0] fails, R[7] and R[6] may be left through, and switch information may be created to shift each of bits R[5] to R[1] by one bit toward the lower bits.

[0057] (Transmitting-Side Switching Circuit 106 ) The transmitting-side switching circuit 106 controls switching and fixing of the transmission path of the video signal in accordance with the switching information of the switch control circuit 105 .

[0058] 9 is a diagram showing an example of the circuit configuration of the transmitting-side switch circuit 106 in embodiment 1. In embodiment 1, it is only necessary to shift each of the RGB components by the same shift number, and as one of the switch circuit options, it is possible to configure the switch circuit with an 8-bit barrel shifter as shown in FIG.

[0059] (Effect) Normally, when the upper bits fail, significant image distortion and color abnormalities occur. When the video signal shows a vehicle and its surroundings, image distortion makes it difficult to identify the vehicle. Furthermore, color abnormalities can cause localized appearance of colors that are significantly different from the surroundings, making it difficult to grasp the perspective of the vehicle and potentially interfering with driving operations.

[0060] According to this embodiment, by detecting a failure in the upper bits and shifting the color components to the lower bits, image distortion and color abnormalities can be suppressed.

[0061] (Shifting with Bypass Switch Control) In the first embodiment, a barrel shifter is used as the transmitting switch circuit 106 to simultaneously shift all eight bits of each of the RGB components for switch control, but this method may be replaced with another switch control method. As one example, a switch circuit may be configured so that each bit of a video signal can select and output an arbitrary video signal, and one bit of each of the eight bits of the RGB components may be bypassed so as to detour to the lower bit side, and this may be replaced with a method in which this is repeated eight bits, making it possible to perform switch control similar to shifting all of the color components.

[0062] (Switch circuit disposed on the receiving side) Furthermore, the receiving side may further include a switch circuit that shifts in the opposite direction to that on the transmitting side. This receiving side switch circuit may be, for example, the barrel shifter shown in FIG. 9 in the first embodiment configured to shift toward the most significant bits (i.e., in the opposite direction). By shifting in the opposite direction using the receiving side switch circuit, it is possible to improve the decrease in brightness level caused by shifting the failed most significant bits on the transmitting side, and to restore the brightness level to a level close to the original 256 gradations.

[0063] (Embodiment 2) Next, a video signal processing device according to embodiment 2 will be described. In the embodiments from embodiment 2 onwards, differences from embodiment 1 will be mainly described, and descriptions of similar parts will be omitted. Parts corresponding to those in embodiment 1 will be described using the same reference numerals.

[0064] In the first embodiment, an advantage is that when a higher-order bit of a video signal is faulty, the higher-order bit can be shifted to a lower-order bit, thereby suppressing image display distortion and color abnormalities. On the other hand, there is a problem in that the brightness decreases when the higher-order bit of a faulty video signal is shifted to a lower-order bit.

[0065] Furthermore, for example, if all bits of the R component are faulty, the R component cannot be transmitted because all bits are faulty even if the bits are shifted within the range of the color components in embodiment 1. In other words, the receiving side receives only the B and G components, but not the R component, resulting in a color abnormality.

[0066] Furthermore, if a video control signal such as a clock signal fails, the video control signal is essential for image display, and there is a problem that the video cannot be reproduced on the receiving side by shift control on the transmitting side alone. In the second embodiment, a configuration is proposed to solve these problems.

[0067] 10 is a circuit diagram showing the configuration of a video signal processing device 200 according to embodiment 2. As shown in Fig. 10, the video signal processing device 200 is configured such that a receiving-side switch circuit 207 is additionally provided on the receiving side of the video signal compared to the configuration of the video signal processing device 100 according to embodiment 1, and the internal circuits of the transmitting-side switch control circuit 205 and the transmitting-side switch circuit 206 are changed accordingly. The wiring 101, the test signal generation circuit 102, the signal collection circuit 103, and the fault diagnosis circuit 104 are the same as those in embodiment 1.

[0068] In the second embodiment, the receiving-side switch circuit 207 added to the receiving side of the video signal can return the video signal to the original wiring connection (i.e., bit) by switching to shift or bypass in the opposite direction to the transmitting-side switch circuit 206. In the second embodiment, the operation of bypassing the video signal will be described using an example in which the most significant bit of the RGB components is disconnected.

[0069] (Operation Flowchart) FIG. 11 is a flowchart showing the operation of the video signal processing device 200 according to the second embodiment.

[0070] Steps S201 to S204 are the same as those in the first embodiment.

[0071] If a failure is detected in S204 (Yes in S204), the switch control circuit 205 creates switch information for the transmitting and receiving sides so as to bypass the failed signal according to the priority in S210.

[0072] In addition, in S211, the transmitting side switch circuit 206 switches the wiring route based on the generated transmitting side switch information.

[0073] In addition, in S212, the receiving side switch circuit 207 switches the wiring route so as to bypass the transmitting side switch circuit 206 in the opposite direction.

[0074] After switching the wiring route, the process returns to S201, and at the timing when a fault is to be checked, the test pattern is transmitted again to repeat the fault check and diagnosis.

[0075] Each component circuit of the second embodiment will be described in detail below.

[0076] (Transmitting-side switch circuit 206 and receiving-side switch circuit 207) Fig. 12 is a circuit diagram showing the detailed circuit configuration of the transmitting-side switch circuit 206 and the receiving-side switch circuit 207. In the second embodiment, the switch circuit configuration shown in Fig. 12 is used so that the transmission path can be switched while bypassing a high-priority signal.

[0077] In the transmitting switch circuit 206, a multiplexer 210 is arranged to receive multiple (here, 27) video signals as input, and a transmitting priority selection register TXREG 211 is arranged to select the video signal to be transmitted (i.e., output) to the wiring 101 from the 27 input signals. As shown in the figure, the inputs to the multiplexer 210 are assigned numbers from 0 to 26 in order, corresponding to the number of video signals, with the lowest number having the highest priority. Here, the multiplexer 210 functions as a selector.

[0078] In the second embodiment, the inputs to the multiplexer 210 are the clock signal, horizontal sync signal, vertical sync signal, R[7], G[7], B[7], R[6], G[6], B[6], ... R[0], G[0], B[0] in that order, and priorities are assigned in the order of 0, 1, 2, 3, 4, 5, 6, 7, 8, ... , 26. Furthermore, as the initial values ​​of the transmitting side priority selection register TXREG211, priority numbers of 0, 1, 2, ... are assigned to TXREG[0], TXREG[1], TXREG[2], ... , TXREG

[26] of the transmitting side priority selection register TXREG211, respectively. , 26 in this order, a clock signal, a horizontal sync signal, a vertical sync signal, R[7], G[7], B[7], ... R[0], G[0], B[0] signals are transmitted on the wiring 101 through the multiplexer 210 on the transmitting side in the initial state according to the priority.

[0079] The receiving side switch circuit 207 has a multiplexer 212 that receives as input the video signals received from the wiring 101, and a receiving side priority selection register RXREG 213 is configured to select the video signals received from the wiring 101. The inputs to the multiplexer 212 are assigned numbers in order from 0 to the number of video signals, with the lowest number having the highest priority. Here, the multiplexer 212 functions as a selector.

[0080] As with the transmitting side, the inputs to the multiplexer 212 of the receiving side switch circuit 207 are clock signal, horizontal sync signal, vertical sync signal, R[7], G[7], B[7], R[6], G[6], B[6], ... R[0], G[0], B[0] in that order, with priorities assigned as 0, 1, 2, 3, 4, 5, 6, 7, 8, ... , 26. Furthermore, as the initial values ​​of the receiving side priority selection register RXREG213, priority numbers of 0, 1, 2, ... are assigned to RXREG[0], RXREG[1], RXREG[2], ... , RXREG

[26] of the receiving side priority selection register RXREG213, respectively. , 26 in that order, the clock signal, horizontal sync signal, vertical sync signal, R[7], G[7], B[7], ... R[0], G[0], B[0] signals coming from the wiring 101 are received through the receiving side multiplexer 212 in the initial state.

[0081] When bypassing a video signal on the transmitting side, the priority number of the failed high-priority video signal is set in the low-priority transmitting side priority selection register TXREG 211. For example, in Fig. 12, if R[7] with a priority number of 3 is disconnected, the setting of TXREG

[24] in the transmitting side priority selection register TXREG 211 for R[0] is changed from 24 to 3 so that R[7] is transmitted using the wiring of R[0], which has a low priority, and the R[7] signal is transmitted using the wiring of R[0].

[0082] Furthermore, on the receiving side, since a video signal different from the initial state is transferred on the wiring 101, it is necessary to return the bit to the position of the original video signal. Therefore, in contrast to the transmitting side, the priority number of the bypassed low-priority wiring is set in the original high-priority receiving side priority selection register RXREG213. For example, if the faulty R[7] signal is bypassed and transmitted using the R[0] wiring, on the receiving side, in contrast to the transmitting side, the setting of RXREG[3] of the high-priority R[7] receiving side priority selection register RXREG213 is changed from 3 to 24, thereby making it possible to receive the R[7] signal coming from the R[0] wiring. This makes it possible to return the bit coming from the R[0] wiring on the receiving side to the position of the original R[7] signal.

[0083] As described above, since the transmitting-side switch circuit 206 and the receiving-side switch circuit 207 switch in conjunction with each other to bypass in the opposite direction, it is more efficient to have a single switch control circuit 205 that controls both switches simultaneously, rather than placing them on the transmitting side and the receiving side separately. Furthermore, since the switch control circuit 205 is consolidated into a single circuit rather than having separate circuits on the transmitting and receiving sides, implementation costs can be reduced. Also, even when one video processing LSI is connected to multiple devices or when there are multiple wiring connections, costs can be reduced by consolidating the switch control circuit 205.

[0084] Additionally, since video control signals such as clock signals and the higher bits of color data information are given higher priority in advance, in this embodiment the switch control circuit 205 determines the priority based on this premise.

[0085] However, there are no particular rules as to which of the video control signal and the upper bits of the color information should be given higher priority, or in what order the upper bits of the three color components should be prioritized, so the settings are not limited to those in embodiment 2, and it is also possible to change the priority of a signal by providing a new switch circuit on the transmitting and receiving sides that can arbitrarily change the priority of the signal.

[0086] 12, for convenience of explanation, the multiplexer 210 and the transmission priority selection register TXREG 211 are arranged in order of decreasing priority, but their actual positions on the circuit do not need to be arranged in this order, and they may be arranged in a different order, such as in the order of the video signal terminals. In FIG. 10, the wiring is arranged in the order of 8 bits of the R component, 8 bits of the G component, 8 bits of the B component, and the video control signal, so the internal arrangement of the transmission side switch circuit 206 can also be rearranged to match this order. The same applies to the reception side switch circuit 207.

[0087] 1 and 10, the test signal generation circuit 102 is placed after the transmission side switch circuit 206. This allows test data to be transmitted without being affected by the switch operation of the transmission side switch circuit 206.

[0088] 1 and 10, the signal collection circuit 103 is arranged in the preceding stage of the receiving switch circuit 207. This allows the pattern transmitted on the wiring 101 to be received as the inspection result without being affected by the switch operation of the receiving switch circuit 207.

[0089] (Test signal generation in transmitting-side switch circuit 206) On the other hand, by configuring the transmitting-side switch circuit 206 as shown in Fig. 12, it is possible to transmit a test pattern similar to that of the test signal generation circuit 102 onto the wiring 101 by controlling the output of the transmitting-side switch circuit 206 to be fixed during testing without providing the test signal generation circuit 102. Fig. 13 is a diagram showing the configuration of a video signal processing device 200 according to embodiment 2 when controlling the output of the transmitting-side switch circuit 206 to be fixed during testing. What differs from the configuration in Fig. 10 is that the test signal generation circuit 102 is not provided.

[0090] 14 is a flowchart showing the control of test signal generation by the switch control circuit 205. First, in S1401, the switch control circuit 205 sets the output of all video signals to a fixed value of 0 at the start of a test in accordance with the value of the transmission priority selection register TXREG.

[0091] Next, in S1402, the switch control circuit 205 controls each video signal bit as a test target to be fixed to 1 in accordance with the value of the transmission-side priority selection register TXREG. Next, in S1403, the switch control circuit 205 performs switch control to return the test target bits that were fixed to 1 to fixed to 0 in accordance with the value of the transmission-side priority selection register TXREG. Thereafter, the switch control circuit 205 sequentially toggles the test target video signal bits in order (i.e., shifts the test target bits one bit at a time) in accordance with the value of the transmission-side priority selection register TXREG (S1401a to S1401b). In this way, by the switch control circuit 205 controlling the transmission-side switch circuit 206 during testing, a test pattern can be transmitted to the wiring 101 for testing.

[0092] In this way, after toggling all video signals (i.e., shifting the test target bits one bit at a time) and transmitting the test pattern, in S1404, the switch control circuit 205 returns the transmission side priority selection register TXREG from the fixed control value and sets it to output video signals in order to return from test mode to normal mode.

[0093] (Transmission-Side Switch Control of Switch Control Circuit 205) FIG. 15 is a flowchart showing the operation of switch control on the transmission side by switch control circuit 205.

[0094] First, in S 1501 , switch control circuit 205 receives the fault diagnosis result from fault diagnosis circuit 104 .

[0095] In S1502, the switch control circuit 205 initializes switch information according to the priority number of the video signal bit. Specifically, the switch information is the setting values ​​of the transmitting-side priority selection register TXREG 211 and the receiving-side priority selection register RXREG 213 shown in FIG. 12.

[0096] By initializing the switch information, switch control can be performed from the initial state without being affected by past failure states.

[0097] Next, the switch control circuit 205 switches the wiring of the video signal having a fault, starting from the bit with the highest priority to the bit with a lower priority that is not having a fault (S1502a to S1502b).

[0098] In S1503, the switch control circuit 205 checks whether there is a fault in the high-priority bit based on the fault diagnosis result. If there is no fault (No in S1503), the switch control circuit 205 checks whether there is a fault in the next high-priority bit. If there is a fault (Yes in S1503), the switch control circuit 205 determines which low-priority bit to bypass the target high-priority bit by searching the bits in order from lowest priority to highest priority (S1503a to S1503b).

[0099] In this loop, in S1504, the switch control circuit 205 checks whether there is a failure in the low priority bit.

[0100] If the low-priority bit being searched for is not faulty (Yes in S1504), bypassing is possible, so in S1505 the switch control circuit 205 changes the high-priority number to be set in the low-priority register TXREG being searched for. Then, in S1506, the switch control circuit 205 sets the value of the high-priority register TXREG so that the faulty high-priority bit is fixed.

[0101] On the other hand, if the low priority bit is faulty (No in S1504), in S1507, the switch control circuit 205 sets the value of the register TXREG so that the faulty low priority bit is fixed, so that the fault does not cause an undefined state.

[0102] In S1508, the switch control circuit 205 increments the fault bit counter, which counts the number of high-priority bits that have been bypassed due to a fault and the number of low-priority faulty bits that have been found during the search on the lower-order bit side.

[0103] In this way, the switch control circuit 205 repeats the above allocation of high-priority bits to low-priority bits until it completes the process of allocating all faulty high-priority bits to the lower-order bit side, or until there are no more low-priority bits available for allocation (S1502a to S1502b, S1503a to S1503b).

[0104] In the above flow, the switch control circuit 205 sets the value of the post-bypass transmission side priority selection register TXREG 211 as switch information.

[0105] (Reception-Side Switch Control of Switch Control Circuit 205) FIG. 16 is a flowchart showing the operation of switch control on the reception side by switch control circuit 205.

[0106] First, in S1601, the switch control circuit 205 reverses the setting of the transmitting priority selection register TXREG (i.e., reverses the relationship between the register to be set and the setting value) and creates the receiving priority selection register RXREG setting. Specifically, assuming that X and Y are priority numbers, when the transmitting priority selection register TXREG[X] = Y, the receiving priority selection register RXREG[Y] = X is set, and this is repeated for the number of video signal bits (S1601a to S1601b). For example, RXREG[TXREG[i]] = i is set.

[0107] Next, in S1602, the switch control circuit 205 uses the failure bit counter counted in FIG. 15 to set the low-priority side of the receiving-side priority selection register RXREG to a fixed control value (S1602a to S1602b). This is because the low-priority bits used in bypass and the failure bits on the low-priority bit side cannot be used as video signals and are therefore fixed. The fixed control is performed by setting an unused value that is not assigned to a video signal in the receiving-side priority selection register RXREG. For example, by setting RXREG[26-i] = 31 (i = 0 to N-1), the low-priority bits of 27 or higher are fixed.

[0108] As described above, the switch control on the receiving side involves switching operations to bypass in the opposite direction to the switch control on the transmitting side, so there is no need to search for low priority bits and it can be created in a few steps from the switch information on the transmitting side.

[0109] In the above explanation, the switch control flows for the sending and receiving sides are separated and the switch information is created, but what is shown in this embodiment is just one example of a switch control method, and the present invention is not limited to this. It is also possible to create switch information for the sending and receiving sides simultaneously.

[0110] (Test Results and Fault Diagnosis Results in Embodiment 2) Fig. 17A is a diagram showing an example of test results at the time of a fault in embodiment 2. RGB components as video signal bits and each bit of the video control signal are arranged vertically, and the test results of each test pattern are arranged horizontally. In embodiment 2, as shown in Fig. 10, the most significant bit of the RGB components of the video signal is disconnected, so the most significant bits of the RGB components in test results 1, 9, and 17 do not toggle to 1 but remain 0.

[0111] 17B is a diagram showing an example of a fault diagnosis result corresponding to the inspection result at the time of the fault in FIG. 17A. Each column shows the fault diagnosis result, priority number, video signal name after the switch on the transmitting side, and video signal name after the switch on the receiving side for each video signal bit. Arrows also indicate the path taken by the faulty video signal bit from the transmitting side to the receiving side.

[0112] The fault diagnosis procedure in fault diagnosis circuit 104 is the same as in embodiment 1. The fault diagnosis result shows that the most significant bit of the three components of the video signal is broken, so that video signal bits R[7], G[7], and B[7] are broken, and the other bits are normal.

[0113] Priority numbers are assigned according to the importance of the video signal, with video control signals such as the clock signal, horizontal sync signal, and vertical sync signal being given the highest priority. Priorities are then assigned from the most significant bit to the least significant bit of each color component. By expanding the priority setting to cover all video signal bits, rather than limiting it to each color component, it is possible to perform signal bypass control across color component boundaries.

[0114] The column after the transmitting side switch in Figure 17B shows the video signal names after the switch as a result of the transmitting side switch control shown in Figure 15. First, of the failed bits, R[7] on the high-priority side has the highest priority of 3. Therefore, a search is performed for non-failed bits from R[7] and it is bypassed to B[0], which has the lowest priority and a priority number of 26. Next, G[7] on the high-priority side has a high priority of 4, so a similar search is performed for bits and it is bypassed to G[0], which has a priority number of 25 on the low-priority side. Next, B[7] on the high-priority side has a high priority of 5 and is bypassed to R[0], which has a priority number of 24 on the low-priority side. Furthermore, the failed R[7], G[7], and B[7] are fixedly controlled.

[0115] The column after the receiving side switch in Figure 17B shows the video signal names after the receiving side switch as a result of the receiving side switch control shown in Figure 16. The receiving side switch control switches to bypass in the opposite direction to the transmitting side switch, and controls to return the video signal bypassed on the transmitting side to its original wiring bit position. The receiving side switch control in Figure 16 returns the R[7] signal bypassed by the priority 26 wiring to the priority 3 signal position, the G[7] signal bypassed by the priority 25 wiring to the priority 4 signal position, and the B[7] signal bypassed by the priority 24 wiring to the priority 5 signal position.

[0116] (Switch Settings of Priority Selection Registers TXREG and RXREG) Figure 18 is a diagram showing an example of the values ​​of the priority selection registers TXREG and RXREG, which arrange video signals in order of priority, before and after switching. The arrows in the diagram indicate the path taken by the video signal as the setting of the priority selection register is changed. Each column in the diagram shows the priority of the video signal, the video signal name, the initial setting value of the transmitting side priority selection register TXREG and the setting value after switching, and the initial setting value of the receiving side priority selection register RXREG and the setting value after switching. In the initial state, the priority selection registers TXREG and RXREG are set to 0, 1, 2, ..., 26, in order, according to the priority of each video signal.

[0117] In the second embodiment, since the most significant bit of the RGB components of the video signal is disconnected, the transmitting-side switch control flow shown in FIG. 15 causes the transmitting-side switch circuit 206 to set the priority numbers R[7], G[7], and B[7] in the low-priority priority selection registers TXREG

[24] to

[26] , respectively, thereby bypassing the high-priority signals R[7], G[7], and B[7] to the low-priority signals R[0], G[0], and B[0], respectively.

[0118] Furthermore, in the switch setting after transmission, the priority selection registers TXREG[3] to [5] of R[7], G[7], and B[7] are set to fixed control values.

[0119] In addition, the switch control on the receiving side performs switch control to bypass in the opposite direction to the switch control on the transmitting side according to the switch control flow on the receiving side shown in Fig. 16. In other words, by setting low-priority bypass numbers to RXREG[3] to [5], the signals R[7], G[7], and B[7] are returned to their original wiring positions, so that the most significant bit signals transmitted with the lower bits of priority 24 to 26 can be received.

[0120] Also, the bits on the low priority side are fixed so that the high priority bits that have been bypassed due to a failure are not used.

[0121] (Effect) This makes it possible to improve the decrease in brightness level that occurs when shifting the upper bits in embodiment 1, and to restore the brightness level to the original gradation. Furthermore, in embodiment 1, the entire RGB color information is shifted to the lower bits to suppress image distortion and color abnormalities, but in embodiment 2, by providing a switch circuit on the receiving side as well, it becomes possible to control so that only the upper bits with a specific fault are bypassed to the lower bits.

[0122] In the second embodiment, a case where the most significant bit of the color information is disconnected has been described. In the third embodiment, the range of failures is expanded to a case where all 8 bits of the R component are disconnected, and control of the switch circuit and bypass operation of the switch circuit are shown.

[0123] Fig. 19 is a circuit diagram showing the configuration of a video signal processing device 200 according to embodiment 3. In Fig. 19, all 8 bits of the R component are disconnected in the wiring 101. The circuit other than the disconnected portion is the same as in embodiment 2.

[0124] In this embodiment, since all of the R components are faulty, the arrows in the transmitting switch circuit 206 and the receiving switch circuit 207 in Fig. 19 show how the R component signal is bypassed using the lower bits of the G and B components. Note that the bypass route in the figure is simplified and different from the actual route to avoid the arrows crossing at the switch circuits and making the diagram complicated.

[0125] (Test Results and Fault Diagnosis Results) Fig. 20A is a diagram showing an example of test results at the time of a fault in embodiment 3. RGB components as video signal bits and each bit of the video control signal are arranged vertically, and the test results of each test pattern are arranged horizontally. In embodiment 3, as shown in Fig. 19, all 8 bits of the R component are disconnected, so in test results 1 to 8, the bits of the R component do not toggle to 1 but are 0, indicating a fault.

[0126] FIG. 20B is a diagram showing an example of a fault diagnosis result corresponding to the inspection result at the time of the fault in FIG. 20A. Each column shows, for each video signal bit, the fault diagnosis result, the priority number, the video signal name after the switch on the transmitting side, and the video signal name after the switch on the receiving side. Arrows also indicate the path taken by the faulty video signal bit from the transmitting side to the receiving side. On the transmitting side, the upper bits of the R component are bypassed to the lower bits of the G and B components. On the receiving side, the bypassed bit signal is switched back to its original bit position by bypassing it in the opposite direction. The operation of the switch control circuit 205 is the same as the operation flowcharts in FIGS. 15 and 16.

[0127] (Switch Settings of Priority Selection Registers TXREG and RXREG) Figure 21 is a diagram showing an example of the values ​​of the priority selection registers TXREG and RXREG before and after switching, which rearrange the video signals in order of priority. The arrows in the diagram indicate the path taken by the video signal as the setting of the priority selection register is changed. Each column in the diagram shows the priority of the video signal, the video signal name, the initial setting value of the transmitting side priority selection register TXREG and the setting value after switching, and the initial setting value of the receiving side priority selection register RXREG and the setting value after switching. In the initial state, the priority selection registers TXREG and RXREG are set to 0, 1, 2, ..., 26, in order, according to the priority of each video signal.

[0128] In the third embodiment, because all eight bits of the R component are broken, the transmitting-side switch circuit 206 bypasses the signal on the upper bit side of the R component with a higher priority to the lower bit side of the G and B components with a lower priority, according to the transmitting-side switch control flow shown in FIG. 15 . For example, by setting the priority of 3 for the highest priority R[7] to the TXREG

[26] for the lowest priority B[0], the R[7] signal is bypassed to the wiring for B[0]. By setting the priority of 6 for the next highest priority R[6] to the TXREG

[25] for the next lowest priority G[0], the R[6] signal is bypassed to the wiring for G[0]. Meanwhile, the priority of 9 for the next highest priority R[5] is skipped because the next lowest priority R[0] is faulty, and is instead set to the TXREG

[23] for the next lowest priority B[1], thereby bypassing the R[5] signal to the wiring for B[1]. The remaining R component signals are similarly bypassed. In addition, in the switch setting after transmission, the priority selection register TXREG is set to a fixed control value so that the bit of the failed R component is fixed.

[0129] 16, the receiving side switch circuit 207 performs switch control to bypass in the opposite direction to the transmitting side switch control. On the receiving side, by setting RXREG[3] to 26, the R[7] signal received from the line with priority number 26 is returned to its original wiring position. By setting RXREG[6] to 25, the R[6] signal received from the line with priority number 25 is returned to its original wiring position. The same applies to the remaining R component signals.

[0130] In addition, in the switch control on the receiving side, RXREG

[19] to RXREG

[26] are set to fixed control values. This is to perform fixed control so that the signal on the higher-order bit side of the R component that is bypassed due to a failure is not used, and to perform fixed control of the low-priority bit side of the originally failed R component.

[0131] (Effect) As described above, even if all 8 bits of the R component fail, the damage caused by the failure can be distributed across the entire video signal using other color information bits, thereby suppressing color abnormalities in the video display and restoring the color display.

[0132] (Embodiment 4) In embodiment 2, a case where the most significant bit of color information is disconnected has been described. In embodiment 4, the range of failures is expanded to assume a case where a video control signal such as a clock signal or a synchronization signal fails, and control of the switch circuit and bypass operation of the switch circuit are shown.

[0133] Fig. 22 is a circuit diagram showing the configuration of a video signal processing device 200 according to embodiment 4. Fig. 22 shows that video control signals such as clock signals and synchronization signals are disconnected in wiring 101. The other circuits are the same as those in embodiment 2.

[0134] The arrows in the transmitting side switch circuit 206 and the receiving side switch circuit 207 in FIG. 22 show how a faulty video control signal is bypassed using the RGB components.

[0135] (Test Results and Fault Diagnosis Results) Fig. 23A is a diagram showing an example of test results when a fault occurs in embodiment 4. RGB components as video signal bits and each bit of the video control signal are arranged vertically, and the test results of each test pattern are arranged horizontally. In embodiment 4, as shown in Fig. 22, there is a break in the 3-bit video control signal, so in test results 25 to 27, the bits of the video control signal do not toggle to 1 but are 0, indicating a fault.

[0136] FIG. 23B shows an example of a fault diagnosis result corresponding to the inspection result at the time of the fault in FIG. 23A. Each column corresponds to a video signal and shows the fault diagnosis result, priority number, video signal name after the switch on the transmitting side, and video signal name after the switch on the receiving side. Based on the inspection results, the fault diagnosis result for the video control signal is determined to be an open circuit. Furthermore, in the priority column, video control signals, such as clock signals and synchronization signals, are essential for image display, so they are assigned a high priority (here, 0 to 2), similar to the higher-order bits of the video data signal. Arrows in the figure also indicate the path taken by the faulty video signal bit between the transmitting side and the receiving side. On the transmitting side, the faulty video control signal is bypassed to the lower-order bits of the RGB components. On the receiving side, a switch circuit switches the bypass in the opposite direction from the transmitting side, returning the bypassed video control signal to its original bit position.

[0137] (Switch Settings of Priority Selection Registers TXREG and RXREG) Figure 24 is a diagram showing an example of the values ​​before and after a switch in the priority selection register that rearranges video signals in order of priority. The arrows in the diagram indicate the path taken by the video signal due to a change in the setting of the priority selection register. Each column in the diagram shows the priority of the video signal, the video signal name, the initial setting value and the setting value after the switch of the transmitting side priority selection register TXREG, and the initial setting value and the setting value after the switch of the receiving side priority selection register RXREG. In the initial state, the priority selection registers TXREG and RXREG are set to 0, 1, 2, ..., 26 in order according to the priority of each video signal.

[0138] In the fourth embodiment, since the 3-bit video control signal is broken, the transmitting-side switch circuit 206 bypasses the high-priority video control signal to the low-priority RGB component's low-bit side by setting the priority number of the video control signal in the register TXREG for the low-priority RGB component's low-priority bits according to the transmitting-side switch control flow shown in FIG. 15 . For example, by setting the priority 0 of the highest-priority clock signal to the TXREG

[26] of the lowest-priority B[0], the clock signal is bypassed to the B[0] wiring. By setting the priority 1 of the next highest-priority horizontal synchronization signal to the TXREG

[25] of the next lowest-priority G[0], the horizontal synchronization signal is bypassed to the G[0] wiring. By setting the priority 2 of the next highest-priority vertical synchronization signal to the TXREG

[24] of the next lowest-priority R[0], the vertical synchronization signal is bypassed to the R[0] wiring. Furthermore, in the switch setting after transmission, TXREG is set to a fixed control value to fix the faulty video control signal.

[0139] The receiving side switch circuit 207 performs switch control to bypass the signal in the opposite direction to the transmitting side switch control, using the receiving side switch control shown in Figure 16. On the receiving side, by setting RXREG[0] to 26, the clock signal received from the line with priority number 26 is returned to its original wiring position. Also, by setting RXREG[1] to 25, the horizontal synchronization signal received from the line with priority number 25 is returned to its original wiring position. Also, by setting RXREG[2] to 24, the vertical synchronization signal received from the line with priority number 24 is returned to its original wiring position.

[0140] In addition, in the switch control on the receiving side, RXREG

[24] to RXREG

[26] are set to fixed control values ​​in order to prevent the video control signal that is bypassed due to a failure from being used as a video data signal.

[0141] (Effect) As a result of the above, even if the wiring 101 for video control signals such as clock signals essential for screen display fails, it is possible to continue displaying video by bypassing these with video data signals having a low priority.

[0142] (Embodiment 5) In the embodiments described so far, the transmitting side and receiving side of the video signal are connected by parallel wiring. In recent years, high-speed serial interfaces using low-voltage amplitude differential transmission methods, such as those adopted in MIPI, LVDS, and HDMI (registered trademark), have become increasingly popular. These high-speed serial interfaces have the advantages of noise resistance, high data rate, low power consumption, and low cost compared to parallel wiring.

[0143] LVDS is an acronym for Low Voltage Differential Signaling, and is widely used in laptops, industrial image processing, medical applications, automobiles, etc. LVDS is a small amplitude differential signaling method that achieves high-speed data transmission with extremely low power consumption and excellent noise resistance.

[0144] The video signal processing device according to this embodiment can also be applied to a high-speed serial interface such as LVDS, etc. As an example, an embodiment in which this proposal is applied to the LVDS system will be described.

[0145] 25 is a circuit diagram showing the configuration of a video signal processing device 300 according to a fifth embodiment. Here, the video signal processing device 300 is shown as being compatible with LVDS wiring 305 that employs a differential transmission method compatible with 28 bits for 4 channels of LVDS. The difference from the video signal processing device 200 is that the LVDS wiring 305 is the target of diagnosis, instead of the parallel wiring 101 for video signals. Furthermore, the video signal processing device 300 includes an LVDS driver 301 in the subsequent stage of a transmitting-side switch circuit 206 compatible with TTL / CMOS signals, and an LVDS receiver 302 in the previous stage of a receiving-side switch circuit 207.

[0146] In this embodiment, the LVDS is a type of LVDS that transmits 7-bit information at high speed serially using a pair of differential signals. This pair of differential signals is called a lane. In FIG. 25, the LVDS has one clock lane and four data lanes. Serial data is transmitted using the four LVDS lanes, and the receiving side samples the data using a synchronization signal sent over the clock lane.

[0147] The LVDS driver 301 includes an LVDS serializer 303. The LVDS serializer 303 is a circuit that converts parallel signals of single-ended standards such as CMOS and TTL into high-speed serial signals, and transmits 7 bits of data in one lane in synchronization with one clock.

[0148] The LVDS receiver 302 also includes an LVDS deserializer 304. The LVDS deserializer 304 is a circuit that converts the high-speed LVDS serial data into a parallel signal conforming to a single-ended standard such as CMOS or TTL.

[0149] (LVDS Data Mapping) Assume that the LVDS serializer 303 and LVDS deserializer 304 in Figure 25 have signals (TA0 to CLK, RA0 to CLK) arranged as shown in the figure. The LVDS serializer 303 serializes the 7-bit parallel data from TA0 to TA6 and transmits it as a differential serial signal TA+ / - on lane 0. On the receiving side, the LVDS deserializer 304 deserializes the differential serial signal RA+ / - and returns it to parallel data from RA0 to RA6. The same applies to the other lanes TB0 to TB6, TC0 to TC6, and TD0 to TD6.

[0150] Figure 26 is a diagram showing an example of data mapping on LVDS lanes. The LVDS data mapping in the diagram is determined by the LVDS format standard used, and Figure 26 shows the bit arrangement of RGB components in the LVDS JEIDA format. In this format, lanes 0 to 2 transmit RGB[2] to RGB[7] and video control signals such as synchronization signals. Lane 3 also transmits RGB[0] and RGB[1].

[0151] (Change in mapping of LVDS serial data in the event of a failure) Fig. 27 is a diagram showing a change in mapping of data on LVDS lanes due to a failure in embodiment 5. That is, assuming that lane 0 of the LVDS wiring 305 in Fig. 25 has failed, Fig. 27 shows how the LVDS serial data mapping changes by applying the video signal bypass device of this embodiment. In Fig. 27, the arrows indicate how the upper bits of the failed lane 0 are bypassed to other lanes with lower priority bits.

[0152] Data mapping is performed in the same manner as in embodiment 2, where the bits for which a fault has been detected are bypassed by the transmitting switch circuit 206, and then serialized by the downstream LVDS serializer 303, thereby enabling serial data to be transmitted using the post-bypass mapping of Figure 27.

[0153] Also, on the receiving side, the data converted to parallel by the LVDS deserializer 304 is returned to its original bit position by switching it in the receiving side switch circuit 207 located in the subsequent stage so as to bypass the video signal in the opposite direction to the transmitting side.

[0154] (Test Results and Fault Diagnosis Results) The test signal generation circuit 102 is arranged after the transmitting switch circuit 206 and before the LVDS driver 301. This allows test data to be serialized through the LVDS driver 301 and transmitted within the lane without being affected by the switch operation of the transmitting switch circuit 206.

[0155] The signal collection circuit 103 is also arranged after the LVDS receiver 302 and before the receiving switch circuit 207. This allows the data transmitted over the lanes of the LVDS wiring 305 to be deserialized by the LVDS receiver 302, after which the inspection results can be stored as parallel data. Furthermore, because it is located before the receiving switch circuit 207, it is not affected by the switch operation, and can receive the pattern transmitted over the lanes of the LVDS wiring 305 as is.

[0156] FIG. 28A is a diagram showing an example of test results when a fault occurs in the fifth embodiment. That is, FIG. 28A shows the test results collected by the signal collection circuit 103. The video signal bits of lanes 0 to 3 and the clock are arranged vertically, and the test results of each test pattern are arranged horizontally. In the fifth embodiment, as shown in FIG. 27, since lane 0 is faulty, the test results of lane 1 to lane 7 do not toggle (i.e., they do not switch between 0 and 1).

[0157] 28B is a diagram showing an example of a fault diagnosis result corresponding to the inspection result at the time of the fault in FIG. 28A. Each column shows the video signal name, the corresponding fault diagnosis result, priority, and the video signal name after switching. The order of the video signal names corresponds to the data mapping of lane 0 of the LVDS wiring 305, and is arranged in the following order from top to bottom: R[2] to R[7] and G[2]; G[3] to G[7], B[2], and B[3] for lane 1; B[4] to B[7], HSYNC, VSYNC, and DE for lane 2; and R[0] and R[1], G[0] and G[1], and B[0] and B[1] for lane 3.

[0158] As a result of the fault diagnosis, based on the inspection results of FIG. 28A, fault diagnosis circuit 104 determines that R[2] to R[7] and G[2] mapped to lane 0 are faulty.

[0159] As in the second embodiment, the higher bits of the video control signals such as clock signals and video data signals are given a higher priority, and the lower bits are given a lower priority.

[0160] In the video signal after the switch on the transmitting side, the R[7], R[6], R[5], R[4], R[3], R[2], and G[2] bits of the failed lane 0 are bypassed to the B[0], G[0], R[0], B[1], G[1], R[1], and B[2] bits of the low-priority data signals, respectively. Because this bypass processing is performed before serialization by the LVDS driver 301, the original mapping position of the video signal of lane 0 changes and becomes the mapping position indicated by the arrow in FIG. 27.

[0161] In addition, the serial data transmitted on the lane is deserialized by the LVDS receiver 302, and the video signal that has become parallel data must be returned to its original data position. The receiving switch circuit 207 bypasses the video signal in the opposite direction to the transmitting switch circuit 206, thereby returning the video signal that has been bypassed to the lower bit side to its original signal position.

[0162] (Changing the Settings of the Priority Selection Registers TXREG and RXREG) Figure 29 is a diagram showing an example of the values ​​of the priority selection registers TXREG and RXREG before and after switching, in which video signals have been rearranged in order of priority. The arrows in the diagram indicate the path taken by the video signal as a result of changing the settings of the priority selection register. Each column in the diagram shows the priority of the video signal, the video signal name, the initial setting value of the transmitting priority selection register TXREG and the setting value after switching, and the initial setting value of the receiving priority selection register RXREG and the setting value after switching. In the initial state, the priority selection registers TXREG and RXREG are set to 0, 1, 2, ..., 27, in order, according to the priority of each video signal.

[0163] On the transmit side, the R[7], R[6], R[5], R[4], R[3], R[2], and G[2] bits of the failed Lane 0 are bypassed to B[0], G[0], R[0], B[1], G[1], R[1], and B[2], respectively, by modifying TXREG to transmit them over the lower priority data wire.

[0164] On the receive side, RXREG is set to bypass in the opposite direction to TXREG, indicating that R[7], R[6], R[5], R[4], R[3], R[2], and G[2] bits of lane 0 are received, bypassed to B[0], G[0], R[0], B[1], G[1], R[1], and B[2].

[0165] (Effect) As described above, since the parallel-serial conversion and serial-parallel conversion are performed by the LVDS serializer 303 and the LVDS deserializer 304, it is possible to configure the video signal processing device 300 of this embodiment in a high-speed serial interface such as LVDS, with the other component circuits being configured in the same manner as in embodiment 2, simply by replacing the wiring 101 of the video signal processing device 200 of embodiment 2 with the LVDS driver 301, the LVDS receiver 302, and the LVDS wiring 305.

[0166] Furthermore, even if a lane for video control signals such as synchronization signals or data enable signals fails, transmission is possible by similarly bypassing the signal to the lower bits of the video signal on another lane and changing the data mapping.

[0167] (Embodiment 6) Up to now, we have shown the case where the transmitting side and receiving side of the video signal are connected by one wiring or cable, but in reality, there are cases where the video processing LSI connects multiple pairs of imaging devices and video display devices through a video interface. In embodiment 6, we will explain the case where the video processing LSI is connected to multiple video signal wirings.

[0168] (Explanation of Configuration) Fig. 30 is a circuit diagram showing the configuration of a video signal processing device 400 according to embodiment 6. This diagram shows the configuration of the video signal processing device 400 when connected to a plurality of wirings 101. Video signals are input from a plurality of image capture devices (image capture devices 1 and 2) on the left side of the diagram, and are subjected to video processing by a video processing circuit 403 in a video processing LSI 402 mounted on a main board 401. The processed video signals are output to a plurality of video display devices 411 and 412 on the right side. In order to deal with video signal failures, a transmitting-side switch circuit 206 and a receiving-side switch circuit 207 are provided on the transmitting and receiving sides of each wiring, respectively.

[0169] 30 does not include the test signal generation circuit 102, but instead, by controlling the output of the transmission side switch circuit 206 to be fixed to 0 or 1 during testing, a test signal for the video signal is transmitted onto the wiring 101, making it possible to test for a fault. By controlling the fixing, the priority selection registers TXREG and RXREG are controlled so that the bit of the signal to be tested is set to 1 and the other bits are set to 0.

[0170] The signal collection circuit 103 stores the transmitted test signal as an inspection result on the receiving side. Furthermore, the fault diagnosis circuit 404 diagnoses a fault in the video signal for each wiring 101 for the video signal from the inspection result.

[0171] Furthermore, since the location of the fault varies depending on the wiring 101 of each device, the switch control circuit 405 extends the switch control method of the second embodiment so as to sequentially control the wiring 101 of the multiple switch circuits (the transmitting switch circuit 206 and the receiving switch circuit 207). In other words, the fault is handled by controlling the multiple video signal sets corresponding to the multiple switch circuits in a time-division manner.

[0172] (Fault diagnosis circuit 404) Figure 31 is a flowchart showing a fault diagnosis method compatible with multiple video interfaces. The fault diagnosis results are arranged in a two-dimensional array so that faults in the signals of individual video interfaces can be identified. In S2901, fault diagnosis circuit 404 initializes a two-dimensional array of fault diagnosis information registers. Next, in S2902, fault diagnosis circuit 404 uses the test results for each video interface to perform fault diagnosis on the video interfaces in order (S2902a to S2902b). The fault diagnosis method is the same as the fault diagnosis flow shown in Figure 6.

[0173] 32 is a flowchart showing a method for controlling the switches of a plurality of video interfaces. In the sixth embodiment, in S3001, the switch control circuit 405 expands and initializes the priority selection registers TXREG and RXREG as a two-dimensional array so that the wirings 101 of a plurality of video signals can be identified, and specifies the IF number as the first index of the register and the priority as the second index.

[0174] Next, for each video interface (S3001a to S3001b), the switch control circuit 405 performs the switch control on the transmission side shown in Fig. 15 in S3002, bypassing the failed bit on the upper bit side to the lower bit. Also, in S3003, the switch control circuit 405 performs the switch control on the reception side shown in Fig. 16, controlling the reception side switch circuit 207 to bypass in the opposite direction to the transmission side, and returning the position of the video signal.

[0175] (Effect) This makes it possible to respond to failures in the wiring 101 for multiple video signals such as camera input and LCD output, and by implementing only one switch control circuit 405 instead of one for each video signal wiring 101, implementation costs can be reduced.

[0176] (Embodiment 7) Up to now, we have explained video signal processing devices for dealing with faults in the video signal wiring. In this embodiment, we will explain how to restore a fault when a fault occurs in the wiring or logic cell inside the video processing circuit.

[0177] Conventionally, when an internal video processing circuit fails due to sticking or the like, a slight failure in the upper bit path can cause a significant image distortion on the video display side. Conventional technology includes a method of bypassing the entire failed circuit when a failure is detected, but bypassing the circuit makes it impossible to use the bypassed video processing function. This embodiment is intended to address this issue.

[0178] 33 is a circuit diagram showing the configuration of a video signal processing device 500 according to embodiment 7. The basic circuit configuration is the same as that of embodiment 2, but in embodiment 7, a receiving-side switch circuit 207 is provided on the left and a transmitting-side switch circuit 206 is provided on the right.

[0179] In Figure 33, a test pattern is input from the test signal generation circuit 102 to the video processing circuit 403, a fault diagnosis is performed based on the test results, and a switch is controlled to shift the higher bits of the video signal to the lower bits, thereby switching the transmission path of the higher bits and improving the distortion of the video display.

[0180] (Explanation of Test Pattern) A test signal is input from test signal generation circuit 102 to video processing circuit 403 , and faults in video processing circuit 403 are diagnosed by fault diagnosis circuit 104 .

[0181] An example of a test signal is a pattern in which, when the test target bits are toggled in order (i.e., the test target bits are shifted one bit at a time), the signal is propagated through multiple cycles within the video processing circuit 403, causing the corresponding output bit to toggle accordingly. Under normal circumstances, the output bit toggles as expected, but if there is a fault in the wiring 101 or cell on the path to the output bit, the expected toggle operation does not occur, making it possible to detect an abnormality on the path.

[0182] Multiple test patterns are input in specific combinations to check the output bits of all video signals, and if an abnormality is found, the higher-order bits are shifted to the lower-order bits to bypass the faulty wiring or logic cell.The video signal shifted to the lower-order bits is then processed, and the brightness of the video signal can be restored by shifting it back to the higher-order bits on the receiving side.

[0183] Furthermore, if there is a failure on the propagation path of a video control signal such as a clock signal or a synchronization signal, it can be dealt with by bypassing it instead of shifting it.

[0184] Furthermore, even if the video processing circuit 403 is not inspected with a test signal, if the user of the device finds abnormal distortion in the video display, by shifting the receiving side switch circuit 207, it is possible to change the transmission path of the video signal of the video processing circuit 403 to the lower bit side and check whether the video display improves, which is one means of failure analysis.

[0185] (Effects) As described above, by diagnosing the location of a fault in the wiring 101 or logic cell inside the video processing circuit 403 and shifting the video signal, it is possible to bypass the fault and prevent the video display from becoming distorted.

[0186] (Summary) As described above, the video signal processing device according to an embodiment of the present disclosure is a video signal processing device 100 that deals with a failure in wiring 101 for transmitting a video signal, and includes a signal collection circuit 103 that collects signals transmitted over wiring 101, a fault diagnosis circuit 104 and the like that creates fault diagnosis information related to a failure in wiring 101 from the signals collected by signal collection circuit 103, a switch control circuit 105 that generates, from the fault diagnosis information created by fault diagnosis circuit 104 and the like, switch information for shifting or bypassing higher-order bits that constitute the video signal to lower-order bits, and a transmission-side switch circuit 106 that is arranged in a stage preceding wiring 101 and switches the path of the bits that constitute the video signal in accordance with the switch information created by switch control circuit 105.

[0187] As a result, the transmitting-side switch circuit 106, which is arranged in a stage preceding the wiring 101, shifts the higher-order bits constituting the video signal to the lower-order bits or bypasses them based on switch information generated from the fault diagnosis information, so that the path of the video signal is switched so as to make use of the higher-order bits of the video signal, which are more susceptible to image quality degradation due to a fault. Thus, even if the wiring transmitting the video signal fails, the video signal processing device 100 is realized, which can transmit the video signal in a manner that suppresses the effects of the failure.

[0188] Here, the video signal processing device 100 may further include a test signal generation circuit 102 that sends a test pattern to the wiring 101, and the signal collection circuit 103 may collect the test pattern transmitted through the wiring 101. This allows a fault in the wiring 101 to be detected using a desired test pattern, thereby shortening the time and increasing the efficiency of fault detection.

[0189] Furthermore, the transmitting switch circuit 206 may send a test pattern to the wiring 101 by outputting a fixed value of 0 or 1 in accordance with an instruction from the switch control circuit 205. This allows the transmitting switch circuit 206 to function as a test signal generation circuit as well, eliminating the need to provide an independent test signal generation circuit and allowing the video signal processing device 200 to be made smaller.

[0190] Furthermore, the video signal processing device 200 may further include a receiving-side switch circuit 207 that switches the bit path so as to shift or bypass lower bits to higher bits in the opposite direction to the switching by the transmitting-side switch circuit 206. This allows the shift or bypass to the lower bits of the video signal by the transmitting-side switch circuit 206 to be restored by the receiving-side switch circuit 207, thereby improving the extreme drop in brightness level.

[0191] The wiring 101 may include wiring 101 within an integrated circuit, wiring 101 on a circuit board, or a cable connecting devices, and may further include parallel wiring or a high-speed interface compatible with LVDS (Low Voltage Differential Signaling) or MIPI (Mobile Industry Processor Interface). This realizes a video signal processing device 300 that can handle various types of wiring failures.

[0192] Furthermore, the switch control circuit 105 may generate switch information based on the fault diagnosis information to control the transmitting switch circuit 106 so that the higher order bits of the video data signal constituting the video signal are given high priority, and the lower order bits that are not faulty are used in order with low priority. This allows for a simple method of reallocating video signal bits, thereby reducing implementation costs.

[0193] Furthermore, when the fault diagnosis information indicates that all bits of any of the multiple color components represented by the video signal are faulty, the switch control circuit 205 may suppress abnormalities in the colors represented by the video signal by generating switch information for controlling the transmitting-side switch circuit 206 to bypass all bits of the faulty color component to the lower bits of other color components. In this way, the failure of all bits of one color component is relieved by the lower bits of the other color components, thereby mitigating abnormalities in the colors reproduced in the video signal.

[0194] Furthermore, when the fault diagnosis information indicates that a bit of a video control signal, including a clock signal and a synchronization signal, contained in the video signal has failed, the switch control circuit 205 may generate switch information for controlling the transmitting switch circuit 206 to bypass the failed control signal bit to the lower bits of the video data signal that constitutes the video signal, thereby maintaining the video display by the video signal. This allows the failure of the video control signal to be repaired by the lower bits of the video data signal, which have less impact, thereby avoiding a situation in which the video signal is not reproduced at all, and video reproduction can continue.

[0195] Furthermore, the switch control circuit 205 may generate switch information for controlling the transmitting-side switch circuit 206 and the receiving-side switch circuit 207 as a single master switch so that the transmitting-side switch circuit 206 and the receiving-side switch circuit 207 operate in conjunction with each other with the shift or bypass directions reversed. This allows the switching control of the transmitting-side switch circuit 206 and the receiving-side switch circuit 207 to be standardized, thereby simplifying the control and reducing implementation costs.

[0196] Furthermore, the video signal processing device 400 may include a plurality of pairs of the transmitting-side switch circuit 206 and the receiving-side switch circuit 207 corresponding to a plurality of video signals, and the switch control circuit 205 may function as a single master switch to simultaneously control the plurality of pairs of the transmitting-side switch circuit 206 and the receiving-side switch circuit 207 corresponding to the plurality of video signals. This realizes the video signal processing device 400 that can deal with failures in a plurality of wires 101 in a system including a plurality of pairs of an imaging device and a video display device.

[0197] Furthermore, a video signal processing method according to an embodiment of the present disclosure is a video signal processing method for dealing with a failure in wiring 101 for transmitting a video signal, and includes a signal collection step of collecting signals transmitted over wiring 101 for transmitting a video signal; a fault diagnosis step of creating fault diagnosis information related to a failure in wiring 101 from the signals collected in the signal collection step; a switch control step of generating, from the fault diagnosis information created in the fault diagnosis step, switch information for shifting or bypassing higher-order bits constituting the video signal to lower-order bits; and a transmission-side switching step of switching the path of the bits constituting the video signal in accordance with the switch information generated in the switch control step prior to transmission of the video signal over wiring 101.

[0198] As a result, prior to transmission of the video signal through the wiring 101, in the transmission side switching step, the higher order bits constituting the video signal are shifted to the lower order bits or bypassed based on switch information generated from the fault diagnosis information, so that the path of the video signal is switched so as to make use of the higher order bits of the video signal that are more susceptible to image quality degradation due to a fault. Thus, even if the wiring transmitting the video signal fails, a video signal processing method is realized that can transmit the video signal in a manner that suppresses the effects of the failure.

[0199] The video signal processing device and video signal processing method according to the present disclosure have been described above based on Embodiments 1 to 7, but the present disclosure is not limited to these Embodiments 1 to 7. As long as they do not deviate from the gist of the present disclosure, various modifications that would occur to a person skilled in the art to be made to Embodiments 1 to 7, and other forms constructed by combining some of the components of Embodiments 1 to 7, are also included within the scope of the present disclosure.

[0200] For example, the invention of the present disclosure may be not only a video signal processing device and a video signal processing method, but also a program that causes a computer to execute all or part of the steps included in the video signal processing method, or a non-transitory recording medium such as a computer-readable DVD that stores the program.

[0201] Furthermore, all or part of the steps included in the video signal processing method according to the present disclosure may be executed by each circuit element in the embodiment, or may be executed by a processor using a memory.

[0202] Furthermore, the video signal processing device according to the present disclosure may include wiring that is the subject of diagnosis.

[0203] The present disclosure can be used as a video signal processing device that can transmit a video signal in a manner that suppresses the impact of a failure even if the wiring that transmits the video signal fails, for example, in video processing systems used in fields such as medicine and automobiles.

[0204] 100, 200, 300, 400, 500 Video signal processing device 101 Wiring 102 Test signal generation circuit 103 Signal collection circuit 104, 404 Fault diagnosis circuit 105, 205, 405 Switch control circuit 106, 206 Transmitting side switch circuit 207 Receiving side switch circuit 210, 212 Multiplexer 211 Transmitting side priority selection register TXREG 213 Receiving side priority selection register RXREG 301 LVDS driver 302 LVDS receiver 303 LVDS serializer 304 LVDS deserializer 305 LVDS wiring 401 Main board 402 Video processing LSI 403 Video processing circuit 411, 412 Video display device

Claims

1. A video signal processing device that handles a failure in a wiring for transmitting a video signal, a signal collection circuit that collects signals transmitted through the wiring; a fault diagnosis circuit that generates fault diagnosis information relating to a fault in the wiring from the signals collected by the signal collection circuit; a switch control circuit that generates, from the fault diagnosis information created by the fault diagnosis circuit, switch information for shifting or bypassing upper bits constituting the video signal to lower bits; a transmitting-side switch circuit arranged in a stage preceding the wiring, for switching paths of bits constituting the video signal in accordance with the switch information generated by the switch control circuit.

2. Further, a test signal generating circuit is provided for transmitting a test pattern to the wiring, 2. The video signal processing device according to claim 1, wherein the signal collection circuit collects the test pattern transmitted through the wiring.

3. 2. The video signal processing device according to claim 1, wherein said transmission side switch circuit outputs a test pattern to said wiring by outputting a fixed value of 0 or 1 in accordance with an instruction from said switch control circuit.

4. The video signal processing device according to any one of claims 1 to 3, further comprising a receiving-side switch circuit that switches a bit path so as to shift lower bits to higher bits or bypass them in a direction opposite to the switching by the transmitting-side switch circuit.

5. The wiring includes wiring within an integrated circuit, wiring on a circuit board, or a cable connecting devices; 4. The video signal processing device according to claim 1, wherein the wiring further includes parallel wiring or a high-speed interface compatible with LVDS (Low Voltage Differential Signaling) or MIPI (Mobile Industry Processor Interface).

6. The video signal processing device according to any one of claims 1 to 3, wherein the switch control circuit generates the switch information from the fault diagnosis information to control the transmitting side switch circuit so that the higher order bits of the video data signal constituting the video signal are given high priority and the lower order bits that are not faulty are used in order with low priority.

7. The video signal processing device according to any one of claims 1 to 3, wherein, when the fault diagnosis information indicates that all bits of any of a plurality of color components indicated by the video signal are faulty, the switch control circuit generates the switch information for controlling the transmitting-side switch circuit to bypass all bits of the faulty color component to lower bits of other color components, thereby suppressing color abnormalities indicated by the video signal.

8. The video signal processing device according to any one of claims 1 to 3, wherein, when the fault diagnosis information indicates that a bit of a video control signal including a clock signal and a synchronization signal included in the video signal is faulty, the switch control circuit generates the switch information for controlling the transmitting-side switch circuit to bypass the faulty bit of the video control signal to a lower bit of a video data signal that constitutes the video signal, thereby maintaining the video display by the video signal.

9. 5. The video signal processing device according to claim 4, wherein the switch control circuit generates the switch information for controlling the transmitting-side switch circuit and the receiving-side switch circuit as one master switch so that the transmitting-side switch circuit and the receiving-side switch circuit operate in conjunction with each other with shift or bypass directions reversed.

10. the video signal processing device includes a plurality of pairs of the transmitting-side switch circuit and the receiving-side switch circuit corresponding to a plurality of video signals; 5. The video signal processing device according to claim 4, wherein the switch control circuit simultaneously controls the plurality of sets of the transmitting-side switch circuits and the receiving-side switch circuits corresponding to the plurality of video signals as one master switch.

11. A video signal processing method for dealing with a failure in a wiring for transmitting a video signal, comprising: a signal collecting step of collecting signals transmitted through a wiring for transmitting video signals; a fault diagnosis step of creating fault diagnosis information relating to a fault in the wiring from the signals collected in the signal collection step; a switch control step of generating, from the fault diagnosis information generated in the fault diagnosis step, switch information for shifting or bypassing upper bits constituting the video signal to lower bits; a transmitting-side switching step of switching the path of bits constituting the video signal in accordance with the switch information generated in the switch control step, prior to transmission of the video signal through the wiring.