Encoding device, encoding method, control circuit, and storage medium

Abstract

An encoding device (1) comprises a division unit (2) that allocates an inputted information bit sequence to input bits of a plurality of polar codes according to an index table (31), and an encoding unit (4) that mutually connects a plurality of polar codes inputted in parallel from the division unit and generates a parallelized polar code. The index table includes: a first input bit index indicating bits determined on the basis of the bit count K of the input bits in the polar code, the number QC of polar codes inputted in parallel to the encoding unit, and the communication path capacity at each bit position in the polar codes; and a second input bit index indicating bits determined on the basis of the communication path capacity and an error rate from among bits not indicated by the first input bit index. The division unit allocates each bit of the information bit sequence to each bit of the plurality of polar codes indicated by the first input bit index and the second input bit index.

Description

Encoding device, encoding method, control circuit, and storage medium

[0001] The present disclosure relates to an encoding device, an encoding method, a control circuit, and a storage medium that perform encoding using polar codes.

[0002] Polar codes polarize bit indices (hereinafter sometimes simply referred to as indices) with large channel capacities and indices with small channel capacities, and assign input bits to indices in descending order of channel capacity, with the remaining indices being frozen bits, which are fixed values, thereby achieving excellent error rate performance. The indices of the input bits and the indices of the frozen bits are determined based on the calculation results by calculating the channel capacity of each index in advance before encoding and decoding the information bit sequence, and are known to the transmitting side that performs encoding and the receiving side that performs decoding.

[0003] Furthermore, there exists a QC (Quasi-Cyclic) polar code that achieves reduction in decoding delay by parallelizing polar codes (see Non-Patent Document 1). A QC polar code is generated by arranging QC polar codes, each with a code length of N, in parallel and connecting them with each other, and the total code length is QC times the code length N (=N*QC).

[0004] In the QC polar code described in Non-Patent Document 1, the positions of the indices for allocating input bits and the indices for allocating frozen bits for each of the QC polar codes arranged in parallel are all the same. Therefore, in the QC polar code described in Non-Patent Document 1, the code length is a multiple of the number QC of parallel polar codes.

[0005] Toshiaki Koike-Akino, and Ye Wang. “Protograph-Based Design for QC Polar Codes”, 2021 IEEE International Symposium on Information Theory(ISIT).

[0006] In the design of the QC Polar code described in Non-Patent Document 1, it is assumed that the number of input bits is a multiple of QC. This condition for setting the number of input bits imposes constraints on practical frame design. Polar codes can achieve excellent error rate performance by concatenating other codes, so it is desirable to be able to create concatenated codes. However, if the setting of the number of input bits is limited, this imposes constraints on the design of concatenated codes and hinders performance improvement.

[0007] The present disclosure has been made in view of the above, and has an object to provide a coding device capable of generating parallelized polar codes without any restrictions on the number of input bits.

[0008] In order to solve the above-mentioned problems and achieve the object, the encoding device of the present disclosure comprises a division unit that assigns an input information bit sequence to input bits of multiple polar codes according to an index table, and an encoding unit that generates parallelized polar codes by interconnecting the multiple polar codes input in parallel from the division unit, wherein the index table includes a first input bit index indicating a bit determined based on the number K of input bits of the polar code, the number QC of polar codes input in parallel to the encoding unit, and the channel capacity of each bit position of the polar code, and a second input bit index indicating a bit determined based on the channel capacity and error rate among the bits not indicated by the first input bit index, and the division unit assigns each bit of the information bit sequence to each bit of the multiple polar codes indicated by the first input bit index and the second input bit index.

[0009] The encoding device according to the present disclosure has an effect of being able to generate parallelized polar codes that are not restricted by the number of input bits.

[0010] FIG. 1 is a diagram for explaining an example of a polar code; FIG. 2 is a diagram showing the structure of a frame corresponding to the index assignment result shown in FIG. 1;

[0011] An encoding device, an encoding method, a control circuit, and a storage medium according to embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings.

[0012] First Embodiment An encoding device according to this embodiment generates a parallelized polar code by connecting multiple polar codes in parallel. First, the polar code to be parallelized and the QC polar code described in Non-Patent Document 1, which serves as a comparative example, will be described.

[0013] FIG. 1 is a diagram illustrating an example of a polar code. FIG. 1 shows an example of index assignment for a polar code with a code length of 8. In FIG. 1, R8 represents a circuit that performs a process of rearranging indexes in bit-reverse order. The channel capacity of each of the 8 bits that make up the polar code output by the encoding circuit is calculated, and the required number of bits are selected in descending order of channel capacity. These indices are used as indices for input bits, and the remaining indices are used as indices for frozen bits. In the example of FIG. 1, the first to third indices and the fifth index from the top are used as indices for frozen bits, and the rest are used as indices for input bits. By assigning indices for input bits according to the number of input bits, polar codes allow any natural number of bits to be input as long as the number of input bits does not exceed the code length.

[0014] Figure 2 is a diagram showing the structure of a frame corresponding to the index allocation results shown in Figure 1. The first to third indexes from the top in Figure 1, which are frozen bits, correspond to the first to third blocks from the left in Figure 2, which are frozen bit blocks.

[0015] Fig. 3 is a conceptual diagram of the QC polar code. As shown in Fig. 3, the QC polar code arranges QC polar codes of the same code length in parallel, performs bit addition connection recursively in encoding, and cyclically shifts bits in the same positions of the parallel polar codes to achieve parallel connection of the polar codes.

[0016] Fig. 4 is a diagram showing an example of a parallel connection method for QC polar codes. In the QC polar code of Fig. 3, bit sums at the same position among the parallelly arranged polar codes are connected in parallel by cyclic shifting each other. Fig. 4 shows a state in which one cyclic shift is performed, where the first and QCth of the QC bit sums are connected, and the second and first are connected. Such cyclic shifts are performed for all bit sums.

[0017] Figure 5 is a diagram showing the structure of a frame corresponding to the QC Polar code shown in Figure 3. The frame structure shown in Figure 5 is a format in which QC frames, each with the same input bit and frozen bit positions, are arranged in parallel. Therefore, there is a constraint that the number of input bits must be a multiple of QC. In the example of Figure 5, the number of input bits is 4*QC.

[0018] Next, a coding device according to a first embodiment will be described. Fig. 6 is a diagram showing an example of the configuration of the coding device 1 according to the first embodiment. The coding device 1 according to the first embodiment includes a dividing unit 2, a storage unit 3, a coding unit 4, and a combining unit 5. The coding device 1 generates parallelized polar codes with a parallel number of QC.

[0019] Input bits, which are an information bit sequence, are input to the division unit 2. The division unit 2 allocates the input information bit sequence to QC input positions of the encoding unit 4 according to an index table 31 stored in the storage unit 3.

[0020] The index table 31 stored in the storage unit 3 stores the indices of the input bits of the polar code and the indices of the frozen bits. For example, in the case of index assignment corresponding to the frame configuration illustrated in FIG. 5 where the parallel number is 8 (QC=8), 4, 6, 7, and 8 are stored as the indices of the input bits, and 1, 2, 3, and 5 are stored as the indices of the frozen bits. When operating according to this index table 31, the division unit 2 assigns each bit input sequentially to the 4th, 6th, 7th, and 8th bits of the 8 bits input to the first input position of the encoding unit 4. After allocating 4 bits, the division unit 2 assigns the 4th, 6th, 7th, and 8th bits of the 8 bits input to the second input position of the encoding unit 4, and the 4th, 6th, 7th, and 8th bits of the 8 bits input to the third input position of the encoding unit 4. The division unit 2 assigns the frozen bits to the 1st, 2nd, 3rd, and 5th bits of the 8 bits input to each input position of the encoding unit 4. Once all the input bits are complete, i.e., once the process of allocating four input bits and four frozen bits to each of the eight input positions of the encoding unit 4 is completed, the dividing unit 2 outputs each bit to the encoding unit 4. In this way, the dividing unit 2 allocates the input information bit sequence to the input bits of the multiple polar codes according to the index table 31.

[0021] The encoding unit 4 is configured with the encoding circuit shown in Fig. 3 and generates a parallelized polar code by interconnecting multiple polar codes. That is, the encoding unit 4 receives input from the division unit 2 and performs the connection processing described with reference to Fig. 4 on the input bit string, specifically, the N-bit polar codes input from each of the QC input positions. The encoding unit 4 inputs the parallelized polar codes to the combination unit 5.

[0022] The combiner 5 combines the polar codes of code length N input in parallel from the encoder 4 and outputs the combined codes one bit at a time.

[0023] The index table 31 will now be described in detail. The index table 31 held in the storage unit 3 of the encoding device 1 is generated in advance according to the following steps #1 to #5. Note that the number of input bits is K, and the jth index of the i-th circuit among the QC parallel encoding circuits that make up the encoding unit 4 is written as idx(i, j). [x] represents the largest integer not exceeding x. '%' represents a modulo operation. The index table 31 may be generated by another device external to the encoding device 1 and passed to the encoding device 1, or the encoding device 1 may have a function for generating the index table 31.

[0024] (Step #1) Of the indices (1, 2, ..., N) corresponding to the code length N, [K / QC] indexes with the largest channel capacities are set as input bit indices. That is, [K / QC] indexes are selected in descending order of channel capacity and set as input bit indices. The input bit index set in step #1 is a first input bit index indicating all of the parallelized QC bits. This first input bit index indicates a bit determined based on the number K of input bits of the polar code, the parallel number QC of the polar code, and the channel capacity of each bit position of the polar code.

[0025] (Step #2) Among the indices (1, 2, ..., N) corresponding to the code length N, select the index with the largest channel capacity ([K / QC]+1), and set this index as A. Among the indices not set as input bit indices in step #1, select the index with the largest channel capacity and set this as A.

[0026] (Step #3) Determine a certain signal-to-noise ratio and check the error rate of idx(1,A), idx(2,A), ..., idx(QC,A). That is, check the error rate of each of the QC bits corresponding to the index A selected in step #2.

[0027] (Step #4) Of the indices idx(i, A) checked in step #3, K% QC indexes with the smallest error rates are set as input bit indices. That is, from the indices idx(i, A) checked in step #3, in order from the index with the smallest error rate, indexes idx(i, A) of the same number as the remainder when K is divided by QC are selected and set as input bit indices. The input bit indices set in step #4 are second input bit indices indicating some of the parallelized QC bits. This second input bit index indicates a bit determined based on the channel capacity and bit error rate at each bit position of the Polar code, among the bits not corresponding to the bits indicated by the first input bit index.

[0028] (Step #5) The remaining indexes that were not used as input bit indexes in steps #1 to #4 are set as frozen bit indexes.

[0029] It should be noted that if the number of input bits K is an integer multiple of the number of parallel operations QC, that is, if K% QC=0, steps #2 to #4 are not executed.

[0030] The index table creation operation of steps #1 to #5 above can be represented by the flowchart in Fig. 7. Fig. 7 is a flowchart showing an example of a method for creating the index table 31 used in the encoding device 1 according to the first embodiment. Here, as an example, the operation of the table creation device will be described. The table creation device may be a device separate from the encoding device 1, or the encoding device 1 may operate as the table creation device.

[0031] The table creation device first selects n indexes based on the number of input bits K, the number of parallel polar codes QC, and the channel capacity (step S1). Specifically, as described in step #1 above, the table creation device selects [K / QC] indexes in descending order of channel capacity.

[0032] The table creation device then checks whether K%QC=0 (step S2). If K%QC=0 (step S2: Yes), the table creation device sets each bit of the selected n indexes as input bits (step S4). That is, the table creation device sets the [K / QC] indexes selected in step S1 as input bit indexes.

[0033] If K%QC=0 is not satisfied (step S2: No), the table creation device sets each bit of the selected n indexes and K%QC bits with the lowest error rate among the QC bits of the index with the largest communication capacity among the unselected indexes as input bits (step S3). That is, the table creation device sets the [K / QC] indexes selected in step S1, and further selects K%QC bits in descending order of error rate from the QC bits of the index with the largest communication capacity among the unselected indexes in step S1 as input bit indexes, and sets the index of each selected bit as input bit index.

[0034] After setting the input bit indexes in step S3 or S4, the table creation device sets the remaining bits as frozen bits (step S5). That is, the table creation device sets the indexes of the remaining bits other than the bits set as input bits as frozen bit indexes.

[0035] A specific example of the index table creation operation will be described with reference to Fig. 8 and Fig. 9. Fig. 8 is a first diagram showing an example of a method for creating the index table 31 used in the encoding device 1 according to the first embodiment, and Fig. 9 is a second diagram showing an example of a method for creating the index table 31 used in the encoding device 1 according to the first embodiment.

[0036] As an example, we will explain how to create the index table 31 when the parallel number QC of the polar code is 4, the code length N is 8, and the number of input bits K is 14. Under these conditions, the number of input bits, 14, is not a multiple of QC=4, and 2 bits remainder is generated. [K / QC]=3, K%QC=2. Figure 8 shows examples of the above steps #1 and #2, and Figure 9 shows examples of the above steps #3 to #5.

[0037] In the example of steps #1 and #2 shown in Figure 8, the channel capacities of the eight indexes are calculated, and the channel capacities of the first to eighth indexes are 0.1, 0.15, 0.2, 0.5, 0.4, 0.7, 0.8, and 0.95. In this case, the sixth, seventh, and eighth indexes have the third largest channel capacities, so they are set as input indexes. Also, the fourth index has the fourth largest channel capacity, so A = 4.

[0038] Next, in the example of steps #3 to #5 shown in Figure 9, the error rate of index A at a certain signal-to-noise ratio is examined, and the results are idx(1,4) is 0.01, idx(2,4) is 0.03, idx(3,4) is 0.003, and idx(4,4) is 0.002. Since K%QC = 14%4 = 2, the indexes idx(4,4) with the smallest error rates and the second smallest idx(3,4) are used as input bit indices, and the remaining indices are used as frozen bit indices. Note that in the example of Figure 9, the bit error rate is examined as an example of an error rate, but it does not necessarily have to be a bit error rate.

[0039] In this embodiment, the indexes of the QC parallel polar codes may not be common among the parallel polar codes, unlike the indexes illustrated in Fig. 5. For this reason, the input bit indexes assigned in steps #3 to #5 are stored in the index table 31 in addition to the indexes assigned in steps #1 and #2. As an example, the above index A and the parallel number of index A corresponding to the input bit index are stored.

[0040] Next, a description will be given of the hardware configuration of the encoding device 1. In the encoding device 1, the dividing unit 2, the storage unit 3, the encoding unit 4, and the combining unit 5 are realized by processing circuits. The processing circuits may be a processor and memory that executes a program stored in a memory, or may be dedicated hardware. The processing circuits are also called control circuits.

[0041] FIG. 10 is a diagram illustrating a configuration example of a processing circuit 90 that implements the encoding device 1 according to the first embodiment, where the processing circuit is implemented by a processor 91 and a memory 92. The processing circuit 90 illustrated in FIG. 10 is a control circuit and includes a processor 91 and a memory 92. When the processing circuit 90 is configured with the processor 91 and the memory 92, the functions of the division unit 2, the encoding unit 4, and the combining unit 5 of the encoding device 1 implemented by the processing circuit 90 are implemented by software, firmware, or a combination of software and firmware. The software or firmware is written as a program and stored in the memory 92. In the processing circuit 90, the functions of the division unit 2, the encoding unit 4, and the combining unit 5 are implemented by the processor 91 reading and executing the program stored in the memory 92. That is, the processing circuit 90 includes the memory 92 for storing a program that results in the processing of the division unit 2, the encoding unit 4, and the combining unit 5 of the encoding device 1. This program can also be said to be a program that causes the encoding device 1 to execute the functions of the division unit 2, the encoding unit 4, and the combining unit 5 implemented by the processing circuit 90. This program may be provided by a storage medium on which the program is stored, or by other means such as a communication medium. The storage unit 3 of the encoding device 1 is realized by the memory 92.

[0042] Here, the processor 91 is, for example, a CPU (Central Processing Unit), a processing device, an arithmetic unit, a microprocessor, a microcomputer, or a DSP (Digital Signal Processor), etc. The memory 92 is, for example, a non-volatile or volatile semiconductor memory such as a RAM (Random Access Memory), a ROM (Read Only Memory), a flash memory, an EPROM (Erasable Programmable ROM), or an EEPROM (Electrically EPROM), a magnetic disk, a flexible disk, an optical disk, a compact disk, a minidisk, or a DVD (Digital Versatile Disc).

[0043] FIG. 11 is a diagram illustrating an example of a processing circuit 93 that implements the encoding device 1 according to the first embodiment and is configured with dedicated hardware. The processing circuit 93 illustrated in FIG. 11 may be, for example, a single circuit, a composite circuit, a programmed processor, a parallel programmed processor, an ASIC (Application Specific Integrated Circuit), an FPGA (Field Programmable Gate Array), or a combination thereof. The processing circuit may be partially implemented with dedicated hardware and partially implemented with software or firmware. In this manner, the processing circuit can implement each function of the encoding device 1 described above using dedicated hardware, software, firmware, or a combination thereof.

[0044] As described above, the encoding device 1 according to this embodiment arranges multiple polar codes in parallel and allocates input bits according to the stored index table 31. The index table 31 is created by assigning [K / QC] indices with the largest channel capacity among the code length N to a first input bit index indicating all of the parallelized QC bits, and further assigning indexes of K%QC bits with the smallest error rate among the QC bits of the remaining indexes with the largest channel capacity to a second input bit index indicating some of the parallelized QC bits. The encoding device 1 according to this embodiment can encode any number of input bits.

[0045] The configurations shown in the above embodiments are merely examples, and may be combined with other known technologies, and parts of the configurations may be omitted or modified without departing from the spirit of the invention.

[0046] 1 encoding device, 2 division unit, 3 storage unit, 4 encoding unit, 5 combination unit, 31 index table

Claims

1. a division unit that allocates an input information bit sequence to input bits of a plurality of polar codes according to an index table; an encoding unit that generates parallelized polar codes by connecting the plurality of polar codes input in parallel from the dividing unit; Equipped with the index table includes: a first input bit index indicating a bit determined based on the number K of the input bits of the polar code, the number QC of the polar codes input in parallel to the encoding unit, and a channel capacity at each bit position of the polar code; and a second input bit index indicating a bit determined based on the channel capacity and an error rate among bits not indicated by the first input bit index; the dividing unit assigns each bit of the information bit sequence to each bit of the plurality of polar codes indicated by the first input bit index and the second input bit index.

1. An encoding device comprising:

2. the first input bit index indicates all bits at bit positions having the same number as a quotient obtained by dividing the number K of the input bits of the polar code having a large communication channel capacity by the number QC of the polar codes input in parallel to the encoding unit; 2. The encoding device according to claim 1.

3. The second input bit index indicates bits of the same number as a remainder obtained by dividing the number K of the input bits of the polar code having the maximum channel capacity and a low error rate by the number QC of the polar codes input in parallel to the encoding unit, among bits not indicated by the first input bit index.

3. The encoding device according to claim 1 or 2.

4. The number K of input bits of the polar code is different from a multiple of the number QC of the polar codes input in parallel to the encoding unit.

3. The encoding device according to claim 1 or 2.

5. An encoding method executed by an encoding device including a division unit and an encoding unit, a first step in which the dividing unit allocates an input information bit sequence to input bits of a plurality of polar codes according to an index table; a second step in which the encoding unit connects the plurality of polar codes input in parallel from the dividing unit to generate parallel polar codes; Including, the index table includes: a first input bit index indicating a bit determined based on the number K of the input bits of the polar code, the number QC of the polar codes input in parallel to the encoding unit, and a channel capacity at each bit position of the polar code; and a second input bit index indicating a bit determined based on the channel capacity and an error rate among bits not indicated by the first input bit index; In the first step, each bit of the information bit sequence is assigned to each bit of the plurality of polar codes indicated by the first input bit index and the second input bit index.

10. A coding method comprising:

6. A control circuit for controlling an encoding device including a division unit and an encoding unit, a first step in which the dividing unit allocates an input information bit sequence to input bits of a plurality of polar codes according to an index table; a second step in which the encoding unit connects the plurality of polar codes input in parallel from the dividing unit to generate parallel polar codes; causing the encoding device to execute the index table includes: a first input bit index indicating a bit determined based on the number K of the input bits of the polar code, the number QC of the polar codes input in parallel to the encoding unit, and a channel capacity at each bit position of the polar code; and a second input bit index indicating a bit determined based on the channel capacity and an error rate among bits not indicated by the first input bit index; In the first step, each bit of the information bit sequence is assigned to each bit of the plurality of polar codes indicated by the first input bit index and the second input bit index. A control circuit comprising:

7. A storage medium for storing a program for controlling an encoding device including a division unit and an encoding unit, The program a first step in which the dividing unit allocates an input information bit sequence to input bits of a plurality of polar codes according to an index table; a second step in which the encoding unit connects the plurality of polar codes input in parallel from the dividing unit to generate parallel polar codes; causing the encoding device to execute the index table includes: a first input bit index indicating a bit determined based on the number K of the input bits of the polar code, the number QC of the polar codes input in parallel to the encoding unit, and a channel capacity at each bit position of the polar code; and a second input bit index indicating a bit determined based on the channel capacity and an error rate among bits not indicated by the first input bit index; In the first step, each bit of the information bit sequence is assigned to each bit of the plurality of polar codes indicated by the first input bit index and the second input bit index. A storage medium characterized by: