Driver IC and Display Device including the same

Abstract

The present invention may provide a display device comprising: a display panel for displaying an image; a driving unit for driving the display panel; and a power circuit for generating a voltage to be supplied to the display panel, wherein the power circuit comprises a resistor series of a circuit for generating a fixed or semi-fixed voltage and a resistor series of a circuit for generating a variable voltage, which are independently configured.

Description

Technology Field

[0001] The present invention relates to a driving unit and a display device including the same. Background Technology

[0002] As information technology advances, the market for display devices, which serve as a medium connecting users and information, is growing. Consequently, the use of display devices such as Light Emitting Display Devices (LEDs), Quantum Dot Display Devices (QDDs), and Liquid Crystal Display Devices (LCDs) is increasing.

[0003] The display devices described above include a display panel containing subpixels, a driving unit that outputs a driving signal for driving the display panel, and a power supply unit that generates power to be supplied to the display panel or the driving unit.

[0004] When driving signals, such as scan signals and data signals, are supplied to subpixels formed on a display panel, the selected subpixel transmits light or emits light directly, thereby displaying an image. The problem to be solved

[0005] The present invention maintains a stable voltage output by configuring a circuit that generates a variable voltage and a circuit that generates a fixed or semi-fixed voltage separately, thereby minimizing the effect of noise generated when the voltage of one side is varied propagating to the other side. means of solving the problem

[0006] The present invention may provide a display device comprising: a display panel for displaying an image; a driving unit for driving the display panel; and a power circuit for generating a voltage to be supplied to the display panel, wherein the power circuit comprises a resistor series of a circuit for generating a fixed or semi-fixed voltage and a resistor series of a circuit for generating a variable voltage, which are independently configured.

[0007] The above power circuit may include a main resistor array comprising resistors connected in series, a main decoder that generates a plurality of main regulating voltages based on a voltage output from a voltage divider node of the main resistor array, and a plurality of main regulator circuits that generate a fixed or semi-fixed voltage based on the plurality of main regulating voltages output from the main decoder.

[0008] The above power circuit may include a sub-resistor array comprising resistors connected in series, a sub-decoder that generates at least one sub-regulating voltage based on a voltage output from a voltage divider node of the sub-resistor array, and at least one sub-regulator circuit that generates the variable voltage based on at least one sub-regulating voltage output from the sub-decoder.

[0009] The above main resistor series and the above sub resistor series can be commonly connected to the output terminal of a reference voltage generating unit that outputs a reference voltage.

[0010] The above multiple main regulator circuits may include a low-pass filter to block high-frequency noise generated within the main resistor array.

[0011] The above variable voltage may be a voltage applied to the anode electrode of an organic light-emitting diode included in a subpixel of the display panel.

[0012] The above variable voltage can be varied when displaying an image on the display panel.

[0013] The above fixed or semi-fixed voltage may include a gate high voltage and a gate low voltage for driving the display panel.

[0014] In another aspect, the present invention may provide a driving unit comprising: an output circuit for outputting a data voltage; and an internal power supply circuit for generating a fixed or semi-fixed voltage and a variable voltage, wherein the internal power supply circuit comprises a fixed or semi-fixed voltage generating circuit including a main resistor series, a main decoder for generating a plurality of main regulating voltages based on a voltage output from a voltage divider node of the main resistor series, and a plurality of main regulator circuits for generating the fixed or semi-fixed voltage based on the plurality of main regulating voltages output from the main decoder, and a variable voltage generating circuit including a sub resistor series, a sub decoder for generating at least one sub regulating voltage based on a voltage output from a voltage divider node of the sub resistor series, and at least one sub regulator circuit for generating the variable voltage based on at least one sub regulating voltage output from the sub decoder.

[0015] The above multiple main regulator circuits may include a low-pass filter to block high-frequency noise generated within the main resistor array. Effects of the invention

[0016] The present invention has the effect of maintaining a stable voltage output by separating a circuit that generates a variable voltage from a circuit that generates a fixed or semi-fixed voltage, thereby minimizing the effect of noise generated when the voltage of one side varies and propagating to the other. Furthermore, since the present invention enables the maintenance of a stable voltage output even during voltage variation that occurs during operation for image display, it has the effect of minimizing the rate of image abnormalities in the display panel. Brief explanation of the drawing

[0017] FIG. 1 is a block diagram schematically showing a light-emitting display device, and FIG. 2 is a configuration diagram schematically showing a subpixel shown in FIG. 1. FIGS. 3 to 6 are drawings for explaining the configuration of a gate-in-panel type gate driving unit. FIG. 7 is a drawing showing a part of a display device applicable to an embodiment of the present invention, FIG. 8 is an example diagram of the configuration of a subpixel applicable to an embodiment of the present invention, and FIG. 9 to 11 are drawings for explaining a driving method of a subpixel shown in FIG. 8. FIG. 12 is a schematic diagram showing the configuration of a driving unit according to a first embodiment of the present invention, and FIG. 13 is a configuration diagram showing the internal power supply circuit according to a first embodiment of the present invention in more detail. FIG. 14 is a configuration diagram showing an internal power supply circuit according to a second embodiment of the present invention in more detail, and FIG. 15 is a diagram explaining the advantages of the internal power supply circuit according to the second embodiment. Specific details for implementing the invention

[0018] The display device according to the present invention may be implemented as a television, video player, personal computer (PC), home theater, automotive electrical system, smartphone, etc., but is not limited thereto. The display device according to the present invention may be implemented as a light-emitting display device (LED), a quantum dot display device (QDD), a liquid crystal display device (LCD), etc. However, for convenience of explanation, a light-emitting display device that directly emits light based on an inorganic light-emitting diode or an organic light-emitting diode is used as an example below.

[0019] FIG. 1 is a block diagram schematically showing a light-emitting display device, and FIG. 2 is a configuration diagram schematically showing a subpixel shown in FIG. 1.

[0020] As illustrated in FIGS. 1 and 2, the light-emitting display device may include an image supply unit (110), a timing control unit (120), a gate driving unit (130), a data driving unit (140), a display panel (150), and a power supply unit (180), etc.

[0021] The video supply unit (set or host system) (110) can output various driving signals along with video data signals supplied from the outside or video data signals stored in internal memory. The video supply unit (110) can supply the data signals and various driving signals to the timing control unit (120).

[0022] The timing control unit (120) can output a gate timing control signal (GDC) for controlling the operation timing of the gate driving unit (130), a data timing control signal (DDC) for controlling the operation timing of the data driving unit (140), and various synchronization signals.

[0023] The timing control unit (120) can supply a data signal (DATA) supplied from the image supply unit (110) along with a data timing control signal (DDC) to the data driving unit (140). The timing control unit (120) may be formed in the form of an IC (Integrated Circuit) and mounted on a printed circuit board, but is not limited thereto.

[0024] The gate driver (130) can output a gate signal (or gate voltage) in response to a gate timing control signal (GDC) supplied from the timing control unit (120). The gate driver (130) can supply a gate signal to subpixels included in the display panel (150) through gate lines (GL1~GLm). The gate driver (130) may be formed in the form of an IC or formed directly on the display panel (150) in a Gate In Panel manner, but is not limited thereto.

[0025] The data driver (140) can sample and latch a data signal (DATA) in response to a data timing control signal (DDC) supplied from the timing control unit (120), and convert the digital data signal into an analog data voltage based on a gamma reference voltage and output it. The data driver (140) can supply the data voltage to subpixels included in the display panel (150) through data lines (DL1~DLn). The data driver (140) may be formed in the form of an IC and mounted on the display panel (150) or mounted on a printed circuit board, but is not limited thereto.

[0026] The power supply unit (180) can generate high potential voltage and low potential voltage based on an external input voltage supplied from the outside and output them through the first power line (EVDD) and the second power line (EVSS). The power supply unit (180) can generate and output not only high potential voltage and low potential voltage, but also voltage required for driving the gate driving unit (130) (e.g., gate voltage including gate high voltage and gate low voltage) or voltage required for driving the data driving unit (140) (drain voltage including drain voltage and half-drain voltage).

[0027] The display panel (150) can display an image in response to a driving signal including a gate signal and a data voltage, and a driving voltage including a high potential voltage and a low potential voltage. The subpixels of the display panel (150) emit light directly. The display panel (150) can be manufactured based on a substrate having rigidity or flexibility, such as glass, silicon, or polyimide. The light-emitting subpixels can be composed of pixels including red, green, and blue, or pixels including red, green, blue, and white.

[0028] For example, a single subpixel (SP) may be connected to a first data line (DL1), a first gate line (GL1), a first power line (EVDD), and a second power line (EVSS), and may include a pixel circuit composed of a switching transistor, a driving transistor, a capacitor, an organic light-emitting diode, etc. Since the subpixel (SP) used in the light-emitting display device directly emits light, the circuit configuration is complex. In addition, there are various compensation circuits to compensate for the degradation of the organic light-emitting diode that emits light, as well as the driving transistor that supplies the driving current required to drive the organic light-emitting diode. Therefore, it is noted that the subpixel (SP) is simply illustrated in the form of a block.

[0029] Meanwhile, in the above description, the timing control unit (120), gate driving unit (130), and data driving unit (140) were described as being separate components. However, depending on the implementation method of the light-emitting display device, one or more of the timing control unit (120), gate driving unit (130), and data driving unit (140) may be integrated into a single IC.

[0030] FIGS. 3 to 6 are drawings for explaining the configuration of a gate-in-panel type gate driving unit.

[0031] As illustrated in FIG. 3, the gate-in-panel type gate driver (130) may include a shift register (131) and a level shifter (135). The level shifter (135) can generate clock signals (Clks) and start signals (Vst), etc., based on signals and voltages output from the timing control unit (120) and the power supply unit (180). The clock signals (Clks) can be generated in the form of J (where J is an integer greater than or equal to 2) with different phases, such as 2-phase, 4-phase, or 8-phase.

[0032] As illustrated in FIGS. 3 and 4, the level shifter (135), unlike the shift register (131), may be formed independently in the form of an IC or included inside the power supply (180). However, this is only one example and is not limited thereto.

[0033] As illustrated in FIG. 5, shift registers (131a, 131b) that output gate signals in a gate-in-panel type gate driver may be placed in a non-display area (NA) of a display panel (150). The shift registers (131a, 131b) may be formed in the form of a thin film on the display panel (150) by the gate-in-panel method. Although the shift registers (131a, 131b) are shown as being placed in the left and right non-display areas (NA) of the display panel (150) as an example, they are not limited thereto.

[0034] As shown in FIG. 6, the shift register (131a) can be connected to the gate high voltage line (VGH), gate low voltage line (VGL), start signal line (VST), first clock signal line (GCLK1), second clock signal line (GCLK2), etc.

[0035] The shift register (131a) includes a first stage (STG1) to a second stage (STGm), and these may have a dependent connection relationship to sequentially output signals. The first stage (STG1) to the second stage (STGm) operate based on signals and voltages supplied through the gate high voltage line (VGH), gate low voltage line (VGL), start signal line (VST), first clock signal line (GCLK1), and second clock signal line (GCLK2), and can output gate signals (Gout[1] to Gout[m]). The gate signals (Gout[1] to Gout[m]) can be output in the form of voltages that can turn on or turn off a transistor formed on a display panel.

[0036] Hereinafter, for convenience of explanation, the present invention is described as an example in which a timing control unit, a data driving unit, and a part of a power supply unit are integrated into a single driving unit, but they may be separated as described in FIG. 1.

[0037] FIG. 7 is a drawing showing a part of a display device applicable to an embodiment of the present invention, FIG. 8 is an example diagram of the configuration of a subpixel applicable to an embodiment of the present invention, and FIG. 9 to 11 are drawings for explaining a driving method of a subpixel shown in FIG. 8.

[0038] As illustrated in FIG. 7, the display device applicable to the embodiment may include a driving unit (160) positioned in a non-display area (NA) on one side (lower side) of the display panel (150). The driving unit (160) is a device in which a part of the timing control unit, data driving unit, and power supply unit described in FIG. 1 are integrated into one. A first shift register (131a) and a second shift register (131b) may be located in the left and right non-display areas (NA) of the display panel (150).

[0039] As illustrated in FIG. 8, the subpixel applicable to the embodiment may include a first transistor (T1), a second transistor (T2), a third transistor (T3), a fourth transistor (T4), a fifth transistor (T5), a sixth transistor (T6), a capacitor (CST), a driving transistor (DT), and an organic light-emitting diode (OLED).

[0040] The first transistor (T1), the second transistor (T2), the third transistor (T3), the fourth transistor (T4), the fifth transistor (T5), the sixth transistor (T6), and the driving transistor (DT) can be implemented as transistors including a silicon semiconductor layer, and the third transistor (T3) can be implemented as a transistor including an oxide semiconductor layer.

[0041] A subpixel applicable to the embodiment may be connected to a first gate line (GL1) comprising a first scan line (SCN1), a second scan line (SCN2), a third scan line (SCN3), and a first light emission control line (EM1). Here, the third scan line (SCN3) may use a scan line included in a preceding or succeeding subpixel other than the currently illustrated subpixel.

[0042] In response to a first scan signal transmitted through the first scan line (SCN1), the third transistor (T3) can be turned on, in response to a second scan signal transmitted through the second scan line (SCN2), the first transistor (T1) can be turned on, and in response to a third scan signal transmitted through the third scan line (SCN3), the fourth and sixth transistors (T4, T6) can be turned on. In response to a first light emission control signal transmitted through the first light emission control line (EM1), the second and fifth transistors (T2, T5) can be turned on.

[0043] As illustrated in FIG. 9, a display device applicable to the embodiment can turn on a third transistor (T3) to compensate for the threshold voltage of a driving transistor (DT), electrically connect the gate electrode and the second electrode of the driving transistor (DT) to create a diode connection state, and then apply a data voltage (Vdata). Subsequently, the driving transistor (DT) can generate a driving current to emit light from an organic light-emitting diode based on the data voltage stored in a capacitor (CST).

[0044] As illustrated in FIG. 10, a display device applicable to the embodiment may apply an OBS voltage (Vobs) through a fourth transistor (T4) that is turned on to maintain brightness during refresh driving. The OBS voltage (Vobs) may be selected as a voltage level capable of forming a specific condition (On Bias Stress; a condition to minimize afterimage visibility due to hysteresis) on the gate electrode of the driving transistor (DT) and the first electrode (Vgs).

[0045] As illustrated in FIG. 11, the display device applicable to the embodiment can perform normal driving at a normal driving frequency and low-speed driving at a driving frequency lower than the normal driving frequency. For example, a still image can be displayed during the low-speed driving section of the display panel, and a video can be displayed during the normal driving section of the display panel. The display device applicable to the embodiment can also perform high-speed driving at a driving frequency faster than the normal driving frequency.

[0046] Meanwhile, the aforementioned Refresh Drive (RF) is one of the driving methods inserted to maintain a constant brightness of the display panel during low-speed driving, and examples include the Frame Skip method, which inserts or skips frames in units of N frames (N is an integer greater than or equal to 2). In the Frame Skip method, a Refresh Section (RF) is inserted in units of N frames (N is an integer greater than or equal to 2), but an Anode Reset Section (AR) that resets the anode of the Organic Light Emitting Diode is added in between. For example, during low-speed driving, the Anode Reset Section (AR) may be added at least every frame, but is not limited thereto.

[0047] As illustrated in FIGS. 8 and 11, the sixth transistor (T6) can be turned on during an anode reset period (AR) that resets the anode of the organic light-emitting diode (OLED). When the sixth transistor (T6) is turned on, the organic light-emitting diode (OLED) can maintain a specific brightness based on a variable voltage delivered through a variable voltage line (VAR). Meanwhile, the variable voltage delivered through the variable voltage line (VAR) can be varied according to its purpose and the duration of application.

[0048] FIG. 12 is a schematic diagram showing the configuration of a driving unit according to a first embodiment of the present invention, and FIG. 13 is a configuration diagram showing the internal power supply circuit according to a first embodiment of the present invention in more detail.

[0049] As illustrated in FIG. 12, the driving unit (160) according to the first embodiment of the present invention may include a data receiving circuit (162), a control circuit (165), an output circuit (168), and an internal power supply circuit (170), etc.

[0050] The data receiving circuit (162) can receive data signals (DATA) and control signals (CONS) supplied from the outside and transmit them to a circuit included internally. The data receiving circuit (162) may also perform a restoration function to restore at least one of the data signals (DATA) and control signals (CONS).

[0051] The control circuit (165) can perform image processing or compensation processing of the data signal (DATA) and generate an internal control signal that controls the circuit contained within. The control circuit (165) can generate a voltage change signal that controls the internal power circuit (170) based on the control signals (CONS), and a start signal to be output through the start signal line (VST).

[0052] The output circuit (168) can perform the function of converting a digital data signal (DATA), which has been processed or compensated by the control circuit (165), into an analog data voltage and outputting it through the data lines (DL1~DLn).

[0053] The internal power circuit (170) can perform the role of generating a gate high voltage, a gate low voltage, and a variable voltage required for the operation of the display panel, and outputting them through the gate high voltage line (VGH), the gate low voltage line (VGL), and the variable voltage line (VAR).

[0054] As illustrated in FIG. 13, the internal power circuit (170) according to the first embodiment of the present invention may include a reference voltage generating unit (171), a main resistor row (172), a sub resistor row (173), a main decoder (174), a sub decoder (175), and a regulator circuit (176), etc.

[0055] The reference voltage generating unit (171) can generate a reference voltage (VREF) to be supplied to the main resistor row (172) and the sub resistor row (173). The reference voltage generating unit (171) can generate a reference voltage (VREF) based on a bandgap reference circuit to generate a stable voltage regardless of changes in power supply voltage or temperature.

[0056] In the embodiment, a resistor series may refer to a group of resistors comprising a plurality of resistors. For example, if a plurality of resistors are connected, the resistor series may refer to a plurality of connected resistors. As another example, a plurality of resistors connected in series, such as the illustrated main resistor series (172) or sub resistor series (173), may be referred to by the term 'resistor series'.

[0057] The main resistor (172) can generate a plurality of first main reference voltages (VREFM1) to Nth main reference voltages (VREFMn) based on the reference voltage (VREF) output from the main voltage generation unit (171).

[0058] The sub-resistor row (173) can serve to generate a plurality of first sub-reference voltages (VREFS1) to Nth sub-reference voltages (VREFSn) based on the reference voltage (VREF) output from the main voltage generation unit (171). That is, the main resistor row (172) and the sub-resistor row (173) can be commonly connected to the output terminal of the main voltage generation unit (171).

[0059] The main decoder (174) can generate a number of second regulating voltages (VREF_REG2) to M regulating voltages (VREF_REG2) based on the first main reference voltage (VREFM1) to the Nth main reference voltage (VREFMn) generated by the main resistor array (172).

[0060] The sub-decoder (175) can generate at least one first regulating voltage (VREF_REG1) based on the first sub-reference voltage (VREFS1) to the Nth sub-reference voltage (VREFSn) generated by the sub-resistance series (173). The sub-decoder (175) can vary the first regulating voltage (VREF_REG1) based on the first voltage change signal (Ctr1[x:0]) output from the control circuit.

[0061] The regulator circuit (176) can generate a second voltage (V2) to a second voltage (Vm), etc., based on a second regulating voltage (VREF_REG2) to a second regulating voltage (VREF_REG2) output from a main decoder (174), and also generate a first voltage (V1) based on a first regulating voltage (VREF_REG1) output from a sub decoder (175). To this end, the regulator circuit (176) may include a first regulator circuit (176a) to a second regulator circuit (176m).

[0062] The variable voltage (Var) output from the first regulator circuit (176a) can be varied in response to specific conditions and specific times during driving for image representation on the display panel. The variable voltage (Var) can be output as a negative voltage or a positive voltage. The variable voltage (Var) can be varied within a negative voltage range or a positive voltage range based on the first voltage change signal (Ctr[x:0]). The first voltage (V1) can be generated and varied for the purpose of applying it to a part where voltage variation is required. The first regulator circuit (176a) can be collectively referred to as a sub-regulator circuit.

[0063] The second voltage (V2) to the M voltage (Vm) output from the second regulator circuit (176b) to the M regulator circuit (176m) may be fixed without varying during driving for image representation on the display panel. The second voltage (V2) to the M voltage (Vm) may have different levels. The second voltage (V2) to the M voltage (Vm) may be generated for the purpose of applying to areas where voltage variation is not required. The second regulator circuit (176b) to the M regulator circuit (176m) may be collectively referred to as the main regulator circuit.

[0064] Meanwhile, in the internal power supply circuit (170) according to the first embodiment of the present invention, the circuits for generating a fixed voltage (172, 174, 176b~176m) and the circuits for generating a variable voltage (173, 175, 176a) are separated. By configuring the fixed voltage generating circuits (172, 174, 176b~176m) and the variable voltage generating circuits (173, 175, 176a) by circuit separation (Reference Voltage Distribution Network), the problem of the influence of noise being propagated to the other side can be prevented even if noise is generated in one side.

[0065] For example, the problem of noise generated when the voltage of the variable voltage generation circuit (173, 175, 176a) is propagated to the fixed voltage generation circuit (172, 174, 176b~176m) can be blocked. This is because there is no path for noise to propagate between the variable voltage generation circuit (173, 175, 176a) and the fixed voltage generation circuit (172, 174, 176b~176m). Meanwhile, noise may be generated at the decoder that is the subject of the voltage change and at the resistor connected thereto.

[0066] FIG. 14 is a configuration diagram showing an internal power supply circuit according to a second embodiment of the present invention in more detail, and FIG. 15 is a diagram explaining the advantages of the internal power supply circuit according to the second embodiment.

[0067] As illustrated in FIG. 14, the internal power circuit (170) according to the second embodiment of the present invention may include a reference voltage generating unit (171), a main resistor array (172), a sub resistor array (173), a main decoder (174), a sub decoder (175), and a regulator circuit (176), etc. Hereinafter, the second embodiment will be described mainly focusing on parts that are specific or different from the first embodiment.

[0068] The reference voltage generation unit (171) can generate a reference voltage (VREF) to be supplied to the main resistor row (172) and the sub resistor row (173). The reference voltage generation unit (171) can generate a reference voltage (VREF) based on the bandgap voltage (VBGR) output from the bandgap reference circuit (BGR Circuit). To this end, the reference voltage generation unit (171) may include an amplifier (AMP), a transistor (TR), a first resistor (R1), and a second resistor (R2), etc. The amplifier (AMP) can generate a reference voltage by controlling the on / off of the transistor (TR) based on the bandgap voltage (VBGR) input to the non-inverting terminal (+) and the feedback voltage input to the inverting terminal (-).

[0069] The main resistor array (172) can serve to generate a plurality of first main reference voltages (VREFM1) to Nth main reference voltages (VREFMn) based on the reference voltage (VREF) output from the main voltage generation unit (171). The main resistor array (172) includes main resistors (RMS) connected in series, and can generate a plurality of first main reference voltages (VREFM1) to Nth main reference voltages (VREFMn) by distributing the voltage into multiple levels through their voltage divider nodes.

[0070] The sub-resistor array (173) can serve to generate a plurality of first sub-reference voltages (VREFS1) to Nth sub-reference voltages (VREFSn) based on the reference voltage (VREF) output from the main voltage generation unit (171). The sub-resistor array (173) can be configured separately and independently from the main resistor array (172). The sub-resistor array (173) includes sub-resistors (RSS) connected in series, and can generate a plurality of first sub-reference voltages (VREFS1) to Nth sub-reference voltages (VREFSn) by distributing the voltage into multiple levels through their voltage divider nodes.

[0071] The main decoder (174) can generate a plurality of second regulating voltages (VREF_REG2) to M regulating voltages (VREF_REG2) based on the first main reference voltage (VREFM1) to the Nth main reference voltage (VREFMn) generated by the main resistor array (172). The main decoder (174) can generate the second regulating voltage (VREF_REG2) to M regulating voltages (VREF_REG2) based on a plurality of decoders. The main decoder (174) can vary at least one of the second regulating voltage (VREF_REG2) to M regulating voltage (VREF_REG2) based on the second to Kth voltage change signals (Ctr2[y:0], Ctr3[w:0], Ctrk[z:0]) output from the control circuit.

[0072] The sub-decoder (175) can generate at least one first regulating voltage (VREF_REG1) based on the first sub-reference voltage (VREFS1) to the Nth sub-reference voltage (VREFSn) generated by the sub-resistor series (173). The sub-decoder (175) can generate the first regulating voltage (VREF_REG1) based on the decoder. The sub-decoder (175) can vary the first regulating voltage (VREF_REG1) based on the first voltage change signal (Ctr1[x:0]) output from the control circuit.

[0073] The regulator circuit (176) can generate voltages such as gate high voltage (Vgh), gate low voltage (Vgl), and high potential voltage (Vdd) based on the second regulating voltage (VREF_REG2) to the second regulating voltage (VREF_REG2) output from the main decoder (174). Additionally, the regulator circuit (176) can generate voltages such as variable voltage (Var) based on the first regulating voltage (VREF_REG1) output from the sub decoder (175).

[0074] To this end, the regulator circuit (176) may include a first regulator circuit (176a) to a second regulator circuit (176m). Additionally, the second regulator circuit (176m) within the second regulator circuit (176b) may each include a low-pass filter (LPF) to block high-frequency noise generated inside the resistors (172, 173) by the instantaneous voltage charging / discharging current when the voltage of the main decoder (174) and the sub-decoder (175) changes. The low-pass filter (LPF) may be selected as a unit gain buffer or an RC filter, etc.

[0075] The variable voltage (Var) output from the first regulator circuit (176a) can be varied in response to specific conditions and specific times during driving for image representation on the display panel. The variable voltage (Var) can be output as a negative voltage or a positive voltage. The variable voltage (Var) can be varied within a negative voltage range or a positive voltage range based on the first voltage change signal (Ctr[x:0]). The first regulator circuit (176a) may be collectively referred to as a sub-regulator circuit.

[0076] The gate high voltage (Vgh), gate low voltage (Vgl), and high potential voltage (Vdd) output from the second regulator circuit (176b) to the second regulator circuit (176m) are fixed during driving for image representation on the display panel, but can be varied when the driving mode (compensation mode, sensing mode, initialization mode, etc.) is changed. The gate high voltage (Vgh), gate low voltage (Vgl), and high potential voltage (Vdd) may have different levels. The second regulator circuit (176b) to the second regulator circuit (176m) may be collectively referred to as the main regulator circuit.

[0077] Meanwhile, in the internal power supply circuit (170) according to the second embodiment of the present invention, the circuit generating semi-fixed voltage (172, 174, 176b~176m) and the circuit generating variable voltage (173, 175, 176a) are separated. By configuring the semi-fixed voltage generating circuit (172, 174, 176b~176m) and the variable voltage generating circuit (173, 175, 176a) to be circuit-separated, the problem of the influence of noise being propagated to the other side can be prevented even if noise is generated in one side.

[0078] Here, the semi-fixed voltage may be a voltage that can be changed among a plurality of predetermined voltages. For example, the semi-fixed voltage may be defined as a voltage selected as at least one of a value 'a' and a value 'b' depending on the situation or condition (e.g., when voltage compensation is required or voltage compensation is performed), and the semi-fixed voltage generating circuit (172, 174, 176b~176m) may selectively output a voltage other than one fixed voltage depending on the predetermined situation or condition.

[0079] In addition, the internal power circuit (170) according to the second embodiment of the present invention may include a low-pass filter (LPF) within the semi-fixed voltage generation circuit (172, 174, 176b~176m). As shown in FIG. 15, the low-pass filter (LPF) can mitigate voltage noise that may be induced during voltage change (VCP). The low-pass filter (LPF) can mitigate voltage noise corresponding to the gain value inside the filter.

[0080] The present invention has the effect of maintaining a stable voltage output by configuring a circuit that generates a variable voltage and a circuit that generates a fixed or semi-fixed voltage separately, thereby minimizing the effect of noise generated when the voltage of one side varies propagating to the other side. Furthermore, since the present invention enables the maintenance of a stable voltage output even when voltage varies during operation for image display, it has the effect of minimizing the rate of image abnormalities in the display panel. Explanation of the symbols

[0081] 150: Display panel 160: Driving unit 170: Internal power circuit 171: Reference voltage generation unit 172: Main resistor series 173: Sub resistor series 174: Main decoder 175: Sub decoder 176: Regulator Circuit

Claims

Claim 1 A display device comprising: a display panel for displaying an image; a driving unit for driving the display panel; and a power circuit for generating a voltage to be supplied to the display panel, wherein the power circuit comprises a main resistor array, a main decoder for generating a plurality of main regulating voltages based on a voltage output from a voltage divider node of the main resistor array, a fixed or semi-fixed voltage generating circuit comprising a plurality of main regulator circuits for generating a fixed or semi-fixed voltage based on the plurality of main regulating voltages output from the main decoder, and a variable voltage generating circuit comprising a sub resistor array, a sub decoder for generating at least one sub regulating voltage based on a voltage output from a voltage divider node of the sub resistor array, and at least one sub regulator circuit for generating a variable voltage based on at least one sub regulating voltage output from the sub decoder, wherein the variable voltage is a voltage applied to the anode electrode of an organic light-emitting diode included in a subpixel of the display panel. Claim 2 delete Claim 3 delete Claim 4 In claim 1, the main resistor series and the sub resistor series are a display device commonly connected to the output terminal of a reference voltage generating unit that outputs a reference voltage. Claim 5 In claim 1, the plurality of main regulator circuits include a low-pass filter for blocking high-frequency noise generated within the main resistor array. Claim 6 delete Claim 7 In claim 1, the variable voltage is a display device that varies when displaying an image on the display panel. Claim 8 In claim 1, the fixed or semi-fixed voltage comprises a gate high voltage and a gate low voltage for driving the display panel, in a display device. Claim 9 An output circuit that outputs a data voltage; and an internal power supply circuit that generates a fixed or semi-fixed voltage and a variable voltage, wherein the internal power supply circuit comprises a fixed or semi-fixed voltage generating circuit including a main resistor array, a main decoder that generates a plurality of main regulating voltages based on a voltage output from a voltage divider node of the main resistor array, and a plurality of main regulator circuits that generate the fixed or semi-fixed voltage based on the plurality of main regulating voltages output from the main decoder, and a variable voltage generating circuit including a sub resistor array, a sub decoder that generates at least one sub regulating voltage based on a voltage output from a voltage divider node of the sub resistor array, and at least one sub regulator circuit that generates the variable voltage based on at least one sub regulating voltage output from the sub decoder, wherein the variable voltage is a voltage applied to the anode electrode of an organic light-emitting diode included in a sub-pixel of a display panel. Claim 10 In claim 9, the plurality of main regulator circuits include a driving unit comprising a low-pass filter for blocking high-frequency noise generated within the main resistor array. Claim 11 In claim 1, the variable voltage is a display device that varies within a negative voltage range or a positive voltage range based on a voltage change signal. Claim 12 In claim 11, the variable voltage is a display device that varies as the sub-decoder varies the sub-regulating voltage based on the voltage change signal.

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