Display panel and display device including the same

Abstract

The display panel includes a first sub-display panel, a second sub-display panel adjacent to the first sub-display panel in a first direction, and a connecting member electrically connecting the first sub-display panel and the second sub-display panel. The first sub-display panel includes a first pixel, a second pixel adjacent to the first pixel and the second sub-display panel, a first low-power voltage wiring that transmits a low-power voltage to the first pixel, and a first gate wiring that is electrically connected to the first pixel and the second pixel, wherein the second pixel receives a low-power voltage from the first low-power voltage wiring. The second sub-display panel includes a third pixel adjacent to the first sub-display panel, and the third pixel is electrically connected to the first gate wiring.

Description

Technology Field

[0001] The present invention relates to a display panel and a display device including the same. More specifically, the present invention relates to a display panel to which a power supply voltage is applied and a display device including the same. Background Technology

[0002] Recently, interest in display devices has been growing. Accordingly, display devices are being manufactured in various types, including organic light emitting diodes (OLEDs), liquid crystal displays (LCDs), and quantum-dot nano light emitting diodes (QNEDs).

[0003] In addition, research is being conducted to enlarge the display device. The enlarged display device may include a plurality of display panels. For example, the display device may include a tiled display device that combines a plurality of display panels to form a single display device.

[0004] A tiled display device may use a conductive connecting member to combine a plurality of display panels. However, the distance between pixels placed adjacent to the connection area of ​​the plurality of display panels may be increased. Accordingly, the connection area (e.g., a seam line) may be visible from the outside. The problem to be solved

[0005] The technical problem of the present invention is conceived in this regard, and the objective of the present invention is to provide a display panel with improved display quality.

[0006] The object of the present invention is to provide a display device including the above-mentioned display panel.

[0007] However, the problem to be solved by the present invention is not limited to the problem mentioned above, and may be expanded in various ways without departing from the spirit and scope of the present invention. means of solving the problem

[0008] A display panel according to embodiments for realizing the purpose of the present invention described above may include a first sub-display panel, a second sub-display panel adjacent to the first sub-display panel in a first direction, and a connecting member electrically connecting the first sub-display panel and the second sub-display panel. The first sub-display panel includes a first pixel, a second pixel adjacent to the first pixel and the second sub-display panel, a first low-power voltage wiring that transmits a low-power voltage to the first pixel, and a first gate wiring electrically connected to the first pixel and the second pixel, wherein the second pixel may receive the low-power voltage from the first low-power voltage wiring. The second sub-display panel includes a third pixel adjacent to the first sub-display panel, and the third pixel may be electrically connected to the first gate wiring.

[0009] In the embodiments, the first sub-display panel further includes a low power voltage transmission wiring, and the low power voltage transmission wiring can be electrically connected to the first low power voltage wiring by a contact hole.

[0010] In the embodiments, the low power supply voltage transmission wiring and the first low power supply voltage wiring may be perpendicular to each other.

[0011] In the embodiments, the second pixel can receive the low power voltage through the low power voltage transmission wiring.

[0012] In the embodiments, the first pixel further includes a plurality of low power voltage connection wires, and the low power voltage connection wires can be electrically connected to the low power voltage transmission wires by a contact hole.

[0013] In the embodiments, the low power supply voltage connection wiring can be electrically connected to the cathode electrode of the light-emitting element.

[0014] In the embodiments, the second sub-display panel may further include a fourth pixel adjacent to the third pixel and spaced apart from the first sub-display panel by the third pixel, a second low-power voltage wiring that applies the low-power voltage to the fourth pixel; and a second gate wiring electrically connected to the first gate wiring, the third pixel, and the fourth pixel.

[0015] In the embodiments, the second sub-display panel further includes a low power voltage transmission wiring, the low power voltage transmission wiring is electrically connected to the second low power voltage wiring by a contact hole, and the third pixel can receive the low power voltage through the low power voltage transmission wiring.

[0016] In the embodiments, the low power voltage transmission wiring may be perpendicular to the second low power voltage wiring.

[0017] In the embodiments, the second pixel further includes a plurality of low power voltage connection wires, and the low power voltage connection wires can be electrically connected to the low power voltage transmission wires by a contact hole.

[0018] In the embodiments, the low power supply voltage connection wiring can be electrically connected to the cathode electrode of the light-emitting element.

[0019] In the embodiments, the first sub-display panel further includes a first connection pad disposed adjacent to the second pixel and the second sub-display panel, and the second sub-display panel may further include a second connection pad disposed adjacent to the third pixel and the first sub-display panel.

[0020] In the embodiments, the first connecting pad and the second connecting pad may come into contact with the connecting member.

[0021] In the embodiments, the first connection pad is electrically connected to the first gate wiring, and the second connection pad may be electrically connected to the second gate wiring that is electrically connected to the third pixel.

[0022] In the embodiments, the first connection pad includes a conductive layer electrically connected to the first gate wiring, and the thickness of the conductive layer may be thicker than the thickness of the first gate wiring.

[0023] In the embodiments, the first connection pad further includes a via insulating layer, and the thickness of the via insulating layer may be thicker than the thickness of the conductive layer.

[0024] In the embodiments, the second connection pad includes a conductive layer connected to the second gate wiring, and the thickness of the conductive layer may be thicker than the thickness of the second gate wiring.

[0025] In the embodiments, the second connection pad further includes a via insulating layer, and the thickness of the via insulating layer may be thicker than the thickness of the conductive layer.

[0026] In the embodiments, the connecting member may include a conductive material.

[0027] In the embodiments, the connecting member may include an anisotropic conductive film.

[0028] A display device according to embodiments for realizing the purpose of the present invention described above may include a gate driver and a display panel disposed on one side of the gate driver and electrically connected to the gate driver. The display panel may include a first sub-display panel, a second sub-display panel adjacent to the first sub-display panel in a first direction, and a connecting member electrically connecting the first sub-display panel and the second sub-display panel. The first sub-display panel includes a first pixel, a second pixel adjacent to the first pixel and the second sub-display panel, a first low-power voltage wiring that transmits a low-power voltage to the first pixel, and a first gate wiring electrically connected to the gate driver, the first pixel, and the second pixel, wherein the second pixel may receive the low-power voltage from the first low-power voltage wiring. The second sub-display panel includes a third pixel adjacent to the first sub-display panel, and the third pixel may be electrically connected to the first gate wiring.

[0029] In the embodiments, the first sub-display panel further includes a low power voltage transmission wiring, and the low power voltage transmission wiring can be electrically connected to the first low power voltage wiring by a contact hole.

[0030] In the embodiments, the first pixel further includes a plurality of low power voltage connection wires, and the low power voltage connection wires can be electrically connected to the low power voltage transmission wires by a contact hole.

[0031] In the embodiments, the low power supply voltage connection wiring can be electrically connected to the cathode electrode of the light-emitting element.

[0032] In the embodiments, the second sub-display panel may further include a fourth pixel adjacent to the third pixel and spaced apart from the first sub-display panel by the third pixel, a second low-power voltage wiring that applies the low-power voltage to the fourth pixel, the first gate wiring, and a second gate wiring electrically connected to the third pixel and the fourth pixel.

[0033] In the embodiments, the second sub-display panel further includes a low power voltage transmission wiring, the low power voltage transmission wiring is electrically connected to the second low power voltage wiring by a contact hole, and the third pixel can receive the low power voltage through the low power voltage transmission wiring.

[0034] In the embodiments, the second pixel further includes a plurality of low power voltage connection wires, and the low power voltage connection wires can be electrically connected to the low power voltage transmission wires by a contact hole.

[0035] In the embodiments, the low power supply voltage connection wiring can be electrically connected to the cathode electrode of the light-emitting element. Effects of the invention

[0036] A display panel according to embodiments of the present invention may include first and second sub-display panels. A connecting member may be arranged to connect the first and second sub-display panels. The first sub-display panel may include a first pixel and a second pixel. The second pixel may receive a low power voltage from the first pixel without including a separate low power voltage wiring. Additionally, the second sub-display panel may include a third pixel and a fourth pixel. The third pixel may receive a low power voltage from the fourth pixel without including a separate power voltage wiring. The third pixel may be arranged adjacent to the second pixel with the connecting member in between.

[0037] Accordingly, since low-power voltage wiring does not need to be placed in the second pixel and the third pixel, additional space can be secured for placing separate components. By placing the connecting member and connecting pads in this space, the difference in the gap between the second pixel and the third pixel may not be large. As a result, the connection area (e.g., seam line) caused by the connecting member and the connecting pads may not be visible from the outside.

[0038] However, the effects of the present invention are not limited to the above effects and may be extended in various ways without departing from the spirit and scope of the present invention. Brief explanation of the drawing

[0039] FIG. 1 is a block diagram showing a display device according to embodiments of the present invention. FIGS. 2 and FIGS. 3 are plan views schematically illustrating embodiments of the display device of FIG. 1. FIGS. 4 to 6 are circuit diagrams showing embodiments of a pixel circuit included in the display device of FIG. 1. FIGS. 7 to 15 are layout drawings showing the first pixel of the display device of FIG. 1. FIGS. 16 and FIGS. 17 are layout drawings showing the second pixel of the display device of FIG. 1. FIG. 18 is a layout drawing showing the first pixel and the second pixel of the display device of FIG. 1. FIG. 19 is a layout drawing showing the third pixel and the fourth pixel of the display device of FIG. 1. FIG. 20 is an enlarged view showing an embodiment of regions A and B of FIG. 2. FIG. 21 is an enlarged view showing an embodiment of regions A and B of FIG. 2. FIG. 22 is a cross-sectional view showing one embodiment cut along line II of FIG. 21. FIG. 23 is a cross-sectional view showing one embodiment cut along line II of FIG. 21. FIG. 24 is a cross-sectional view showing one embodiment cut along the line II-II' of FIG. 21. FIG. 25 is a cross-sectional view showing one embodiment cut along the line II-II' of FIG. 21. Specific details for implementing the invention

[0040] Hereinafter, embodiments of the present invention will be described in more detail with reference to the attached drawings. Identical components in the drawings are given the same reference numerals, and redundant descriptions of identical components are omitted.

[0041] FIG. 1 is a block diagram showing a display device according to embodiments of the present invention, and FIG. 2 and FIG. 3 are plan views schematically showing embodiments of the display device of FIG. 1.

[0042] Referring to FIGS. 1 to 3, the display device may include a display panel (DP), a data driver (DDV), a gate driver (GDV), and a timing control unit (CON).

[0043] In the embodiments, the display panel (DP) may include a plurality of sub-display panels. For example, as shown in FIG. 2, the display panel (DP) may include sub-display panels (SDP1, SDP2, SDP3, SDP4) arranged in a matrix form. Additionally, as shown in FIG. 3, the display panel (DP) may include display panels (SDP5, DP6, DP7, DP8) combined in a first direction (DR1). Although FIG. 2 and FIG. 3 show the display panel (DP) including four display panels, this is exemplary and not limited thereto. For example, the display panel (DP) may include N display panels (where N is a natural number greater than or equal to 2).

[0044] The display panel (DP) may include a plurality of pixel regions. Each of the pixel regions may include a pixel. The pixel may include a plurality of sub-pixels. The pixel may be connected to the light-emitting structure. The display panel (DP) may display an image through the light-emitting structure. For example, the light-emitting structure may include an organic light-emitting diode (OLED), a quantum-dot organic light-emitting diode (QDOLED), a quantum-dot nano light-emitting diode (QNED), etc.

[0045] The timing control unit (CON) can generate a gate control signal (GCTRL), a data control signal (DCTRL), and output image data (ODAT) based on a control signal (CTRL) and input image data (IDAT) provided from the outside. For example, the control signal (CTRL) may include a vertical synchronization signal, a horizontal synchronization signal, an input data enable signal, a master clock signal, etc. For example, the input image data (IDAT) may be RGB data including red image data, green image data, and blue image data. Alternatively, the input image data (IDAT) may include magenta image data, cyan image data, and yellow image data.

[0046] The gate driver (GDV) can generate gate signals based on the gate control signal (GCTRL) provided by the timing control unit (CON). For example, the gate control signal (GCTRL) may include a vertical start signal, a clock signal, etc.

[0047] The gate driver (GDV) is electrically connected to the display panel (DP) and can sequentially output the gate signals. Each of the pixels can receive a data voltage according to the control of each of the gate signals.

[0048] The data driving unit (DDV) can generate the data voltage based on the data control signal (DCTRL) and the output image data (ODAT) provided by the timing control unit (CON). For example, the data control signal (DCTRL) may include an output data enable signal, a horizontal start signal, a load signal, etc.

[0049] The data driving unit (DDV) is electrically connected to the display panel (DP) and can generate a plurality of data voltages. Each of the pixels can transmit a signal for brightness corresponding to each of the data voltages to the light-emitting structure.

[0050] FIGS. 4 to 6 are circuit diagrams showing embodiments of a pixel circuit included in the display device of FIG. 1, and FIGS. 7 to 15 are layout drawings showing a first pixel of the display device of FIG. 1.

[0051] Referring to FIGS. 4, FIGS. 5, FIGS. 6 and FIGS. 7, the first pixel may be placed in a first pixel area (EA1). For example, the first pixel area (EA1) may be located in area A of FIG. 2. The first pixel may include a plurality of subpixels (e.g., a first subpixel (SP1), a second subpixel (SP2), and a third subpixel (SP3) of FIG. 13). For example, the first subpixel (SP1) of FIG. 13 may correspond to the first pixel circuit (PC1) of FIG. 4, the second subpixel (SP2) of FIG. 13 may correspond to the second pixel circuit (PC2) of FIG. 5, and the third subpixel (SP3) of FIG. 13 may correspond to the third pixel circuit (PC3) of FIG. 6.

[0052] The first pixel may include a first metal layer. The first metal layer may include a conductive material. For example, the first metal layer may include titanium (Ti), copper (Cu), etc. However, this is exemplary, and the first metal layer may further include a conductive material.

[0053] The first metal layer may include a power supply voltage wiring, a sensing wiring (SL1), a first transmission electrode (110), a second transmission electrode (120) and a third transmission electrode (130), a first data wiring (DL1), a second data wiring (DL2) and a third data wiring (DL3).

[0054] The above power voltage wiring may include a low power voltage wiring (ELVSS1) and a high power voltage wiring (ELVDD1). A low power voltage (ELVSS) may be applied to the low power voltage wiring (ELVSS1).

[0055] The above high power voltage wiring (ELVDD1) may be placed in the first direction (DR1) of the above low power power wiring (ELVSS1). A high power voltage (ELVDD) may be applied to the above high power voltage wiring (ELVDD1).

[0056] The sensing wiring (SL1) may be placed between the low power voltage wiring (ELVSS1) and the high power voltage wiring (ELVDD1). An initialization voltage (VINT) may be applied to the sensing wiring (SL1).

[0057] The sensing wiring (SL1), the low power voltage wiring (ELVSS1), and the high power voltage wiring (ELVDD1) can be extended in a second direction (DR2) perpendicular to the first direction (DR1).

[0058] The first data line (DL1), the second data line (DL2), and the third data line (DL3) may be spaced apart from each other in the first direction (DR1). A data voltage (DATA) may be applied to the first data line (DL1), the second data line (DL2), and the third data line (DL3). For example, a red data voltage may be applied to the first data line (DL1), a green data voltage may be applied to the second data line (DL2), and a blue data voltage may be applied to the third data line (DL3).

[0059] Referring to FIGS. 4, 5, 6, 8, and 9, the first pixel may include a second metal layer. The second metal layer may be disposed on the first metal layer. The second metal layer may include a conductive material (e.g., a transparent conductive material). For example, the second metal layer may include IGZO, etc. However, this is exemplary, and the second metal layer may further include a conductive material.

[0060] The second metal layer may include a first active pattern (ACT1), a second active pattern (ACT2), a third active pattern (ACT3), a fourth active pattern (ACT4), a fifth active pattern (ACT5), a sixth active pattern (ACT6), a seventh active pattern (ACT7), an eighth active pattern (ACT8), and a ninth active pattern (ACT9).

[0061] The first active pattern (ACT1) can serve as the channel for the first transistor (T1). The fourth active pattern (ACT4) can serve as the channel for the fourth transistor (T4). The seventh active pattern (ACT7) can serve as the channel for the seventh transistor (T7). The second active pattern (ACT2) can serve as the channel for the second transistor (T2). The fifth active pattern (ACT5) can serve as the channel for the fifth transistor (T5). The eighth active pattern (ACT8) can serve as the channel for the eighth transistor (T8). The third active pattern (ACT3) can serve as the channel for the third transistor (T3). The sixth active pattern (ACT6) can serve as the channel for the sixth transistor (T6). The ninth active pattern (ACT9) can serve as the channel for the ninth transistor (T9).

[0062] Referring to FIGS. 4, 5, 6, 10, and 11, the first pixel may include a third metal layer. The third metal layer may be disposed on the second metal layer. The third metal layer may include a conductive material. For example, the third metal layer may include titanium (Ti), copper (Cu), etc. However, this is exemplary, and the third metal layer may further include a conductive material.

[0063] The first gate pattern (GATE1) can partially overlap with the first active pattern (ACT1). The first gate pattern (GATE1) can serve as the gate of the first transistor (T1).

[0064] The second gate pattern (GATE2) may partially overlap with the second active pattern (ACT2), the fifth active pattern (ACT5), and the eighth active pattern (ACT8). The second gate pattern (GATE2) may serve as the gate for the second transistor (T2), the fifth transistor (T5), and the eighth transistor (T8).

[0065] The third gate pattern (GATE3) may partially overlap with the third active pattern (ACT3), the sixth active pattern (ACT6), and the ninth active pattern (ACT9). The third gate pattern (GATE3) may serve as the gate for the third transistor (T3), the sixth transistor (T6), and the ninth transistor (T9).

[0066] The fourth gate pattern (GATE4) may partially overlap with the fourth active pattern (ACT4). The fourth gate pattern (GATE4) may serve as the gate of the fourth transistor (T4).

[0067] The fifth gate pattern (GATE5) can partially overlap with the fifth active pattern (ACT5). The fifth gate pattern (GATE5) can serve as the gate of the seventh transistor (T7).

[0068] Referring to FIGS. 4, 5, 6, 11, 12, and 13, the first pixel may include a fourth metal layer. The fourth metal layer may be disposed on the third metal layer. The fourth metal layer may include a conductive material. For example, the third metal layer may include titanium (Ti), copper (Cu), etc. However, this is exemplary, and the fourth metal layer may further include a conductive material.

[0069] The above-mentioned fourth metal layer may include a first connecting electrode (CE1), a second connecting electrode (CE2), a third connecting electrode (CE3), a fourth connecting electrode (CE4), a fifth connecting electrode (CE5), a sixth connecting electrode (CE6), a seventh connecting electrode (CE7), an eighth connecting electrode (CE8), a ninth connecting electrode (CE9), a tenth connecting electrode (CE10), an eleventh connecting electrode (CE11), a gate wiring (CL1), and power supply voltage transfer wiring (CL2).

[0070] The first connecting electrode (CE1) can electrically connect the sensing wiring (SL1) and the third transistor (T3), the sixth transistor (T6), and the ninth transistor (T9). An initialization voltage (VINT) flowing through the sensing wiring (SL1) can be applied to the first connecting electrode (CE1) through a contact hole. Afterward, the first connecting electrode (CE1) can be connected to each of the third active pattern (ACT3), the sixth active pattern (ACT6), and the ninth active pattern (ACT9) through a contact hole.

[0071] The second connecting electrode (CE2) can electrically connect the high power voltage wiring (ELVDD1) and the first transistor (T1), the fourth transistor (T4), and the seventh transistor (T7). The high power voltage (ELVDD) flowing through the high power voltage wiring (ELVDD1) can be applied to the second connecting electrode (CE2) through the contact hole. After that, the second connecting electrode (CE1) can be connected to each of the first active pattern (ACT1), the fourth active pattern (ACT4), and the seventh active pattern (ACT7) through the contact hole.

[0072] The third connecting electrode (CE3) can be electrically connected to the first active pattern (ACT1) through a contact hole. A high power supply voltage (ELVDD) can be applied to the third connecting electrode (CE3). Through this, the third connecting electrode (CE3) can form the first gate pattern (GATE1) and the first capacitor (CST1). Additionally, the third connecting electrode (CE3) can be electrically connected to the third active pattern (ACT3) through a contact hole. Through this, the high power supply voltage (ELVDD) can be transmitted to the third transistor (T3). Additionally, the third connecting electrode (CE3) can be connected to the first gate electrode (GATE1) by a contact hole. The third connecting electrode (CE3) can transmit the first data voltage (DATA1) to the third transistor (T3).

[0073] The fourth connecting electrode (CE4) can be electrically connected to the first gate pattern (GATE1) by a contact hole. The fourth connecting electrode (CE4) can be electrically connected to the second active pattern (ACT2) by a contact hole. The first data voltage (DATA1) flowing through the first data wiring (DL1) can be applied to the fourth connecting electrode (CE4).

[0074] The fifth connection electrode (CE5) can be electrically connected to the first data wiring (DL1) by a contact hole. The fifth connection electrode (CE5) can be electrically connected to the second active pattern (ACT2) by a contact hole. Through this, the fifth connection electrode (CE5) can transmit the first data voltage (DATA1) to the second transistor (T2).

[0075] The sixth connecting electrode (CE6) can be electrically connected to the fourth active pattern (ACT4) by a contact hole. Through this, a high power voltage (ELVDD) can be applied to the sixth connecting electrode (CE6). The sixth connecting electrode (CE6) can be electrically connected to the second transfer electrode (120) by a contact hole. The sixth connecting electrode (CE6) can form a second capacitor (CST2) with the fourth gate electrode (GATE4). The sixth connecting electrode (CE6) can be electrically connected to the sixth active pattern (ACT6) by a contact hole. Through this, an initialization voltage (VINT) can be applied to the sixth connecting electrode (CE6).

[0076] The seventh connecting electrode (CE7) can be electrically connected to the fourth gate pattern (GATE4) by a contact hole. Additionally, the seventh connecting electrode (CE7) can be electrically connected to the fifth active pattern (ACT5) by a contact hole. Through this, a second data voltage (DATA2) can be applied to the seventh connecting electrode (CE7).

[0077] The eighth connecting electrode (CE8) can be electrically connected to the fifth gate pattern (GATE5) by a contact hole. Additionally, the eighth connecting electrode (CE8) can be electrically connected to the eighth active pattern (ACT8) by a contact hole. Through this, the third data voltage (DATA3) can be applied to the eighth connecting electrode (CE8).

[0078] The ninth connection electrode (CE9) can be electrically connected to the second data wiring (DL2) by a contact hole. Additionally, the ninth connection electrode (CE9) can be electrically connected to the fifth active pattern (ACT5) by a contact hole. Through this, the second data voltage (DATA2) can be applied to the fifth transistor (T5).

[0079] The 10th connection electrode (CE10) can be electrically connected to the 3rd data wiring (DL3) by a contact hole. Additionally, the 10th connection electrode (CE10) can be electrically connected to the 8th active pattern (ACT8) by a contact hole. Through this, the 3rd data voltage (DATA3) can be applied to the 8th transistor (T8).

[0080] The 11th connecting electrode (CE11) can be electrically connected to the 7th active pattern (ACT7) by a contact hole. A high power supply voltage (ELVDD) can be applied to the 11th connecting electrode (CE11). The 11th connecting electrode (CE11) can be electrically connected to the 9th active pattern (ACT9) by a contact hole. An initialization voltage (VINT) can be applied to the 11th connecting electrode (CE11). Additionally, the 11th connecting electrode (CE11) can be electrically connected to the 3rd transfer electrode (130) by a contact hole. Through this, the 3rd transfer electrode (130) can form the 5th gate pattern (GATE5) and the 3rd capacitor (CST3).

[0081] The gate wiring (CL1) can be extended in the first direction (DR1). The gate wiring (CL1) can be connected to the gate driver (GDV) of FIG. 1. Through this, a gate signal (GS) can flow through the gate wiring (CL1). The gate wiring (CL1) can be electrically connected to the second gate pattern (GATE2). Through this, the gate signal (GS) can be applied to the second transistor (T2), the fifth transistor (T5), and the eighth transistor (T8).

[0082] The low power voltage transmission wiring (CL2) may be extended in the first direction (DR1). The low power voltage transmission wiring (CL2) may be electrically connected to the low power voltage wiring (ELVSS1) by a contact hole. The low power voltage (ELVSS) flowing in the second direction (DR2) through the low power voltage wiring (EVLSS1) may flow in the second direction (DR2) through the low power voltage transmission wiring (CL2).

[0083] Referring to FIGS. 4, 5, 6, 13, 14, and 15, the first pixel may include a fifth metal layer. The fifth metal layer may be disposed on the fourth metal layer. The fifth metal layer may include a conductive material. For example, the fifth metal layer may include aluminum (Al), etc. However, this is exemplary, and the fifth metal layer may further include a conductive material. In the embodiments, the fifth metal layer may serve as a reflective layer.

[0084] The above fifth metal layer may include a first low power supply voltage connection wire (CL3), a second low power supply voltage connection wire (CL4), a third low power supply voltage connection wire (CL5), a first high power supply voltage connection wire (CL6), a second high power supply voltage connection wire (CL7), and a third high power supply voltage connection wire (CL8).

[0085] The first low-power voltage connection wiring (CL3), the second low-power voltage connection wiring (CL4), and the third low-power voltage connection wiring (CL5) can be electrically connected to the low-power power transmission wiring (CL2) by means of contact holes. Through this, a low-power voltage (ELVSS) can be applied to the first low-power voltage connection wiring (CL3), the second low-power voltage connection wiring (CL4), and the third low-power voltage connection wiring (CL5). The first low-power voltage connection wiring (CL3), the second low-power voltage connection wiring (CL4), and the third low-power voltage connection wiring (CL5) can be connected to the cathode electrode of a light-emitting element. In the embodiments, the light-emitting element may include an organic light-emitting diode (OLED), a quantum-dot organic light-emitting diode (QDOLED), a quantum-not nano light-emitting diode (QNED), etc.

[0086] The first high power supply voltage connection wiring (CL6) can be electrically connected to the third connection electrode (CE3) by means of a contact hole. The first high power supply voltage connection wiring (CL6) can receive a high power supply voltage (ELVDD) from the third connection electrode (CE3). The first high power supply voltage connection wiring (CL6) can be electrically connected to the first anode electrode of a light-emitting element.

[0087] The second high power supply voltage connection wiring (CL7) can be electrically connected to the first connection electrode (CE11) by means of a contact hole. The second high power supply voltage connection wiring (CL7) can receive a high power supply voltage (ELVDD) from the first connection electrode (CE11). The second high power supply voltage connection wiring (CL7) can be electrically connected to the second anode electrode of a light-emitting element.

[0088] The third high power supply voltage connection wiring (CL8) can be electrically connected to the sixth connection electrode (CE6) by a contact hole. The third high power supply voltage connection wiring (CL8) can receive a high power supply voltage (ELVDD) from the sixth connection electrode (CE6). The third high power supply voltage connection wiring (CL8) can be electrically connected to the third anode electrode of the light-emitting element.

[0089] FIGS. 16 and FIGS. 17 are layout drawings showing a second pixel of the display device of FIG. 1. The second pixel may be substantially identical to the first pixel of FIG. 16, except that it does not include low power voltage wiring in the first metal layer. Accordingly, the description of redundant configurations is omitted.

[0090] Referring to FIGS. 4, FIGS. 5, FIGS. 6, FIGS. 16, and FIGS. 17, the second pixel may be placed in the second pixel area (EA2). For example, the second pixel area (EA2) may be located in area A of FIG. 2. The second pixel may include a first subpixel (SP1), a second subpixel (SP2), and a third subpixel (SP3). For example, the first subpixel (SP1) may correspond to the first pixel circuit (PC1), the second subpixel (SP2) may correspond to the second pixel circuit (PC2), and the third subpixel (SP3) may correspond to the third pixel circuit (PC3).

[0091] The second pixel may receive a low power supply voltage (ELVSS) from the first pixel. In embodiments, the gate wiring (CL1) and the low power supply voltage transfer wiring (CL2) may extend to the second pixel region (EA2). The second pixel may be electrically connected to the gate wiring (CL1) and the low power supply voltage transfer wiring (CL2). The second pixel may be connected to the cathode electrodes of the light-emitting element through a plurality of low power supply voltage connection wirings (CL3, CL4, CL5). Additionally, the second pixel may be connected to the anode electrodes of the light-emitting element through a plurality of high power supply voltage connection wirings (CL6, CL7, CL8).

[0092] In this way, the second pixel can receive the low power voltage (ELVSS) from the first pixel without having the low power voltage wiring separately arranged. Accordingly, the second pixel can additionally utilize the space where the low power voltage wiring was previously arranged. For example, the second pixel can move in a third direction (DR3) opposite to the first direction (DR1) by the width (D1) of the space where the low power voltage wiring was previously arranged.

[0093] FIG. 18 is a layout drawing showing the first pixel, the second pixel, and the connection pad of the display device of FIG. 1.

[0094] Referring to FIG. 18, the first pixel and the second pixel may be arranged adjacently. The gate wiring (CL1) and the low power voltage transfer wiring (CL2) may extend from the first pixel area (EA1) to the second pixel area (EA2). In embodiments, the gate wiring (CL1) may be connected to the connection pad (PAD). The connection pad (PAD) may be placed in the first pad area (PA1).

[0095] FIG. 19 is a layout drawing showing the third pixel and the fourth pixel of the display device of FIG. 1.

[0096] Referring to FIG. 19, the display device may include a third pixel and a fourth pixel. The third pixel may be placed in a third pixel area (EA3). For example, the third pixel area (EA3) may be located in area B of FIG. 2. The third pixel may have a structure substantially identical to that of the second pixel. The fourth pixel may be placed in a fourth pixel area (EA4). For example, the fourth pixel area (EA4) may be located in area B of FIG. 2. The structure of the fourth pixel may have a structure substantially identical to that of the first pixel. That is, the fourth pixel may include a low power voltage wiring (ELVSS1), and the third pixel may not include a low power voltage wiring. The third pixel may receive the low power voltage (ELVSS) from the fourth pixel. Thus, the third pixel may additionally utilize the space that does not include the low power voltage wiring. For example, a connection pad (PAD) may be placed in the space. The above connection pad (PAD) can be electrically connected to the gate wiring (CL1).

[0097] Accordingly, even if the connection pad (PAD) is placed in the third pixel area (EA3), the distance between the third pixel and the pixel placed in the third direction (DR3) of the third pixel (e.g., the second pixel in FIG. 18) may not increase significantly. The distance between the first to fourth pixels placed in the first to fourth light-emitting areas (EA1, EA2, EA3, EA4) may be maintained substantially the same. Thus, the connection area (e.g., a seam line) may not be visible in the part where a plurality of sub-display panels are connected in the display device. That is, a difference in the distance between the first to fourth pixels may occur, thereby preventing the connection area from being visible from the outside.

[0098] FIG. 20 is an enlarged view showing an embodiment of regions A and B of FIG. 2.

[0099] Referring to FIGS. 2, FIGS. 3 and FIGS. 20, the display device may include a first connecting member (AM1). In embodiments, the first connecting member (AM1) may include a conductive material. For example, the first connecting member (AM1) may include an anisotropic conductive film. The first adhesive member (AM1) may include a plurality of conductive balls (SB). In this case, the conductive balls (SB) may overlap with the connecting pads (PAD) in the second direction (DR2). The gate signal (GS) may flow only through the conductive balls (SB) within the first connecting member (AM1). Thus, the conductive balls (SB) may be arranged to overlap the entire area A and the area B, and may overlap with the pads.

[0100] Area A and Area B can be bonded by the first connecting member (AM1). Area A and Area B can be electrically connected by the first connecting member (AM1). That is, the first connecting member (AM1) can electrically connect the first sub-display panel (SDP1) and the second sub-display panel (SDP2). For example, the gate signal (GS) flowing through the gate wiring (CL1) in Area A can be transmitted to Area B through the connecting pads (PAD) and the first connecting member (AM1). The gate signal (GS) can flow through the gate wiring (CL1) in Area B.

[0101] In the embodiments, at least one first pixel, at least one second pixel, and at least one connection pad (PAD) may be disposed in the A region. At least one third pixel, at least one fourth pixel, and at least one connection pad (PAD) may be disposed in the B region. As described above, the structure of the first pixel and the fourth pixel may be substantially identical, and the structure of the second pixel and the third pixel may be substantially identical.

[0102] FIG. 21 is an enlarged view showing an embodiment of regions A and B of FIG. 2. FIG. 21 may be substantially identical to FIG. 21 except for the type of connecting member. Accordingly, the description of redundant components is omitted.

[0103] Referring to FIGS. 2, 3 and 21, the display device may include a second connecting member (AM2). The second connecting member (AM2) may bond the first sub-display panel (SDP1) and the second sub-display panel (SDP2). In embodiments, the second connecting member (AM2) may include a conductive material. For example, the second connecting member (AM2) may include a conductive film. For example, the second connecting member (AM2) may include an adhesive silver paste. In addition, the second connecting member (AM2) may include a material that is adhesive to connect the A region and the B region, and conductive to transmit the gate signal (GS) between the A region and the B region. In this case, since the second connecting member (AM2) is conductive itself, it may be positioned to overlap only with the connecting pads (PAD). That is, the second connecting member (AM2) can overlap with the connecting pads (PAD) in the second direction (DR2). Through this, the A area and the B area can be electrically connected by the second connecting member (AM2). That is, the second connecting member (AM2) can electrically connect the first sub-display panel (SDP1) and the second sub-display panel (SDP2).

[0104] The second pixel and the third pixel included in FIGS. 20 and FIGS. 21 may not include low power voltage wiring. Accordingly, the width of the first direction (DR1) of the second pixel area (EA2) and the third pixel area (EA3) may be reduced. As a result, the difference in spacing between the pixel areas may be minimized even when the pads (PAD) and connecting members (AM1, AM2) are arranged. For example, the distance between the third direction (DR3) end of the first pixel area (EA1) and the third direction (DR3) end of the second pixel area (EA2) may be defined as D2, and the distance between the first direction (DR1) end of the fourth pixel area (EA4) and the first direction (DR1) end of the third pixel area (EA3) may be defined as D2. Additionally, the distance between the third direction (DR3) end of the second pixel area (EA2) and the third direction (DR3) end of the third pixel area (EA3) can be defined as D3, and the distance between the first direction (DR1) end of the second pixel area (EA2) and the first direction (DR1) end of the third pixel area (EA3) can be defined as D3. In the present invention, since low-power voltage wiring is not placed in the second pixel area (EA2) and the third pixel area (EA3), space for placing the pads (PAD) can be secured. Furthermore, even if the pads (PAD) are placed, the difference between D2 and D3 may not increase. Through this, viewers viewing the display device may perceive that the spacing between the first to fourth pixels is constant, and as a result, the seam-line caused by the connecting members (AM1, AM2) and pads (PAD) may not be visible to the viewers.

[0105] FIG. 22 is a cross-sectional view showing one embodiment cut along line II of FIG. 21.

[0106] Referring to FIGS. 2, 21 and 22, the display device may include a substrate (100), a first conductive layer (200), a second conductive layer (300), a via insulating layer (400), an inorganic insulating layer (500), and a partition (600).

[0107] The substrate (100) may include a rigid material or a flexible material. A first conductive layer (200) may be disposed on the substrate (100). The first conductive layer (200) may include the same material as the third metal layer of FIG. 10. The first conductive layer (200) may be formed simultaneously with the third metal layer.

[0108] The second conductive layer (300) may be disposed on the first conductive layer (200). The second conductive layer (300) may include the same material as the fourth metal layer of FIG. 12. The second conductive layer (300) may be formed simultaneously with the fourth metal layer. The second conductive layer (300) may be connected to the gate wiring (CL1) of FIG. 21. That is, the gate signal (GS) flowing through the gate wiring (CL1) may be applied to the gate wiring (CL1).

[0109] The first conductive layer (200) and the second conductive layer (300) can come into contact. The thickness of the first conductive layer (200) and the second conductive layer (300) is increased so that an electrical signal can flow effectively. Through this, the gate signal (GS) transmitted through the gate wiring (CL1) can flow effectively through the first conductive layer (200) and the second conductive layer (300).

[0110] The via insulating layer (400) may include an insulating material. For example, the via insulating layer (400) may include silicon oxide, silicon nitride, silicon oxynitride, polyamide, etc. The thickness of the via insulating layer (400) may be thicker than the thickness of the conductive layers (200, 300). Through this, the via insulating layer (400) can secure a contact area with the second connecting member (AM2). Through this, the adhesion between the first sub-display panel (SDP1) and the second sub-display panel (SDP2) and the second connecting member (AM2) can be improved. Although FIGS. 22 to 25 describe the second connecting member (AM2), the same can be applied to the first connecting member (AM1) of FIG. 20.

[0111] The above partition (600) may be disposed on a substrate. The above partition (600) may include an insulating material. The above partition (600) may include an organic insulating material and an inorganic insulating material. For example, the above partition (600) may have a structure in which an organic insulating material and an inorganic insulating material are laminated.

[0112] The inorganic insulating layer (500) may be disposed on the via insulating layer (400) and the partition (600). In the embodiments, the inorganic insulating layer (500) may include an inorganic insulating material. Thus, the inorganic insulating layer (500) can protect the display device from external substances and external shocks.

[0113] FIG. 23 is a cross-sectional view showing an embodiment cut along line II of FIG. 21. FIG. 23 may be substantially identical to FIG. 22 except that a third conductive layer (150) is added. Accordingly, the description of redundant components is omitted.

[0114] Referring to FIGS. 2, FIGS. 21 and FIGS. 23, the third conductive layer (150) may be disposed on the substrate (100). The third conductive layer (150) may include the same material as the first metal layer of FIG. 7. The third conductive layer (150) may be formed simultaneously with the first metal layer. The first conductive layer (200) may be disposed on the third conductive layer (150).

[0115] In the embodiments, the first conductive layer (200), the second conductive layer (300), and the third conductive layer (150) can be in contact with each other. Through this, the gate signal (GS) transmitted through the gate wiring (CL1) can effectively flow through the first conductive layer (200), the second conductive layer (300), and the third conductive layer (150).

[0116] FIG. 24 is a cross-sectional view showing one embodiment cut along the line II-II' of FIG. 21.

[0117] Referring to FIGS. 2, FIGS. 21 and FIGS. 24, the first conductive layer (200) may be disposed on the substrate (100). The first conductive layer (200) may overlap with the first pad region (PA1). The first insulating layer (110) may be disposed in the third direction (DR3) of the first conductive layer (200). The first insulating layer (110) may include an insulating material. For example, the first insulating layer (110) may include silicon oxide, silicon nitride, silicon oxynitride, etc.

[0118] The second conductive layer (300) may be disposed on the first conductive layer (200). The second conductive layer (300) may be connected to the gate wiring (CL1). The via insulating layer (400) and the inorganic insulating layer (500) may be disposed on the second conductive layer (300).

[0119] In the embodiments, as the first conductive layer (200) and the second conductive layer (300) come into contact, the gate signal (GS) flowing through the gate wiring (CL1) can be effectively transmitted in the pad regions (PA1, PA2).

[0120] The first pad region (PA1) and the second pad region (PA2) may be connected by the second connecting member (AM2). The thickness of the via insulating layer (400) may be thicker than the thickness of the conductive layers (200, 300). The contact area between the second connecting member (AM2) and the first sub-display panel (SDP1) and the second sub-display panel (SDP2) may be increased. Accordingly, the adhesion between the first sub-display panel (SDP1) and the second sub-display panel (SDP2) may be improved.

[0121] FIG. 25 is a cross-sectional view showing an embodiment cut along the line II-II' of FIG. 21. FIG. 25 may be substantially identical to FIG. 24 except for the third conductive layer (150) and the second insulating layer (120). Accordingly, the description of the overlapping components is omitted.

[0122] Referring to FIGS. 2, FIGS. 21 and FIGS. 25, the third conductive layer (150) may be disposed on the substrate (100). The first conductive layer (200) may be disposed on the third conductive layer (150). The second conductive layer (300) may be disposed on the first conductive layer (200).

[0123] The second insulating layer (120) may be disposed on the substrate (100). The gate wiring (CL1) may be disposed on the second insulating layer (120). The second insulating layer (120) may include an organic insulating material, an inorganic insulating material, etc. For example, the second insulating layer (120) may include an organic insulating material. The second insulating layer (120) may have a structure in which an organic insulating material and an inorganic insulating material are laminated.

[0124] In the embodiments, as the first conductive layer (200), the second conductive layer (300), and the third conductive layer (150) come into contact, the gate signal (GS) flowing through the gate wiring (CL1) can be effectively transmitted in the pad regions (PA1, PA2).

[0125] Although the foregoing description refers to exemplary embodiments of the present invention, those skilled in the art will understand that various modifications and changes can be made to the present invention without departing from the spirit and scope of the invention as set forth in the following claims. Industrial applicability

[0126] The present invention may be applied to a display panel and a display device including the same. For example, the display panel may be applied to a smartphone, tablet, laptop, or monitor.

[0127] Although the present invention has been described above with reference to exemplary embodiments, those skilled in the art will understand that various modifications and changes can be made to the invention without departing from the spirit and scope of the invention as set forth in the following claims. Explanation of the symbols

[0128] 100: Substrate 150: Third conductive layer 200: 1st Challenge Floor 300: 2nd Challenge Floor 400: Via insulation layer CL1: Gate wiring CL2: Low power voltage transfer wiring ELVSS1: Low power voltage wiring EVLDD1: High power supply wiring SL1: Sensing wiring CL3, CL4, CL5: Low power supply voltage connection wiring CL6, CL7, CL8: High power supply voltage connection wiring DL1, DL2, DL3: Data wiring

Claims

Claim 1 A display panel comprising: a first sub-display panel; a second sub-display panel adjacent to the first sub-display panel in a first direction; and a connecting member electrically connecting the first sub-display panel and the second sub-display panel, wherein the first sub-display panel comprises: a first pixel; a second pixel adjacent to the first pixel and the second sub-display panel; a first low-power voltage wiring that transmits a low-power voltage to the first pixel; and a first gate wiring electrically connected to the first pixel and the second pixel, wherein the second pixel receives the low-power voltage from the first low-power voltage wiring, and the second sub-display panel comprises: a third pixel adjacent to the first sub-display panel; and a second gate wiring electrically connected to the third pixel, wherein the third pixel is electrically connected to the first gate wiring, and the connecting member electrically connects the first gate wiring of the first sub-display panel and the second gate wiring of the second sub-display panel. Claim 2 A display panel according to claim 1, wherein the first sub-display panel further includes a low power voltage transmission wiring, and the low power voltage transmission wiring is electrically connected to the first low power voltage wiring by a contact hole. Claim 3 A display panel according to claim 2, characterized in that the low power supply voltage transmission wiring and the first low power supply voltage wiring are perpendicular to each other. Claim 4 A display panel according to claim 2, wherein the second pixel receives the low power voltage through the low power voltage transmission wiring. Claim 5 A display panel according to claim 2, wherein the first pixel further comprises a plurality of low power supply voltage connection wires, and the low power supply voltage connection wires are electrically connected to the low power supply voltage transmission wires by contact holes. Claim 6 A display panel according to claim 5, characterized in that the low power supply voltage connection wires are electrically connected to the cathode electrode of a light-emitting element. Claim 7 A display panel according to claim 1, wherein the second sub-display panel further comprises: a fourth pixel adjacent to the third pixel, spaced apart from the first sub-display panel by the third pixel, and electrically connected to the second gate wiring; and a second low-power voltage wiring that applies the low-power voltage to the fourth pixel. Claim 8 A display panel according to claim 7, wherein the second sub-display panel further includes a low power voltage transmission wiring, the low power voltage transmission wiring is electrically connected to the second low power voltage wiring by a contact hole, and the third pixel receives the low power voltage through the low power voltage transmission wiring. Claim 9 A display panel according to claim 8, characterized in that the low power supply voltage transmission wiring is perpendicular to the second low power supply voltage wiring. Claim 10 A display panel according to claim 8, wherein the second pixel further comprises a plurality of low power supply voltage connection wires, and the low power supply voltage connection wires are electrically connected to the low power supply voltage transmission wires by a contact hole. Claim 11 A display panel according to claim 10, characterized in that the low power supply voltage connection wires are electrically connected to the cathode electrode of a light-emitting element. Claim 12 A display panel according to claim 1, wherein the first sub-display panel further comprises a first connection pad disposed adjacent to the second pixel and the second sub-display panel, and the second sub-display panel further comprises a second connection pad disposed adjacent to the third pixel and the first sub-display panel. Claim 13 A display panel according to claim 12, wherein the first connecting pad and the second connecting pad are in contact with the connecting member. Claim 14 A display panel according to claim 13, wherein the first connection pad is electrically connected to the first gate wiring and the second connection pad is electrically connected to the second gate wiring. Claim 15 A display panel according to claim 14, wherein the first connection pad comprises a conductive layer electrically connected to the first gate wiring, and the thickness of the conductive layer is thicker than the thickness of the first gate wiring. Claim 16 A display panel according to claim 15, wherein the first connecting pad further comprises a via insulating layer, and the thickness of the via insulating layer is thicker than the thickness of the conductive layer. Claim 17 A display panel according to claim 14, wherein the second connection pad includes a conductive layer connected to the second gate wiring, and the thickness of the conductive layer is thicker than the thickness of the second gate wiring. Claim 18 A display panel according to claim 17, wherein the second connecting pad further comprises a via insulating layer, and the thickness of the via insulating layer is thicker than the thickness of the conductive layer. Claim 19 A display panel according to claim 1, wherein the connecting member comprises a conductive material. Claim 20 A display panel according to claim 1, wherein the connecting member comprises an anisotropic conductive film. Claim 21 A gate driver; and a display panel disposed on one side of the gate driver and electrically connected to the gate driver, wherein the display panel comprises: a first sub-display panel; a second sub-display panel adjacent to the first sub-display panel in a first direction; and a connecting member electrically connecting the first sub-display panel and the second sub-display panel, wherein the first sub-display panel comprises: a first pixel; a second pixel adjacent to the first pixel and the second sub-display panel; a first low-power voltage wiring that transmits a low-power voltage to the first pixel; and a first gate wiring that is electrically connected to the gate driver, the first pixel and the second pixel, wherein the second pixel receives the low-power voltage from the first low-power voltage wiring, and the second sub-display panel comprises: a third pixel adjacent to the first sub-display panel; A display device comprising a second gate wiring electrically connected to the third pixel, wherein the third pixel is electrically connected to the first gate wiring, and the connecting member electrically connects the first gate wiring of the first sub-display panel and the second gate wiring of the second sub-display panel. Claim 22 A display device according to claim 21, wherein the first sub-display panel further includes a low power supply voltage transmission wiring, and the low power supply voltage transmission wiring is electrically connected to the first low power supply voltage wiring by a contact hole. Claim 23 A display device according to claim 22, wherein the first pixel further comprises a plurality of low power supply voltage connection wires, and the low power supply voltage connection wires are electrically connected to the low power supply voltage transmission wires by a contact hole. Claim 24 A display device according to claim 23, characterized in that the low power supply voltage connection wires are electrically connected to the cathode electrode of a light-emitting element. Claim 25 A display device according to claim 21, wherein the second sub-display panel further comprises: a fourth pixel adjacent to the third pixel, spaced apart from the first sub-display panel by the third pixel, and electrically connected to the second gate wiring; and a second low-power voltage wiring that applies the low-power voltage to the fourth pixel. Claim 26 A display device according to claim 25, wherein the second sub-display panel further includes a low power supply voltage transmission wiring, the low power supply voltage transmission wiring is electrically connected to the second low power supply voltage wiring by a contact hole, and the third pixel receives the low power supply voltage through the low power supply voltage transmission wiring. Claim 27 A display device according to claim 26, wherein the second pixel further comprises a plurality of low power supply voltage connection wires, and the low power supply voltage connection wires are electrically connected to the low power supply voltage transmission wires by means of contact holes. Claim 28 A display device according to claim 27, characterized in that the low power supply voltage connection wires are electrically connected to the cathode electrode of a light-emitting element.

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