Optical-based distributed integrated memory system
The distributed integrated memory system using silicon photonics addresses data transfer limitations in larger computing systems by enabling unified memory access across multiple SoCs, enhancing resource utilization and scalability.
KR102999760B1Active Publication Date: 2026-08-05APPLE INC
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Patent Information
- Application Number
- KR1020267008659
- Authority / Receiving Office
- KR · KR
- Patent Type
- Patents
- Current Assignee / Owner
- Priority Date
- 2024-03-20
- Filing Date
- 2024-08-22
- Publication Date
- 2026-08-05
- Estimated Expiration
- 2044-08-22
AI Technical Summary
Technical Problem
Larger computing systems face limitations in data transfer between SoCs due to the integrated memory architecture being limited to elements within a single SoC, reducing the benefits of unified memory access.
Method used
A distributed integrated memory system using silicon photonics is implemented, allowing processors to share a unified memory architecture across multiple SoCs through optical interfaces and memory die packages, enabling scalable and efficient data transfer.
Benefits of technology
This solution enables greater resource utilization and easy scaling of computing systems by allowing processors to access distributed memory, achieving high bandwidth and low latency, thus creating the largest UMA machine designed to date.
✦ Generated by Eureka AI based on patent content.
Abstract
Techniques relating to computing systems using silicon photonics are disclosed. In some embodiments, the computing system comprises a plurality of compute die packages, each comprising processors configured to execute program instructions that operate on data stored in distributed memory accessible through an integrated memory architecture. The computing system further comprises a plurality of memory die packages configured to implement an integrated memory architecture, wherein a given memory die package among the memory die packages comprises one or more optical interfaces configured to receive memory requests from processors and one or more memory controllers configured to access a portion of the distributed memory in response to the received memory requests.
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