Device performane analysis apparatus and method

The device performance analysis apparatus and method provide a quick and intuitive solution for analyzing ASICs and APs by using status detectors and generators to insert and identify performance analysis codes, reducing analysis time and enabling efficient operation period understanding.

US20260169893A1Pending Publication Date: 2026-06-18SK HYNIX INC
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Patent Information

Authority / Receiving Office
US · United States
Patent Type
Applications(United States)
Current Assignee / Owner
SK HYNIX INC
Filing Date
2025-04-11
Publication Date
2026-06-18

AI Technical Summary

⚠Technical Problem

Existing performance analysis methods for ASICs and APs are time-consuming and difficult due to the need for reverse calculation from program counters, especially when compilation optimization is high, and repeated analysis is required to meet performance requirements.

⚗Method used

A device performance analysis apparatus and method that includes a status detector and a status output signal generator to quickly and intuitively analyze performance by inserting analysis codes with status identification numbers, allowing for intuitive location identification and reduced analysis time.

🎯Benefits of technology

Significantly reduces analysis time and enables intuitive understanding of chip operations by expressing operation periods as single status values, enabling developers to specify desired operation periods for various types of performance analysis.

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Abstract

A device performance analysis apparatus includes: a status detector configured to acquire a first status identification number stored by an analysis code embedded in a software configured to drive a device based on a preset parameter; and a status output signal generator configured to output a first status output value corresponding to the first status identification number acquired by the status detector to the outside.
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