Display panel and display apparatus

Abstract

A display panel and a display apparatus. The display panel comprises: a pixel circuit (100A), which comprises a drive transistor (T3), a threshold value compensation transistor (T2) and a data writing transistor (T4); a gate line (GT1), which is connected to a gate electrode of the threshold value compensation transistor (T2) and extends in a first direction (X); and a scanning line (GT2), which is connected to a gate electrode of the data writing transistor (T4) and extends in the first direction (X), wherein a first electrode of the threshold value compensation transistor (T2) is connected to a first electrode of the drive transistor (T3), a second electrode of the threshold value compensation transistor (T2) is connected to a gate electrode of the drive transistor (T3), the data writing transistor (T4) is connected to a second electrode of the drive transistor (T3), the material of an active layer of the threshold value compensation transistor (T2) comprises low-temperature polycrystalline silicon, the gate line (GT1) and the scanning line (GT2) are arranged in a second direction (Y), the gate line (GT1) is different from the scanning line (GT2), and an active layer (A4) of the data writing transistor (T4) is located, in the second direction (Y), on the side of an active layer (A3) of the drive transistor (T3) that is away from an active layer (A2) of the threshold value compensation transistor (T2).

Description

Display panel and display device

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This patent application claims priority to Chinese Patent Application No. 202310348033.4 filed on April 3, 2023, and the contents disclosed in the above-mentioned Chinese patent application are hereby cited in their entirety as part of the embodiments of the present disclosure. Technical Field

[0003] At least one embodiment of the present disclosure relates to a display panel and a display device. Background Art

[0004] With the continuous development of display technology, active-matrix organic light-emitting diode (AMOLED) display technology has been increasingly used in display devices such as mobile phones, tablets, and digital cameras due to its advantages such as self-luminescence, wide viewing angle, high contrast, low power consumption, and high response speed.

[0005] Summary of the Invention

[0006] At least one embodiment of the present disclosure relates to a display panel and a display device to avoid or reduce display defects such as afterimages and smears.

[0007] At least one embodiment of the present disclosure provides a display panel, comprising: a base substrate; a pixel circuit located on the base substrate and comprising a driving transistor, a threshold compensation transistor, and a data writing transistor, a gate line connected to the gate of the threshold compensation transistor and extending along a first direction; and a scan line connected to the gate of the data writing transistor and extending along the first direction; a first electrode of the threshold compensation transistor is connected to the first electrode of the driving transistor, a second electrode of the threshold compensation transistor is connected to the gate of the driving transistor, and the data writing transistor is connected to the second electrode of the driving transistor; a material of an active layer of the threshold compensation transistor comprises low-temperature polysilicon; the gate line and the scan line are arranged along the second direction, the second direction intersecting with the first direction; the gate line and the scan line are different; and the active layer of the data writing transistor is located on a side of the active layer of the driving transistor away from the active layer of the threshold compensation transistor in the second direction.

[0008] For example, the gate line and the scan line are respectively arranged on both sides of the active layer of the driving transistor.

[0009] For example, the display panel also includes a light-emitting element, the pixel circuit is configured to drive the light-emitting element, and the pixel circuit also includes a first reset transistor connected to the gate of the driving transistor; the light-emitting element includes a first electrode, a second electrode, and a light-emitting functional layer located between the first electrode and the second electrode, and the first electrode is closer to the base substrate than the second electrode.

[0010] For example, the orthographic projection of the first electrode of the light-emitting element on the substrate overlaps with the orthographic projection of the active layer of the first reset transistor on the substrate, and the orthographic projection of the first electrode of the light-emitting element on the substrate overlaps with the orthographic projection of the active layer of the threshold compensation transistor on the substrate.

[0011] For example, the orthographic projection of the first electrode of the light-emitting element on the base substrate covers the orthographic projection of at least one of the first active layer and the second active layer on the base substrate.

[0012] For example, the active layer of the first reset transistor includes a first channel and a second channel, the first channel and the second channel are connected through a first conductive portion, and the active layer of the threshold compensation transistor includes a third channel and a fourth channel, the third channel and the fourth channel are connected through a second conductive portion.

[0013] For example, the orthographic projection of the first electrode of the light-emitting element on the base substrate covers the orthographic projection of at least one of the first conductive portion and the second conductive portion on the base substrate.

[0014] For example, the orthographic projection of the first electrode of the light-emitting element on the base substrate overlaps with the orthographic projection of the first conductive portion on the base substrate, and the orthographic projection of the first electrode of the light-emitting element on the base substrate overlaps with the orthographic projection of the second conductive portion on the base substrate.

[0015] For example, the display panel also includes a light-emitting control signal line, and the pixel circuit also includes a first light-emitting control transistor. The orthographic projection of the light-emitting control signal line on the base substrate overlaps with the orthographic projection of the active layer of the first light-emitting control transistor on the base substrate. The first light-emitting control transistor and the data writing transistor are connected through a first conductive connecting member. The orthographic projection of the light-emitting control signal line on the base substrate overlaps with the orthographic projection of the first conductive connecting member on the base substrate.

[0016] For example, the first conductive connection member and the active layer of the first light emission control transistor are located in different layers.

[0017] For example, one end of the first conductive connection is connected to the data writing transistor through a first via hole, and the other end of the first conductive connection is connected to the first light emission control transistor through a second via hole.

[0018] For example, the first via hole is located between the light emitting control signal line and the scan line.

[0019] For example, an orthographic projection of the light emitting control signal line on the base substrate does not overlap with an orthographic projection of the data writing transistor on the base substrate.

[0020] For example, the display panel also includes a storage capacitor and a first power line, the first plate of the storage capacitor is connected to the gate of the driving transistor, the second plate of the storage capacitor is connected to the first power line, and the first power line is configured to provide a first power supply voltage to the pixel circuit.

[0021] For example, the orthographic projection of the first power line on the base substrate overlaps with the orthographic projection of the active layer of the first reset transistor on the base substrate, and overlaps with the orthographic projection of the active layer of the threshold compensation transistor on the base substrate.

[0022] For example, the first power line includes a first conductive line and a second conductive line, the first conductive line is closer to the base substrate than the second conductive line, and the first conductive line and the second conductive line are connected.

[0023] For example, the second conductive line includes a first protrusion protruding along the first direction, and an orthographic projection of the first protrusion on the base substrate overlaps with an orthographic projection of at least one of the first channel and the second channel of the active layer of the first reset transistor on the base substrate.

[0024] For example, a plurality of first conductive lines are arranged along a first direction, and at least one first conductive line includes a plurality of sub-lines intermittently arranged along a second direction, where the second direction intersects the first direction.

[0025] For example, the display panel also includes a first initialization line and a second initialization line, wherein the pixel circuit also includes a second reset transistor, the second reset transistor is connected to the first electrode of the light-emitting element, the first initialization line is connected to the first reset transistor, the second initialization line is connected to the second reset transistor, the first initialization line includes a first initialization signal line extending along the first direction and a first initialization connection line extending along the second direction, the second initialization line includes a second initialization signal line extending along the first direction and a second initialization connection line extending along the second direction, and the first initialization connection line, the first wire, and the second initialization connection line are arranged adjacent to each other in sequence along the first direction.

[0026] For example, the first initialization connection line includes a second conductive connection member, the first initialization signal line and the first reset transistor are connected via the second conductive connection member, and the second conductive connection member is located between two adjacent sub-lines.

[0027] For example, the second wire has a main body and a branch, the branch extends from the main body, and the orthographic projection of the first electrode of the light-emitting element on the base substrate overlaps with the orthographic projection of the main body on the base substrate, and overlaps with the orthographic projection of the branch on the base substrate.

[0028] For example, the display panel further includes a leveling element, the orthographic projection of the first electrode of the light-emitting element on the base substrate overlaps with the orthographic projection of the leveling element on the base substrate, and the leveling element and the branch portion are respectively arranged on both sides of the main portion.

[0029] For example, the leveling element and the main body are located in the same layer and are spaced apart from each other. The leveling element extends along the second direction. The leveling element is connected to the first electrode of the light-emitting element through a third via hole.

[0030] For example, the width of the main body portion is greater than the width of the branch portion, and greater than the width of the leveling element in the first direction.

[0031] For example, the first initialization signal line has a block, and the orthographic projection of the conductive portion connected to two spaced-apart channels in the active layer of the threshold compensation transistor on the base substrate overlaps with the orthographic projection of the block on the base substrate.

[0032] For example, the first electrode of the light emitting element has a second protrusion, and the orthographic projection of the second protrusion on the base substrate overlaps with the orthographic projection of at least one of the active layer of the first reset transistor and the active layer of the threshold compensation transistor on the base substrate.

[0033] For example, the display panel also includes a block, the first wire and the block are connected through a fourth via, and the conductive part in the active layer of the threshold compensation transistor connected to the two spaced channels has an orthographic projection on the base substrate that overlaps with the orthographic projection of the block on the base substrate.

[0034] At least one embodiment of the present disclosure further provides a display device, comprising any of the above-mentioned display panels. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly introduced below. Obviously, the drawings in the following description only relate to some embodiments of the present disclosure, rather than limiting the present disclosure.

[0036] FIG1 is a schematic diagram of a display panel illuminated by strong light.

[0037] FIG2 is a brightness waveform curve of a display panel before and after illumination.

[0038] FIG3 is a schematic diagram of a pixel circuit and a light-emitting element in a sub-pixel of a display panel.

[0039] 4 to 10 are plan views of a single-layer structure in a display panel provided by some embodiments of the present disclosure.

[0040] 11 to 20 are plan views of a stacked structure in a display panel provided by some embodiments of the present disclosure.

[0041] FIG21A is a cross-sectional view taken along line B1 - B2 of FIG16 .

[0042] FIG21B is a cross-sectional view taken along line B3 - B4 of FIG16 .

[0043] 22 to 24 are plan views of a single-layer structure in a display panel provided by some embodiments of the present disclosure.

[0044] 25A to 30 are plan views of a stacked structure in a display panel provided by some embodiments of the present disclosure.

[0045] 31 to 34 are plan views of a stacked structure in a display panel provided by some embodiments of the present disclosure.

[0046] FIG35 is a plan view of a conductive pattern layer LY4 in a display panel provided by an embodiment of the present disclosure.

[0047] FIG36 is a stacked diagram of an active pattern layer M0 , a conductive pattern layer LY1 , ​​and a conductive pattern layer LY2 in a display panel provided by an embodiment of the present disclosure. DETAILED DESCRIPTION

[0048] To make the purpose, technical solutions, and advantages of the embodiments of the present disclosure more clear, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the accompanying drawings of the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, not all of the embodiments. Based on the described embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure.

[0049] Unless otherwise defined, the technical or scientific terms used in this disclosure should have the usual meanings understood by people with ordinary skills in the field to which this disclosure belongs. The words "first", "second" and similar words used in this disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. Similarly, words such as "one", "an" or "the" do not indicate a quantity limitation, but rather indicate the existence of at least one. Words such as "include" or "comprise" mean that the elements or objects preceding the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Words such as "connect" or "connected" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the object being described changes, the relative positional relationship may also change accordingly.

[0050] In a typical AMOLED display panel, the data writing transistor and the threshold compensation transistor share the same control line, and the driving transistor is prone to hysteresis, resulting in display defects such as afterimages and smearing.

[0051] In a display panel provided by some embodiments of the present disclosure, a data writing transistor and a threshold compensation transistor use different control lines.

[0052] AMOLED display panels consist of multiple pixels, each of which consists of multiple sub-pixels. Each sub-pixel includes a pixel circuit and a light-emitting element. The pixel circuit provides a driving current to drive the light-emitting element. Some AMOLED display panels, such as those found in mobile phones, have been found to exhibit issues such as reddening and flickering when exposed to strong light.

[0053] Figure 1 is a schematic diagram of a display panel illuminated by strong light. Figure 2 is a luminance waveform curve of a display panel before and after illumination. Figure 3 is a schematic diagram of a pixel circuit and light-emitting element in a sub-pixel of a display panel.

[0054] As shown in FIG. 1 , the display panel 900 has a display side S1 and an opposite side S2 , where the opposite side S2 is opposite to the display side S1 .

[0055] As shown in Figure 1, a strong light source 902 illuminates the display panel 900 on its display side S1. The angle between the light from the strong light source 902 and the normal line L0 of the display panel 900 is angle θ. The camera component 901 is perpendicular to the display panel 900 and captures the entire display panel 900. Some display panels are prone to problems such as reddening and flickering under strong light.

[0056] As shown in Figure 1, the angle θ can be 45°. In the embodiment of the present disclosure, when strong light illuminates the display panel, in the case of oblique light, the angle θ is 45°. If the angle θ is 90°, that is, the angle between the light of the strong light source 902 and the normal of the display panel 900 is 90°, the strong light source 902 illuminates the display panel 900 on the display side S1, which is a case of top light illumination. If the angle θ is 90°, the strong light source 902 illuminates the display panel 900 on the opposite side S2, which is a case of bottom light illumination. For example, when top light illumination or bottom light illumination is performed, the light intensity can be 10,000 nits. For example, in the case of oblique light, the strong light source 902 can use a flashlight, but is not limited to this.

[0057] As shown in FIG3 , the display panel includes a plurality of sub-pixels 100. FIG3 shows one sub-pixel 100. As shown in FIG3 , each sub-pixel 100 includes a pixel circuit 100a and a light-emitting element 100b. Pixel circuit 100a drives light-emitting element 100b. Pixel circuit 100a drives light-emitting element 100b to emit light. Pixel circuit 100a provides a driving current to drive light-emitting element 100b to emit light. The pixel circuit shown in FIG3 may be a pixel circuit of a low-temperature polysilicon (LTPS) AMOLED commonly used in related art.

[0058] As shown in Figure 3, the pixel circuit 100a includes six switching transistors (T1-T2, T4-T7), a driving transistor T3, and a storage capacitor Cst. The six switching transistors are respectively a data writing transistor T4, a threshold compensation transistor T2, a light emitting control transistor T5, a light emitting control transistor T6, a reset transistor T1, and a reset transistor T7. The light emitting element 100b includes a first electrode E1 and a second electrode E2 and a light emitting functional layer located between the first electrode E1 and the second electrode E2. For example, the first electrode E1 is an anode and the second electrode E2 is a cathode. Figure 3 shows nodes N1, N2, N3, and N4.

[0059] The pixel circuit includes a driving transistor, and the threshold voltage Vth and the leakage current Ioff of the driving transistor are important parameters related to the display effect.

[0060] Table 1 shows the illumination characteristics of a light-emitting element in a display panel. As can be seen from Table 1, the threshold voltage Vth of the driving transistor does not change much before and after illumination, but the leakage current Ioff deteriorates significantly.

[0061] Table 1. Changes in illumination characteristics of light-emitting elements in display panels

[0062] In some embodiments, a pixel may include a red sub-pixel, a green sub-pixel, and a blue sub-pixel. Table 2 shows the color coordinate values ​​of the display panel before and after illumination. Analysis shows that the color coordinate y value changes significantly after illumination. The decrease in y value indicates that the green sub-pixel's luminescence is weakened.

[0063] Table 2. Color coordinate values ​​of the display panel before and after illumination

[0064] As shown in Figure 2, before illumination, the current of the display panel dropped to 556.04 / 590.78 = 94.12%, and after illumination, the current of the display panel dropped to 455.33 / 590.78 = 77.07%. Illumination increases the leakage current Ioff and reduces the brightness.

[0065] From the above analysis, we can see that after exposure to light, the leakage current Ioff of the pixel circuit changes. The green sub-pixel is more sensitive. The increase in leakage current Ioff increases the leakage of the reset transistor and threshold compensation transistor connected to the gate of the drive transistor. This causes the gate voltage of the green sub-pixel's drive transistor to be too high, resulting in a decrease in the luminance of the green sub-pixel, and ultimately causing the screen to turn pink or red. At the same time, due to the increase in leakage current Ioff, the gate voltage of the drive transistor is unstable, resulting in aggravated flicker under low-frequency display.

[0066] As for the dusting, it is because the green sub-pixel is more sensitive. The above process also occurs in the red and blue sub-pixels, but with the same change in current, the red and blue sub-pixels are not as sensitive because the light-emitting functional layer of the light-emitting element (the light-emitting material that emits green light) is not so sensitive, and there will not be much difference in light emission. However, the green sub-pixel is more sensitive and the brightness decays severely, which will cause dusting.

[0067] Some embodiments of the present disclosure provide a display panel that uses the first electrode of a light-emitting element to shield the channel of a reset transistor and a channel of a threshold compensation transistor connected to the gate of a driving transistor, thereby preventing strong light from irradiating the channel and affecting the characteristics of the transistor, thereby causing problems such as powdering and flickering.

[0068] As shown in FIG3 , the display panel includes gate lines GT1, scan lines GT2, data lines DT, first power lines PL1, second power lines PL2, emission control signal lines EML, initialization lines INT, and reset control signal lines RST. For example, the reset control signal lines RST include reset control signal lines RST1 and RST2. The first power line PL1 is configured to provide a constant first voltage signal VDD to the sub-pixel 100, and the second power line PL2 is configured to provide a constant second voltage signal VSS to the sub-pixel 100, where the first voltage signal VDD is greater than the second voltage signal VSS. The gate line GT1 is configured to provide a scan signal SCAN1 to the sub-pixel 100, the scan line GT2 is configured to provide a scan signal SCAN2 to the sub-pixel 100, the data line DT is configured to provide a data signal (data voltage) DATA to the sub-pixel 100, the emission control signal line EML is configured to provide a emission control signal EM to the sub-pixel 100, the reset control signal line RST1 is configured to provide a reset control signal RESET1 to the sub-pixel 100, and the reset control signal line RST2 is configured to provide a reset control signal RESET2 (scan signal SCAN2) to the sub-pixel 100. The initialization line INT1 is configured to provide a first initialization signal Vinit1 to the sub-pixel 100. The initialization line INT2 is configured to provide a second initialization signal Vinit2 to the sub-pixel 100. For example, the first initialization signal Vinit1 and the second initialization signal Vinit2 are constant voltage signals whose magnitudes can be, for example, between the first voltage signal VDD and the second voltage signal VSS, but are not limited thereto. For example, the first initialization signal Vinit1 and the second initialization signal Vinit2 can both be less than or equal to the second voltage signal VSS. For example, the initialization line INT1 and the initialization line INT2 are insulated from each other to provide different initialization signals.

[0069] As shown in FIG3 , the driving transistor T3 is electrically connected to the light emitting element 100 b and outputs a driving current to drive the light emitting element 100 b to emit light under the control of the scan signal SCAN1 , the scan signal SCAN2 , the data signal DATA, the first voltage signal VDD, the second voltage signal VSS and other signals.

[0070] For example, the light emitting element 100 b includes an organic light emitting diode (OLED), and the light emitting element 100 b emits red light, green light, blue light, or white light when driven by its corresponding pixel circuit 100 a.

[0071] For example, as shown in FIG3 , the gate T4g of the data writing transistor T4 is connected to the scan line GT2 , the first electrode T4a of the data writing transistor T4 is connected to the data line DT, and the second electrode T4b of the data writing transistor T4 is connected to the second electrode T3b of the driving transistor T3 .

[0072] For example, as shown in Figure 3, the pixel circuit 100a also includes a threshold compensation transistor T2, the gate T2g of the threshold compensation transistor T2 is connected to the gate line GT1, the first electrode T2a of the threshold compensation transistor T2 is connected to the first electrode T3a of the driving transistor T3, and the second electrode T2b of the threshold compensation transistor T2 is connected to the gate T3g of the driving transistor T3.

[0073] For example, as shown in Figure 3, the display panel also includes a light-emitting control signal line EML, and the pixel circuit 100a also includes a light-emitting control transistor T5 and a light-emitting control transistor T6. The gate T5g of the light-emitting control transistor T5 is connected to the light-emitting control signal line EML, the first electrode T5a of the light-emitting control transistor T5 is connected to the first power line PL1, and the second electrode T5b of the light-emitting control transistor T5 is connected to the second electrode T3b of the driving transistor T3; the gate T6g of the light-emitting control transistor T6 is connected to the light-emitting control signal line EML, the first electrode T6a of the light-emitting control transistor T6 is connected to the first electrode T3a of the driving transistor T3, and the second electrode T6b of the light-emitting control transistor T6 is connected to the first electrode E1 of the light-emitting element 100b.

[0074] As shown in FIG3 , the reset transistor T1 is connected to the gate T3g of the driving transistor T3 and is configured to reset the gate T3g of the driving transistor T3. The reset transistor T7 is connected to the first electrode E1 of the light-emitting element 100 b and is configured to reset the first electrode E1 of the light-emitting element 100 b. The initialization line INT1 is connected to the gate T3g of the driving transistor T3 via the reset transistor T1. The initialization line INT2 is connected to the first electrode E1 of the light-emitting element 100 b via the reset transistor T7.

[0075] For example, as shown in FIG3 , the first electrode T1 a of the reset transistor T1 is connected to the initialization line INT1 , the second electrode T1 b of the reset transistor T1 is connected to the gate T3 g of the drive transistor T3 , and the gate T1 g of the reset transistor T1 is connected to the reset control signal line RST1 .

[0076] For example, as shown in FIG3 , the first electrode T7a of the reset transistor T7 is connected to the initialization line INT2 , the second electrode T7b of the reset transistor T7 is connected to the first electrode E1 of the light emitting element 100b , and the gate T7g of the reset transistor T7 is connected to the reset control signal line RST2 .

[0077] As shown in Figure 3, the first power line PL1 is configured to provide a first voltage signal VDD to the pixel circuit 100a; the pixel circuit also includes a storage capacitor Cst, a first plate Ca of the storage capacitor Cst is connected to the gate T3g of the driving transistor T3, and a second plate Cb of the storage capacitor Cst is connected to the first power line PL1 and the first electrode T5a of the light-emitting control transistor T5, respectively.

[0078] For example, as shown in FIG3 , the display panel further includes a second power line PL2 , and the second power line PL2 is connected to the second electrode E2 of the light emitting element 100 b .

[0079] As shown in FIG3 , the gate line GT1 is connected to the gate T2g of the threshold compensation transistor T2. The scan line GT2 is connected to the gate T4g of the data writing transistor T4. For example, in one sub-pixel, the gate line GT1 is configured to provide the n-th row scan signal SCAN1(n), and the scan line GT2 is configured to provide the n-th row scan signal SCAN2(n).

[0080] In some embodiments of the present disclosure, as shown in FIG3 , the first plate Ca of the storage capacitor Cst is connected to the gate electrode T3g of the driving transistor T3, and the first plate Ca of the storage capacitor Cst is connected to the reset transistor T1 and the threshold compensation transistor T2, respectively. For example, as shown in FIG3 , the first plate Ca of the storage capacitor Cst is connected to the second electrode T1b of the reset transistor T1 and the second electrode T2b of the threshold compensation transistor T2, respectively.

[0081] Figures 4 to 10 are plan views of a single-layer structure in a display panel provided by some embodiments of the present disclosure. Figures 11 to 20 are plan views of a laminated structure in a display panel provided by some embodiments of the present disclosure. Figure 21A is a cross-sectional view along line B1-B2 of Figure 16. Figure 21B is a cross-sectional view along line B3-B4 of Figure 16. Figures 22 to 24 are plan views of a single-layer structure in a display panel provided by some embodiments of the present disclosure. Figures 25A to 30 are plan views of a laminated structure in a display panel provided by some embodiments of the present disclosure. Figures 31 to 34 are plan views of a laminated structure in a display panel provided by some embodiments of the present disclosure.

[0082] In the embodiments of the present disclosure, the upper right corner of a plan view represents a single layer included in the view.

[0083] 4 is a plan view of an active pattern layer M0 in a display panel according to an embodiment of the present disclosure. The embodiment of the present disclosure is described by taking the active pattern layer M0 comprising polysilicon as an example.

[0084] Figure 5 is a plan view of a conductive pattern layer LY1 in a display panel according to an embodiment of the present disclosure. As shown in Figure 5 , the conductive pattern layer LY1 includes a gate line GT1, an emission control signal line EML, a reset control signal line RST2 / a scan line GT2, and a reset control signal line RST1.

[0085] 5 , the reset control signal line RST2 and the scan line GT2 are integrated into one structure. That is, the reset control signal line RST2 and the scan line GT2 are the same signal line.

[0086] As shown in FIG. 5 , the gate line GT1 extends in the direction X, the emission control signal line EML extends in the direction X, the reset control signal line RST2 / the scan line GT2 extends in the direction X, and the reset control signal line RST1 extends in the direction X.

[0087] As shown in FIG. 5 , the gate line GT1 , the emission control signal line EML, the reset control signal line RST2 / the scan line GT2 , and the reset control signal line RST1 are sequentially arranged along the direction Y.

[0088] 5 shows the gate T3g of the driving transistor T3, which also serves as the first plate Ca of the storage capacitor Cst. That is, the gate T3g of the driving transistor T3 and the first plate Ca of the storage capacitor Cst are an integrated structure.

[0089] Figure 6 is a plan view of a conductive pattern layer LY2 in a display panel according to an embodiment of the present disclosure. As shown in Figure 6 , the conductive pattern layer LY2 includes a block BK, a first initialization signal line INT11, a second initialization signal line INT21, and a second plate Cb of a storage capacitor Cst.

[0090] As shown in FIG. 6 , the first initialization signal line INT11 extends along the X direction, and the second initialization signal line INT21 extends along the X direction.

[0091] As shown in FIG6 , the first initialization signal line INT11 includes a main signal line INTm and a protrusion PRa extending from the main signal line INTm. The block BK is located within the space enclosed by the main signal line INTm, two adjacent protrusions PRa, and the second plate Cb of the storage capacitor Cst. As shown in FIG6 , the main signal line INTm extends in a direction X, and the protrusion PRa intersects the main signal line INTm. For example, the protrusion PRa is perpendicular to the main signal line INTm.

[0092] As shown in FIG6 , the second electrode plate Cb has an opening K0 to facilitate the connection of the conductive connecting member C1 (as shown in FIG7 ) to the first electrode plate Ca (the gate T3 g of the driving transistor T3 ).

[0093] As shown in FIG6 , two adjacent second electrode plates Cb are an integrated structure.

[0094] Figure 7 is a plan view of a conductive pattern layer LY3 in a display panel according to an embodiment of the present disclosure. As shown in Figure 7 , the conductive pattern layer LY3 includes a first conductive line PL11 , a first initialization connection line INT12 , a second initialization connection line INT22 , and conductive connectors C1 to C6 .

[0095] As shown in FIG. 7 , the first conductive line PL11 extends along the Y direction, the first initialization connection line INT12 extends along the Y direction, and the second initialization connection line INT22 extends along the Y direction.

[0096] Fig. 8 is a plan view of a conductive pattern layer LY4 in a display panel according to an embodiment of the present disclosure. As shown in Fig. 8 , the conductive pattern layer LY4 includes a data line DT, a second conductive line PL12, a connection electrode CEm, and a connection electrode CEn.

[0097] Figure 9 is a plan view of an electrode pattern layer LY5 in a display panel according to an embodiment of the present disclosure. As shown in Figure 9 , the electrode pattern layer LY5 includes a plurality of first electrodes E1 , a first electrode E11 , a first electrode E12 , a first electrode E13 , and a first electrode E14 .

[0098] FIG10 is a plan view of a pixel defining layer (PDL) in a display panel according to an embodiment of the present disclosure. As shown in FIG10 , the pixel defining layer (PDL) includes an opening (OPN). As shown in FIG10 , the pixel defining layer (PDL) is shown with the opening (OPN) therein.

[0099] Figure 11 is a stackup diagram of an active pattern layer M0, a conductive pattern layer LY1, and a conductive pattern layer LY2 in a display panel provided in accordance with an embodiment of the present disclosure. Figure 12 is a stackup diagram of an active pattern layer M0, a conductive pattern layer LY1, a conductive pattern layer LY2, a via structure VH1, and a conductive pattern layer LY3 in a display panel provided in accordance with an embodiment of the present disclosure. Figure 13 is a stackup diagram of an active pattern layer M0, a conductive pattern layer LY1, a conductive pattern layer LY2, a via structure VH1, a conductive pattern layer LY3, a via structure VH2, a conductive pattern layer LY4, and a via structure VH3 in a display panel provided in accordance with an embodiment of the present disclosure. Figure 14 is a stackup diagram of an active pattern layer M0, a conductive pattern layer LY1, and a conductive pattern layer LY4 in a display panel provided in accordance with an embodiment of the present disclosure. Figure 15 is a stackup diagram of an active pattern layer M0, a conductive pattern layer LY1, and an electrode pattern layer LY5 in a display panel provided in accordance with an embodiment of the present disclosure. Figure 16 is a stackup diagram of an active pattern layer M0, a conductive pattern layer LY1, a conductive pattern layer LY2, a via structure VH1, a conductive pattern layer LY3, a via structure VH2, a conductive pattern layer LY4, a via structure VH3, an electrode pattern layer LY5, and a pixel defining layer PDL in a display panel provided in accordance with an embodiment of the present disclosure. Figure 17 is a stackup diagram of a via structure VH1 and a conductive pattern layer LY3 in a display panel provided in accordance with an embodiment of the present disclosure. Figure 18A is a stackup diagram of a conductive pattern layer LY4 and a via structure VH3 in a display panel provided in accordance with an embodiment of the present disclosure. Figure 18B is a stackup diagram of a conductive pattern layer LY4 and an electrode pattern layer LY5 in a display panel provided in accordance with an embodiment of the present disclosure. Figure 19 is a stackup diagram of an electrode pattern layer LY5 and a pixel defining layer PDL in a display panel provided in accordance with an embodiment of the present disclosure. Figure 20 is a stackup diagram of a via structure VH1 and a conductive pattern layer LY3 in a display panel provided in accordance with an embodiment of the present disclosure. Fig. 21A is a cross-sectional view taken along line B1-B2 of Fig. 16. Fig. 21B is a cross-sectional view taken along line B3-B4 of Fig. 16. For clarity, Fig. 16 omits the light emitting functional layer and the second electrode E2.

[0100] As shown in Figure 21A, in the display panel, a buffer layer BL is provided on the base substrate BS, a blocking layer BA is provided on the buffer layer BL, an active pattern layer M0 is provided on the blocking layer BA, an insulating layer 601 is provided on the active pattern layer M0, a conductive pattern layer LY1 is provided on the insulating layer 601, an insulating layer 602 is provided on the conductive pattern layer LY1, a conductive pattern layer LY2 is provided on the insulating layer 602, an insulating layer 603 is provided on the conductive pattern layer LY2, a conductive pattern layer LY3 is provided on the insulating layer 603, an insulating layer 604 is provided on the conductive pattern layer LY3, a conductive pattern layer LY4 is provided on the insulating layer 604, an insulating layer 605 is provided on the conductive pattern layer LY4, an electrode pattern layer LY5 is provided on the insulating layer 605, a pixel defining layer PDL is provided on the electrode pattern layer LY5, a light-emitting functional layer FL is provided in the opening OPN of the pixel defining layer PDL, and a second electrode E2 is provided on the light-emitting functional layer FL.

[0101] It should be noted that, in the embodiments of the present disclosure, the light-emitting functional layer FL of the light-emitting element may include the electroluminescent layer itself and a common layer located on both sides of the electroluminescent layer. For example, the common layer may include at least one of a hole injection layer, a hole transport layer, an electron injection layer and an electron transport layer.

[0102] As shown in Figure 21A , via structure VH1 refers to a via that connects components in conductive pattern layer LY3 to components in the underlying film layer. The film layer underlying conductive pattern layer LY3 includes active pattern layer M0, conductive pattern layer LY1, and conductive pattern layer LY2. As shown in Figure 21A , via structure VH1 refers to a via that penetrates at least one of insulating layer 603, insulating layer 602, and insulating layer 601.

[0103] For example, in an embodiment of the present disclosure, as shown in FIG. 17 , the via structure VH1 includes vias V1 to V17 .

[0104] As shown in FIG21A , the via structure VH2 refers to a via hole that connects a component in the conductive pattern layer LY4 to a component in the conductive pattern layer LY3 . As shown in FIG21A , the via structure VH2 refers to a via hole that penetrates the insulating layer 604 .

[0105] For example, in an embodiment of the present disclosure, the via structure VH2 includes a via Va, a via Vb, a via Vc, and a via Vd.

[0106] As shown in FIG21A , the via structure VH3 refers to a via hole that connects a component in the electrode pattern layer LY5 with a component in the conductive pattern layer LY3 . As shown in FIG21A , the via structure VH3 refers to a via hole that penetrates the insulating layer 605 .

[0107] As shown in FIG. 21A , the insulating layer 605 may include a passivation layer PVX and a planarization layer PLN, but is not limited thereto.

[0108] For example, in an embodiment of the present disclosure, as shown in FIG. 25A and FIG. 25B , the via structure VH3 includes a via Vn and a via Vm.

[0109] FIG21B shows vias V8, V16, and V17. As shown in FIG21B , the first conductive line PL11 is connected to the block BK via via V8. As shown in FIG21B , the first initialization connection line INT12 is connected to the first initialization signal line INT11 via via V16, and the first initialization connection line INT12 is connected to the first electrode T1a of the reset transistor T1 via via V17.

[0110] FIG 21B also shows a second conductive line PL12, a gate line GT1, and a reset control signal line RST1.

[0111] 21B also shows conductive portion P1 and conductive portion P2. The orthographic projection of block BK on base substrate BS overlaps with the orthographic projection of conductive portion P2 on base substrate BS, and the orthographic projection of second initialization signal line INT21 on base substrate BS overlaps with the orthographic projection of conductive portion P1 on base substrate BS.

[0112] As shown in Figures 9 and 15 , subpixel 101 includes a first electrode E11, subpixel 102 includes a first electrode E12, subpixel 103 includes a first electrode E13, and subpixel 104 includes a first electrode E14. The embodiments of the present disclosure are described using subpixel 101 as a blue subpixel, subpixel 102 as a red subpixel, subpixel 103 as a green subpixel, and subpixel 104 as a green subpixel. Of course, the subpixels can also emit light of other colors, and the subpixel's light emission can be customized as needed.

[0113] Figure 22 is a plan view of a conductive pattern layer LY4 in a display panel according to an embodiment of the present disclosure. Figure 23 is a plan view of a pixel defining layer PDL in a display panel according to an embodiment of the present disclosure. Figure 24 is a plan view of an electrode pattern layer LY5 in a display panel according to an embodiment of the present disclosure. Figure 25A is a stackup diagram of the conductive pattern layer LY4 and the via structure VH3 in a display panel according to an embodiment of the present disclosure. Figure 25B is a stackup diagram of the conductive pattern layer LY4, the via structure VH3, and the electrode pattern layer LY5 in a display panel according to an embodiment of the present disclosure. Figure 26 is a stackup diagram of the electrode pattern layer LY5 and the pixel defining layer PDL in a display panel according to an embodiment of the present disclosure. Figure 27 is a stackup diagram of the active pattern layer M0, the conductive pattern layer LY1, the conductive pattern layer LY4, and the via structure VH3 in a display panel according to an embodiment of the present disclosure. Figure 28 is a stackup diagram of the active pattern layer M0, the conductive pattern layer LY1, and the electrode pattern layer LY5 in a display panel according to an embodiment of the present disclosure. Figure 29 is a stackup diagram of an active pattern layer M0, a conductive pattern layer LY1, a conductive pattern layer LY2, a via structure VH1, a conductive pattern layer LY4, and a via structure VH3 in a display panel provided in accordance with an embodiment of the present disclosure. Figure 30 is a stackup diagram of an active pattern layer M0, a conductive pattern layer LY1, a conductive pattern layer LY2, a via structure VH1, a conductive pattern layer LY4, an electrode pattern layer LY5, and a pixel defining layer PDL in a display panel provided in accordance with an embodiment of the present disclosure.

[0114] 3 to 30 , embodiments of the present disclosure provide a display panel including a base substrate BS, a pixel circuit 100 a , and a light emitting element 100 b .

[0115] As shown in Figures 3 to 30, the pixel circuit 100a is located on a base substrate BS and includes a driving transistor T3, a threshold compensation transistor T2, and a data writing transistor. The threshold compensation transistor T2 is configured to perform threshold compensation on the driving transistor T3.

[0116] As shown in Figures 3 to 30, the display panel further includes a gate line GT1 and a scan line GT2. The gate line GT1 is connected to the gate T2g of the threshold compensation transistor T2 and extends along the direction X. The scan line GT2 is connected to the gate T4g of the data write transistor T4 and extends along the direction X. The first electrode T2a of the threshold compensation transistor T2 is connected to the first electrode T3a of the drive transistor T3, the second electrode T2b of the threshold compensation transistor T2 is connected to the gate T3g of the drive transistor T3, and the data write transistor T4 is connected to the second electrode T3b of the drive transistor T1. The gate line GT1 and the scan line GT2 are arranged along the direction Y, and the direction X intersects with the direction Y. The gate line GT1 and the scan line GT2 are different. The active layer A4 of the data write transistor T4 is located on the side of the active layer A3 of the drive transistor T3 away from the active layer A2 of the threshold compensation transistor T2 in the direction Y.

[0117] For example, the material of the active layer A2 of the threshold compensation transistor T2 includes low temperature polysilicon (LTPS).

[0118] In the display panel provided by the embodiment of the present disclosure, the gate line GT1 and the scan line GT2 are different, so that the data writing transistor T4 and the threshold compensation transistor T2 are independently controlled. The gate line GT1 and the scan line GT2 can be input with signals separately, which can lengthen the low-level time of the threshold compensation transistor T2 and the on-time of the threshold compensation transistor T2, thereby lengthening the threshold compensation time of the driving transistor T3 and improving the threshold compensation effect.

[0119] For example, the data writing transistor T4 and the threshold compensation transistor T2 may not be turned on at the same time, and may not be turned off at the same time. For example, when the data writing transistor T4 is turned on, the threshold compensation transistor T2 is turned off.

[0120] The display panel provided by the embodiment of the present disclosure can turn off the threshold compensation transistor T2 when the data writing transistor T4 is turned on, and perform hysteresis adjustment on the driving transistor T3, which is beneficial to improving the display quality of low-frequency display.

[0121] For example, in some embodiments, after the data signal is written into the second electrode T3b of the driving transistor T3 through the data writing transistor T4, the gate of the driving transistor T3 can be reset through the reset transistor T1, thereby extending the reset time of the gate of the driving transistor T3.

[0122] In the display panel provided by the embodiments of the present disclosure, the gate line GT1 and the scan line GT2 are different, and the data write transistor T4 and the threshold compensation transistor T2 can be independently controlled. This can avoid or eliminate display defects such as afterimages and smearing, thereby improving display quality. For example, the data write transistor T4 and the threshold compensation transistor T2 can be independently controlled to allow the gate T3g of the drive transistor T3 to have a longer reset time, reset the source and drain of the drive transistor T3, allow the drive transistor T3 to have a longer threshold compensation time, and allow the drive transistor T3 to be adjusted for hysteresis or bias during a skip frame.

[0123] As shown in FIG3 to FIG30 , the light emitting element 100 b includes a first electrode E1 , a second electrode E2 , and a light emitting functional layer FL located between the first electrode E1 and the second electrode E2 . The first electrode E1 is closer to the base substrate BS than the second electrode E2 .

[0124] As shown in Figures 3, 14 to 16, and 28, the pixel circuit 100a further includes a reset transistor T1 connected to the gate T3g of the driving transistor T3. The reset transistor T1 is configured to reset the gate T3g of the driving transistor T3. The reset transistor T1 includes an active layer A1. The threshold compensation transistor T2 includes an active layer A2. The orthographic projection of the first electrode E1 of the light-emitting element 100b on the base substrate BS overlaps with the orthographic projection of the active layer A1 on the base substrate BS. The orthographic projection of the first electrode E1 of the light-emitting element 100b on the base substrate BS overlaps with the orthographic projection of the active layer A2 on the base substrate BS.

[0125] The display panel provided by the embodiment of the present disclosure adopts a method in which the first electrode E1 of the light-emitting element 100b overlaps with the active layer A1 and the active layer A2, which can prevent the active layer A1 and the active layer A2 from being affected by light, avoid affecting the characteristics of the reset transistor T1 and the threshold compensation transistor T2, reduce the problem of redness or pinkness during display, and reduce the flicker problem caused by light.

[0126] Of course, in other embodiments, the first electrode E1 of the light emitting element 100b may overlap with one of the active layer A1 and the active layer A2.

[0127] For example, the orthographic projection of the first electrode E1 of the light emitting element 100 b on the base substrate BS covers the orthographic projection of at least one of the active layer A1 and the active layer A2 on the base substrate BS.

[0128] For example, as shown in FIG14 , the active layer A1 includes a channel A11 and a channel A12 , which are connected via a conductive portion P1 , and the active layer A2 includes a channel A21 and a channel A22 , which are connected via a conductive portion P2 .

[0129] As shown in Figures 7, 17 and 27, the second conductive line PL12 includes a protrusion P12 protruding along the direction X, and the orthographic projection of the protrusion P12 on the base substrate overlaps with the orthographic projection of at least one of the channel A11 and the channel A12 of the active layer A1 of the reset transistor T1 on the base substrate to further shield at least one of the channel A11 and the channel A12 of the active layer A1.

[0130] As shown in Figures 7, 17 and 27, the orthographic projection of the protrusion P12 on the base substrate overlaps with the orthographic projection of at least one of the channels A21 and A22 of the active layer A2 of the threshold compensation transistor T2 on the base substrate to further block at least one of the channels A11 and A12 of the active layer A1.

[0131] For example, the pattern of the conductive pattern layer LY4 in Figures 27, 29, and 30 is the same as the pattern of the conductive pattern layer LY4 shown in Figure 22. For example, the pattern of the electrode pattern layer LY5 in Figure 30 is the same as the pattern of the electrode pattern layer LY5 in Figure 28. For example, the boundary of the first electrode E1 in the electrode pattern layer LY5 in Figure 30 can be seen from the boundary of the first electrode E1 in the electrode pattern layer LY5 in Figure 28.

[0132] For example, an orthographic projection of the first electrode E1 of the light emitting element 100 b on the base substrate BS overlaps with an orthographic projection of at least one of the conductive portion P1 and the conductive portion P2 on the base substrate BS.

[0133] In the display panel provided by the embodiments of the present disclosure, the first electrode E1 overlaps with the conductive portion P1 and the conductive portion P2, thereby stabilizing the voltage on the conductive portion P1 and the voltage on the conductive portion P2 and preventing voltage jumps. Of course, the embodiments of the present disclosure are not limited to this. In other embodiments, the first electrode E1 does not overlap with at least one of the conductive portion P1 and the conductive portion P2.

[0134] For example, the orthographic projection of the first electrode E1 of the light-emitting element 100b on the base substrate BS covers the orthographic projection of the conductive portion P1 on the base substrate BS, and the orthographic projection of the first electrode E1 of the light-emitting element 100b on the base substrate BS covers the orthographic projection of the conductive portion P2 on the base substrate BS. Of course, the embodiments of the present disclosure are not limited to this. In other embodiments, the first electrode E1 does not cover at least one of the conductive portion P1 and the conductive portion P2.

[0135] For example, referring to Figures 5, 11, 12 to 16, the display panel further includes a light-emitting control signal line EML, the pixel circuit 100a further includes a light-emitting control transistor T5 and a data writing transistor T4, the orthographic projection of the light-emitting control signal line EML on the base substrate BS overlaps with the orthographic projection of the active layer A5 of the light-emitting control transistor T5 on the base substrate BS, the light-emitting control transistor T5 and the data writing transistor T4 are connected through a conductive connection C1, and the orthographic projection of the light-emitting control signal line EML on the base substrate BS overlaps with the orthographic projection of the conductive connection C1 on the base substrate BS.

[0136] In the display panel provided by the embodiment of the present disclosure, since the data writing transistor T4 and the threshold compensation transistor T2 are driven separately, the active layer A4 of the data writing transistor T4 needs to be separated. By using a conductive connection C1 jumper, the data writing transistor T4 avoids the light-emitting control signal line EML (avoids the lateral driving signal of the light-emitting control transistor T5).

[0137] For example, referring to Figures 5, 11, 12 to 16, the conductive connection member C1 is located on a different layer from the active layer A5 of the light emitting control transistor T5. The active layer A5 is located on the active pattern layer M0, and the conductive connection member C1 is located on the conductive pattern layer LY3.

[0138] For example, the conductive connection member C1 and the active layer A5 of the light emission control transistor T5 may be made of different materials. For example, the conductive connection member C1 may be made of a conductive material, and the active layer A5 may be made of a semiconductor. For another example, the conductive connection member C1 may be made of a metal, and the active layer A5 may be made of polysilicon.

[0139] Figure 14 shows the active layer A1 of the reset transistor T1, the active layer A2 of the threshold compensation transistor T2, the active layer A3 of the driving transistor T3, the active layer A4 of the data writing transistor T4, the active layer A5 of the light emitting control transistor T5, the active layer A6 of the light emitting control transistor T6, and the active layer A7 of the reset transistor T7.

[0140] In the embodiments of the present disclosure, the active layer of a transistor refers to the channel of the transistor. The material of the active layer (channel) of the transistor is a semiconductor material and has semiconductor properties.

[0141] For example, referring to FIG. 12 to FIG. 16 , one end of the conductive connection member C1 is connected to the data writing transistor T4 through the via hole V1 , and the other end of the conductive connection member C1 is connected to the light emission control transistor T5 through the via hole V2 .

[0142] For example, referring to Figures 3, 5, and 11 to 16, the display panel further includes a scan line GT2, which is connected to the gate T4g of the data write transistor T4. A via V1 is located between the emission control signal line EML and the scan line GT2. For example, the scan line GT2 and the gate T4g are integrally formed.

[0143] For example, referring to FIG. 12 to FIG. 16 , the via hole V2 is located between the light emission control signal line EML and the gate line GT1 .

[0144] For example, referring to Figures 12 to 16 , the orthographic projection of the emission control signal line EML on the base substrate BS does not overlap with the orthographic projection of the data write transistor T4 on the base substrate BS. Therefore, the data write transistor T4 avoids the emission control signal line EML (avoids the lateral drive signal of the emission control transistor T5).

[0145] For example, referring to Figures 4, 11, and 12 to 16, a pixel circuit of a display panel includes an active pattern M1 and an active pattern M2. The active pattern M1 includes an active layer A1, an active layer A2, an active layer A3, an active layer A5, and an active layer A6. The active pattern M2 includes an active layer A4. The active pattern M1 and the active pattern M2 are spaced apart from each other. Of course, in other embodiments, the active pattern M1 includes at least one of the active layer A1, the active layer A2, the active layer A3, the active layer A5, and the active layer A6. As shown in Figure 14, the active layers A1 to A6 are the portions of the active pattern layer M0 covered by the conductive pattern layer LY1. As shown in Figure 14, the portion of the active pattern layer M0 not covered by the conductive pattern layer LY1 is conductive and is a conductor, which can be referred to as a conductor portion and can serve as the first or second electrode of the transistor.

[0146] It should be noted that the transistors used in the embodiments of the present disclosure may all be thin film transistors or field effect transistors or other switching devices with the same characteristics. The source and drain of the transistor used here may be symmetrical in structure, so the source and drain may be structurally indistinguishable. In the embodiments of the present disclosure, in order to distinguish the two poles of the transistor other than the gate, one of the poles is directly described as the first pole and the other pole as the second pole, so the first pole and the second pole of all or part of the transistors in the embodiments of the present disclosure can be interchangeable as needed. For example, the first pole of the transistor described in the embodiments of the present disclosure may be a source pole, and the second pole may be a drain pole; or, the first pole of the transistor may be a drain pole, and the second pole may be a source pole.

[0147] For example, as shown in FIG3 , the display panel further includes a storage capacitor Cst and a first power line PL1. A first plate Ca of the storage capacitor Cst is connected to the gate T3g of the driving transistor T3, and a second plate Cb of the storage capacitor Cst is connected to the first power line PL1. The first power line PL1 is configured to provide a first power voltage to the pixel circuit 100a. The first power voltage is the first voltage signal VDD.

[0148] For example, as shown in FIG. 7 and FIG. 8 , the first power line PL1 includes a first conductive line PL11 and a second conductive line PL12 . The first conductive line PL11 is closer to the base substrate BS than the second conductive line PL12 . The first conductive line PL11 and the second conductive line PL12 are connected.

[0149] As shown in Figures 7 and 8, the first conductive line PL11 is located in the conductive pattern layer LY3, and the second conductive line PL12 is located in the conductive pattern layer LY4. Referring to Figures 7, 8, and 21A, when manufacturing a display panel, the conductive pattern layer LY3 is formed first, followed by the insulating layer 604, and then the conductive pattern layer LY4 is formed on the insulating layer 604. The components in the conductive pattern layer LY3 are formed before those in the conductive pattern layer LY4. Therefore, the first conductive line PL11 in the conductive pattern layer LY3 is closer to the base substrate BS than the second conductive line PL12 in the conductive pattern layer LY4.

[0150] As shown in Figures 7, 8, and 13, the first conductive line PL11 and the second conductive line PL12 are connected through a via hole. As shown in Figure 13, the first conductive line PL11 and the second conductive line PL12 are connected through a via hole Vb.

[0151] For example, as shown in Figures 17 and 20, in the display panel, the first conductive line PL11 extends along the direction Y, multiple first conductive lines PL11 are arranged along the direction X, at least one first conductive line PL11 includes multiple sub-lines PLa discontinuous along the direction Y, and the direction Y intersects the direction X.

[0152] For example, as shown in FIG13 , in the display panel, the first conductive line PL11 and the block BK are connected through a via. As shown in FIG13 , the first conductive line PL11 and the block BK are connected through a via V8. This arrangement of the block BK facilitates wiring.

[0153] For example, as shown in Figures 11 and 13, the orthographic projection of the block BK on the base substrate overlaps the orthographic projection of the conductive portion P2 on the base substrate. The block BK and the conductive portion P2 form a capacitor (stabilizing capacitor), and the block BK plays a role in stabilizing the voltage on the conductive portion P2.

[0154] As shown in Figures 24 and 26, due to process limitations, two adjacent first electrodes E1 have a minimum spacing. In this case, the channels of the reset transistor T1 and the threshold compensation transistor T2 may not be completely shielded. As shown in Figures 14 and 29, to prevent light from affecting the characteristics of the transistors and to improve the redness or pinking problem, the first power line PL1 (second conductor PL12) is used for further shielding. As shown in Figure 29, the orthographic projection of the first power line PL1 (second conductor PL12) on the base substrate BS overlaps with the orthographic projection of the active layer A2 of the threshold compensation transistor T2 on the base substrate BS. As shown in Figure 29, the orthographic projection of the first power line PL1 (second conductor PL12) on the base substrate BS overlaps with the orthographic projection of at least one of the active layer A1 of the reset transistor T1 and the active layer A2 of the threshold compensation transistor T2 on the base substrate BS. For example, as shown in Figures 22 and 27 , in the display panel, the orthographic projection of the first power line PL1 (second conductive line PL12) on the base substrate BS overlaps with the orthographic projection of the active layer A1 on the base substrate BS, and also overlaps with the orthographic projection of the active layer A2 on the base substrate BS. Figure 29 illustrates an example in which the orthographic projection of the first power line PL1 (second conductive line PL12) on the base substrate BS overlaps with both the orthographic projections of the active layer A1 of the reset transistor T1 and the active layer A2 of the threshold compensation transistor T2 on the base substrate BS.

[0155] For example, in order to stabilize the voltage of the node N1 and improve the display effect, as shown in Figures 22 and 27, the orthographic projection of the first power line PL1 (second wire PL12) on the base substrate BS overlaps with the orthographic projection of the active layer A3 of the driving transistor T3 on the base substrate BS.

[0156] For example, as shown in Figures 3 to 30, the display panel also includes a first initialization line INT1 and a second initialization line INT2, wherein the pixel circuit 100a also includes a reset transistor T7, the reset transistor T7 is connected to the first electrode E1 of the light-emitting element 100b, the first initialization line INT1 is connected to the reset transistor T1, and the second initialization line INT2 is connected to the reset transistor T7.

[0157] For example, as shown in Figures 6, 7, 12, and 13, the first initialization line INT1 includes a first initialization signal line INT11 extending along the direction X and a first initialization connection line INT12 extending along the direction Y, and the second initialization line INT2 includes a second initialization signal line INT21 extending along the direction X and a second initialization connection line INT22 extending along the direction Y, and the first initialization connection line INT12, the first conductive line PL11, and the second initialization connection line INT22 are arranged in sequence. As shown in Figure 7, the first initialization connection line INT12, the first conductive line PL11, and the second initialization connection line INT22 are arranged in sequence along the direction X. As shown in Figure 7, the first initialization connection line INT12, the first conductive line PL11, and the second initialization connection line INT22 are arranged adjacent to each other in sequence along the direction X. For example, the arrangement of the first initialization connection line INT12, the first conductive line PL11, and the second initialization connection line INT22 is not limited to that shown in Figure 7. For example, based on Figure 7, the positions of the first initialization connection line INT12 and the second initialization connection line INT22 can be swapped.

[0158] As shown in Figures 12 and 13, the first initialization signal line INT11 and the first initialization connection line INT12 are connected through a via. As shown in Figures 12 and 13, the first initialization signal line INT11 and the first initialization connection line INT12 are connected through a via V6.

[0159] As shown in Figures 12 and 13, the second initialization signal line INT21 and the second initialization connection line INT22 are connected through a via. As shown in Figures 12 and 13, the second initialization signal line INT21 and the second initialization connection line INT22 are connected through a via V10.

[0160] For example, as shown in Figures 8, 13, 18A, 18B, 25A, and 25B, in a display panel, second conductive line PL12 includes a main portion MP and branch portions BR. The branch portions BR branch out from the main portion MP. The orthographic projection of the first electrode E1 of light-emitting element 100b on base substrate BS overlaps with the orthographic projection of the main portion MP on base substrate BS, and also overlaps with the orthographic projection of the branch portions BR on base substrate BS. The main portion MP extends along direction Y. The main portion MP and the branch portions BR serve to level the first electrode E1 of light-emitting element 100b, improving its flatness, thereby preventing color shift and enhancing display quality.

[0161] For example, as shown in Figures 8, 13, 18A, 18B, 22, 25A, and 25B, the display panel further includes a leveling element FT. The orthographic projection of the first electrode E1 of the light-emitting element 100b on the base substrate BS overlaps with the orthographic projection of the leveling element FT on the base substrate BS. The leveling element FT and the branch portions BR are respectively disposed on either side of the main portion MP. The leveling element FT and the branch portions BR both serve to level the first electrode E1 of the light-emitting element 100b, thereby preventing left-right color shift and improving display quality.

[0162] For example, as shown in Figures 8, 13, 18A, 18B, 22, 25A, and 25B, the leveling element FT and the main body MP are located on the same layer and spaced apart. In the embodiment of the present disclosure, the leveling element FT is provided on one side of the main body MP, thereby allowing the branch portion BR to be provided on the other side of the main body MP to prevent left-right color shift and improve display quality.

[0163] For example, as shown in FIG. 8 , FIG. 13 , FIG. 18A, FIG. 18B, FIG. 22 , FIG. 25A, and FIG. 25B, the width of the main body MP is greater than the width of the branch portion BR.

[0164] For example, as shown in Figures 8, 13, 18A, 18B, 22, 25A, and 25B, the width of the main body MP is greater than the width of the leveling element FT and greater than the width of the leveling element FT in the direction X.

[0165] For example, as shown in FIG. 8 , FIG. 13 , FIG. 18A, FIG. 18B, FIG. 22 , FIG. 25A, and FIG. 25B, the leveling element FT is connected to the first electrode E1 of the light emitting element through a via hole Vn.

[0166] In the embodiments of the present disclosure, the width of a component may refer to a dimension perpendicular to its extending direction.

[0167] For example, as shown in Figures 16, 24 and 28, in the display panel, the first electrode E1 of the light emitting element 100b has a protrusion PR, and the orthographic projection of the protrusion PR on the base substrate BS overlaps with the orthographic projection of at least one of the active layer A1 and the active layer A2 on the base substrate BS.

[0168] 22 and 27 , the orthographic projection of the branch portion BR on the base substrate BS overlaps with the orthographic projection of the active layer A4 on the base substrate BS. That is, the orthographic projection of the branch portion BR on the base substrate BS overlaps with the orthographic projection of the data writing transistor T4 on the base substrate BS.

[0169] 22 and 27 , the orthographic projection of the data line DT on the base substrate BS overlaps with the orthographic projection of the active layer A6 on the base substrate BS. That is, the orthographic projection of the data line DT on the base substrate BS overlaps with the orthographic projection of the emission control transistor T6 on the base substrate BS.

[0170] 3, 4 to 7, 12, and 13, one end of the conductive connector C2 is connected to the gate T3g (first electrode Ca) of the driving transistor T3 through a via V4, and one end of the conductive connector C2 is connected to the second electrode T1b of the reset transistor T1 (the second electrode T2b of the threshold compensation transistor T2) through a via V5.

[0171] 3 , 4 to 7 , 12 , and 13 , one end of the conductive connection member C3 is connected to the second electrode T6 b of the light emitting control transistor T6 through a via V13 .

[0172] 13 and 16 , the other end of the conductive connection member C3 is connected to the conductive connection member CEn through a via Vc.

[0173] 3 , 4 to 7 , 12 , and 13 , one end of the conductive connector C4 is connected to the first electrode T7 a of the reset transistor T7 through a via V11 , and the other end of the conductive connector C4 is connected to the second initialization signal line INT21 through a via V12 .

[0174] 3 , 4 to 7 , 12 , and 13 , one end of the conductive connection member C5 is connected to the first electrode T4 a of the data writing transistor T4 through a via V9 .

[0175] 3 , 4 to 7 , 12 , and 13 , the data line DT is connected to the other end of the conductive connection member C5 through the via Va.

[0176] 3 , 4 to 7 , 12 , and 13 , one end of the conductive connector C6 is connected to the first electrode T1 a of the reset transistor T1 through a via V7 , and the other end of the conductive connector C6 is connected to the first initialization signal line INT11 through a via V6 .

[0177] 3, 13, and 17, the first conductive line PL11 is connected to the second plate Cb of the storage capacitor Cst through a via V3.

[0178] 3 , 13 , and 17 , one end of the conductive connection CEn is connected to the conductive connection C3 through a via Vc.

[0179] 3 , 13 , and 17 , the other end of the conductive connection member CEn is connected to the first electrode E1 of the light emitting element through a via hole Vn.

[0180] 3 , 13 , and 17 , one end of the conductive connection CEm is connected to the conductive connection C3 through a via Vd.

[0181] 3 , 13 , and 17 , the other end of the conductive connection member CEm is connected to the first electrode E1 of the light emitting element through the via hole Vm.

[0182] 13 , the conductive connecting member CEn and the conductive connecting member CEm are connecting members in different sub-pixels.

[0183] 3 , 13 , and 17 , the first conductive line PL11 is connected to the first electrode T5 a of the light emission control transistor T5 through a via V14 .

[0184] 3 , 13 , and 17 , the conductive connection member C6 is connected to the first initialization connection line INT12 through the first initialization signal line INT11 .

[0185] 3 , 13 , and 17 , the conductive connection member C4 is connected to the second initialization connection line INT22 through the second initialization signal line INT21 .

[0186] 3 , 13 , and 17 , the second initialization signal line INT21 and the first electrode T7 a of the reset transistor T7 are connected through a via V15 .

[0187] 3 , 13 , 16 , 17 and 21B , the first initialization connection line INT12 and the first initialization signal line INT11 are connected through a via V16 , and the first initialization connection line INT12 and the first electrode T1 a of the reset transistor T1 are connected through a via V17 .

[0188] As shown in FIG7 , FIG17 , FIG20 and FIG21B , the first initialization connection line INT12 includes a conductive connection member 66 , the first initialization signal line INT11 and the reset transistor T1 are connected via the conductive connection member 66 , and the conductive connection member 66 is located between two adjacent sub-lines PLa.

[0189] FIG31 is a stacked diagram of an active pattern layer M0 , a conductive pattern layer LY1 , ​​and an electrode pattern layer LY5 in a display panel provided by an embodiment of the present disclosure.

[0190] Figure 32 is a stackup diagram of an active pattern layer M0, a conductive pattern layer LY1, a conductive pattern layer LY2, a via structure VH1, a conductive pattern layer LY3, a via structure VH2, a conductive pattern layer LY4, a via structure VH3, an electrode pattern layer LY5, and a pixel defining layer PDL in a display panel provided by an embodiment of the present disclosure.

[0191] Figure 33 is a stackup diagram of an active pattern layer M0, a conductive pattern layer LY1, a conductive pattern layer LY2, a via structure VH1, a conductive pattern layer LY3, a via structure VH2, a conductive pattern layer LY4, a via structure VH3, an electrode pattern layer LY5, and a pixel defining layer PDL in a display panel provided by an embodiment of the present disclosure.

[0192] FIG34 is a stacked diagram of an active pattern layer M0 , a conductive pattern layer LY1 , ​​and an electrode pattern layer LY5 in a display panel provided by an embodiment of the present disclosure.

[0193] The display panels shown in Figures 31 and 32 illustrate actual sub-pixels. The display panels shown in Figures 33 and 34 demonstrate another pixel structure. The display panels shown in Figures 31 to 34 also prevent the active layers A1 and A2 from being affected by light, preventing any impact on the characteristics of the reset transistor T1 and the threshold compensation transistor T2, thereby alleviating reddish or pinkish coloration during display and reducing flicker caused by light.

[0194] Figures 31 and 32 illustrate an example in which the orthographic projection of the first electrode E1 of the light-emitting element on the base substrate BS covers the active layer A1 and the orthographic projection of the active layer A2 on the base substrate. For example, in an embodiment of the present disclosure, the first electrode E1 has a protrusion PR at the chamfer. The protrusion PR is provided to shield the active layer (channel).

[0195] For example, in the embodiment of the present disclosure, the first electrode E1 has a protrusion PR at a chamfered corner, and the opening OPN has a chamfered corner at the protrusion PR. The protrusion PR is provided to shield the active layer (channel).

[0196] For example, in embodiments of the present disclosure, as shown in Figures 26, 28, and 30, the first electrode E1 of the sub-pixel 101 has a protrusion PR at a chamfered corner. The protrusion PR is used to block the channel of the threshold compensation transistor T2 to prevent the chamfer from blocking the channel of the threshold compensation transistor T2. Furthermore, the opening OPN has a chamfered corner at the protrusion PR. The protrusion PR is provided to block the active layer (channel). The shape of the first electrode E1 of the light-emitting element in Figure 30 can be shown in Figure 28.

[0197] As shown in Figures 28 and 31 to 34, in each of the sub-pixels 101, 102, and 103 in the display panel, the orthographic projection of the first electrode E1 of the light-emitting element on the base substrate overlaps the orthographic projection of the active layer A1 and the orthographic projection of the active layer A2 on the base substrate. That is, in each of the sub-pixels 101, 102, and 103 in the display panel, the orthographic projection of the first electrode E1 of the light-emitting element on the base substrate overlaps the active layer A1 and overlaps the orthographic projection of the active layer A2 on the base substrate.

[0198] As shown in Figures 33 and 34, in each of the sub-pixels 101, 102, 103, and 104 in the display panel, the orthographic projection of the first electrode E1 of the light-emitting element on the substrate covers the active layer A1 and the orthographic projection of the active layer A2 on the substrate. That is, in each of the sub-pixels 101, 102, 103, and 104 in the display panel, the orthographic projection of the first electrode E1 of the light-emitting element on the substrate covers the active layer A1 and covers the orthographic projection of the active layer A2 on the substrate.

[0199] In the embodiments of the present disclosure, component A covering component B means that component A completely covers component B. The orthographic projection of component A on the base substrate covers the orthographic projection of component B on the base substrate means that the orthographic projection of component A on the base substrate completely covers component B.

[0200] FIG35 is a plan view of a conductive pattern layer LY4 in a display panel provided in an embodiment of the present disclosure. Compared with the display panel shown in FIG8 , the display panel shown in FIG35 has an adjusted shape of the branch portion BR. As shown in FIG35 , the branch portion BR is T-shaped. This arrangement can make the supporting branch portion BR more evenly stressed, thereby improving the flatness of the first electrode E1 of the light-emitting element. As shown in FIG35 , the branch portion BR includes a portion extending in the direction X and a portion extending in the direction Y. The portion of the branch portion BR extending in the direction Y is connected to the main body MP through the portion of the branch portion BR extending in the direction X. For example, the branch portion BR shown in FIG8 is 7-shaped.

[0201] Figure 36 shows a stackup diagram of the active pattern layer M0, conductive pattern layer LY1, and conductive pattern layer LY2 in a display panel according to an embodiment of the present disclosure. Compared to the display panel shown in Figure 11, in the display panel shown in Figure 36, the first initialization signal line INT11 includes a block BK. The orthographic projection of the conductive portion P2 in the active layer A2 of the threshold compensation transistor T2, which is connected to two spaced-apart channels (channel A21 and channel A22), overlaps with the orthographic projection of the block BK on the substrate. This arrangement also stabilizes the voltage on the conductive portion P2.

[0202] An embodiment of the present disclosure further provides a display device, comprising any of the above-mentioned display panels.

[0203] For example, the display device includes an OLED or a product including an OLED. For example, the display device includes any product or component with a display function, such as a television, a digital camera, a mobile phone, a watch, a tablet computer, a laptop computer, a navigation system, etc., which includes the above-mentioned display panel.

[0204] The above description is based on the 7T1C pixel circuit 100a as an example, and the embodiments of the present disclosure include but are not limited to this. It should be noted that the embodiments of the present disclosure do not limit the number of thin-film transistors and the number of capacitors included in the pixel circuit 100a. For example, in some other embodiments, the pixel circuit 100a of the display panel can also be a structure including other numbers of transistors, such as a 7T2C structure, a 6T1C structure, a 6T2C structure or a 9T2C structure, and the embodiments of the present disclosure do not limit this. Of course, the display panel can also include a pixel circuit 100a with less than 7 transistors.

[0205] In the embodiment of the present disclosure, the components located in the same layer may be formed from the same film layer through the same patterning process. For example, the components located in the same layer may be located on a surface of the same component away from the base substrate BS.

[0206] Some figures illustrate direction Z, which is perpendicular to the main surface of the substrate. The main surface of the substrate is the surface used to fabricate various components. The top surface of the substrate in a cross-sectional view is the main surface of the substrate. Directions X and Y are both parallel to the main surface of the substrate. For example, directions X and Y intersect. Furthermore, for example, directions X and Y are perpendicular. Direction Z is perpendicular to direction X and also perpendicular to direction Y.

[0207] For example, the transistors in the pixel circuits of the embodiments of the present disclosure are all thin-film transistors. For example, the conductive pattern layer LY1, the conductive pattern layer LY2, the conductive pattern layer LY3, and the conductive pattern layer LY4 are all made of metal materials. For example, the conductive pattern layer LY1 and the conductive pattern layer LY2 are formed of metal materials such as nickel and aluminum, but are not limited thereto. For example, the conductive pattern layer LY3 and the conductive pattern layer LY4 are formed of materials such as titanium and aluminum, but are not limited thereto. For example, the conductive pattern layer LY3 and the conductive pattern layer LY4 are respectively formed of three sublayers of Ti / Al / Ti, but are not limited thereto. For example, the base substrate can be a glass substrate or a polyimide substrate, but are not limited thereto and can be selected as needed. For example, the buffer layer BL, the barrier layer BA, the insulating layer 601, the insulating layer 602, the insulating layer 603, the insulating layer 604, and the insulating layer 605 are all made of insulating materials. For example, the material of the insulating layer 605 includes an organic insulating material, which includes, but is not limited to, a resin. For example, the insulating layer 601, the insulating layer 602, the insulating layer 603, and the insulating layer 604 may be made of an inorganic insulating material, such as at least one of silicon oxide, silicon nitride, and silicon oxynitride.

[0208] For example, the materials of the first electrode E1 and the second electrode E2 of the light-emitting element can be selected as needed. In some embodiments, the first electrode E1 can be made of at least one of a transparent conductive metal oxide and silver, but is not limited thereto. For example, the first electrode E1 can be made of a structure comprising three sub-layers of ITO-Ag-ITO. In some embodiments, the second electrode E2 can be made of a low-work-function metal, such as at least one of magnesium and silver, but is not limited thereto.

[0209] The following points need to be explained.

[0210] (1) Unless otherwise defined, technical or scientific terms used herein shall have the same meaning as those generally understood by persons having ordinary skill in the art to which this disclosure pertains. The terms “first,” “second,” and similar terms used in this disclosure do not denote any order, quantity, or importance, but are used only to distinguish different components.

[0211] (2) In the drawings of the embodiments of the present disclosure, only the structures related to the embodiments of the present disclosure are involved, and other structures can refer to the general design.

[0212] (3) For the sake of clarity, the thickness of layers or regions in the drawings used to describe the embodiments of the present disclosure are exaggerated. It will be understood that when an element such as a layer, film, region, or substrate is referred to as being "on" or "under" another element, the element may be "directly on" or "under" the other element, or intervening elements may be present.

[0213] (4) Unless there is any conflict, the embodiments of the present disclosure and the features therein may be combined with each other.

[0214] The above description is merely a specific embodiment of the present disclosure, but the scope of protection of the present disclosure is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in this disclosure should be included in the scope of protection of the present disclosure. Therefore, the scope of protection of the present disclosure should be based on the scope of protection of the claims.

Claims

1. A display panel, comprising: substrate substrate; A pixel circuit is located on the substrate and includes a driving transistor, a threshold compensation transistor, and a data writing transistor; A gate line connected to the gate of the threshold compensation transistor and extending along a first direction; as well as A scan line connected to the gate of the data writing transistor and extending along the first direction, The first electrode of the threshold compensation transistor is connected to the first electrode of the driving transistor, the second electrode of the threshold compensation transistor is connected to the gate of the driving transistor, and the data writing transistor is connected to the second electrode of the driving transistor. The material of the active layer of the threshold compensation transistor includes low temperature polysilicon, The gate lines and the scan lines are arranged along the second direction, the second direction intersects the first direction, and the gate lines are different from the scan lines. The active layer of the data write transistor is located on a side of the active layer of the drive transistor that is away from the active layer of the threshold compensation transistor in the second direction.

2. The display panel according to claim 1, wherein: The gate line and the scan line are respectively arranged on two sides of the active layer of the driving transistor.

3. The display panel according to claim 1 or 2, further comprising a light emitting element, wherein: The pixel circuit is configured to drive the light emitting element, The pixel circuit further includes a first reset transistor connected to the gate of the driving transistor; The light emitting element includes a first electrode, a second electrode, and a light emitting functional layer located between the first electrode and the second electrode, wherein the first electrode is closer to the base substrate than the second electrode.

4. The display panel according to claim 3, wherein: The orthographic projection of the first electrode of the light-emitting element on the substrate overlaps with the orthographic projection of the active layer of the first reset transistor on the substrate, and the orthographic projection of the first electrode of the light-emitting element on the substrate overlaps with the orthographic projection of the active layer of the threshold compensation transistor on the substrate.

5. The display panel according to claim 4, wherein: The orthographic projection of the first electrode of the light emitting element on the base substrate covers the orthographic projection of at least one of the first active layer and the second active layer on the base substrate.

6. The display panel according to any one of claims 3 to 5, wherein: The active layer of the first reset transistor includes a first channel and a second channel, the first channel and the second channel are connected through a first conductive portion, and the active layer of the threshold compensation transistor includes a third channel and a fourth channel, the third channel and the fourth channel are connected through a second conductive portion.

7. The display panel according to claim 6, wherein: The orthographic projection of the first electrode of the light emitting element on the base substrate covers the orthographic projection of at least one of the first conductive portion and the second conductive portion on the base substrate.

8. The display panel according to claim 6 or 7, wherein: The orthographic projection of the first electrode of the light-emitting element on the base substrate overlaps with the orthographic projection of the first conductive portion on the base substrate, and the orthographic projection of the first electrode of the light-emitting element on the base substrate overlaps with the orthographic projection of the second conductive portion on the base substrate.

9. The display panel according to any one of claims 4 to 8, further comprising a light emitting control signal line, wherein: The pixel circuit also includes a first light-emitting control transistor, the orthographic projection of the light-emitting control signal line on the substrate overlaps with the orthographic projection of the active layer of the first light-emitting control transistor on the substrate, the first light-emitting control transistor and the data writing transistor are connected via a first conductive connection, and the orthographic projection of the light-emitting control signal line on the substrate overlaps with the orthographic projection of the first conductive connection on the substrate.

10. The display panel according to claim 9, wherein: The first conductive connection member and the active layer of the first light emission control transistor are located in different layers.

11. The display panel according to claim 9 or 10, wherein: One end of the first conductive connection member is connected to the data writing transistor through a first via hole, and the other end of the first conductive connection member is connected to the first light emission control transistor through a second via hole.

12. The display panel according to any one of claims 9 to 11, wherein: The first via hole is located between the light emitting control signal line and the scan line.

13. The display panel according to any one of claims 9 to 12, wherein: An orthographic projection of the light emission control signal line on the base substrate does not overlap with an orthographic projection of the data writing transistor on the base substrate.

14. The display panel according to any one of claims 4 to 13, further comprising a storage capacitor and a first power line, wherein: The first plate of the storage capacitor is connected to the gate of the driving transistor, and the second plate of the storage capacitor is connected to the first power line, which is configured to provide a first power supply voltage to the pixel circuit.

15. The display panel according to claim 14, wherein: An orthographic projection of the first power line on the base substrate overlaps with an orthographic projection of an active layer of the first reset transistor on the base substrate, and overlaps with an orthographic projection of an active layer of the threshold compensation transistor on the base substrate.

16. The display panel according to claim 14 or 15, wherein: The first power line includes a first wire and a second wire, the first wire is closer to the base substrate than the second wire, and the first wire is connected to the second wire.

17. The display panel according to claim 16, wherein: The second conductive line includes a first protruding portion protruding along the first direction, and an orthographic projection of the first protruding portion on the base substrate overlaps an orthographic projection of at least one of a first channel and a second channel of an active layer of the first reset transistor on the base substrate.

18. The display panel according to claim 16 or 17, wherein: A plurality of first conductive lines are arranged along a first direction, and at least one first conductive line includes a plurality of sub-lines intermittently arranged along a second direction, and the second direction intersects the first direction.

19. The display panel according to any one of claims 16 to 18, further comprising a first initialization line and a second initialization line, wherein: The pixel circuit also includes a second reset transistor, which is connected to the first electrode of the light-emitting element, the first initialization line is connected to the first reset transistor, the second initialization line is connected to the second reset transistor, the first initialization line includes a first initialization signal line extending along a first direction and a first initialization connection line extending along a second direction, the second initialization line includes a second initialization signal line extending along the first direction and a second initialization connection line extending along the second direction, and the first initialization connection line, the first wire, and the second initialization connection line are arranged adjacent to each other in sequence along the first direction.

20. The display panel according to claim 19, wherein: The first initialization connection line includes a second conductive connection member, the first initialization signal line and the first reset transistor are connected via the second conductive connection member, and the second conductive connection member is located between two adjacent sub-lines.

21. The display panel according to any one of claims 16 to 20, wherein: The second wire has a main body and a branch, the branch branching out from the main body, and the orthographic projection of the first electrode of the light-emitting element on the base substrate overlaps with the orthographic projection of the main body on the base substrate, and overlaps with the orthographic projection of the branch on the base substrate.

22. The display panel according to claim 21, further comprising a leveling element, wherein: The orthographic projection of the first electrode of the light emitting element on the base substrate overlaps with the orthographic projection of the leveling element on the base substrate, and the leveling element and the branch portions are respectively arranged on both sides of the main portion.

23. The display panel according to claim 22, wherein: The leveling element and the main body are located in the same layer and are arranged at intervals. The leveling element extends along the second direction. The leveling element is connected to the first electrode of the light emitting element through a third via hole.

24. The display panel according to any one of claims 21 to 23, wherein: The width of the main body portion is greater than the width of the branch portion, and greater than the width of the leveling element in the first direction.

25. The display panel according to any one of claims 19 to 20, wherein: The first initialization signal line has a stopper, and an orthographic projection of a conductive portion in the active layer of the threshold compensation transistor connected to two spaced channels on the base substrate overlaps with an orthographic projection of the stopper on the base substrate.

26. The display panel according to any one of claims 3 to 25, wherein: The first electrode of the light emitting element has a second protrusion, and an orthographic projection of the second protrusion on the base substrate overlaps with an orthographic projection of at least one of an active layer of the first reset transistor and an active layer of the threshold compensation transistor on the base substrate.

27. The display panel according to any one of claims 16 to 25, further comprising a stopper, wherein: The first conductive line and the block are connected through a fourth via hole, and an orthographic projection of a conductive portion in the active layer of the threshold compensation transistor connected to two spaced channels on the base substrate overlaps with an orthographic projection of the block on the base substrate.

28. A display device comprising the display panel according to any one of claims 1-27.

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