Multiplexing circuit, multiplexing module, display device, and driving method

Abstract

The present disclosure provides a multiplexing circuit, a multiplexing module, a display device, and a driving method. The multiplexing circuit is electrically connected to M data voltage supply terminals and multiple columns of data lines, respectively, the multiplexing circuit comprises N multiplexing control lines and N multiplexing circuits, and the n-th multiplexing circuit comprises M multiplexing sub-circuits; the n-th multiplexing control line comprises M control lines; the m-th multiplexing sub-circuit comprised in the n-th multiplexing circuit is electrically connected to the m-th control line comprised in the n-th multiplexing control line, the m-th data voltage supply terminal and the corresponding data line, respectively, and is used for, under the control of a control signal supplied by the m-th control line, writing a data voltage supplied by the m-th data voltage supply terminal into the corresponding data line; N and M are both integers greater than 1, n is a positive integer less than or equal to N, and m is a positive integer less than or equal to M. The present disclosure can reduce the use quantity of data drivers while ensuring that the resolution of a display product remains unchanged.

Description

Multiplexing circuit, multiplexing module, display device and driving method

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to Chinese patent application No. 202310812831.8 filed in China on June 30, 2023, the entire contents of which are incorporated herein by reference. Technical Field

[0003] The present disclosure relates to the field of display technology, and in particular to a multiplexing circuit, a multiplexing module, a display device, and a driving method. Background Art

[0004] In the related art, in a display product, the number of data drivers is large, and the price of the data drivers is high, resulting in a high cost of the current display product.

[0005] Summary of the Invention

[0006] In one aspect, an embodiment of the present disclosure provides a multiplexing circuit electrically connected to M data voltage supply terminals and a plurality of column data lines, respectively. The multiplexing circuit includes N multiplexing control lines and N multiplexing circuits, wherein the nth multiplexing circuit includes M multiplexing sub-circuits; the nth multiplexing control line includes M control lines;

[0007] The mth multiplexing sub-circuit included in the nth multiplexing circuit is electrically connected to the mth control line, the mth data voltage supply terminal and the corresponding data line included in the nth multiplexing control line, and is used to write the data voltage provided by the mth data voltage supply terminal into the corresponding data line under the control of the control signal provided by the mth control line;

[0008] Both N and M are integers greater than 1, n is a positive integer less than or equal to N, and m is a positive integer less than or equal to M.

[0009] Optionally, the multiplexing circuit includes a first multiplexing control line, a second multiplexing control line, a first multiplexing circuit, and a second multiplexing circuit;

[0010] The first multiplexed control line includes a first control line and a second control line; the second multiplexed control line includes a third control line and a fourth control line;

[0011] The first multiplexing circuit includes a first multiplexing sub-circuit and a second multiplexing sub-circuit; the second multiplexing circuit includes a third multiplexing sub-circuit and a fourth multiplexing sub-circuit;

[0012] The first multiplexing sub-circuit is electrically connected to the first control line, the first data voltage supply terminal and the first column data line respectively, and is used to write the data voltage provided by the first data voltage supply terminal into the first column data line under the control of the first control signal provided by the first control line;

[0013] The second multiplexing sub-circuit is electrically connected to the second control line, the second data voltage supply terminal and the second column data line respectively, and is used to write the data voltage provided by the second data voltage supply terminal into the second column data line under the control of the second control signal provided by the second control line;

[0014] The third multiplexing sub-circuit is electrically connected to the third control line, the first data voltage supply terminal and the third column data line respectively, and is used to write the data voltage provided by the first data voltage supply terminal into the third column data line under the control of a third control signal provided by the third control line;

[0015] The fourth multiplexing sub-circuit is electrically connected to the fourth control line, the second data voltage supply end and the fourth column data line respectively, and is used to write the data voltage provided by the second data voltage supply end into the fourth column data line under the control of a fourth control signal provided by the fourth control line.

[0016] Optionally, the first multiplexing sub-circuit includes a first transistor, and the second multiplexing sub-circuit includes a second transistor;

[0017] The gate of the first transistor is electrically connected to the first control line, the first electrode of the first transistor is electrically connected to the first data voltage supply terminal, and the second electrode of the first transistor is electrically connected to the first column data line;

[0018] A gate of the second transistor is electrically connected to the second control line, a first electrode of the second transistor is electrically connected to the second data voltage supply terminal, and a second electrode of the second transistor is electrically connected to the second column data line.

[0019] Optionally, both the first transistor and the second transistor are n-type transistors; or both the first transistor and the second transistor are p-type transistors.

[0020] Optionally, the third multiplexing sub-circuit includes a third transistor, and the fourth multiplexing sub-circuit includes a fourth transistor;

[0021] The gate of the third transistor is electrically connected to the third control line, the first electrode of the third transistor is electrically connected to the first data voltage supply terminal, and the second electrode of the third transistor is electrically connected to the third column data line;

[0022] A gate of the fourth transistor is electrically connected to the fourth control line, a first electrode of the fourth transistor is electrically connected to the second data voltage supply terminal, and a second electrode of the fourth transistor is electrically connected to the fourth column data line.

[0023] Optionally, the third transistor and the fourth transistor are both n-type transistors; or, the third transistor and the fourth transistor are both p-type transistors.

[0024] The embodiment of the present disclosure further provides a multiplexing module, comprising a plurality of the above-mentioned multiplexing circuits.

[0025] The embodiment of the present disclosure further provides a display device, comprising a data driver, a plurality of columns of data lines and the above-mentioned multiplexing module;

[0026] The data driver is used to provide a data voltage to the multiplexing module through a data voltage supply terminal;

[0027] The data line is used to receive the data voltage provided by the multiplexing module.

[0028] Optionally, the data driver provides a control signal to each control line through at least one corresponding output channel.

[0029] Optionally, the display device includes a display panel, a data driver and a plurality of control lines;

[0030] The data driver is disposed on a first side of the display panel, and the plurality of control lines are disposed between the data driver and an effective display area of ​​the display panel;

[0031] The data driver is further configured to provide a control signal input to the control line.

[0032] Optionally, the control line includes a first end and a second end;

[0033] The first output channel of the data driver is electrically connected to the first end, and the second output channel of the data driver is electrically connected to the second end. The data driver is used to provide a control signal to the first end through the first output channel and to provide a control signal to the second end through the second output channel.

[0034] Optionally, the display device includes a display panel, at least two data drivers and a plurality of control lines;

[0035] The data driver is disposed on a first side of the display panel, and the plurality of control lines are disposed between the data driver and an effective display area of ​​the display panel;

[0036] The data driver is further configured to provide a control signal input to the control line.

[0037] Optionally, the control line is electrically connected to the at least two data drivers through at least three access points, and is used to receive a control signal provided by the data drivers.

[0038] Optionally, the display device includes a first data driver and a second data driver;

[0039] The first output channel of the first data driver is electrically connected to the first end of the control line, and the first output channel of the second data driver is electrically connected to the second end of the control line;

[0040] The second output channel of the first data driver and the second output channel of the second data driver are both electrically connected to the middle node of the control line;

[0041] The first data driver is configured to provide a control signal to the control line through a first output channel and a second output channel thereof;

[0042] The second data driver is configured to provide a control signal to the control line through a first output channel and a second output channel thereof.

[0043] Optionally, the display device according to at least one embodiment of the present disclosure further includes multiple rows of gate lines and multiple rows and columns of pixel circuits;

[0044] The pixel circuits are electrically connected to corresponding row gate lines and corresponding column data lines respectively, and are used to control and receive data voltages provided by corresponding column data lines under the control of gate drive signals provided by corresponding row gate lines.

[0045] The present disclosure also provides a driving method, which is applied to the above-mentioned display device. The driving method includes:

[0046] The data driver provides the data voltage to the multiplexing module through the data voltage supply terminal;

[0047] The data line receives the data voltage provided by the multiplexing module.

[0048] Optionally, the display device further includes a plurality of rows of gate lines and two multiplexing control lines; a is a positive integer;

[0049] When the gate line in row 2a-1 is turned on, the first multiplexing control line first controls the corresponding multiplexing transistor to turn on, and then the second multiplexing control line controls the corresponding multiplexing transistor to turn on;

[0050] When the gate line in row 2a is turned on, the second multiplexing control line first controls the corresponding multiplexing transistor to turn on, and then the first multiplexing control line controls the corresponding multiplexing transistor to turn on.

[0051] Optionally, the display device further includes a plurality of rows of gate lines and two multiplexing control lines; a is a positive integer;

[0052] When the gate line of row 2a-1 is turned on, the second multiplexing control line first controls the corresponding multiplexing transistor to turn on, and then the first multiplexing control line controls the corresponding multiplexing transistor to turn on;

[0053] When the gate line in row 2a is turned on, the first multiplexing control line first controls the corresponding multiplexing transistor to turn on, and then the second multiplexing control line controls the corresponding multiplexing transistor to turn on. BRIEF DESCRIPTION OF THE DRAWINGS

[0054] FIG1 is a structural diagram of a multiplexing circuit according to at least one embodiment of the present disclosure;

[0055] FIG2 is a circuit diagram of a multiplexing circuit according to at least one embodiment of the present disclosure;

[0056] FIG3A is a schematic diagram of some transistors included in a multiplexing module according to at least one embodiment of the present disclosure;

[0057] FIG3B is a waveform diagram of a first control signal provided by M11 in at least one embodiment of the present disclosure;

[0058] FIG3C is a waveform diagram of a multiplexing control signal provided by a multiplexing control line in the related art;

[0059] FIG4 is a layout diagram of at least one embodiment shown in FIG3A;

[0060] FIG5 is a layout diagram of the gate metal layer in FIG4 ;

[0061] FIG6 is a layout diagram of the semiconductor layer in FIG4;

[0062] FIG7 is a layout diagram of the source and drain metal layers in FIG4 ;

[0063] FIG8 is a layout diagram of the second conductive layer in FIG4;

[0064] FIG9 is a structural diagram of a display device according to at least one embodiment of the present disclosure;

[0065] FIG10 is a structural diagram of a display device according to at least one embodiment of the present disclosure;

[0066] FIG11 is a layout diagram of the middle portion of at least one embodiment shown in FIG10 ;

[0067] FIG12 is a layout diagram of the gate metal layer in FIG11;

[0068] FIG13 is a layout diagram of the source / drain metal layer in FIG11 ;

[0069] FIG14 is a layout diagram of the second conductive layer in FIG11;

[0070] 15 is a schematic diagram showing the connection relationship between part of the pixel circuit and part of the multiplexing transistors included in the display device according to at least one embodiment of the present disclosure;

[0071] FIG16 is a timing diagram of the operation of at least one embodiment shown in FIG15 ;

[0072] FIG17 is a timing diagram of the operation of at least one embodiment shown in FIG15 ;

[0073] FIG. 18 is an operation timing diagram of at least one embodiment shown in FIG. 15 . DETAILED DESCRIPTION

[0074] The following will be combined with the accompanying drawings in the embodiments of the present disclosure to clearly and completely describe the technical solutions in the embodiments of the present disclosure. Obviously, the embodiments described are only part of the embodiments of the present disclosure, not all of the embodiments. Based on the embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without making any creative efforts are within the scope of protection of the present disclosure.

[0075] The transistors used in all embodiments of the present disclosure may be thin film transistors, field effect transistors, or other devices with the same characteristics. In the embodiments of the present disclosure, to distinguish the two electrodes of the transistor except the gate, one electrode is referred to as the first electrode and the other electrode is referred to as the second electrode.

[0076] In actual operation, when the transistor is a thin film transistor or a field effect transistor, the first electrode may be a drain electrode, and the second electrode may be a source electrode; or, the first electrode may be a source electrode, and the second electrode may be a drain electrode.

[0077] The multiplexing circuit according to the embodiment of the present disclosure is electrically connected to M data voltage supply terminals and multiple column data lines, respectively. The multiplexing circuit includes N multiplexing control lines and N multiplexing circuits. The nth multiplexing circuit includes M multiplexing sub-circuits; the nth multiplexing control line includes M control lines.

[0078] The mth multiplexing sub-circuit included in the nth multiplexing circuit is electrically connected to the mth control line, the mth data voltage supply terminal and the corresponding data line included in the nth multiplexing control line, and is used to write the data voltage provided by the mth data voltage supply terminal into the corresponding data line under the control of the control signal provided by the mth control line;

[0079] Both N and M are integers greater than 1, n is a positive integer less than or equal to N, and m is a positive integer less than or equal to M.

[0080] In the related art, in TDDI (Touch and Display Driver Integration) products, the number of data drivers is large, and the price of data drivers is high, resulting in a high cost of current TDDI products. Based on this, the embodiments of the present disclosure propose a data signal multiplexing circuit that uses at least two multiplexing control lines and one data voltage supply terminal to drive at least two columns of data lines, so that the number of data voltage supply terminals used is small, and the number of data drivers used can be reduced while ensuring that the resolution of the display product remains unchanged. At the same time, in order to reduce the load of the multiplexing control line, the multiplexing control line is set to include at least two control lines, and the at least two control lines are driven by different channels of the data driver. The number of transistors driven by each control line is reduced compared to the number of transistors driven by the relevant multiplexing control line. The load of the control line is reduced, which can effectively reduce the rise time and fall time of the control signal on the control line, greatly improving the charging capacity of the control line.

[0081] In at least one embodiment of the present disclosure, N and M are both equal to 2 as an example, but the present invention is not limited thereto. In actual operation, N and M may be integers greater than 1.

[0082] The multiplexing circuit according to at least one embodiment of the present disclosure includes a first multiplexing control line, a second multiplexing control line, a first multiplexing circuit, and a second multiplexing circuit;

[0083] The first multiplexed control line includes a first control line and a second control line; the second multiplexed control line includes a third control line and a fourth control line;

[0084] The first multiplexing circuit includes a first multiplexing sub-circuit and a second multiplexing sub-circuit; the second multiplexing circuit includes a third multiplexing sub-circuit and a fourth multiplexing sub-circuit;

[0085] The first multiplexing sub-circuit is electrically connected to the first control line, the first data voltage supply terminal and the first column data line respectively, and is used to write the data voltage provided by the first data voltage supply terminal into the first column data line under the control of the first control signal provided by the first control line;

[0086] The second multiplexing sub-circuit is electrically connected to the second control line, the second data voltage supply terminal and the second column data line respectively, and is used to write the data voltage provided by the second data voltage supply terminal into the second column data line under the control of the second control signal provided by the second control line;

[0087] The third multiplexing sub-circuit is electrically connected to the third control line, the first data voltage supply terminal and the third column data line respectively, and is used to write the data voltage provided by the first data voltage supply terminal into the third column data line under the control of a third control signal provided by the third control line;

[0088] The fourth multiplexing sub-circuit is electrically connected to the fourth control line, the second data voltage supply end and the fourth column data line respectively, and is used to write the data voltage provided by the second data voltage supply end into the fourth column data line under the control of a fourth control signal provided by the fourth control line.

[0089] In a specific implementation, the multiplexing circuit may include a first multiplexing control line, a second multiplexing control line, a first multiplexing circuit and a second multiplexing circuit, the first multiplexing control line may include a first control line and a second control line, the second multiplexing control line may include a third control line and a fourth control line, the first multiplexing sub-circuit writes the data voltage provided by the first data voltage supply end into the first column data line under the control of the first control signal, the second multiplexing sub-circuit writes the data voltage provided by the second data voltage supply end into the second column data line under the control of the second control signal, the third multiplexing sub-circuit writes the data voltage provided by the first data voltage supply end into the third column data line under the control of the third control signal; the fourth multiplexing sub-circuit writes the data voltage provided by the second data voltage supply end into the fourth column data line under the control of the fourth control signal.

[0090] As shown in FIG1 , the multiplexing circuit according to at least one embodiment of the present disclosure is electrically connected to a first data voltage supply terminal S1, a second data voltage supply terminal S2, a first column data line D1, a second column data line D2, a third column data line D3, and a fourth column data line D4, respectively. The multiplexing circuit includes a first multiplexing control line, a second multiplexing control line, a first multiplexing circuit, and a second multiplexing circuit.

[0091] The first multiplexing control line includes a first control line M11 and a second control line M12, and the second multiplexing control line includes a third control line M21 and a fourth control line M22;

[0092] The first multiplexing circuit includes a first multiplexing sub-circuit 11 and a second multiplexing sub-circuit 12, and the second multiplexing circuit includes a third multiplexing sub-circuit 13 and a fourth multiplexing sub-circuit 14;

[0093] The first multiplexing sub-circuit 11 is electrically connected to the first control line M11, the first data voltage supply terminal S1 and the first column data line D1 respectively, and is used to write the data voltage provided by the first data voltage supply terminal S1 into the first column data line D1 under the control of the first control signal provided by the first control line M11;

[0094] The second multiplexing sub-circuit 12 is electrically connected to the second control line M12, the second data voltage supply terminal S2, and the second column data line D2, respectively, and is configured to write the data voltage provided by the second data voltage supply terminal S2 into the second column data line D2 under the control of the second control signal provided by the second control line M12;

[0095] The third multiplexing sub-circuit 13 is electrically connected to the third control line M13, the first data voltage supply terminal S1 and the third column data line D3, respectively, and is used to write the data voltage provided by the first data voltage supply terminal S1 into the third column data line D3 under the control of the third control signal provided by the third control line M13;

[0096] The fourth multiplexing sub-circuit 14 is electrically connected to the fourth control line M14, the second data voltage supply terminal S2 and the fourth column data line D4, respectively, and is used to write the data voltage provided by the second data voltage supply terminal S2 into the fourth column data line D4 under the control of the fourth control signal provided by the fourth control line M14.

[0097] In at least one embodiment of the multiplexing circuit shown in FIG1 of the present disclosure, when working, the first control signal provided by the first control line M11 and the second control signal provided by the second control line M12 may be the same, the third control signal provided by the third control line M13 and the fourth control signal provided by the fourth control line M14 may be the same, the first control line M11, the second control line M12, the third control line M13, and the fourth control line M14 are electrically connected to the first output channel of the data driver, the second output channel of the data driver, the third output channel of the data driver, and the fourth output channel of the data driver, respectively, and the corresponding output channels of the data driver provide control signals to each control line respectively. The number of transistors driven by each control line is halved compared to the number of transistors driven by the corresponding multiplexed control line, the load of the control line is reduced, and the rise time and fall time of the control signal on the control line can be effectively reduced, thereby improving the charging capacity of each control line.

[0098] In at least one embodiment of the multiplexing circuit shown in FIG. 1 of the present disclosure, each control line may also be electrically connected to at least two output channels of the data driver to enhance the driving capability of the control line.

[0099] Optionally, the first multiplexing sub-circuit includes a first transistor, and the second multiplexing sub-circuit includes a second transistor;

[0100] The gate of the first transistor is electrically connected to the first control line, the first electrode of the first transistor is electrically connected to the first data voltage supply terminal, and the second electrode of the first transistor is electrically connected to the first column data line;

[0101] A gate of the second transistor is electrically connected to the second control line, a first electrode of the second transistor is electrically connected to the second data voltage supply terminal, and a second electrode of the second transistor is electrically connected to the second column data line.

[0102] Optionally, both the first transistor and the second transistor are n-type transistors; or both the first transistor and the second transistor are p-type transistors.

[0103] Optionally, the third multiplexing sub-circuit includes a third transistor, and the fourth multiplexing sub-circuit includes a fourth transistor;

[0104] The gate of the third transistor is electrically connected to the third control line, the first electrode of the third transistor is electrically connected to the first data voltage supply terminal, and the second electrode of the third transistor is electrically connected to the third column data line;

[0105] A gate of the fourth transistor is electrically connected to the fourth control line, a first electrode of the fourth transistor is electrically connected to the second data voltage supply terminal, and a second electrode of the fourth transistor is electrically connected to the fourth column data line.

[0106] Optionally, the third transistor and the fourth transistor are both n-type transistors; or, the third transistor and the fourth transistor are both p-type transistors.

[0107] As shown in FIG2 , based on at least one embodiment of the multiplexing circuit shown in FIG1 , the first multiplexing sub-circuit includes a first transistor T1 , and the second multiplexing sub-circuit includes a second transistor T2 ;

[0108] The gate of the first transistor T1 is electrically connected to the first control line M11, the source of the first transistor T1 is electrically connected to the first data voltage supply terminal S1, and the drain of the first transistor T1 is electrically connected to the first column data line D1;

[0109] The gate of the second transistor T2 is electrically connected to the second control line M12, the source of the second transistor T2 is electrically connected to the second data voltage supply terminal S2, and the drain of the second transistor T2 is electrically connected to the second column data line D2;

[0110] The third multiplexing sub-circuit includes a third transistor T3, and the fourth multiplexing sub-circuit includes a fourth transistor T4;

[0111] The gate of the third transistor T3 is electrically connected to the third control line M13, the source of the third transistor T3 is electrically connected to the first data voltage supply terminal S1, and the drain of the third transistor T3 is electrically connected to the third column data line D3;

[0112] A gate of the fourth transistor T4 is electrically connected to the fourth control line M14 , a source of the fourth transistor T4 is electrically connected to the second data voltage supply terminal S2 , and a drain of the fourth transistor T4 is electrically connected to the fourth column data line D4 .

[0113] In at least one embodiment of the multiplexing circuit shown in FIG. 2 , all transistors are n-type transistors, but the present invention is not limited thereto.

[0114] When at least one embodiment of the multiplexing circuit shown in FIG2 is in operation, a data providing cycle may include a first multiplexing phase and a second multiplexing phase;

[0115] In the first multiplexing stage, M11 and M12 both provide high voltage signals, T1 and T2 are both turned on, S1 is connected to D1, S2 is connected to D2, and data voltage is provided to D1 through S1 and data voltage is provided to D2 through S2.

[0116] In the second multiplexing stage, M13 and M14 both provide high voltage signals, T3 and T4 are both turned on, S1 is connected to D3, S2 is connected to D4, and data voltage is provided to D3 through S1 and data voltage is provided to D4 through S2.

[0117] The multiplexing module described in the embodiment of the present disclosure includes multiple multiplexing circuits as described above.

[0118] FIG3A is a schematic diagram showing some transistors included in a multiplexing module according to at least one embodiment of the present disclosure.

[0119] As shown in FIG3A , the multiplexing module according to at least one embodiment of the present disclosure includes a first multiplexing circuit and a second multiplexing circuit;

[0120] The first multiplexing circuit includes a first transistor T1, a second transistor T2, a third transistor T3 and a fourth transistor T4;

[0121] The second multiplexing circuit includes a fifth transistor T5, a sixth transistor T6, a seventh transistor T7 and an eighth transistor T8;

[0122] The gate of the first transistor T1 is electrically connected to the first control line M11, the source of the first transistor T1 is electrically connected to the first data voltage supply terminal S1, and the drain of the first transistor T1 is electrically connected to the first column data line D1;

[0123] The gate of the second transistor T2 is electrically connected to the second control line M12, the source of the second transistor T2 is electrically connected to the second data voltage supply terminal S2, and the drain of the second transistor T2 is electrically connected to the second column data line D2;

[0124] The gate of the third transistor T3 is electrically connected to the third control line M13, the source of the third transistor T3 is electrically connected to the first data voltage supply terminal S1, and the drain of the third transistor T3 is electrically connected to the third column data line D3;

[0125] The gate of the fourth transistor T4 is electrically connected to the fourth control line M14, the source of the fourth transistor T4 is electrically connected to the second data voltage supply terminal S2, and the drain of the fourth transistor T4 is electrically connected to the fourth column data line D4;

[0126] The gate of the fifth transistor T5 is electrically connected to the first control line M11, the source of the fifth transistor T5 is electrically connected to the third data voltage supply terminal S3, and the drain of the fifth transistor T5 is electrically connected to the fifth column data line D5;

[0127] The gate of the sixth transistor T6 is electrically connected to the second control line M12, the source of the sixth transistor T6 is electrically connected to the fourth data voltage supply terminal S4, and the drain of the sixth transistor T6 is electrically connected to the sixth column data line D6;

[0128] The gate of the seventh transistor T7 is electrically connected to the third control line M13, the source of the seventh transistor T7 is electrically connected to the third data voltage supply terminal S3, and the drain of the seventh transistor T7 is electrically connected to the seventh data line D7;

[0129] The gate of the eighth transistor T8 is electrically connected to the fourth control line M14, the source of the eighth transistor T8 is electrically connected to the fourth data voltage supply terminal S4, and the drain of the eighth transistor T8 is electrically connected to the eighth data line D8.

[0130] In at least one embodiment shown in FIG. 3A , T1 , T2 , T3 , T4 , T5 , T6 , T7 , and T8 are all n-type transistors, but the present invention is not limited thereto.

[0131] When operating, at least one embodiment of the present disclosure shown in FIG. 3A may include a first multiplexing phase and a second multiplexing phase.

[0132] In the first multiplexing stage, M11 and M12 both provide high voltage signals, T1, T2, T5, and T6 are all turned on, S1 is connected to D1, S2 is connected to D2, and data voltage is provided to D1 through S1 and to D2 through S2; S3 is connected to D5, S4 is connected to D6, and data voltage is provided to D5 through S3 and to D6 through S4;

[0133] In the second multiplexing stage, M13 and M14 both provide high voltage signals, T3, T4, T7 and T8 are all turned on, S1 is connected to D3, S2 is connected to D4, and data voltage is provided to D3 through S1, and data voltage is provided to D4 through S2; S3 is connected to D7, S4 is connected to D8, and data voltage is provided to D7 through S3, and data voltage is provided to D8 through S4.

[0134] In at least one embodiment shown in FIG. 3A of the present disclosure, the number of transistors used is halved, and S1 drives D1 and D3, and S2 drives D2 and D4. When S1 provides a positive polarity data voltage, D1 and D3 provide a positive polarity data voltage, and when S2 provides a negative polarity data voltage, D2 and D4 provide a negative polarity data voltage, thereby achieving the purpose of having opposite polarities of the data voltages on the data lines adjacent to the pixel area.

[0135] FIG3B is a waveform diagram of a first control signal provided by M11 in at least one embodiment of the present disclosure;

[0136] FIG. 3C is a waveform diagram of a multiplexing control signal provided by a multiplexing control line in the related art.

[0137] Comparing FIG3B and FIG3C , the rise time and fall time of the first control signal provided by M11 are shorter, while in the related art, the rise time and fall time of the multiplexing control signal M1 provided by the multiplexing control line are longer.

[0138] In at least one embodiment of the present disclosure, the rise time of the first control signal provided by M11 can be 0.26μs, and the fall time of the first control signal provided by M11 can be 0.25μs. In the related art, the rise time of the multiplexed control signal M1 is 0.46μs, and the fall time of the multiplexed control signal M1 is 0.45μs. It can be seen from the above that in at least one embodiment of the present disclosure, the control signal is more beneficial to charging.

[0139] FIG. 4 is a layout diagram of at least one embodiment shown in FIG. 3A .

[0140] FIG. 5 is a layout diagram of the gate metal layer in FIG. 4 .

[0141] In Figure 5, the gate labeled G1 is T1, the gate labeled G2 is T2, the gate labeled G3 is T3, the gate labeled G4 is T4, the gate labeled G5 is T5, the gate labeled G6 is T6, the gate labeled G7 is T7, and the gate labeled G8 is T8.

[0142] FIG. 6 is a layout diagram of the semiconductor layer in FIG. 4 .

[0143] In FIG6 , A1 is the active pattern of T1, A2 is the active pattern of T2, A3 is the active pattern of T3, A4 is the active pattern of T4, A5 is the active pattern of T5, A6 is the active pattern of T6, A7 is the active pattern of T7, and A8 is the active pattern of T8.

[0144] FIG. 7 is a layout diagram of the source / drain metal layer in FIG. 4 .

[0145] In Figure 7, the source-drain pattern labeled SD1 is T1, the source-drain pattern labeled SD2 is T2, the source-drain pattern labeled SD3 is T3, the source-drain pattern labeled SD4 is T4, the source-drain pattern labeled SD5 is T5, the source-drain pattern labeled SD6 is T6, the source-drain pattern labeled SD7 is T7, and the source-drain pattern labeled SD8 is T8.

[0146] FIG. 8 is a layout diagram of the second conductive layer in FIG. 4 .

[0147] In Figure 4, the gate metal layer, the semiconductor layer, the source-drain metal layer and the second conductive layer can be arranged in sequence along the direction away from the substrate. A first conductive layer can be provided between the source-drain metal layer and the second conductive layer. The first conductive layer can be a common electrode layer of the entire layer; the second conductive layer can be a pixel electrode layer, and in the display area, the second conductive layer can include a pixel electrode; the first conductive layer and the second conductive layer can both be made of ITO (indium tin oxide), but are not limited to this.

[0148] In at least one embodiment of the present disclosure, a touch electrode layer may be further provided between the source / drain metal layer and the first conductive layer, but the present invention is not limited thereto.

[0149] The display device according to the embodiment of the present disclosure includes a data driver, a plurality of columns of data lines and the above-mentioned multiplexing module;

[0150] The data driver is used to provide a data voltage to the multiplexing module through a data voltage supply terminal;

[0151] The data line is used to receive the data voltage provided by the multiplexing module.

[0152] In an embodiment of the present disclosure, the display device may include a data driver and the multiplexing module described above, and the data driver provides a data voltage to a corresponding data line for the multiplexing resistor via a data voltage supply terminal.

[0153] Optionally, the data driver provides a control signal to each of the control lines through at least one corresponding output channel, so as to enhance the driving capability of each control line.

[0154] In at least one embodiment of the present disclosure, the display device includes a display panel, a data driver, and a plurality of control lines;

[0155] The data driver is disposed on a first side of the display panel, and the plurality of control lines are disposed between the data driver and an effective display area of ​​the display panel;

[0156] The data driver is further configured to provide a control signal input to the control line.

[0157] In a specific implementation, the display device may include only one data driver, and the control line may be provided between the data driver and the effective display area of ​​the display panel, and the data driver provides a control signal to the control line.

[0158] Optionally, the control line includes a first end and a second end;

[0159] The first output channel of the data driver is electrically connected to the first end, and the second output channel of the data driver is electrically connected to the second end. The data driver is used to provide a control signal to the first end through the first output channel and to provide a control signal to the second end through the second output channel.

[0160] In a specific implementation, when the display device includes a data driver, the data driver can be electrically connected to the first end of the control line through an output channel, and electrically connected to the second end of the control line through another output channel, and provide a control signal to the control line through the first end and the second end respectively to enhance the driving capability of the control line.

[0161] In one embodiment of the present disclosure, when the display panel is a display product with a resolution of 1200×2000, the display panel includes 2000 rows of pixel circuits, and the number of data lines included in the display panel is 3600 columns. If one data voltage supply end of the data driver drives two columns of data lines, one data driver is required; in this case, the data driver can be electrically connected to the first end of the control line through an output channel, and electrically connected to the second end of the control line through another output channel, so as to improve the driving capability of the control line.

[0162] As shown in FIG9 , the area labeled A0 is the effective display area, and the area labeled SI is the data driver;

[0163] The line marked M11 is the first control line;

[0164] The data driver SI is disposed below A0, and the first control line M11 is disposed between the data driver SI and the effective display area A0;

[0165] The data driver SI is electrically connected to the first end of the first control line M11 through the first output channel CH1 located on the left side thereof;

[0166] The data driver SI is electrically connected to the second end of the first control line M11 through the second output channel CH2 located on the right side thereof;

[0167] Both ends of the first control line M11 are driven simultaneously.

[0168] In at least one embodiment of the present disclosure, the second control line M12 , the third control line M13 , and the fourth control line M14 may be driven in the same manner as the first control line M11 , and all may be driven simultaneously from both ends of the line.

[0169] In at least one embodiment of the present disclosure, the display device includes a display panel, at least two data drivers, and a plurality of control lines;

[0170] The data driver is disposed on a first side of the display panel, and the plurality of control lines are disposed between the data driver and an effective display area of ​​the display panel;

[0171] The data driver is further configured to provide a control signal input to the control line.

[0172] In a specific implementation, when the display device includes at least two data drivers, the control line may be provided between the data driver and the effective display area of ​​the display panel, and the data driver provides a control signal input to the control line.

[0173] In at least one embodiment of the present disclosure, the control line is electrically connected to the at least two data drivers through at least three access points, and is configured to receive a control signal provided by the data drivers.

[0174] In a specific implementation, the control line can be electrically connected to the at least two data drivers through at least three access points to receive a control signal, which can further enhance the driving capability of the control line.

[0175] Optionally, the display device includes a first data driver and a second data driver;

[0176] The first output channel of the first data driver is electrically connected to the first end of the control line, and the first output channel of the second data driver is electrically connected to the second end of the control line;

[0177] The second output channel of the first data driver and the second output channel of the second data driver are both electrically connected to the middle node of the control line;

[0178] The first data driver is configured to provide a control signal to the control line through a first output channel and a second output channel thereof;

[0179] The second data driver is configured to provide a control signal to the control line through a first output channel and a second output channel thereof.

[0180] In a specific implementation, for a display panel with a resolution of 1840×2944, the number of rows of pixel circuits included in the display panel is 1840 rows, the number of data lines included in the display panel is 8832 columns, and a driving architecture that uses one data voltage supply terminal to drive two columns of data lines requires 4416 data voltage supply terminals; the number of channels of each data driver is 2400, so two data drivers are required.

[0181] As shown in FIG10 , the effective display area is labeled A0, the first data driver is labeled SI1, the second data driver is labeled SI2, and the first control line is labeled M11.

[0182] The first control line M11 is provided between the data driver and the effective display area A0;

[0183] The first output channel CH11 of the first data driver SI1 is electrically connected to the first end of the first control line M11, and the first output channel CH21 of the second data driver SI2 is electrically connected to the second end of the first control line M11;

[0184] The second output channel CH12 of the first data driver SI1 and the second output channel CH22 of the second data driver SI2 are both electrically connected to the middle node N0 of the control line;

[0185] The first data driver SI1 provides a control signal to the first control line M11 through CH11 and CH12;

[0186] The second data driver SI2 provides a control signal to the first control line M11 through CH21 and CH22.

[0187] In specific implementation, the driving method of the second control line M12, the driving method of the third control line M13 and the driving method of the fourth control line M14 are the same as the driving method of the first control line M11. Each line is connected to the driving signal at three positions to further enhance the driving capability of each control signal.

[0188] FIG. 11 is a layout diagram of the middle portion of at least one embodiment shown in FIG. 10 , illustrating the connection relationship between the connection line between two data drivers and the middle nodes of each control line.

[0189] In FIG11 , M01 is a first connection line between the first source driver and the second source driver, M02 is a second connection line between the first source driver and the second source driver, M03 is a third connection line between the first source driver and the second source driver, and M04 is a connection line between the first source driver and the second source driver;

[0190] M01 is electrically connected to M11 through the first connection portion L1, M02 is electrically connected to M12 through the second connection portion L2, M03 is electrically connected to M13 through the third connection portion L3, and M04 is electrically connected to M14 through the fourth connection portion L4.

[0191] FIG12 is a layout diagram of the gate metal layer in FIG11 , where M01 , M02 , M03 , M04 , M11 , M12 , M13 , and M14 may all be formed in the gate metal layer.

[0192] FIG13 is a layout diagram of the source / drain metal layer in FIG11 .

[0193] FIG. 14 is a layout diagram of the second conductive layer in FIG. 11 , where L1 , L2 , L3 , and L4 may be formed.

[0194] The display device according to at least one embodiment of the present disclosure further includes a plurality of rows of gate lines and a plurality of rows and columns of pixel circuits;

[0195] The pixel circuits are electrically connected to corresponding row gate lines and corresponding column data lines respectively, and are used to control and receive data voltages provided by corresponding column data lines under the control of gate drive signals provided by corresponding row gate lines.

[0196] In a specific implementation, the display device may include multiple rows of gate lines and multiple rows and columns of pixel circuits. The pixel circuits receive data voltages provided by data lines under the control of gate drive signals.

[0197] The display device described in the embodiment of the present disclosure may be a TDDI product, but is not limited thereto. In actual operation, the display device may also be other types of display products.

[0198] The driving method described in the embodiment of the present disclosure is applied to the above-mentioned display device, and the driving method includes:

[0199] The data driver provides the data voltage to the multiplexing module through the data voltage supply terminal;

[0200] The data line receives the data voltage provided by the multiplexing module.

[0201] In at least one embodiment of the present disclosure, the display device further includes a plurality of rows of gate lines and two multiplexing control lines; a is a positive integer;

[0202] When the gate line in row 2a-1 is turned on, the first multiplexing control line first controls the corresponding multiplexing transistor to turn on, and then the second multiplexing control line controls the corresponding multiplexing transistor to turn on;

[0203] When the gate line in row 2a is turned on, the second multiplexing control line first controls the corresponding multiplexing transistor to turn on, and then the first multiplexing control line controls the corresponding multiplexing transistor to turn on.

[0204] Among them, the first multiplexing control line may include a first control line and a second control line, the second multiplexing control line may include a third control line and a fourth control line, the first control line and the second control line respectively control corresponding multiplexing transistors, and the third control line and the fourth control line respectively control corresponding multiplexing transistors.

[0205] In a specific implementation, when the odd-numbered row gate lines are turned on, the corresponding multiplexing transistors can be controlled to turn on through the first multiplexing control line, and then the corresponding multiplexing transistors can be controlled to turn on through the second multiplexing control line; after the even-numbered row gate lines are turned on, the corresponding multiplexing transistors can be controlled to turn on through the second multiplexing control line, and then the corresponding multiplexing transistors can be controlled to turn on through the first multiplexing control line. In this way, the frequency of the control signals on each multiplexing control line is low and the power consumption is small.

[0206] In at least one embodiment of the present disclosure, the display device further includes a plurality of rows of gate lines and two multiplexing control lines; a is a positive integer;

[0207] When the gate line of row 2a-1 is turned on, the second multiplexing control line first controls the corresponding multiplexing transistor to turn on, and then the first multiplexing control line controls the corresponding multiplexing transistor to turn on;

[0208] When the gate line in row 2a is turned on, the first multiplexing control line first controls the corresponding multiplexing transistor to turn on, and then the second multiplexing control line controls the corresponding multiplexing transistor to turn on.

[0209] Among them, the first multiplexing control line may include a first control line and a second control line, the second multiplexing control line may include a third control line and a fourth control line, the first control line and the second control line respectively control corresponding multiplexing transistors, and the third control line and the fourth control line respectively control corresponding multiplexing transistors.

[0210] In a specific implementation, when the odd-numbered row gate lines are turned on, the corresponding multiplexing transistors can be controlled to turn on through the second multiplexing control line, and then the corresponding multiplexing transistors can be controlled to turn on through the first multiplexing control line; after the even-numbered row gate lines are turned on, the corresponding multiplexing transistors can be controlled to turn on through the first multiplexing control line, and then the corresponding multiplexing transistors can be controlled to turn on through the second multiplexing control line. In this way, the frequency of the control signals on each multiplexing control line is low and the power consumption is small.

[0211] As shown in FIG15 , the first multiplexing control line includes a first control line M11 that controls the first transistor T1 , and the second multiplexing control line includes a third control line M13 that controls the third transistor T3 ;

[0212] The terminal labeled S1 is a first data voltage supply terminal;

[0213] The pixel circuit labeled P11 is the first row and first column, and the pixel circuit labeled P13 is the first row and third column;

[0214] P11 and P13 are both electrically connected to the first row gate line GT1, P11 is electrically connected to the first column data line D1, and P13 is electrically connected to the third column data line D3;

[0215] The pixel circuit labeled P21 is the second row and first column, and the pixel circuit labeled P23 is the second row and third column;

[0216] P21 and P23 are both electrically connected to the second row gate line GT2, P21 is electrically connected to the first column data line D1, and P23 is electrically connected to the third column data line D3;

[0217] The pixel circuit labeled P31 is the third row and first column, and the pixel circuit labeled P33 is the third row and third column;

[0218] P31 and P33 are both electrically connected to the third row gate line GT3, P31 is electrically connected to the first column data line D1, and P33 is electrically connected to the third column data line D3.

[0219] When at least one embodiment shown in FIG. 15 is in operation, when driving the first row of pixel circuits,

[0220] As shown in FIG16 , the potential of the first gate drive signal output by GT1 first rises from a low voltage to a high voltage. Then, the control signal output by M11 rises from a low voltage to a high voltage. T1 is turned on to write the data voltage provided by S1 to the first column data line D1. When the potential of the first gate drive signal is a high voltage, P11 receives the data voltage provided by D1.

[0221] As shown in FIG17 , the potential of the first gate drive signal output by GT1 first rises from a low voltage to a high voltage. Then, the control signal output by M13 rises from a low voltage to a high voltage. T3 is turned on to write the data voltage provided by S1 to the third column data line D3. When the potential of the first gate drive signal is a high voltage, P13 receives the data voltage provided by D3.

[0222] T1 and T3 are n-type transistors.

[0223] In specific implementation, at least one embodiment shown in FIG. 15 can be driven in a bow shape during operation, that is, as shown in FIG. 18 ,

[0224] GT1 is turned on first. Then, in the first time period P1, M11 outputs a high voltage signal. M11 first controls T1 to turn on and writes the data voltage to P11. Then, in the second time period P2, M13 outputs a high voltage signal. M13 controls T3 to turn on and writes the data voltage to P13.

[0225] After that, GT2 is turned on, and then in the third time period P3, M13 outputs a high voltage signal, M13 first controls T3 to turn on, and writes the data voltage to P23. Then in the fourth time period P4, M11 outputs a high voltage signal, and M11 controls T1 to turn on, and writes the data voltage to P21.

[0226] Afterwards, GT3 is turned on, and then in the fifth time period P5, M11 outputs a high voltage signal, M11 first controls T1 to turn on, and writes the data voltage to P31, and then in the sixth time period P6, M13 outputs a high voltage signal, and M13 controls T3 to turn on, and writes the data voltage to P33.

[0227] FIG. 18 is an operation timing diagram of at least one embodiment shown in FIG. 15 .

[0228] As shown in FIG18 , the frequencies of the control signals provided by M11 and M13 are relatively low, which is beneficial to reducing power consumption.

[0229] In at least one embodiment of the present disclosure, the width-to-length ratio of each multiplexing transistor may be greater than or equal to 50 and less than or equal to 100, but is not limited thereto.

[0230] The above is a preferred embodiment of the present disclosure. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the principles described in the present disclosure. These improvements and modifications should also be regarded as the scope of protection of the present disclosure.

Claims

1. A multiplexing circuit, electrically connected to M data voltage supply terminals and a plurality of column data lines, respectively, the multiplexing circuit comprising N multiplexing control lines and N multiplexing circuits, the nth multiplexing circuit comprising M multiplexing sub-circuits; the nth multiplexing control line comprising M control lines; The mth multiplexing sub-circuit included in the nth multiplexing circuit is electrically connected to the mth control line, the mth data voltage supply terminal and the corresponding data line included in the nth multiplexing control line, respectively, and is used to write the data voltage provided by the mth data voltage supply terminal into the corresponding data line under the control of the control signal provided by the mth control line; Both N and M are integers greater than 1, n is a positive integer less than or equal to N, and m is a positive integer less than or equal to M.

2. The multiplexing circuit as claimed in claim 1, wherein: The multiplexing circuit includes a first multiplexing control line, a second multiplexing control line, a first multiplexing circuit and a second multiplexing circuit; The first multiplexed control line includes a first control line and a second control line; the second multiplexed control line includes a third control line and a fourth control line; The first multiplexing circuit includes a first multiplexing sub-circuit and a second multiplexing sub-circuit; the second multiplexing circuit includes a third multiplexing sub-circuit and a fourth multiplexing sub-circuit; The first multiplexing subcircuit is electrically connected to the first control line, the first data voltage supply terminal and the first column data line respectively, and is used to write the data voltage provided by the first data voltage supply terminal into the first column data line under the control of the first control signal provided by the first control line; The second multiplexing subcircuit is electrically connected to the second control line, the second data voltage supply terminal and the second column data line respectively, and is used to write the data voltage provided by the second data voltage supply terminal into the second column data line under the control of the second control signal provided by the second control line; The third multiplexing sub-circuit is electrically connected to the third control line, the first data voltage supply terminal and the third column data line respectively, and is used to write the data voltage provided by the first data voltage supply terminal into the third column data line under the control of the third control signal provided by the third control line; The fourth multiplexing sub-circuit is electrically connected to the fourth control line, the second data voltage supply terminal and the fourth column data line respectively, and is used to write the data voltage provided by the second data voltage supply terminal into the fourth column data line under the control of a fourth control signal provided by the fourth control line.

3. The multiplexing circuit as claimed in claim 2, wherein: The first multiplexing subcircuit includes a first transistor, and the second multiplexing subcircuit includes a second transistor; The gate of the first transistor is electrically connected to the first control line, the first electrode of the first transistor is electrically connected to the first data voltage supply terminal, and the second electrode of the first transistor is electrically connected to the first column data line; A gate of the second transistor is electrically connected to the second control line, a first electrode of the second transistor is electrically connected to the second data voltage supply terminal, and a second electrode of the second transistor is electrically connected to the second column data line.

4. The multiplexing circuit as claimed in claim 3, wherein: The first transistor and the second transistor are both n-type transistors; or, the first transistor and the second transistor are both p-type transistors.

5. The multiplexing circuit as claimed in claim 2, wherein: The third multiplexing sub-circuit includes a third transistor, and the fourth multiplexing sub-circuit includes a fourth transistor; The gate of the third transistor is electrically connected to the third control line, the first electrode of the third transistor is electrically connected to the first data voltage supply terminal, and the second electrode of the third transistor is electrically connected to the third column data line; A gate of the fourth transistor is electrically connected to the fourth control line, a first electrode of the fourth transistor is electrically connected to the second data voltage supply terminal, and a second electrode of the fourth transistor is electrically connected to the fourth column data line.

6. The multiplexing circuit as claimed in claim 5, wherein: The third transistor and the fourth transistor are both n-type transistors; or, the third transistor and the fourth transistor are both p-type transistors.

7. A multiplexing module, comprising a plurality of multiplexing circuits according to any one of claims 1 to 6.

8. A display device comprising a data driver, a plurality of columns of data lines and the multiplexing module as claimed in claim 7; The data driver is used to provide a data voltage to the multiplexing module through a data voltage supply terminal; The data line is used to receive the data voltage provided by the multiplexing module.

9. The display device according to claim 8, wherein: The data driver provides a control signal to each control line through at least one corresponding output channel.

10. The display device according to claim 8, wherein: The display device includes a display panel, a data driver and a plurality of control lines; The data driver is disposed on a first side of the display panel, and the plurality of control lines are disposed between the data driver and an effective display area of ​​the display panel; The data driver is further configured to provide a control signal input to the control line.

11. The display device according to claim 10, wherein: The control line includes a first end and a second end; The first output channel of the data driver is electrically connected to the first end, and the second output channel of the data driver is electrically connected to the second end. The data driver is used to provide a control signal to the first end through the first output channel and to provide a control signal to the second end through the second output channel.

12. The display device according to claim 9, wherein: The display device includes a display panel, at least two data drivers and a plurality of control lines; The data driver is disposed on a first side of the display panel, and the plurality of control lines are disposed between the data driver and an effective display area of ​​the display panel; The data driver is further configured to provide a control signal input to the control line.

13. The display device according to claim 12, wherein: The control line is electrically connected to the at least two data drivers through at least three access points, and is used to receive a control signal provided by the data driver.

14. The display device according to claim 13, wherein: The display device includes a first data driver and a second data driver; The first output channel of the first data driver is electrically connected to the first end of the control line, and the first output channel of the second data driver is electrically connected to the second end of the control line; The second output channel of the first data driver and the second output channel of the second data driver are both electrically connected to the middle node of the control line; The first data driver is used to provide a control signal to the control line through its first output channel and its second output channel; The second data driver is used to provide the The control line provides the control signal.

15. The display device according to any one of claims 8 to 14, wherein: Also includes a plurality of rows of gate lines and a plurality of rows and columns of pixel circuits; The pixel circuit is electrically connected to the corresponding row gate line and the corresponding column data line respectively, and is used for controlling and receiving the data voltage provided by the corresponding column data line under the control of the gate driving signal provided by the corresponding row gate line.

16. A driving method, applied to the display device according to any one of claims 8 to 15, the driving method comprising: The data driver provides a data voltage to the multiplexing module through a data voltage supply terminal; The data line receives the data voltage provided by the multiplexing module.

17. The driving method according to claim 16, wherein: The display device further comprises a plurality of rows of gate lines and two multiplexing control lines; a is a positive integer; When the gate line of row 2a-1 is turned on, the first multiplexing control line first controls the corresponding multiplexing transistor to turn on, and then the second multiplexing control line controls the corresponding multiplexing transistor to turn on; When the gate line in row 2a is turned on, the second multiplexing control line first controls the corresponding multiplexing transistor to turn on, and then the first multiplexing control line controls the corresponding multiplexing transistor to turn on.

18. The driving method according to claim 16, wherein: The display device further comprises a plurality of rows of gate lines and two multiplexing control lines; a is a positive integer; When the gate line of row 2a-1 is turned on, the second multiplexing control line first controls the corresponding multiplexing transistor to turn on, and then the first multiplexing control line controls the corresponding multiplexing transistor to turn on; When the gate line in row 2a is turned on, the first multiplexing control line first controls the corresponding multiplexing transistor to turn on, and then the second multiplexing control line controls the corresponding multiplexing transistor to turn on.

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