Systems and methods for automatic absolute timing in distributed clock systems using precision time synchronizing combined with reference propagation-based time drift correction

Abstract

An example includes a master device having a master clock and transmitting to a slave device a synchronization (SYNC) signal and master time stamp. The slave device, having a slave clock, transmits a request to the master device which responds with a reply with a master subsequent time stamp. The slave device, using the master time stamps and slave device time stamps, calculates an offset between the master and slave clocks, and using the offset adjusts the slave clock. In an example the slave device is arranged with a stable propagation path from the master device. The master device transmits over the propagation path a succession of reference signals, at times synched to the master clock, each carrying information from which the slave device detects reference signal arrival times. Using the arrival times the slave device detects time drift of the slave clock relative to the master clock, and in response performs time shift correction.

Description

[0001] SYSTEMS AND METHODS FOR AUTOMATIC ABSOLUTE TIMING IN DISTRIBUTED CLOCK SYSTEMS USING PRECISION TIME SYNCHRONIZING COMBINED WITH REFERENCE PROPAGATION-BASED TIME DRIFT CORRECTION

[0002] TECHNICAL FIELD

[0003] The present disclosure relates generally to clock synchronization, and, more particularly, to providing absolute timing to systems of distributed, untethered clocks, through protocol based synchronization combined with reference propagation- based correction of time-drifts.

[0004] BACKGROUND

[0005] Various systems utilize a plurality of devices, such as but not limited to measurement devices, which must be spaced apart, e.g., spatially distributed or capable of being spatially distributed, with each device performing clocked operations using the device’s local clock oscillator. In many of such applications, the local clocks, due to various resource constraints, are in an untethered arrangement, i.e., have no timing cable connecting the local clocks together. Notwithstanding the clocks being untethered, many applications require the clocks be synchronous with one another in order for the system to perform its intended function. The required “synchronization” can include not only frequency and phase but also absolute timing, i.e., a requirement that all the devices generate, synchronously, the very same absolute time stamp (TS) sequence, e.g., TS(1), TS(2), ..., etc.

[0006] There are various technical shortcomings, though, in current techniques directed to providing such absolute timing in distributed clock systems.

[0007] For example, use of timing signals from Global Positioning Satellite (GPS) system is a known technique directed to synchronizing distributed clocks. However, GPS has shortcomings related to such use. One is that GPS signals often do not adequately penetrate buildings and other structures and therefore may not work well in urban or suburban settings. Also, anomalies in the ionosphere and troposphere can induce delays in GPS signal propagation, which can be substantial, e.g., several to tens of nanoseconds or more, and time varying. For at least these example reasons, GPS may not be an acceptable synchronization signal source in various applications using a plurality of clocks distributed among spatially separated devices. Another shortcoming, for example in certain known master-slave synchronization techniques, is an accumulating time shift between the slave clocks and the master clock, which can arise from the non-trivial time occupied, e.g., by the master-slave inter-communications and internal processing operations during each of the successive instances of the synchronization process.

[0008] SUMMARY

[0009] Systems and methods according to one or more embodiments can provide a low complexity, flexible, reliable, low cost technical solution to the current GPS signal based clock synchronization technique’s susceptibility to GPS signal availability and anomalies.

[0010] Systems and methods according to one or embodiments can also provide, while maintaining low complexity and low cost, a practical, stable and reliable technical solution to the problem of accumulating time shift between slave clocks and the master clock.

[0011] According to one or more embodiments one example system for successively synchronizing, and time drift correcting multiple clocks can comprise a first device that can have a first clock configured to generate a first clock signal and a synchronization (SYNC) signal and can include a first device data processor, communicatively coupled to the first clock and to a first device SYNC transceiver and to a first device transmitter (TX) that can be wireless. An example system, in one or more embodiments, can further comprise a second device, which can be spatially separated from the first device at a location wherein the environment provides a stable RF propagation path from the first device to the second device. In an example system according to one or more embodiments, the second device can include a second clock configured to generate a second clock signal and that can be communicatively coupled to a second device data processor that can be coupled to a second device SYNC transceiver and to a second device receiver (RX). In an example system according to one or more embodiments,, the first device data processor can be further configured to initiate, responsive to the SYNC signal, a synchronization process that can be configured to detect a clock offset, at the second device, between the second clock signal and the first clock signal and the synchronization process can comprise communications between the first device data processor and the second device data processor via the first device SYNC transceiver and the second device SYNC transceiver. According to various embodiments, in an example system the second device data processor can be further configured to cause the second clock to adjust a second clock frequency or second clock phase in accordance with the detected clock offset. In an example system according to one or more embodiments, the first device data processor can be further configured to cause the first device TX to transmit a succession of instances of a reference (REF) signal for reception by the second device RX, over the stable propagation path from the first device TX to the second device RX. In an example system according to one or more embodiments the second device data processor can be further configured to detect, based on processing of the second device RX receptions of the succession of instances of the REF signal, a time drift of the second clock signal relative to the first clock signal, and to perform a correcting time shift of the second clock based on the detected time drift.

[0012] According to one or more embodiments one example method for successively synchronizing, and time drift correcting of multiple, spatially separated clocks can include steps comprising generating in a first device, positioned at a first location in an environment, a first clock signal and a synchronization (SYNC) signal. In one example method according to one or more embodiments steps can further comprise generating in a second device a second clock signal, wherein the second device can be positioned at a second location in the environment, spatially separated from the first location, and the first location and the second location can be respectively positioned in the environment such that a stable propagation path is provided from the first location to the second location. In one example method according to one or more embodiments, steps can further comprise the first device initiating, responsive to or associated with the SYNC signal, a synchronization process that can be performed by the first device and the second device, and can be configured to detect at the second device a clock offset between the second clock signal and the first clock signal. According to one or more embodiments, in one example method, the synchronization process can include steps comprising the first device communicating first device time stamp information to the second device and the second device determining the clock offset based at least in pail on the first device time stamp information, and a step comprising the second device causing the second clock to adjust a second clock frequency or a second clock phase, or both, in accordance with the detected clock offset. According to one or more embodiments, in one example method, steps can further comprise the first device transmitting a succession of instances of a reference (REF) signal for reception by the second device, over the stable propagation path from the first device to the second device, and the second device performing steps comprising detecting, based on a receiving of the succession of instances of the REF signal, a time drift of the second clock signal relative to the first clock signal, and performing a correcting time shift of the second clock based on the detected time drift.

[0013] This Summary is provided to introduce examples of disclosed concepts in simplified form. The introduced examples, and further examples are described in more detail in the Detailed Description below. It will be understood that this Summary is not intended to indicate key features or essential features of the claimed subject matter.

[0014] BRIEF DESCRIPTION OF THE DRAWINGS

[0015] A further understanding of the nature and advantages of the embodiments may be realized by reference to the following drawings. It will be understood that the drawings show illustrative, not limitative examples. It will also be understood that drawing graphics are scaled for readability and therefore various functions and features are not necessarily drawn to a scale consistent with physical implementations, Further, in the drawings similar components or features may have the same reference label.

[0016] Fig. 1 shows a functional block schematic of one implementation for one system for automatic absolute timing in distributed untethered clocks using a combination of precision time synchronization and reference propagation based time drift correction in accordance with one or more embodiments.

[0017] Fig. 2 shows a high level flow diagram of example operations in one example process for successive precision time synchronization in a combination method for automatic absolute timing in distributed untethered clocks using a combination of successive precision time synchronization and reference propagation based time drift correction in accordance with various embodiments.

[0018] Fig. 3 shows one example operational step flow in one arrangement of a precision time protocol (PTP) synchronization process in accordance with various embodiments.

[0019] Fig. 4 shows a high level flow diagram of example operations in one example process for successive reference propagation path based time drift correction in a combination method for automatic absolute timing in distributed untethered clocks using a combination of successive precision time synchronization and reference propagation path based time drift correction in accordance with various embodiments. Fig. 5 shows a functional block schematic of one example implementation of one system for automatic absolute timing in distributed untcthcrcd clocks using a combination of wireless precision time synchronization and reference propagation based time drift compensation in accordance with one or more embodiments.

[0020] Fig. 6 shows a functional block schematic of one implementation of one sliding correlator channel sounder system providing multipath channel sounding with a combination of wireless link based precision time synchronization and reference propagation based time drift correction in accordance with various embodiments.

[0021] Fig. 7 shows a high level operation flow diagram of operations in one example process for implementing the Algorithm 1 reference propagation based method for successive time drift correction in accordance with various embodiments.

[0022] Fig. 8 shows a functional block schematic of one implementation of one sliding correlator channel sounder system providing multipath channel sounding with a combination of cablebased precision time synchronization and reference propagation path based time drift correction in accordance with various embodiments.

[0023] Fig. 9 shows a functional block schematic of one implementation of one system for applications comprising, for example, modular test and measurement equipment to provide, among other technical features, phase synchronization between a main instrument and remote extenders in accordance with various embodiments.

[0024] Fig. 10 shows a functional block schematic of one alternative implementation of one system for applications comprising, for example, modular test and measurement equipment to provide, among other features, phase synchronization between a main instrument and remote extenders in accordance with various embodiments.

[0025] Fig. 11 shows a functional block schematic of one implementation of one example system according to one or more embodiments for using PTP over wireless links along with algorithm 1 and algorithm 2 to achieve, for example and without limitation, phase synchronization and elimination of clock drift.

[0026] Fig. 12 shows a functional block schematic of one implementation of one system, in a non-limiting illustrative operating state, providing time synchronization of unmanned aerial vehicle (UAV) clocks in a dynamic distributed network of UAV s, for accurate localization and positioning of UAVs.. Fig. 13 shows a functional block schematic of one master device computer system configured to perform various master device precision time synchronization and reference propagation path based time drift correction operations and processes in accordance with the disclosed embodiments.

[0027] Fig. 14 shows a functional block schematic of one slave device computer system configured to perform various clock device precision time synchronization and reference propagation path based time drift correction operations and processes in accordance with the disclosed embodiments.

[0028] While the embodiments described herein are susceptible to various modifications and alternative forms, specific embodiments have been shown by way of example in the drawings and will be described in detail herein. However, the exemplary embodiments described herein are not intended to be limited to the particular forms disclosed. Rather, the instant disclosure covers all modifications, equivalents, and alternatives falling within the scope of the appended claims.

[0029] DETAILED DESCRIPTION

[0030] Methods according to one or more embodiments described herein for successively synchronizing and time drift correcting of multiple, spatially separated clocks can be implemented in a system comprising, for example, a first device positioned at a first location in an environment, and a second device positioned at a second location in the environment, spatially separated from the first location. According to one or more embodiments the first location and the second location can be respectively positioned in the environment such that a stable propagation path is provided from the first location to the second location. As described in more detail in subsequent sections, according to one or more embodiments the stable RF propagation path can be, but is not limited to being, one stable RF path among multiple RF paths from the first location to the second location. The stable RF path can be, for example and without limitation, a path having one strong reflector or can be a direct path from the first location to the second location.

[0031] An example implementing system can include in the first device an RF transmitter (TX) configured to a transmit a radio frequency (RF) signal over the stable RF propagation path through the environment to the second device at the second location. In an example implementing system the first device can further include a first device clock oscillator that can be configured to feed a first device clock configured to generate a first clock signal. In an example implementing system the second device can further include a second device clock oscillator that can be configured to feed a second device clock configured to generate a second clock signal.

[0032] An example implementing system according to one or more embodiments can further include in the first device a first programmable data processor communicatively coupled to the TX and to a first synchronization transceiver, and in the second device a second programmable data processor that can be communicatively coupled to the RX and to a second synchronization transceiver. In an example implementing system according to one or more embodiments the first programmable data processor can also be communicatively coupled to a first instruction memory and can be clocked by the first clock signal, and the second programmable data processor can be communicatively coupled to a second instruction memory and can be clocked by the second clock signal.

[0033] In an example implementing system according to one or more embodiments the first programmable data processor can be so configured for example and without limitation by processor-executable instructions stored in the first instruction memory, to selectively cause the first synchronization transceiver to transmit a clock synchronization initiation signal toward the second device. In an example implementing system according to one or more embodiments the first programmable data processor and the second programmable data processor can be further configured to mutually perform a clock synchronization process, by steps starling with the second programmable data processor, in response to receiving the clock synchronization initiation signal, causing the second synchronization transceiver to transmit a clock synchronization process response signal toward the second device.

[0034] The clock synchronization process can be configured, as described in more detail in later sections of this written description, to provide the second programmable data processor with sufficient information to determine, at the second device, an offset between the second clock and the first clock, and to correspondingly adjust, based on the determined offset, a frequency and / or a phase of the second clock, e.g., by generating and injecting into the second clock a second clock synchronization signal.

[0035] According to one or more embodiments, by adjustments comprising for example appropriate configuring of the processor-executable instructions stored in the first instruction memory and the processor-executable instructions stored in the second instruction memory, the first programmable data processor and the second programmable data processor can be further configured to perform the clock synchronization process in accordance with the Precision Time Protocol (PTP) wherein the first clock is a master clock, and the second clock is a slave clock. Example implementations according to such configuration are described in more detail later in this disclosure, e.g., in reference to Fig. 5 and Fig. 6.

[0036] For certain applications, notwithstanding the substantial technical benefits of the successive precision synchronization, over a time interval a time shift may accumulate between the slave clocks and the master clock. This can arise from time durations that may be occupied, e.g., in certain hardware implementations in the context of certain applications, by the masterslave inter-communications and internal processing operations during each of the successive instances of the PTP synchronization process.

[0037] Systems and methods according to one or more further embodiments can provide, among other features and benefits, a practical, effective, low cost technical solution to such accumulating time shift, by a combining of the successive precision synchronization embodiments with reference propagation-based time shift correction according to one or more embodiments.

[0038] In example systems and methods according to one or more further embodiments implementation of reference propagation-based time shift correction in combination with the successive precision synchronization can comprise adding to the first device a capability, e.g., by further configuring the first programmable data processor to control the first device TX to successively transmit reference signal that is configured, e.g., by modulating a transmitted RF signal to arrive at the second device with a time varying waveforms that can enable the second device to detect time of arrival of the waveform, relative to the second clock signal. One example implementation by which the second device can perform such detecting by configuring the second programmable data processor to perform a correlation of the received RF waveform that can include detecting a correlation peak from sliding a matching template, wherein “matching” can mean the template matches the time varying waveform of the reference signal over a demodulation of the received RF signal, matching template, a time of arrival relative to the time for the receiving. It will be understood that as used herein the term ‘clock’ can encompass clock devices, apparatuses, or units or equivalents thereof and can encompass periodic signals comprising digital signals or analog signals, for example and without limitation, impulses, time or frequency waveform shapes that are disclosed, explicitly or implicitly, as causing or triggering operations, actions, or events such as but not limited to, digital or analog state changes or state refreshments, and / or as providing, or functioning as, or being used as periodic time references or reference points.

[0039] For further illustration, example implementations of several alternative embodiments are described in more detail in paragraphs below.

[0040] Example System for Synchronized Untethered Clocks Via Successive PTP Combined With Successive Reference Propagation Path Based Time Drift Correction

[0041] Fig. 1 shows a functional block schematic of one implementation for one example system 100 for automatic absolute timing in distributed untethered clocks using a combination of precision time synchronization and reference propagation path based time drift correction in accordance with one or more embodiments.

[0042] The example system 100 includes a master device 102 positioned at a first location in an environment, and a second device 104 positioned at a second location in the environment, spatially separated from the first location. The example system 100 can include in the master device 102 a master device oscillator 106 configured to generate a master oscillator signal (labeled in Fig. 1 as “MO signal”) and feed the MO signal to a master device processor clock 108 that can be configured to generate a master clock signal (labeled in Fig. 1 as “MCK”). In the example system 100 the master device 102 can further include a master device processor 110, which can be clocked by MCK and can be communicatively coupled to and configured to control operation(s) of a master device transmitter (hereinafter alternatively referred to as “master TX 112 and a master reference signal generator 114 that can feed signals to the master TX 112. Example processes and operations in processes of master device processor 110 control of operation(s) of the master TX 112 and the master reference signal generator 114 are described in more detail in subsequent paragraphs.

[0043] Continuing to refer to Fig. 1, the example system 100 can further include in the master device 102 a master device time stamp 116 and a master clock synchronization (labeled as “SYNC” on Fig. 1) signal generator 118 , each communicatively coupled to and therefore controllable by the master device processor 110. According to various embodiments the master device 102 can also include a master device synchronization transceiver 120 having a master device synchronization transmitter 120T and a master device synchronization receiver 120R. The example system 100 can further include in the slave device 104 a slave device oscillator 124 configured to generate slave oscillator signal and feed the slave oscillator signal to a slave device processor clock 126 that can be configured to generate a slave clock signal. In the example system 100 the slave device 104 can further include a slave device processor 128, which can be clocked by slave device clock and can be communicatively coupled to and configured to receive and control certain operations of a slave device receiver 130, e.g., a wireless RF receiver with superheterodyne down-converting capabilities (hereinafter alternatively referred to as “slave RX 130. Example processes and operations of the slave device processor 128 are described in more detail in subsequent paragraphs.

[0044] The example system 100 can further include in the slave device 104 a slave device time stamp 134 and a slave clock synchronization signal generator 136 , each communicatively coupled to and therefore controllable by the slave device processor 128. According to various embodiments the slave device 104 can also include a slave device synchronization transceiver 138 having a slave device synchronization transmitter 138T and a slave device synchronization receiver 138R

[0045] It will be understood that Fig. 1 is a functional block schematic wherein blocks represent functionalities, and do not imply or limit hardware implementations to including a separate, individual hardware unit or structure corresponding to each block. For example, one implementation of the master device processor 110 can be, for example and without limitation, a hardware processing resource having processing capability to perform all functions, e.g., all processing, monitoring, receiving, and controlling functions and operations described herein as performed by the master device processor 110 and perform the signal generating functions and operations disclosed herein, explicitly or implicitly, as performed by the master reference signal generator 114. Such implementations of the master device processor 110 can comprise, as described in more detail later in this disclosure, e.g., in reference to Fig 14, one or more digital processor units communicatively coupled, e.g., by a master device instruction storage that stores processor executable instructions that cause the one or more digital processor units to perform the processes and operations described as performed by the master device processor 110, e.g., control of operation(s) of the master TX 112, the master reference signal generator 114.

[0046] Fig. 2 shows a high level flow diagram 200 of example operations in one example successive precision time protocol (PTP) synchronization process in a method for automatic absolute timing in distributed untethered clocks using a combination of successive precision time synchronization and successive reference propagation path based time drift correction in accordance with various embodiments.

[0047] Operation flow in accordance with the Fig. 2 diagram 200 can include the master device processor 110 causing the master device SYNC TX 120T to transmit the SYNC signal, for reception by the slave device SYNC RX 138R and, using for example the master device time stamp 116, transmit in association with the SYNC a master device time, a master device first time stamps indicating a time, in terms of the master device time stamps, of transmitting the SYNC. Operations according to the flow 200 can proceed from the transmitting at 202 to the slave device processor 128 causing the slave device SYNC TX 138T to transmit for reception by the master device SYNC RX 120R, a delay request. Details of the delay request and of slave processor operations, e.g., slave device time stamping operations, associated with transmitting the delay request are described in more detail in subsequent paragraphs, e.g., in reference to Fig. 3. Details of the master device transmitting, in step 206, the delay reply for reception by the slave device SNC RX 138R, are also described in more detail in reference to Fig. 3. Operations according to the flow can proceed from the slave device receiving the delay reply to the slave device, based at least in part on the master device stamps associated with the SYNC signal and the master device’s relay reply, detecting clock offset, at the slave device, between the slave clock and the master clock. The offset, in some embodiments, can be between the slave clock signal and the master clock signal, or between the slave time stamps and the master time stamps, or both.

[0048] Fig. 3 shows one example operational step flow in one arrangement of a precision time protocol (PTP) synchronization process in accordance with various embodiments. Operations and progression of operation according to the flow 300 can include the master device recording a timestamp, which can be referred to as a master device first time stamp (visible in Fig. 3 as T}M, with the M superscript indicating “master device” and the subscript indicating the time stamp position among the master device time stamps.) In the Fig. 3 example the master device first time stamp T“is 83 seconds (visible as “83 5”). . Upon receiving it 2 s later, the slave also records a timestamp (Ts- 835) and waits for a ‘Follow-up’ packet. After clock cycles, master processor transmits TMthe Follow up packet; When received, the slave processor device calculates TM- Tsand adds it to its current time. This partial correction adjusts the slave clock from 86s to 104s in Fig.3, but is missing a propagation delay component (here, 2 s). Hence, the slave records TS = 108s timestamp and sends out a ‘Delay-request’. The master records TM = 112s and sends back a ‘Delayreply’ with TM . Assuming a reciprocal channel where Delay-request and Delay-reply propagate in equal duration, the propagation delay is calculated as (TM -TS) / 2 and added to the slave time to achieve synchronization at 117 s.

[0049] Fig. 4 shows a high level flow diagram 400 of example operations in one example process for successive reference propagation path based time drift correction in a combination method for automatic absolute timing in distributed untethered clocks using a combination of successive precision time synchronization and reference propagation path based time drift correction in accordance with various embodiments.

[0050] The process can comprise the master device transmitting the succession of instances of the REF signal by successively generating a first device pseudorandom (PN) bit sequence, modulating a radio frequency (RF) carrier by the successively generated PN bit sequence to generate a successively PN modulated RF earner, and transmitting, as the succession of instances of the REF signal, the successively PN modulated RF carrier via the first device TX. And the slave processor device as extracting as an extracted PN bit sequence, the successively generated PN bit sequence from the successively PN modulated RF carrier, and determining respective times, relative to the second clock signal, of receiving the succession of instances of the REF signal by steps including incrementally sliding and correspondingly correlating a PN reference signal against the extracted periodic PN bit sequence.

[0051] Example System for Synchronized Untethered Clocks Via Wireless Link Successive PTP With Successive Reference Propagation Path Based Time Drift Correction

[0052] According to one or more embodiments, a system can include a master device and a slave device that can be spatially separated from the master device. According to various embodiments the master device can include a master clock communicatively coupled to a master device processor that can be coupled to a master device wireless synchronization (SYNC) transceiver, and to a master device wireless radio frequency (RF) transmitter and a master device wireless RF receiver. The master clock device can be configured to generate a master clock signal and to generate, in a successive manner having time spacings that can be consistent or that can vary, a master SYNC signal. The slave clock device can be configured to generate a slave clock signal and a slave SYNC signal for comparison against the master SYNC signal. The slave device can comprise a slave clock device that can be communicatively coupled to a slave device processor that in turn can be communicatively coupled to a slave device wireless SYNC transceiver. According to one or more embodiments the master device wireless SYNC transceiver can comprise a master device wireless SYNC transmitter and a master device wireless SYNC transceiver and the slave device wireless SYNC transceiver can comprise a slave device wireless SYNC transceiver and a slave device wireless SYNC receiver.

[0053] Fig. 5 shows a functional block schematic of one example implementation of one system 500 for automatic absolute timing in using distributed untethered clocks using with a combination of wireless precision time synchronization and reference propagation path based time drift compensation in accordance with one or more embodiments.

[0054] As described in reference to Fig. 1, according to one or more embodiments the master device processor can be configured to cause the master device RF transmitter to successively transmit a reference (REF) signal. The REF signal, in accordance with one or more embodiments, can have for example and without limitation a waveform providing for sharp cross-correlation detection in the slave device by, e.g., sliding along the REF signal relative a matching filter or template.

[0055] As will be understood by persons of ordinary skill upon reading this disclosure in its entirety, implementations and arrangements of systems in accordance with one or more embodiments can include the master device and one slave device being respective instances of selectively reconfigurable devices that can be selectively switchable, at least for purposes of wireless link synchronization of untethered clocks and for novel compensations of time drift, between a master device mode and a slave device mode.

[0056] According to one or more embodiments, the master device processor and the slave device processor can be configured to establish a wireless link between one another, e.g., through respective controlling of the master device wireless transceiver and the slave device wireless transceiver

[0057] The master device processor clock can connect to the master device processor and, for example, by operation of a master device processor clock synchronization circuit, can synchronize to the master device pulsed SYNC signal generated by the master device clock. The master device TX can communicate the master device pulsed SYNC signal, over the wireless link and through the slave device RX, to the slave device processor. A slave device clock can connect to the slave device processor and, for example, by operation of a slave device processor clock synchronization circuit, can synchronize the slave device clock to the master clock processor.

[0058] Motion and changes in the wireless medium can vary the synchronization accuracy between master and slave device processor clocks, compared to a cable connection, which is accurate to a sub-nanosecond. For example, a software-based PTP is implemented over a dedicated wireless link created by the master device SYNC transceiver. The slave device SYNC receiver connects to this link to maintain a single hop for greater accuracy. The master and slave devices use their SYNC transmitter and receiver to establish and maintain the link.

[0059] Sliding Correlation Based Channel Sounder with Wireless PTP Synchronization

[0060] Sliding correlation based channel sounding can use cross-correlation between pseudorandom noise (PN) sequences to study radio propagation behavior in the time domain, such as described in T. Rappaport, Wireless communications: Principles and practice, 2nd ed. Prentice Hall, 2002, and D. Shakya et al., “A wideband sliding correlation channel sounder in 65 nm CMOS: Evaluation board performance, ” IEEE Transactions on Circuits and Systems II: Express Briefs, pp. 3043-3047, 2021.].

[0061] In an embodiment, at a first device a binary phase shift keying can modulate an RF carrier with the PN sequence generated, e.g., at a fast chip rate (hereinafter represented as the variable a) such as, but not limited to, a = 500 mega chips per second (Mcps), modulate a radio frequency (RF) carrier with the 500 Mcps PN sequence in a superheterodyne architecture

[0021] and transmit the PN sequence modulated RF carrier over a multipath to a second device. At the second device a receive (RX) antenna, can receive multiple replicas of the transmitted PN sequence modulated RF carrier due to multipath. The multiple components can be downconverted by the second device to the baseband as in-phase and quadrature components. Also at the second device, an identical PN sequence can be generated at a slightly slower chip rate, (hereinafter represented as the variable 0) e.g., but without limitation, 0 = 499.9375 Mcps and then correlated with the downconverted received signal. The slight difference in the chip rates at the TX and RX , e.g., the first device a being 500 Mcps and the second device 0 being 499.9375 Mcps, causes the received signal to slide over the slower replica PN sequence, which generates a time-dilated PDP with peaks where a PN auto-correlation is achieved. The sliding correlation can produce a time-dilation of the PDP by a slide factor, y, resulting in a processing gain (Gp), as in Equation (1) below, and bandwidth compression while rejecting external interference, as described in the two technical publications identified above.

[0062] Gp[dB] = lO logig(y) [dB], Equation (1) where y = a - fl),

[0063] Moreover, time-dilation can ease nanosecond clock synchronization requirements allowing PTP over Wi-Fi to synchronize untethered TX and RX. Fig.1 shows the block diagram of the 142 GHz sliding correlation channel sounder at NYU.

[0064] Fig. 6 shows a functional block schematic of one implementation of one sliding correlator channel sounder system providing multipath channel sounding with a combination of wireless link based precision time synchronization and reference propagation based time drift correction in accordance with various embodiments.

[0065] As illustrated in Fig. 6, in an example implementation two Raspberry Pi (RPi) devices can establish a wireless medium for clock synchronization using PTP. The RPi master can synchronize to the 1 PPS signal from the TX Rubidium (Rb) clock. The slave RPi clock can synchronize to the master RPi via PTP and can generate a 1 PPS signal to synchronize the RX Rb clock. Motion and changes in the wireless medium can vary the synchronization accuracy between master and slave RPi clocks, compared to a cable connection, which is accurate to a sub-nanosecond. A software-based PTP can be implemented over a dedicated Wi-Fi hotspot link created by the RPi master at the TX. The RPi slave at the RX can connect to this hotspot to maintain a single hop for greater accuracy, based on the results in Table I. The RPi master and slave can use their on-board Wi-Fi modules to establish and maintain the link.

[0066] A PDP time drift was observable between successive 3- minute measurement sweeps during radio propagation measurement campaigns without PTP implementation. It was prominent when the TX and RX were moved to new locations in a campaign day Several measurement sweeps were performed at a T-R location pair before TX and / or RX were moved to a different spot.

[0067] Fig. 7 shows a high level operation flow diagram 600 of operations in one example process for implementing an Algorithm 1 process for periodic PDP drift correction. Sliding Correlation Based Channel Sounder with Cable Connected Synchronization and Successive PPP Correction for Absolute Timing

[0068] Fig. 8 shows a functional block schematic of one implementation of one sliding correlator channel sounder system providing multipath channel sounding with a combination of cablebased precision time synchronization and reference propagation path based time drift correction in accordance with various embodiments.

[0069] Modular Test and Measurement Equipment

[0070] Scientific experimentation may have test and measurement requirements that involve observing physically separate subjects but requires a common reference. Particularly with testing and verifying radio and antenna systems, large physical separation over several meters may be desired. Recently, Anritsu introduced the modular vector network analyzers ME7869A that provide phase synchronized S-parameter measurements up to 100 m distance using RF-over- optical fiber connections. RF test and measurement manufacturers such as Anritsu, Keysight, or Rohde & Schwarz are increasingly interested in building modular devices and lab ecosystems with interconnected equipment such as network analyzers, spectrum analyzers, signal generators, oscilloscopes, waveform generators, and much more. Especially when testing wireless transceiver systems, such test equipment might require accurate phase synchronization when the transmitter and receiver radios need to be connected to separate test hardware but need precise synchronization, and PTP-based algorithms can prove efficient in synchronizing them.

[0071] Fig. 9 shows one example functional block schematic of one arrangement 800 of one example system according to a concept for leveraging wireless PTP and successive measurements of an internal calibration standard to achieve phase synchronization between the main instrument and remote extenders.

[0072] Referring to Fig. 9,

[0073] Step 1 - Use a 1-pulse per second (IppS) beat signal to synchronize the “Radio Unit” on the “Main Test instrument.”

[0074] Step 2 - Use PTP to synchronize the internal clock of the “Remote Measurement Extenders” to the clock of the “Radio Unit” and thus the “Main Test Instrument” clock.

[0075] Step 3 - Successively measure the “predefined internal clock calibration unit” to eliminate clock drift using an approach close to Algorithm 1. Fig. 10 shows a functional block schematic of one alternative implementation 1000 of the concept embodied in the Fig. 9 arrangement, also comprising an Algorithm 2-bascd tracking of clock drift. Applications can include, for example and without limitation, extended test measurements. As shown in Fig. 10, Algorithm 2 may be run in a background processing thread.

[0076] Distributed Repeaters and Reconfigurable Intelligent Surfaces

[0077] The dense cellular networks for 5G and 6G deployments may leverage repeaters and reconfigurable intelligent surfaces to extend the coverage of cellular base stations. However, to ensure coherent signaling among the several base stations, repeaters, intelligent surfaces, and users that operate in a common cellular network, time and phase synchronization methods can contribute to sustaining the highly directional and dynamic links.

[0078] Fig. 11 shows a conceptual implementation according to various embodiments for using PTP over wireless links along with algorithms 1 and 2 to achieve, for example and without limitation, phase synchronization and eliminating clock drift.

[0079] Referring to Fig. 11,

[0080] Step 1 - Antenna systems can identify propagation delays between one another in a network;

[0081] Step 2 - The propagation delay information can be used to implement PTP between the antenna systems and repeaters in the network, synchronizing to the “grandmaster clock” that connects to antenna system 1; and

[0082] Step 3 - Algorithm 1 for successive drift correction may be implemented by antenna systems and repeaters connected to antenna system 1 using pilot reference signals. Phase and timing errors may, thus, be removed between antenna systems and repeaters in the network.

[0083] Algorithm 2 may be implemented locally at each antenna system to keep track of clock drift in the event, e.g., of signal blockage to antenna system 1.

[0084] Servers and Data Centers

[0085] Data centers can include hundreds of servers and can carry tremendous data traffic, primarily through devices networked over ethemet or optical fiber. Wireless links to accurately synchronize server clocks and support short-range THz links are envisioned between servers, which can eliminate the cabling requirements between servers and other networking hardware. Further, synchronized time stamps can prove valuable when organizing and coordinating the flow of data within a data center or between data centers. UAV Swarms

[0086] Coordinated unmanned aerial vehicles (UAVs) arc envisioned to be employed in several applications such as cellular networks, agriculture, delivery, etc. However, such a dynamic distributed network of UAVs can require time synchronization for accurate localization and positioning. Time synchronization based on a common reference can improve positioning accuracy for each UAV while facilitating coordination among the swarm.

[0087] Fig. 12 shows a functional block schematic of one implementation of one system, in a non-limiting illustrative operating state, providing time synchronization of unmanned aerial vehicle (UAV) clocks in a dynamic distributed network of UAV s, for accurate localization and positioning of UAVs. Features can include, for example, time synchronization based on a common reference, which can improve positioning accuracy for each UAV while facilitating coordination among the swarm.

[0088] Further, the UAVs can locate the central drone controller at any time during operation using directional electronic beam sweeping with an on-board antenna array to synchronize the local clock and calculate position relative to the central drone controller.

[0089] Wireless Sensor Networks

[0090] Similar to data loggers, wireless sensor networks (WSNs) are distributed systems that are contemplated as utilizing low accuracy and low power clocks in a widespread deployment of sensors. For time-synchronized sensor measurements and logging, WSNs would greatly benefit from synchronizing to a PTP master to remove any timing offsets between sensor measurements and synchronize sleep-wake cycles and algorithms for power saving. As an example, a governing node can broadcast time synchronization signals, which sensor nodes can synchronize to before making readings and recording the reading with a timestamp.

[0091] Servers and Data Centers

[0092] Data centers can include hundreds of servers and can carry tremendous data traffic, primarily through devices networked over ethemet or optical fiber. Wireless links to accurately synchronize server clocks and support short-range THz links are envisioned between servers, which can eliminate the cabling requirements between servers and other networking hardware. Further, synchronized time stamps can prove valuable when organizing and coordinating the flow of data within a data center or between data centers. loT Devices

[0093] The intcmct-of-things (loT) may include a large collection of interconnected distributed sensors, actuators, and embedded computers with free-running clocks. In applications involving real-time control, automation, and monitoring, the drift between clocks can lead to coordination issues and failures. Thus, synchronizing loT nodes through a centralized architecture or between individual nodes to overcome clock drift and remove timing errors is an important application.

[0094] Fig. 13 shows a functional block schematic of one master device computer system 1300 configured to perform various master device precision time synchronization and reference propagation path based time drift correction operations and processes in accordance with the disclosed embodiments.

[0095] Fig. 14 shows a functional block schematic of one slave device computer system 1400 configured to perform various clock device precision time synchronization and reference propagation path based time drift correction operations and processes in accordance with the disclosed embodiments.

[0096] The foregoing description, for purpose of explanation, has been described with reference to specific embodiments. However, the specific embodiment are not intended to be exhaustive or to limit the invention to the precise forms disclosed. Many modifications and variations are possible in view of the above teachings. The specific embodiments were chosen and described in order to best explain the principles of the present systems and methods and their practical applications, to thereby enable others skilled in the art to best utilize the present systems and methods and various embodiments with various modifications as may be suited to the particular use contemplated.

[0097] Where a range of values is provided in this disclosure, it is understood that each intervening value, to the tenth of the unit of the lower limit unless the context clearly dictates otherwise, between the upper and lower limit of that range and any other stated or intervening value in that stated range, is encompassed within the invention. The upper and lower limits of these smaller ranges may independently be included in the smaller ranges and are also encompassed within the invention, subject to any specifically excluded limit in the stated range. Where the stated range includes one or both of the limits, ranges excluding either or both of those included limits are also included in the invention. Except where otherwise stated, the terms “a” or “an,” as used in the specification and claims, arc to be construed as meaning “at least one of.” In addition, this statement is intended to serve as antecedent basis for use of such exclusive terminology as “solely”, “only”, and the like in connection with the recitation of claim elements, or use of a “negative” limitation. In addition, for ease of use, the words “including” and “having,” as used in the specification and claims, are interchangeable with and have the same meaning as the word “comprising.” In addition, the term “based on” as used in the specification and the claims is to be construed as meaning “based at least in part upon.”

[0098] Ordinal terms such as “first,” “second,” “third,” etc., as used in this specification and the appended claims to modify, for example, act(s), step(s), functional block(s), signal(s), instruction(s), element(s) is to be understood as a labelling to individually identify separate act(s), step(s), functional block(s), signal(s), instruction(s), and / or element(s), and is not to be understood, except where stated otherwise, to be any indication of temporal or spatial ordering, or of priority.

Claims

CLAIMSWhat is claimed is:

1. A successively synchronizing, time drift correcting multiple clock system, comprising: a first device including a first clock configured to generate a first clock signal and a synchronization (SYNC) signal and communicatively coupled to the first clock a first device data processor communicatively coupled to a first device SYNC transceiver and to a first device transmitter (TX), the first device TX being wireless; and a second device including a second clock configured to generate a second clock signal and communicatively coupled to the second clock a second device data processor communicatively coupled to a second device SYNC transceiver and to a second device receiver (RX), the second device RX being wireless, wherein the first device data processor is further configured to initiate, in response to the SYNC signal, a synchronization process that is configured to detect a clock offset, at the second device, between the second clock signal and the first clock signal and that comprises communications between the first device data processor and the second device data processor via the first device SYNC transceiver and the second device SYNC transceiver, the second device data processor is further configured to cause the second clock to adjust a second clock frequency or second clock phase in accordance with the detected clock offset, the first device data processor is further configured to cause the first device TX to transmit a succession of instances of a reference (REF) signal for reception by the second device RX, over a stable propagation path from the first device TX to the second device RX, and the second device data processor is further configured to detect, based on the second device RX receiving the succession of instances of the REF signal, a time drift of the second clock signal relative to the first clock signal, andperform a correcting time shift of the second clock based on the detected time drift.

2. The successively synchronizing, time drift correcting multiple clock system of claim 1, wherein the first device data processor and the second device data processor are further mutually configured to perform the synchronization process as a precision time protocol (PTP) process comprising: the first device data processor communicating to the second device data processor the SYNC signal and a corresponding time stamp indicating a first device time stamp of the SYNC signal, by steps comprising one or more transmissions from the first device SYNC transceiver to the second device SYNC transceiver the second device data processor, in response to receiving the SYNC signal and the corresponding time stamp, communicating a delay request to the first device data processor, by steps comprising a transmission from the second device SYNC transceiver to the first device SYNC transceiver, the first device data processor, in response to receiving the delay request, communicating a delay reply to the second device data processor, by steps comprising another transmission from the first device SYNC transceiver to the second device SYNC transceiver, and the second device data processor, based at least in pail on the time stamp and the request reply, detecting the clock offset between the second clock signal and the first clock signal.

3. The successively synchronizing, time drift correcting multiple clock system of claim 1, wherein the first device data processor and the second device data processor are further mutually configured to establish a wireless link between one another, and to perform synchronization process by steps comprising: the second device data processor controlling the second device SYNC transceiver to communicate over the wireless link for reception by the first device SYNC transceiver, requests for timing information, the first device data processor controlling the first device SYNC transceiver to communicate the timing information over the wireless link for reception by the seconddevice SYNC transceiver, in association with the SYNC signal and with receiving the requests for the timing information, and the second device data processor determining the clock offset based at least in part on the timing information received over the wireless link.

4. The successively synchronizing, time drift correcting multiple clock system of claim 3, wherein the first device data processor and the second device data processor are also mutually configured to establish the wireless connection between one another by steps comprising the first data processor establishing, via the first device SYNC transceiver, a dedicated Wi-Fi hotspot; and the second device data processor joining, via the second device SYNC transceiver, the dedicated Wi-Fi hotspot.

5. The successively synchronizing, time drift correcting multiple clock system of claim 1, wherein: the first device data processor is further configured to transmit the succession of instances of the REF signal by: successively generating a first device pseudorandom (PN) bit sequence, modulating a radio frequency (RF) carrier by the successively generated PN bit sequence to generate a successively PN modulated RF carrier, and transmitting, as the succession of instances of the REF signal, the successively PN modulated RF carrier via the first device TX; and the second device data processor is further configured to: extract, as an extracted PN bit sequence, the successively generated PN bit sequence from the successively PN modulated RF carrier, and determine respective times, relative to the second clock signal, of receiving the succession of instances of the REF signal by steps including incrementally sliding and correspondingly correlating a PN reference signal against the extracted periodic PN bit sequence.

6. The successively synchronizing, time drift correcting multiple clock system of claim 5, wherein: the first device PN bit sequence has a first device bits per second (BPS) rate, the second device data processor is further configured to perform the incrementally sliding and correspondingly correlating the PN reference signal against the extracted periodic PN bit sequence by steps comprising: generating the PN reference signal as a second device PN bit sequence that is a duplicate of the first device PN bit sequence and has a second device BPS rate, the second device BPS rate being lower than the first device BPS rate by an amount that causes the extracted PN bit sequence to slide over the second device PN bit sequence, to generate a time-dilated PDP with peaks where a PN auto-correlation is achieved.

7. The successively synchronizing, time drift correcting multiple clock system of claim 1, wherein: the first device data processor is further configured to generate a pseudorandom (PN) sequence at a first device chips per second (CPS) rate, the first device further comprises a radio frequency (RF) carrier signal generator configured to generate an RF carrier signal, and a modulator configured to receive the RF carrier signal and the PN sequence and to generate, in response, an RF carrier modulated by the PN sequence at the first device CPS rate; the first device data processor is further configured to cause the first device TX to transmit the RF carrier modulated by the PN sequence, for reception over a multipath propagation path by the second device RX; the second device data processor is further configured to: generate a second device duplicate of the PN sequence at a second device CPS rate, the second device CPS rate being offset from the first device CPS rate, receive from the second device RX the multipath components of the transmitted RF carrier modulated by the PN sequence signal and to extract a coherent sum of respective PN sequences carried by each multipath,generate time dilated power delay profile (PDP) based on sliding correlation of the second device duplicate of the PN sequence with the extracted coherent sum of PN sequences.

8. A method for successively synchronizing, and time drift correcting of multiple, spatially separated clocks, comprising: a generating in a first device, positioned at a first location in an environment, a first clock signal and a synchronization (SYNC) signal; generating in a second device a second clock signal, the second device being positioned at a second location in the environment, the second location being spatially separated from the first location, and the first location and the second location being respectively positioned in the environment such that a stable propagation path is provided from the first location to the second location; the first device initiating, in response to the SYNC signal, a synchronization process performed by the first device and the second device, which is configured to detect a clock offset at the second device between the second clock signal and the first clock signal and comprises the first device communicating timing information to the second device and the second device determining the clock offset based at least in part on the timing information; the second device causing the second clock to adjust a second clock frequency or a second clock phase, or both, in accordance with the detected clock offset; the first device transmitting a succession of instances of a reference (REF) signal for reception by the second device, over the stable propagation path from the first device to the second device; the second device performing steps comprising detecting, based on a receiving the succession of instances of the REF signal, a time drift of the second clock signal relative to the first clock signal, and performing a correcting time shift of the second clock based on the detected time drift.

9. The method of claim 8 for successively synchronizing and time drift correcting multiple, spatially separated clocks, wherein:the transmitting the succession of instances of the REF signal includes the first device: successively generating a pseudorandom (PN) bit sequence, modulating a radio frequency (RF) carrier by the successively generated PN bit sequence to generate a successively PN modulated RF carrier, and transmitting, as the succession of instances of the REF signal, the successively PN modulated RF carrier via the first device TX; and the detecting, based on the receiving the succession of instances of the REF signal, the time drift of the second clock signal relative to the first clock signal, includes second device steps of: extracting, as an extracted periodic PN bit sequence, the successively generated PN bit sequence from the successively PN modulated RF carrier, and determining respective times, relative to the second clock signal, of receiving the succession of instances of the REF signal by steps comprising incrementally sliding and correspondingly correlating a PN reference signal against the extracted periodic PN bit sequence.

10. A sliding correlation channel sounder with successive synchronizing, and successive time drift correcting of multiple clocks, comprising: a master device configured to generate a master clock signal having a master clock frequency and to successively generate, based on the master clock signal, a synchronization (SYNC) signal and a sequence of master device time stamps; and a slave device arranged at a location spatially separated from the master device with a multipath propagation path from the master device, configured to generate a second clock signal and generate, based on the slave clock signal, a sequence of slave device time stamps, wherein the master device is further configured to: transmit the SYNC signal to the slave device, transmit to the slave device, in association with transmitting the SYNC signal, a master device first time stamp, from the sequence of master device time stamps, indicating a master device time of the transmitting the SYNC;transmit to the slave device, over the multipath propagation path, an RF carrier modulated by a master device pseudorandom (PN) sequence at a master device chips per second (CPS) rate; the slave device is further configured to assign, in response to receiving the SYNC signal, a slave device first time stamp indicating a time, in terms of the sequence of slave device time stamps, of receiving the SYNC signal, determine, based at least in part on the master device first time stamp and the slave device first time, an offset between the slave device time stamps and the master device time stamps and, based on the offset, to perform a synchronizing of the slave device time stamps to the master device time stamps, generate a slave device duplicate of the master device PN sequence at a slave device CPS rate, the slave device CPS rate being lower than the master device CPS rate offset from the first device CPS rate, receive from the multipath propagation path multipath components of the transmitted RF carrier modulated by the master PN sequence signal, extract a coherent sum of respective PN sequences carried by each multipath, and and generate a time dilated power delay profile (PDP) based on a sliding correlation of the slave device duplicate of the master device PN sequence with the extracted coherent sum of PN sequences.1 l.A method for successive correction of power delay profile (PDP) time drift, the method comprising steps of: a) arranging the master device of the claim 10 sliding correlation channel sounder at a T location in an environment, and arranging the slave device of the claim 10 sliding correlation channel sounder at an R location in the environment, the R location being separated from the T location by the multipath propagation channel and transmitting, by the master device, over the multipath propagation channel for reception by the slave device, the RF carrier modulated by a master device PN sequence at the master device CPS rate;b) finding, by the slave device, a strongest multipath component (MPC) direction for the step a) arrangement of the master device at the T location and the slave device at the R location, and assigning the strongest MPC direction as a reference MPC; c) storing in the slave device the MPC peak position in the PDP as Pl; d) storing the TX azimuth and elevation and the RX azimuth and elevation as a reference position; e) beginning a standard measurement sweep for the claim 10 channel sounder; f) after completion of the step e) sweep, returning the master device and the slave device to the reference positions; g) re-recording, in a storage, the MPC peak position for the reference MPC as P2; h) circular shifting the PDP by Pl - P2; and i) repeating steps e) through h) until all measurement sweeps are complete.

Images