Epitaxial wafer, radio frequency device, terminal radio frequency module, and terminal device

Abstract

The present application provides an epitaxial wafer (100), a radio frequency device (1), a terminal radio frequency module, and a terminal device. The epitaxial wafer (100) comprises a silicon substrate layer (10) and an epitaxial layer (20) which are stacked. The epitaxial layer (20) further comprises a nucleation layer (201) stacked on the surface of the silicon substrate layer (10). Moreover, air gaps are provided at the interface of the silicon substrate layer (10) and the nucleation layer (201). On the basis of the special structure and parameter design at the interface of the silicon substrate layer (10) and the nucleation layer (201) in the epitaxial wafer (100), the epitaxial wafer (100) may be used for providing a radio frequency device having low radio frequency loss.

Description

Epitaxial wafers, RF devices, terminal RF modules and terminal equipment

[0001] This application claims priority to the Chinese patent application filed with the China Patent Office on October 28, 2023, with application number 202311422361.0 and application name “Epitaxial wafer, radio frequency device, terminal radio frequency module and terminal equipment”, all contents of which are incorporated by reference into this application. Technical Field

[0002] The embodiments of the present application relate to the field of semiconductor technology, and specifically to epitaxial wafers, radio frequency devices, terminal radio frequency modules and terminal equipment. Background Art

[0003] Currently, most RF devices utilize Group III nitride semiconductors, represented by gallium nitride (GaN), particularly GaN-based heterostructure RF devices on silicon carbide substrates. Theoretically, these structures can also be grown on silicon substrates, allowing for the fabrication of larger, lower-cost RF devices. However, using silicon substrates can lead to significant RF losses in these devices, reducing their efficiency.

[0004] In order to reduce the severe RF losses caused by the conduction of the silicon substrate in GaN-based RF integrated circuit devices on silicon substrates, the industry often uses high-resistivity silicon wafers as silicon substrates, but the improvement effect is limited; this is largely attributed to the presence of parasitic conductive channels at the interface between the silicon substrate and the GaN-based epitaxial structure. Therefore, some technicians have tried to remove the silicon substrate in some areas to eliminate the parasitic conductive channels at the interface between the silicon substrate and the epitaxial structure. However, such an operation is not only difficult to process, but also affects the structural stability of the RF device, which is also not conducive to the promotion and application of GaN-based RF integrated circuit devices. Therefore, there is an urgent need to provide a new epitaxial wafer that can reduce the RF loss of the silicon substrate and ensure the structural stability and quality of the epitaxial structure and RF device.

[0005] Summary of the Invention

[0006] In view of this, the embodiments of the present application provide an epitaxial wafer, an RF device, a terminal RF module and a terminal device. Based on the special structure and parameter design at the interface between the silicon substrate layer and the nucleation layer in the epitaxial wafer, it can be used to provide an RF device with low RF loss.

[0007] According to a first aspect of an embodiment of the present application, an epitaxial wafer is provided, comprising a stacked silicon substrate layer and an epitaxial layer, wherein the epitaxial layer comprises a nucleation layer stacked on a surface of the silicon substrate;

[0008] The silicon substrate layer has a plurality of first blind holes on a surface close to the nucleation layer, and the nucleation layer has a plurality of second blind holes on a surface close to the silicon substrate layer, wherein any one of the second blind holes is arranged corresponding to one of the first blind holes, and an orthographic projection of the second blind hole on the silicon substrate layer overlaps with the corresponding first blind hole;

[0009] Wherein, the depth of the first blind hole is greater than or equal to 200 nm.

[0010] The above-mentioned special structural design can make the interface between the silicon substrate layer and the nucleation layer have multiple "air gaps"; and the depth of the above-mentioned "air gaps" in the silicon substrate layer is ≥200nm, which can effectively cut off the parasitic conductive channel at the interface between the silicon substrate layer and the nucleation layer, thereby better suppressing the parasitic conductivity effect at the above-mentioned interface, and then the above-mentioned epitaxial wafer can be used to provide a radio frequency device with lower radio frequency loss.

[0011] In some embodiments of the present application, the depth of the first blind via is 200nm-500nm. By controlling the depth of the first blind via within this range, the air gap formed by the first blind via can fully exert its effect, severing the parasitic conductive channel between the silicon substrate layer and the nucleation layer, while also ensuring that the silicon substrate layer has strong support for the structure superimposed on its surface. This also facilitates the production of epitaxial wafers and improves the crystal quality of the epitaxial layer, thereby further improving the power and efficiency of radio frequency devices when used therein.

[0012] In some embodiments of the present application, the number of the second blind holes is the same as the number of the first blind holes, and the plurality of the first blind holes are arranged in a one-to-one correspondence with the plurality of the second blind holes. The epitaxial wafer having the above structure is easy to manufacture and has a good effect in suppressing radio frequency loss.

[0013] In some embodiments of the present application, the depth of the second blind hole is 300nm-500nm. Controlling the depth of the second blind hole within the above range is beneficial to ensuring the structural strength and mechanical properties of the nucleation layer itself, and is conducive to the air gap to play a better role in suppressing parasitic conduction.

[0014] In some embodiments of the present application, the inner diameter of the first blind via is uniform throughout the stacking direction of the silicon substrate layer and the epitaxial layer. This ensures that the silicon substrate layer maintains structural uniformity in the region from the plane of the first blind via's end face to the surface of the silicon substrate layer facing away from the nucleation layer. This effectively cuts off the parasitic conductive channel, maximizes the benefit of the air gap it contributes to, and further reduces RF losses in the resulting RF device.

[0015] In some embodiments of the present application, the angle between the sidewall of the first blind via and the surface of the silicon substrate layer near the nucleation layer is 85°-90°. This allows the inner diameter of the first blind via to vary slightly or remain constant along the stacking direction of the silicon substrate layer and the nucleation layer, thereby preventing incomplete destruction of the parasitic conductive channel and thus affecting the air gap gain due to an uneven structure of the first blind via.

[0016] In some embodiments of the present application, the opening diameter of the first blind hole is 100 nm to 1000 nm. Controlling the opening diameter of the first blind hole within the above range not only facilitates preparation, but more importantly, can achieve a relatively ideal effect of cutting off the parasitic conductive channel.

[0017] In some embodiments of the present application, the opening of the first blind hole is circular or n-gonal, where n > 8. Thus, the air gap formed by the first blind hole has a good benefit, which helps to suppress radio frequency loss when the epitaxial wafer is used in a radio frequency device.

[0018] In some embodiments of the present application, the plurality of first blind holes are periodically arranged in a first direction, wherein the first direction is perpendicular to the stacking direction of the silicon substrate layer and the nucleation layer. This is done to ensure the structural uniformity of the silicon substrate layer and to minimize the risk of cracks arising from uneven stress distribution or insufficient bearing capacity within the silicon substrate layer during subsequent applications. Furthermore, given the potential for many repeating units (a gate and the regions containing a drain and a source located on either side of the gate are considered the same repeating unit) or circuit elements in a radio frequency device, the parasitic conductive channels in different regions at the first interface are effectively cut off during subsequent applications, thereby better suppressing the radio frequency loss of the radio frequency device.

[0019] In some embodiments of the present application, along the first direction, the minimum distance between the openings of two adjacent first blind vias on the silicon substrate layer is 200nm-1000nm. Controlling the arrangement period of the first blind vias within the aforementioned range also controls the distribution density of the first blind vias. Thus, when applied to RF devices, this facilitates achieving air gaps within any repeating unit, thereby suppressing RF losses and improving RF device performance.

[0020] In some embodiments of the present application, the plurality of first blind vias are arranged in a regular hexagonal periodic pattern in the first direction. This regular hexagonal periodic pattern facilitates the subsequent growth of the epitaxial layer and ensures good crystal quality of the epitaxial layer, thereby improving the power and efficiency of radio frequency devices when used therein.

[0021] In some embodiments of the present application, the nucleation layer is a two-dimensional nucleation layer. The two-dimensional nucleation layer has high crystal quality, so when the epitaxial wafer is used in a radio frequency device, it can improve the power and efficiency of the radio frequency device, greatly enhance the device performance, and increase its market competitiveness.

[0022] In some embodiments of the present application, the thickness of the nucleation layer is 300nm-1000nm. This ensures high structural integrity and crystal quality of the nucleation layer, which helps ensure and improve the overall crystal quality of the epitaxial layer. Furthermore, a suitable thickness can avoid the risk of cracking in the nucleation layer, thereby improving the overall performance of the epitaxial wafer.

[0023] In some embodiments of the present application, the nucleation layer includes a two-dimensional nucleation layer and a three-dimensional nucleation layer stacked in sequence, with the two-dimensional nucleation layer disposed adjacent to the silicon substrate layer. This allows for a balanced approach to both epitaxial layer crystal quality and production efficiency, thereby improving the cost-effectiveness of the epitaxial layer.

[0024] In some embodiments of the present application, the thickness of the two-dimensional nucleation layer is 300nm-500nm, and the thickness of the three-dimensional nucleation layer is 200nm-500nm. This improves the crystal quality of the nucleation layer while also increasing the production efficiency of the epitaxial wafer, further facilitating the preparation and application of the epitaxial wafer.

[0025] In some embodiments of the present application, the nucleation layer is an aluminum nitride layer. Aluminum nitride has a high band gap (up to 6.2 eV) and possesses the characteristics of high resistance, high hardness, high chemical stability, high breakdown electric field, and low dielectric loss, which can further improve the performance of the final RF device.

[0026] In some embodiments of the present application, the dislocation density of the two-dimensional nucleation layer is less than 5×10 9 / cm 2 The surface roughness of the two-dimensional nucleation layer is less than 0.5 nm. When the two-dimensional nucleation layer meets the above conditions, it indicates that the crystal quality of the two-dimensional nucleation layer is high, which can improve the power and efficiency performance of the final RF device.

[0027] In some embodiments of the present application, the molar ratio of the Group V element to the Group III element in the two-dimensional nucleation layer is 1:(20-100). This facilitates obtaining a two-dimensional nucleation layer, improves the crystal quality of the epitaxial wafer, and improves the power and efficiency of the final RF device.

[0028] In some embodiments of the present application, the molar ratio of the Group V element to the Group III element in the three-dimensional nucleation layer is 1:(100-2000). In this way, the three-dimensional nucleation layer is easily obtained, and the production efficiency of the epitaxial wafer is improved.

[0029] In some embodiments of the present application, the epitaxial layer also includes a stress regulation layer, a high-resistance buffer layer, a channel layer, an insertion layer, a barrier layer and a cap layer stacked in sequence; wherein the stress regulation layer is arranged on the surface of the nucleation layer away from the silicon substrate layer.

[0030] In some embodiments of the present application, the room temperature resistivity of the silicon substrate layer is greater than or equal to 2000Ω·cm. This can reduce the radio frequency loss caused by the silicon substrate layer itself and improve the performance of the final radio frequency device.

[0031] A second aspect of the embodiments of the present application provides a method for preparing an epitaxial wafer, comprising:

[0032] Providing a silicon substrate, and forming a plurality of the first blind holes on one side surface of the silicon substrate to obtain the silicon substrate layer;

[0033] The epitaxial layer is grown on the surface of the silicon substrate layer having the first blind hole, and the epitaxial layer includes the nucleation layer.

[0034] The preparation method has simple steps, strong process controllability, high production efficiency, and is suitable for large-scale industrial production.

[0035] In some embodiments of the present application, a two-dimensional nucleation layer is grown on a surface of a silicon substrate layer having a first blind hole; the growth temperature of the two-dimensional nucleation layer is 1000°C-1200°C, the growth pressure is 50mbar-100mbar, and the molar ratio of Group V elements to Group III elements in the growth raw material is 1:(20-100). This can induce lateral atomic migration and thus lateral atomic growth, thereby facilitating the production of a two-dimensional nucleation layer, reducing its nucleation island density and increasing its size, thereby reducing the dislocation density introduced by the initial closure of the two-dimensional nucleation layer, and thereby improving the crystal quality of the two-dimensional nucleation layer.

[0036] Some embodiments of the present application further include growing a three-dimensional nucleation layer on a surface of the two-dimensional nucleation layer facing away from the silicon substrate layer; the three-dimensional nucleation layer is grown at a temperature of 900°C to 1100°C, a growth pressure of 100mbar to 300mbar, and a molar ratio of Group V elements to Group III elements in the growth material of 1:(100-2000). This can induce atoms to grow both horizontally and vertically, thereby increasing the growth rate of the nucleation layer and, in turn, improving the production efficiency of epitaxial wafers.

[0037] A third aspect of an embodiment of the present application provides a radio frequency device, comprising a drain, a source, a gate and the epitaxial wafer provided in the first aspect of the embodiment of the present application; the drain, source and gate are arranged on the surface of the epitaxial layer away from the silicon substrate layer, and the drain and the source are arranged on opposite sides of the gate and are isolated from each other.

[0038] Due to the use of the epitaxial wafer provided in the embodiment of the present application, the above-mentioned radio frequency device has low radio frequency loss, low production cost and can be prepared into a larger size.

[0039] In some implementations of the present application, the radio frequency device is a power amplifier.

[0040] A fourth aspect of an embodiment of the present application provides a terminal radio frequency module, comprising the radio frequency device and antenna provided in the third aspect of the embodiment of the present application, wherein the radio frequency device is used to amplify the radio frequency signal and output it to the antenna for outward radiation.

[0041] The above-mentioned terminal RF module can combine high efficacy, high efficiency and low RF loss, and has strong market competitiveness.

[0042] The fifth aspect of the embodiment of the present application provides a terminal device, including the terminal radio frequency module provided by the fourth aspect of the embodiment of the present application. The terminal device has a good market prospect. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] FIG1A is a top view of a silicon substrate layer provided in one embodiment of the present application;

[0044] FIG1B is a schematic structural diagram of a cross section of a silicon substrate layer provided in one embodiment of the present application;

[0045] FIG2 is a schematic structural diagram of a cross section of a silicon substrate layer and a nucleation layer of an epitaxial wafer provided in one embodiment of the present application;

[0046] FIG3 is a schematic structural diagram of a cross section of a silicon substrate layer and a nucleation layer of an epitaxial wafer provided in another embodiment of the present application;

[0047] FIG4 is a schematic diagram of the cross-sectional structure of an epitaxial wafer provided in one embodiment of the present application;

[0048] FIG5 is a schematic diagram of the cross-sectional structure of an epitaxial wafer provided in another embodiment of the present application;

[0049] FIG6 is a schematic structural diagram of a radio frequency device provided in an embodiment of the present application;

[0050] FIG7 is a process flow chart of preparing a radio frequency device provided in one embodiment of the present application.

[0051] Explanation of the accompanying figures: 100-epitaxial wafer; 10-silicon substrate layer; 20-epitaxial layer; 201-nucleation layer; 201a-two-dimensional nucleation layer; 201b-three-dimensional nucleation layer; 202-stress regulation layer; 203-high-resistance buffer layer; 204-channel layer; 205-insertion layer; 206-barrier layer; 207-cap layer; 1-RF device; 2-drain; 3-source; 4-gate; 5-interconnect metal; 6-passivation layer. DETAILED DESCRIPTION

[0052] In the semiconductor industry chain, especially the third-generation semiconductor industry chain, RF devices generally include epitaxial wafers and structures arranged on the epitaxial wafers. The epitaxial wafers include a substrate layer and an epitaxial layer. If the materials of the substrate layer and the epitaxial layer are different, it is a heterogeneous structure. Among them, epitaxial wafers with epitaxial layers of group III nitrides such as gallium nitride (GaN) can enable RF devices to achieve excellent performance such as large bandgap width, high breakdown electric field, high saturation electron drift velocity and strong polarization effect. In particular, RF devices based on GaN-based epitaxial wafers with silicon or silicon carbide as substrates also have excellent characteristics such as high power density and applicability at high frequencies. Currently, commercial GaN-based RF devices generally use relatively expensive silicon carbide substrates, which is mainly due to the serious RF losses of GaN RF devices on silicon. However, the production technology of silicon wafers is mature, high-quality, and large in size, allowing for the production of larger epitaxial wafers. Furthermore, the cost of silicon wafers is relatively low. Combined with the excess capacity of wafer foundries, GaN-on-silicon RF devices offer a significant cost advantage. Furthermore, due to the mature silicon-based large-scale integrated circuit production process, GaN-on-silicon RF devices also have good manufacturing potential. Therefore, resolving the RF loss issue in GaN-on-silicon RF devices is particularly important and is key to promoting the large-scale application of low-cost GaN-based RF devices.

[0053] The industry has attempted to address this issue by using high-resistance silicon substrates, but the improvement has been limited. This is likely due to the strong polarization effect of Group III nitrides, which creates electron channels at the interface between the silicon substrate and the superstructure, forming parasitic conductance, which leads to significant RF losses during operation of the RF device.

[0054] To address the above technical issues, an embodiment of the present application provides an epitaxial wafer comprising: a stacked silicon substrate layer and an epitaxial layer, the epitaxial layer comprising a nucleation layer stacked on the surface of the silicon substrate; a plurality of first blind holes 101 on the surface of the silicon substrate layer adjacent to the nucleation layer, and a plurality of second blind holes 210 on the surface of the nucleation layer adjacent to the silicon substrate layer, wherein each second blind hole 210 is arranged corresponding to a first blind hole 101, and the orthographic projection of the second blind hole 210 on the silicon substrate layer overlaps with the corresponding first blind hole 101; wherein the depth of the first blind hole 101 is greater than or equal to 200 nm. In an embodiment of the present application, the presence and parameters of the first blind holes 101 and the second blind holes 210 can be characterized by observing a cross-section of the epitaxial wafer using a scanning electron microscope (SEM). The depth of the first blind hole 101 refers to the dimension of the first blind hole 101 in the direction in which the silicon substrate layer and the nucleation layer are stacked.

[0055] Referring to Figures 1A-5 , an epitaxial wafer 100 includes a stacked silicon substrate layer 10 and an epitaxial layer 20. The epitaxial layer 20 includes a nucleation layer 201 stacked on the surface of the silicon substrate layer 10. The surface of the silicon substrate layer 10 near the nucleation layer 201 has a plurality of first blind holes 101, and the surface of the nucleation layer 201 near the silicon substrate layer 10 has a plurality of second blind holes 210. Each second blind hole 210 corresponds to a first blind hole 101. For example, in one set of corresponding first blind holes 101 and second blind holes 210, the orthographic projection of the second blind hole 210 on the silicon substrate layer 10 overlaps with the first blind hole 101. At this point, an "air gap" formed by the first blind holes 101 and the second blind holes 210 exists at the interface between the silicon substrate layer 10 and the nucleation layer 201. This air gap extends from the interior of the silicon substrate layer 10 to the interior of the nucleation layer 201. The triangular notch in Figure 1A represents a common positioning notch in commercially available silicon substrates.

[0056] As can be understood, the silicon substrate layer 10 has a first surface and a second surface disposed oppositely, and the nucleation layer 201 has a third surface and a fourth surface disposed oppositely. For ease of description, the first surface is defined as the surface of the silicon substrate layer 10 close to the nucleation layer 201, and the third surface is defined as the surface of the nucleation layer 201 close to the silicon substrate layer 10. The interface between the silicon substrate layer 10 and the nucleation layer 201 is defined as the "first interface." As can be understood, the first interface is also essentially the interface between the silicon substrate layer 10 and the epitaxial layer 20. A first direction is defined, which is perpendicular to the stacking direction of the silicon substrate layer 10 and the epitaxial layer 20. A second direction is defined, which is the stacking direction of the silicon substrate layer 10 and the epitaxial layer 20.

[0057] In the embodiment of the present application, the nucleation layer 201 completely covers the first surface of the silicon substrate layer 10 .

[0058] The above-mentioned special structural design can provide multiple "air gaps" at the interface between the silicon substrate layer 10 and the nucleation layer 201; and the depth of the above-mentioned "air gaps" in the silicon substrate layer 10 is ≥200nm (that is, the depth d of the first blind hole 101 is ≥200nm), which can effectively cut off the parasitic conductive channel at the first interface, thereby effectively suppressing the parasitic conductivity effect at the first interface, and thus the above-mentioned epitaxial wafer 100 can be used to provide a radio frequency device with low radio frequency loss. If the depth of the above-mentioned air gaps in the silicon substrate layer 10 is too small, a continuous parasitic conductive layer will still form at the interface between the silicon substrate layer 10 and the epitaxial layer 20, and a high concentration of hole conduction will exist, making it impossible for the air gaps to successfully play the role of cutting off the parasitic conductive channel, and almost losing their suppressive effect on radio frequency loss. Specifically, the depth of the first blind hole 101 (the depth of the air gap in the silicon substrate layer 10) can be, but is not limited to, 200nm, 220nm, 250nm, 280nm, 300nm, 320nm, 350nm, 380nm, 400nm, 420nm, 450nm, 480nm, 500nm, 520nm, 550nm, etc.

[0059] In some embodiments of the present application, the depth (d) of the first blind hole 101 is 200nm-500nm. In other words, the depth of the air gap in the silicon substrate layer 10 is 200nm-500nm. By controlling the depth of the first blind hole 101 within the above range, the air gap formed by it can fully exert its effect and cut off the parasitic conductive channel at the first interface, and can also ensure that the silicon substrate layer 10 has a strong support force for its surface superimposed structure. The epitaxial wafer 100 is easy to manufacture and the crystal quality of the epitaxial layer 20 is high, so that when it is used in a radio frequency device, it is more conducive to improving its power and efficiency. Specifically, the depth (d) of the first blind hole 101 can be, but is not limited to, 200nm, 210nm, 240nm, 260nm, 290nm, 310nm, 340nm, 390nm, 410nm, 430nm, 440nm, 460nm, 490nm, 500nm, etc.

[0060] Considering that in some embodiments, the second blind holes 210 are caused by the preparation process used for the epitaxial wafer 100, specifically, the nucleation layer 201 is directly grown on the surface of the silicon substrate layer 10 having the multiple first blind holes 101, and atoms are less likely to settle on non-close-packed crystal planes (first blind hole regions), the material of the nucleation layer 201 settles and grows on close-packed crystal planes (non-first blind hole regions), and the material grown on the surface of the non-first blind hole regions can gradually close together, thereby forming the second blind holes 210. Therefore, in some specific embodiments, the number of second blind holes 210 is the same as the number of first blind holes 101, and the multiple first blind holes 101 are arranged in a one-to-one correspondence with the second blind holes 210.

[0061] In some embodiments of the present application, the depth of the second blind hole 210 is 300nm-500nm. It is understandable that in some cases, other functional layers are superimposed on the surface of the nucleation layer 201 facing away from the silicon substrate layer 10. Controlling the depth of the second blind hole 210 within the above range can not only ensure its own structural strength and mechanical properties, provide better support for the subsequent upper structure, but also facilitate the air gap to play a better role in suppressing parasitic conduction. Specifically, the depth of the second blind hole 210 can be, but is not limited to, 300nm, 320nm, 350nm, 380nm, 400nm, 420nm, 450nm, 480nm, 500nm, etc. In this case, the total depth of the air gap in the stacking direction of the silicon substrate layer 10 and the epitaxial layer 20 is 500nm-1000nm. Specifically, the total depth of the air gap in the stacking direction of the silicon substrate layer 10 and the epitaxial layer 20 may be, but is not limited to, 500 nm, 520 nm, 550 nm, 580 nm, 600 nm, 620 nm, 650 nm, 680 nm, 700 nm, 720 nm, 750 nm, 780 nm, 800 nm, 820 nm, 850 nm, 880 nm, 900 nm, 920 nm, 950 nm, 980 nm, 1000 nm, etc. Those skilled in the art may select the depth according to actual production needs.

[0062] In some embodiments of the present application, the opening shape of the first blind hole 101 is circular or n-gonal, where n>8; it can be understood that n is a positive integer. In this way, the air gap formed by the first blind hole 101 has a better benefit, and when the epitaxial wafer 100 is used in a radio frequency device, it is beneficial to suppress radio frequency losses. Specifically, the opening shape of the first blind hole 101 can be a nonagon, a decagon, an eleven-gon, a dodecagon, a fourteen-gon, a pentagon, a seventeen-gon, an octagon, an icosagon, etc. In some specific embodiments of the present application, the opening shape of the first blind hole 101 is preferably circular. In this way, it is more conducive to suppressing radio frequency losses of radio frequency devices.

[0063] In some embodiments of the present application, the inner diameter of the first blind hole 101 is equal everywhere along the stacking direction of the silicon substrate layer 10 and the epitaxial layer 20. In this way, in the area between the plane where the end faces of the multiple first blind holes 101 are located and the first surface, the silicon substrate layer 10 has good structural uniformity, which can better cut off the parasitic conductive channel, so that the benefit of the air gap formed by its participation can be better, which is more conducive to reducing the RF loss of the final RF device. At this time, in some specific embodiments, the sidewall of the first blind hole 101 is perpendicular to the first surface. However, considering the process accuracy and preparation difficulty, in other embodiments, the inner diameter of the first blind hole 101 gradually increases or decreases along the stacking direction of the silicon substrate layer 10 and the epitaxial layer 20. At this time, there is an inclination angle between the sidewall of the first blind hole 101 and the first surface.

[0064] In some embodiments of the present application, referring to FIG1B , the angle (α) between the sidewall of the first blind hole 101 and the first surface is 85°-90°. In some specific embodiments, the angle is 90°, and the sidewall of the first blind hole 101 is perpendicular to the first surface. In this case, the structural uniformity of the first blind hole 101 is good, which is conducive to improving the benefit of the air gap and better cutting off the parasitic conductive channel at the first interface. When the angle is greater than or equal to 85° and less than 90°, there is a small inclination angle between the sidewall of the first blind hole 101 and the first surface. Based on the depth of the first blind hole 101 being ≥200nm, the inner diameter of the first blind hole 101 along the second direction changes little, which can avoid the phenomenon that the parasitic conductive channel is not completely destroyed due to the uneven structure of the first blind hole 101, thereby affecting the benefit of the air gap.

[0065] In order to increase the benefit of the air gap and better suppress the parasitic conductivity effect at the first interface, in some embodiments of the present application, the opening diameter of the first blind hole 101 is 100nm-1000nm. Controlling the opening diameter of the first blind hole 101 within the above range is not only easy to prepare, but more importantly, it can achieve a more ideal effect of cutting off the parasitic conductive channel. During the preparation process of the epitaxial wafer 100, the parameters of the first blind hole 101 are all inherited from the structure of the silicon substrate layer 10, but at least in some cases, the nucleation layer 201 is gradually grown on the first surface of the silicon substrate layer 10. The opening diameter of the first blind hole 101 may also affect the parameters of the second blind hole 210 (for example, depth) and the crystal quality of the nucleation layer 201. At this time, controlling the opening diameter of the first blind hole 101 within the above range can ensure that the subsequently grown nucleation layer 201 is easy to close and has good crystal quality. Specifically, the opening diameter of the first blind hole 101 can be, but is not limited to, 100 nm, 150 nm, 200 nm, 250 nm, 300 nm, 350 nm, 400 nm, 450 nm, 500 nm, 550 nm, 600 nm, 650 nm, 700 nm, 750 nm, 800 nm, 850 nm, 900 nm, 950 nm, 1000 nm, etc. In the embodiment of the present application, the opening diameter of the first blind hole 101 can be tested using an SEM. When the opening shape of the first blind hole 101 is circular, the opening diameter refers to the diameter of the opening; when the opening shape of the first blind hole 101 is an n-gon, the opening diameter refers to the diameter of the circumscribed circle of the n-gon.

[0066] Based on the epitaxial wafer 100 preparation technology and process parameters, at least in some cases, the second blind hole 210 is formed during the growth process of the nucleation layer 201. Therefore, the inner diameter of the second blind hole 210 may gradually decrease along the second direction, or may vary irregularly, and this application does not impose any limitations on this. In some specific embodiments, the inner diameter of the second blind hole 210 varies within a range of 100nm-1000nm along the second direction. Specifically, the inner diameter of the second blind hole 210 may be, but is not limited to, 100nm, 150nm, 200nm, 250nm, 300nm, 350nm, 400nm, 450nm, 500nm, 550nm, 600nm, 650nm, 700nm, 750nm, 800nm, 850nm, 900nm, 950nm, 1000nm, etc.

[0067] In some embodiments of the present application, in the first direction, multiple first blind holes 101 are arranged periodically. That is, multiple first blind holes 101 are arranged periodically on the first surface. This is to ensure the structural uniformity of the silicon substrate layer 10 and fully reduce the risk of cracks in subsequent applications due to uneven internal stress distribution or insufficient bearing capacity; it is also considered that there may be many repeating units in the RF device (a gate and the area where a drain and a source are located on both sides of it are regarded as the same repeating unit) or circuit elements. In order to ensure that in the subsequent application process, the parasitic conductive channels in different areas at the first interface are well cut off, the RF loss of the RF device can be better suppressed. It can be understood that the multiple second blind holes 210 correspond to the multiple first blind holes 101 one by one. At this time, the multiple second blind holes 210 are arranged periodically on the third surface. In other words, the air gap formed by the first blind holes 101 and the second blind holes 210 is arranged periodically at the first interface.

[0068] In some embodiments of the present application, in the first direction, a plurality of first blind holes 101 are arranged in a regular hexagonal periodic pattern. Specifically, the regular hexagonal periodic pattern can be understood as follows: except for the first blind holes 101 located at the edge of the epitaxial wafer 100, any first blind hole 101 is surrounded by six first blind holes 101, and the lines connecting the geometric centers of the openings of the six first blind holes 101 on the silicon substrate layer 10 in sequence form a regular hexagon. The first blind holes 101 are arranged in a regular hexagonal periodic pattern, which is beneficial to the subsequent growth of the epitaxial layer 20 and to ensuring that the crystal quality of the epitaxial layer 20 is good, thereby improving its power and efficiency when used in radio frequency devices. It can be understood that at this time, the air gap formed by the first blind hole 101 and the second blind hole 210 is arranged in a regular hexagonal periodic pattern at the first interface.

[0069] In some embodiments of the present application, referring to FIG1A , the arrangement period a of the first blind vias 101 is 200 nm to 1000 nm. Specifically, in the first direction, the minimum distance a between the openings of two adjacent first blind vias 101 on the silicon substrate layer 10 is 200 nm to 1000 nm. Controlling the arrangement period of the first blind vias 101 within the above range also controls the distribution density of the first blind vias 101 and the air gaps. Thus, when applied to radio frequency devices, it is beneficial to achieve air gaps within any repeating unit to suppress radio frequency losses, thereby improving the performance of the radio frequency device. Specifically, the arrangement period of the first blind vias 101 can be, but is not limited to, 200 nm, 250 nm, 300 nm, 350 nm, 400 nm, 450 nm, 500 nm, 550 nm, 600 nm, 650 nm, 700 nm, 750 nm, 800 nm, 850 nm, 900 nm, 950 nm, 1000 nm, etc. In some specific embodiments, referring to FIG1A , the plurality of first blind holes 101 are periodically arranged in a regular hexagonal pattern, and the arrangement period a is 200 nm to 1000 nm. Similarly, the arrangement period a of the air gaps formed by the first blind holes 101 and the second blind holes 210 is 200 nm to 1000 nm.

[0070] In the embodiment of the present application, the specific material of the nucleation layer 201 can be selected from the group III / V compounds available on the GaN-based epitaxial wafer 100. In some specific embodiments, the two-dimensional nucleation layer 201a is an aluminum nitride layer.

[0071] In some embodiments of the present application, the nucleation layer 201 is a two-dimensional nucleation layer. The two-dimensional nucleation layer has high crystal quality, so when the epitaxial wafer 100 is used in a radio frequency device, it can improve the power and efficiency of the radio frequency device, greatly enhance the device performance, and increase its market competitiveness.

[0072] In some specific embodiments of the present application, referring to FIG. 2 , the nucleation layer 201 is a two-dimensional nucleation layer, and the thickness of the nucleation layer 201 is 300 nm to 1000 nm. This ensures that the structural integrity of the nucleation layer 201 is high, and its inherent crystal quality is high, which is also more conducive to ensuring and improving the overall crystal quality of the epitaxial layer 20. Furthermore, the appropriate thickness can avoid the risk of cracking in the nucleation layer 201, thereby improving the overall performance of the epitaxial wafer 100. Specifically, the thickness of the nucleation layer 201 can be, but is not limited to, 300 nm, 350 nm, 400 nm, 450 nm, 500 nm, 550 nm, 600 nm, 650 nm, 700 nm, 750 nm, 800 nm, 850 nm, 900 nm, 950 nm, 1000 nm, etc.

[0073] In some embodiments of the present application, referring to FIG3 , the nucleation layer 201 includes a two-dimensional nucleation layer 201a and a three-dimensional nucleation layer 201b stacked in sequence, with the two-dimensional nucleation layer 201a disposed adjacent to the silicon substrate layer 10. The two-dimensional nucleation layer 201a is a nucleation layer 201 formed by atoms growing primarily along the first direction, while the three-dimensional nucleation layer 201b is a nucleation layer 201 formed by atoms growing simultaneously in the first and second directions. First, growing the two-dimensional nucleation layer 201a on the surface of the silicon substrate layer 10 can reduce the nucleation conduction density, dislocation density, and crystal size, thereby improving the crystal quality of the nucleation layer 201. This can further improve the crystal quality of other epitaxial layers 20 subsequently grown on the surface of the nucleation layer 201, thereby enhancing the power and efficiency of the final RF device. Based on the above differences, the crystal quality of the two-dimensional nucleation layer 201a is relatively higher, and its arrangement close to the silicon substrate layer 10 can ensure the better quality of the epitaxial wafer 100; the growth rate of the three-dimensional nucleation layer 201b is relatively fast, so at this time, the production efficiency of the epitaxial wafer 100 can be improved while taking into account the quality of the epitaxial wafer 100.

[0074] In some specific embodiments, the thickness of the two-dimensional nucleation layer 201a is 300nm-500nm, and the thickness of the three-dimensional nucleation layer 201b is 200nm-500nm. This improves the crystal quality of the nucleation layer 201 while also increasing the production efficiency of the epitaxial wafer 100, further facilitating the preparation and application of the epitaxial wafer 100. Specifically, in the above case, the thickness of the two-dimensional nucleation layer 201a can be, but is not limited to, 300nm, 320nm, 350nm, 380nm, 400nm, 420nm, 450nm, 480nm, or 500nm; the thickness of the three-dimensional nucleation layer 201b can be, but is not limited to, 200nm, 220nm, 250nm, 280nm, 300nm, 320nm, 350nm, 380nm, 400nm, 420nm, 450nm, 480nm, or 500nm.

[0075] In some embodiments, the two-dimensional nucleation layer 201a and the three-dimensional nucleation layer 201b are both made of aluminum nitride. Aluminum nitride has a wide band gap (up to 6.2 eV) and possesses high electrical resistance, high hardness, high chemical stability, high breakdown electric field, and low dielectric loss, which can further enhance the performance of the final RF device.

[0076] The high crystal quality of the two-dimensional nucleation layer 201a can be specifically reflected in the dislocation density and surface roughness. In some specific embodiments of the present application, the dislocation density of the two-dimensional nucleation layer 201a is less than 5×10 9 / cm 2 , for example, 1.5×10 9 / cm 2 -3×10 9 / cm2 The surface roughness of the two-dimensional nucleation layer 201a is less than 0.5 nm, for example, 0.2 nm to 0.35 nm. The dislocation density is defined as the total length of dislocation lines contained in a unit volume of a crystal, or the number of dislocation lines passing through a unit cross-sectional area of ​​a crystal. Specifically, the dislocation density of the two-dimensional nucleation layer 201a can be tested using a transmission electron microscope (TEM); the surface roughness of the two-dimensional nucleation layer 201a can be tested using an atomic force microscope (AFM).

[0077] In an embodiment of the present application, when a second blind hole 210 is provided on the third surface of the nucleation layer 201, and the nucleation layer 201 includes a stacked two-dimensional nucleation layer 201a and a three-dimensional nucleation layer 201b, the following situations may be included: the second blind hole 210 penetrates the two-dimensional nucleation layer 201a and extends into the three-dimensional nucleation layer 201b; or, the second blind hole 210 does not penetrate the two-dimensional nucleation layer 201a.

[0078] In some embodiments of the present application, the molar ratio of the group V elements to the group III elements in the two-dimensional nucleation layer 201a is 1:(20-100). For example, when the material of the two-dimensional nucleation layer 201a is AlN, the molar ratio of the N element to the Al element in the two-dimensional nucleation layer 201a is 1:(20-100). In this way, it is easy to obtain the two-dimensional nucleation layer 201a, which is beneficial to improving the crystal quality of the epitaxial wafer 100 and the power and efficiency of the final RF device. Specifically, in the two-dimensional growth layer, the molar ratio of the group V elements to the group III elements can be, but is not limited to, 1:20, 1:30, 1:40, 1:50, 1:60, 1:70, 1:80, 1:90, 1:95, 1:98, etc.

[0079] In some embodiments of the present application, the molar ratio of the Group V element to the Group III element in the three-dimensional nucleation layer 201b is 1:(100-2000). For example, when the three-dimensional nucleation layer 201b is made of AlN, the molar ratio of the N element to the Al element in the three-dimensional nucleation layer 201b is 1:(100-2000). This facilitates the production of the three-dimensional nucleation layer 201b and improves the production efficiency of the epitaxial wafer 100. Specifically, in the three-dimensional nucleation layer 201b, the amount ratio of group V elements to group III elements can be, but is not limited to, 1:120, 1:150, 1:180, 1:200, 1:250, 1:300, 1:350, 1:400, 1:500, 1:600, 1:700, 1:800, 1:900, 1:1000, 1:1200, 1:1500, 1:1800, etc.

[0080] In some embodiments of the present application, the room-temperature resistivity of the silicon substrate layer 10 is greater than or equal to 2000 Ω·cm. For example, it is between 3000 Ω·cm and 5000 Ω·cm, or greater than 5000 Ω·cm. This can reduce RF losses caused by the silicon substrate layer 10 itself and improve the performance of the final RF device.

[0081] In the embodiments of the present application, the thickness of the silicon substrate layer 10 is not specifically limited and can be any thickness known in the art. However, it is understood that since the depth of the first blind hole 101 is ≥ 200 nm, the thickness of the silicon substrate layer 10 is at least > 200 nm. For example, the thickness of the silicon substrate layer 10 can be 100 μm to 1000 μm.

[0082] In some embodiments of the present application, referring to Figures 4-5, the epitaxial layer 20 also includes a stress regulation layer 202, a high-resistance buffer layer 203, a channel layer 204, an insertion layer 205, a barrier layer 206 and a cap layer 207 stacked in sequence; wherein the stress regulation layer 202 is arranged on the surface of the nucleation layer 201 away from the silicon substrate layer 10. In this case, the epitaxial wafer 100 includes a silicon substrate layer 10, a nucleation layer 201 (the nucleation layer 201 is a two-dimensional nucleation layer), a stress regulation layer 202, a high-resistance buffer layer 203, a channel layer 204, an insertion layer 205, a barrier layer 206, and a cap layer 207, which are stacked in sequence, and a plurality of air gaps are periodically arranged at the interface between the silicon substrate layer 10 and the nucleation layer 201; or, the epitaxial wafer 100 includes a silicon substrate layer 10, a two-dimensional nucleation layer 201a, a three-dimensional nucleation layer 201b, a stress regulation layer 202, a high-resistance buffer layer 203, a channel layer 204, an insertion layer 205, a barrier layer 206, and a cap layer 207, which are stacked in sequence, and a plurality of air gaps are periodically arranged at the interface between the silicon substrate layer 10 and the two-dimensional nucleation layer 201a. The cap layer 207 can be used to provide an ohmic contact.

[0083] The above-mentioned stress control layer 202 includes but is not limited to a single layer of GaN, a single layer of AlGaN, a multi-layer Al composition gradient AlGaN layer, an Al composition linear gradient AlGaN layer, an AlN / GaN superlattice layer, an AlGaN / GaN superlattice layer, and an AlN / AlGaN superlattice layer. In the embodiment of the present application, there is no specific restriction on the thickness of the stress control layer 202, and ordinary technicians in this field can adjust it according to actual application needs. Specifically, the thickness of the stress control layer 202 can be 50nm-1000nm. In the embodiment of the present application, there is no restriction on the thickness of the AlN / GaN superlattice layer, the AlGaN / GaN superlattice layer, the AlN single layer, the GaN single layer, the AlGaN single layer in the AlN / AlGaN superlattice layer, and the number of repetition periods of the above-mentioned superlattice layers.

[0084] The above-mentioned high-resistance buffer layer 203 includes but is not limited to an AlGaN layer (Al% <10%) and a GaN layer. In some specific embodiments, when the high-resistance buffer layer 203 includes an AlGaN layer, the molar content of Al in the AlGaN layer is <10%, for example, 1%, 2%, 5%, 6%, 8%, etc. In this way, it is beneficial to improve the resistivity of the AlGaN layer, ensure the good quality of the AlGaN layer, and avoid introducing parallel channels in the epitaxial wafer 100, thereby helping to ensure the performance of the final RF device. In the embodiment of the present application, there is no specific restriction on the thickness of the high-resistance buffer layer 203, and ordinary technicians in this field can adjust it according to actual application needs. Specifically, the thickness of the high-resistance buffer layer 203 can be 200nm-2000nm.

[0085] The channel layer 204 includes, but is not limited to, a GaN layer. In the embodiments of the present application, the thickness of the channel layer 204 is not specifically limited, and can be adjusted by a person skilled in the art based on actual application needs. Specifically, the thickness of the channel layer 204 can be 150 nm to 400 nm.

[0086] The insertion layer 205 includes, but is not limited to, an AlN layer. In the present embodiment, the thickness of the insertion layer 205 is not specifically limited, and can be adjusted by a person skilled in the art based on actual application needs. Specifically, the thickness of the insertion layer 205 can be 0.5 nm to 1.5 nm.

[0087] The barrier layer 206 includes, but is not limited to, a III-N barrier layer 206 , such as an AlN layer, an AlGaN layer, an InAlN layer, or an InAlGaN layer. In the present embodiment, the thickness of the barrier layer 206 is not specifically limited, and can be adjusted by a person skilled in the art based on actual application requirements. Specifically, the thickness of the barrier layer 206 can range from 5 nm to 30 nm.

[0088] The cap layer 207 includes but is not limited to a GaN layer. In the embodiment of the present application, there is no specific limitation on the thickness of the cap layer 207 , and those skilled in the art can adjust it according to actual application needs. Specifically, the thickness of the GaN cap layer can be 1 nm to 5 nm.

[0089] The present embodiment further provides a method for preparing an epitaxial wafer, which can be used to prepare the aforementioned epitaxial wafer 100, comprising:

[0090] S01. Providing a silicon substrate, forming a plurality of first blind holes on one surface of the silicon substrate, wherein the depth of the first blind holes is ≥200 nm, to obtain a silicon substrate layer;

[0091] S02. Growing an epitaxial layer on the surface of the silicon substrate layer having the first blind hole (i.e., the aforementioned first surface), the epitaxial layer including a nucleation layer. On a non-close-packed crystal plane, atoms are largely unable to settle, so the first blind hole can be retained in the resulting epitaxial wafer, and a second blind hole is formed during the closing process of the nucleation layer. In some embodiments, a second blind hole is formed at a corresponding position to any first blind hole.

[0092] The preparation method has simple steps, strong process controllability, high production efficiency, and is suitable for large-scale industrial production.

[0093] In some embodiments of the present application, in step S01 , the method of forming the plurality of first blind holes on the first surface includes but is not limited to nanoimprinting, etching, electrochemical corrosion, etc.

[0094] In some embodiments of the present application, before performing step S02, the silicon substrate having the first blind hole is surface treated, and the surface treatment method includes but is not limited to cleaning with at least one of organic solvents such as acetone, ethanol, isopropanol, etc., and then cleaning with hydrofluoric acid, or an aqueous solution of hydrofluoric acid and hydrochloric acid, or Piranha solution, and then rinsing with deionized water and drying.

[0095] In some embodiments of the present application, in step S02, a vapor phase epitaxial process is used to grow an epitaxial layer.

[0096] In some embodiments of the present application, in step S02 , growing an epitaxial layer on the first surface includes: growing a two-dimensional nucleation layer on the first surface.

[0097] In some specific embodiments, growing a two-dimensional nucleation layer on the first surface includes placing a silicon substrate in a reaction chamber, introducing a growth material required for growing the two-dimensional nucleation layer into the reaction chamber, controlling the molar ratio of group V elements to group III elements in the growth material to be 1:(20-100), a growth temperature of 900°C-1200°C, and a growth pressure (pressure in the reaction chamber) of 50mbar-100mbar. In this way, atoms can be induced to migrate laterally, thereby inducing lateral atomic growth, thereby facilitating the production of a two-dimensional nucleation layer, reducing the density of its nucleation islands and increasing the size of the nucleation islands, thereby reducing the dislocation density introduced by the closure of islands in the early stages of growth of the two-dimensional nucleation layer, and thereby facilitating the improvement of the crystal quality of the two-dimensional nucleation layer. Specifically, the amount ratio of the V group element (for example, N element) to the III group element (for example, Al element) in the growth raw material can be, but is not limited to, 1:20, 1:30, 1:40, 1:50, 1:60, 1:70, 1:80, 1:90, 1:95, 1:98. The growth temperature of the two-dimensional nucleation layer can be, but is not limited to, 900°C, 920°C, 950°C, 980°C, 1000°C, 1020°C, 1050°C, 1080°C, 1100°C, 1120°C, 1150°C, 1180°C, 1200°C, etc. The growth pressure of the two-dimensional nucleation layer can be, but is not limited to, 5mbar, 60mbar, 80mbar, 100mbar, etc. In some specific embodiments of the present application, the nucleation island density is 10 10 cm 2 -5×10 10 cm 2 , the size of the nucleation islands is 10nm-50nm. Specifically, in the above steps, the growth of the two-dimensional nucleation layer is interrupted and the density and size of the nucleation islands are measured using SEM or AFM.

[0098] In some embodiments of the present application, in step S02, growing an epitaxial layer on the first surface includes sequentially growing a two-dimensional nucleation layer and a three-dimensional nucleation layer on the first surface. In some specific embodiments, after the two-dimensional growth layer is formed, the temperature and pressure in the reaction chamber are changed, and the growth raw materials are adjusted to grow the three-dimensional nucleation layer, wherein the growth temperature of the three-dimensional nucleation layer is 900°C-1100°C, the growth pressure is 100mbar-300mbar, and the molar ratio of the group V elements to the group III elements in the growth raw materials is 1:(100-2000). In this way, atoms can be induced to grow both horizontally and vertically simultaneously, thereby increasing the growth rate of the nucleation layer and thereby improving the production efficiency of the epitaxial wafer.

[0099] Specifically, the molar ratio of the Group V element (e.g., N) to the Group III element (e.g., Al) in the growth material of the three-dimensional nucleation layer may be, but is not limited to, 1:120, 1:150, 1:180, 1:200, 1:250, 1:300, 1:350, 1:400, 1:500, 1:600, 1:700, 1:800, 1:900, 1:1000, 1:1200, 1:1500, or 1:1800. The growth temperature of the three-dimensional nucleation layer may be, but is not limited to, 900° C., 920° C., 950° C., 980° C., 1000° C., 1020° C., 1050° C., 1080° C., or 1100° C. The growth pressure of the three-dimensional nucleation layer may be, but is not limited to, 100 mbar, 120 mbar, 150 mbar, 180 mbar, 200 mbar, 220 mbar, 250 mbar, 280 mbar, 300 mbar, etc.

[0100] In the above steps, the aforementioned growth raw materials can be selected from materials known to those skilled in the art based on the composition of the nucleation layer, as long as they can successfully grow the nucleation layer. When the nucleation layer is an AlN layer, the growth raw materials include an aluminum source and a nitrogen source, wherein the aluminum source includes but is not limited to trimethylaluminum, and the nitrogen source includes but is not limited to ammonia.

[0101] In some embodiments of the present application, step S02 further includes sequentially growing a stress control layer, a high-resistance buffer layer, a channel layer, an insertion layer, a barrier layer, and a cap layer on the surface of the nucleation layer facing away from the silicon substrate layer.

[0102] In the above step S02, when growing the stress control layer, high-resistance buffer layer, channel layer, insertion layer, barrier layer and cap layer, the growth materials and process parameter control required for each of them can be any growth materials and process parameters known in the field, and those skilled in the art can select and adjust them according to application needs.

[0103] Referring to Figure 6, an embodiment of the present application further provides a radio frequency device 1, comprising a drain 2, a source 3, a gate 4, and an epitaxial wafer 100 provided in an embodiment of the present application. The drain 2, source 3, and gate 4 are arranged on the surface of the epitaxial layer 20 facing away from the silicon substrate layer 10, and the drain 2 and source 3 are arranged on opposite sides of the gate 4 and are isolated from each other. Due to the use of the epitaxial wafer 100 provided in an embodiment of the present application, the radio frequency device 1 has low radio frequency loss, low production cost, and can be prepared in a larger size, thus having good market competitiveness. In some specific embodiments, the radio frequency device 1 is a power amplifier.

[0104] In some embodiments of the present application, the drain electrode 2 is in contact with the cap layer 207, the source electrode 3 is in contact with the cap layer 207, and an ohmic contact is formed between the source electrode 3 and the cap layer 207, and an ohmic contact is formed between the drain electrode 2 and the cap layer 207. The materials of the source electrode 3 and the drain electrode 2 can be a Ti layer, an Al layer, a Ni layer, and an Au layer stacked in sequence.

[0105] In some embodiments of the present application, the RF device 1 further includes a passivation layer 6, which is disposed on the surface of the epitaxial layer 201 facing away from the silicon substrate layer 10. The passivation layer 6 is provided with a plurality of openings, and the drain 2, source 3, and gate 4 are respectively located within these openings. The passivation layer 6 can suppress the trapping effect of surface states, thereby improving the performance of the RF device 1. In the embodiments of the present application, the material of the passivation layer 6 is not limited; those skilled in the art may select a material according to actual needs. For example, SiO2, SiNx, etc.

[0106] In some embodiments of the present application, interconnect metal 5 is provided on the surface of the source electrode 3, the drain electrode 2, and the gate electrode 4 facing away from the epitaxial wafer 100, and the interconnect metal 5 is exposed through the passivation layer 6. A single RF device 1 may have multiple repeating units or circuit elements. The interconnect metal 5 is used to connect different repeating units or circuit elements, transmit electronic signals, and provide power. The material of the interconnect metal 5 can be a conductive metal commonly used in the art, such as copper and gold.

[0107] In some embodiments of the present application, referring to FIG. 7 , the preparation of the radio frequency device 1 may include:

[0108] S11, preparing an ohmic contact on the surface of the epitaxial wafer 100 facing away from the silicon substrate layer 10 to obtain a drain electrode 2 and a source electrode 3;

[0109] S12. Considering that multiple groups of radio frequency devices 1 can be fabricated simultaneously on one epitaxial wafer 100, different regions are insulated and isolated to prevent mutual influence between the multiple devices.

[0110] S13, preparing a passivation layer 6 and performing a hole opening process;

[0111] S14, performing gate groove etching and gate preparation.

[0112] In some embodiments of the present application, the method further includes S15: forming interconnect metals 5 on the surfaces of the source 3 , the drain 2 , and the gate 4 facing away from the epitaxial wafer 100 .

[0113] In some embodiments of the present application, at least one first blind hole is included between the orthographic projection of the drain electrode 2 on the silicon substrate layer 10 and the orthographic projection of the gate electrode 4 on the silicon substrate layer 10. In this way, each repeating unit of the RF device 1 includes at least one air gap, thereby effectively suppressing the RF loss of any repeating unit and significantly reducing the RF loss of the RF device. The air gap can be formed by the first blind hole or by both the first blind hole and the second blind hole.

[0114] In some specific embodiments of the present application, the above effect can be achieved by regulating the arrangement period of the first blind holes (that is, the arrangement period of the air gaps) and the distance between the source and the drain. Specifically, the arrangement period of the first blind holes is a, the distance between the source and the drain is b, and the opening diameter of the first blind hole is c, then a, b, c satisfy b≥a+2c, where a, b, c are measured in the same unit. In some specific embodiments, the distance b between the source and the drain is 1μm-3μm. In this way, it is easy to manufacture and helps to ensure the performance of the RF device.

[0115] An embodiment of the present application also provides a terminal radio frequency module, including the radio frequency device and antenna provided in the embodiment of the present application, wherein the radio frequency device is used to amplify the radio frequency signal and output it to the antenna for outward radiation.

[0116] In some specific embodiments, the terminal RF module is a 5G RF module.

[0117] The present application also provides a terminal device including the terminal radio frequency module provided in the present application. Due to the terminal radio frequency module provided in the present application, the terminal device has good market competitiveness. In some specific embodiments, the terminal device includes but is not limited to a mobile phone.

[0118] In the embodiment of the present application, “-” represents a range value, including the endpoint values ​​at both ends. For example, the value of a can be 0.5-15, which means that the value of a can be between 0.5 and 15, and includes the endpoint values ​​0.5 and 15.

Claims

1. An epitaxial wafer, characterized in that: It comprises a stacked silicon substrate layer and an epitaxial layer, wherein the epitaxial layer comprises a nucleation layer stacked on the surface of the silicon substrate; The surface of the silicon substrate layer close to the nucleation layer has a plurality of first blind holes, and the surface of the nucleation layer close to the silicon substrate layer has a plurality of second blind holes, any of the second blind holes is arranged corresponding to one of the first blind holes, and the orthographic projection of the second blind hole on the silicon substrate layer overlaps with the corresponding first blind hole; Wherein, the depth of the first blind hole is greater than or equal to 200 nm.

2. The epitaxial wafer according to claim 1, characterized in that: The depth of the first blind hole is 200nm-500nm.

3. The epitaxial wafer according to claim 1 or 2, characterized in that: The number of the second blind holes is the same as the number of the first blind holes, and the plurality of the first blind holes and the plurality of the second blind holes are arranged in a one-to-one correspondence.

4. The epitaxial wafer according to any one of claims 1 to 3, characterized in that: The depth of the second blind hole is 300nm-500nm.

5. The epitaxial wafer according to any one of claims 1 to 4, characterized in that: The inner diameter of the first blind hole is equal everywhere along the stacking direction of the silicon substrate layer and the epitaxial layer.

6. The epitaxial wafer according to any one of claims 1 to 5, characterized in that: The angle between the side wall of the first blind hole and the surface of the silicon substrate layer close to the nucleation layer is 85°-90°.

7. The epitaxial wafer according to any one of claims 1 to 6, characterized in that: The opening diameter of the first blind hole is 100nm-1000nm.

8. The epitaxial wafer according to any one of claims 1 to 7, characterized in that: The opening of the first blind hole is circular or n-gonal, wherein n>8.

9. The epitaxial wafer according to any one of claims 1 to 8, characterized in that: In a first direction, the plurality of first blind holes are arranged periodically; wherein the first direction is perpendicular to a stacking direction of the silicon substrate layer and the nucleation layer; Along the first direction, a minimum distance between openings of two adjacent first blind holes on the silicon substrate layer is 200 nm-1000 nm.

10. The epitaxial wafer according to claim 9, characterized in that: In the first direction, the plurality of first blind holes are periodically arranged in a regular hexagon.

11. The epitaxial wafer according to any one of claims 1 to 10, characterized in that: The nucleation layer is a two-dimensional nucleation layer.

12. The epitaxial wafer according to claim 11, characterized in that: The thickness of the nucleation layer is 300nm-1000nm.

13. The epitaxial wafer according to any one of claims 1 to 10, characterized in that: The nucleation layer includes a two-dimensional nucleation layer and a three-dimensional nucleation layer stacked in sequence, and the two-dimensional nucleation layer is arranged close to the silicon substrate layer.

14. The epitaxial wafer according to claim 13, characterized in that: The thickness of the two-dimensional nucleation layer is 300nm-500nm; the thickness of the three-dimensional nucleation layer is 200nm-500nm.

15. The epitaxial wafer according to any one of claims 1 to 14, characterized in that: The nucleation layer is an aluminum nitride layer.

16. The epitaxial wafer according to any one of claims 11 to 15, characterized in that: The dislocation density of the two-dimensional nucleation layer is less than 5×10 9 / cm 2 ; The surface roughness of the two-dimensional nucleation layer is less than 0.5nm.

17. The epitaxial wafer according to any one of claims 11 to 16, characterized in that: The molar ratio of the group V elements to the group III elements in the two-dimensional nucleation layer is 1:(20-100).

18. The epitaxial wafer according to any one of claims 13 to 14, characterized in that: The molar ratio of the group V elements to the group III elements in the three-dimensional nucleation layer is 1:(100-2000).

19. The epitaxial wafer according to any one of claims 1 to 18, characterized in that: The epitaxial layer also includes a stress regulating layer, a high resistance buffer layer, a channel layer, an insertion layer, a barrier layer and a cap layer which are stacked in sequence; Wherein, the stress regulating layer is arranged on a surface of the nucleation layer away from the silicon substrate layer.

20. The epitaxial wafer according to any one of claims 1 to 19, characterized in that: The room temperature resistivity of the silicon substrate layer is greater than or equal to 2000Ω·cm.

21. The method for preparing an epitaxial wafer according to any one of claims 1 to 20, characterized in that: include: Providing a silicon substrate, and forming a plurality of the first blind holes on a surface of one side of the silicon substrate to obtain the silicon substrate layer; The epitaxial layer is grown on the surface of the silicon substrate layer having the first blind hole, and the epitaxial layer includes the nucleation layer.

22. The preparation method according to claim 21, characterized in that: The step of growing the nucleation layer on the surface of the silicon substrate layer having the first blind hole comprises: A two-dimensional nucleation layer is grown on the surface of the silicon substrate layer having the first blind hole; the growth temperature of the two-dimensional nucleation layer is 1000°C-1200°C, the growth pressure is 50mbar-100mbar, and the amount of substance ratio of the group V elements to the group III elements in the growth raw material is 1:(20-100).

23. The preparation method according to claim 22, characterized in that: It also includes growing a three-dimensional nucleation layer on the surface of the two-dimensional nucleation layer away from the silicon substrate layer; the growth temperature of the three-dimensional nucleation layer is 900℃-1100℃, the growth pressure is 100mbar-300mbar, and the amount of substance ratio of group V elements to group III elements in the growth raw material is 1:(100-2000).

24. A radio frequency device, characterized in that: It includes a drain, a source, a gate and an epitaxial wafer as described in any one of claims 1 to 20; the drain, source and gate are arranged on the surface of the epitaxial layer away from the silicon substrate layer, and the drain and the source are arranged on opposite sides of the gate and isolated from each other.

25. The radio frequency device according to claim 24, characterized in that: The drain electrode includes at least one first blind hole between an orthographic projection of the drain electrode on the silicon substrate layer and an orthographic projection of the gate electrode on the silicon substrate layer.

26. A terminal radio frequency module, characterized in that: It comprises the radio frequency device and antenna as described in claim 24 or 25, wherein the radio frequency device is used to amplify the radio frequency signal and output it to the antenna for outward radiation.

27. A terminal device, characterized in that: Including the terminal radio frequency module as described in claim 26.

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