Device and method for mitigating multipath interference

Abstract

A device for mitigating multipath interference in a direct-detection receiver is provided, comprising an interleaver, a filter, an equalizer and a deinterleaver. The interleaver receives one or more input blocks of symbols, the one or more input blocks and the respective symbols being received in sequential order, arranges the received symbols into one or more even blocks and one or more odd blocks, and further provides the one or more even and odd blocks to a filter. The equalizer processes one or more even blocks and one or more odd blocks of symbols after being filtered by the filter. The deinterleaver receives one or more even blocks and one or more odd blocks of symbols after being processed by the equalizer, and arranges them into one or more output blocks of symbols that are output in a same sequential order as the symbols received by the interleaver.

Description

[0001] DEVICE AND METHOD FOR MITIGATING MULTIPATH INTERFERENCE

[0002] TECHNICAL FIELD

[0003] The present disclosure relates to a device for mitigating multipath interference (MPI) in a direct-detection receiver within an intensity-modulation optical transmission system. The disclosure further provides a corresponding method for a device for mitigating MPI in a direct-detection receiver within an intensity-modulation optical transmission system, and a computer program product to perform the method.

[0004] BACKGROUND

[0005] Optical MPI appears in optical links, for example within datacenters and other short reach optical interconnect scenarios. It typically occurs due to dirty end-facets of optical connectors, as well as splices along a fiber link. Furthermore, reflectance at transmitter interfaces and at receiver interfaces leads to additional reflections of the travelling optical waves. At the receiver, a transmitted signal and its reflected copies interfere after direct detection. The interference of both signals results in a low frequency noise component.

[0006] Conventional Digital Signal Processors (DSPs) in direct-detection receivers include feedforward equalization, noise-whitening filtering (or post-filtering) and Maximum Likelihood Sequence Estimation (MLSE) / Maximum A-posteriori Probability (MAP) blocks. The memory of the noise-whitening filter and the MLSE / MAP is typically restricted to a single symbol and is mainly utilized to whiten the high-frequency noise. The high-frequency noise before the noise-whitening filter is enhanced due to bandwidth limitation of electro-optical components and the minimum mean squared error (MMSE) based feed forward equalizer (FFE) in high-speed transceivers.

[0007] Since MPI results in a low-frequency noise component, MPI is not inherently mitigated by the usual single-memory noise-whitening filter and the following MLSE / MAP blocks.

[0008] FIG. 5 shows a conventional DSP block processing architecture. For illustration purposes, only four parallel processing lanes are shown in FIG. 5. However, an actual number of parallel block processing lanes depends on a ratio of symbol-rate to an application-specific integrated circuit (ASIC) clock rate, which can be larger than 100. In this conventional architecture, the first N symbols are processed by the upper lane, the next N symbols by the second lane, and so on. The blocks 501 of N symbols go through a noise-whitening filter 502 with memory 1 followed by an MLSE / MAP equalizer 503. Each parallel processing lane outputs N symbols 504 in parallel. The equalizer 503 may include an algorithm for MAP detection, for example a BCJR algorithm.

[0009] In order to suppress both low-frequency and high-frequency noise components as well as interference terms in the conventional DSP architectures, as e.g. the one depicted in FIG. 5, low-pass and high-pass filters are required. In the conventional DSP architectures, this may be achieved by increasing the memory of the noise-whitening filter and the MLSE / MAP blocks. However, this results in a huge increment of MLSE / MAP complexity, limiting the implementation of DSPs with MPI.

[0010] Conventional solutions based on MLSE / MAP for mitigating MPI are too complex, provide limited improvement, require receiver hardware modifications and lead to excessively high- power consumption, making them unfeasible to implement.

[0011] SUMMARY

[0012] In view of the above, this disclosure aims to improve conventional solutions for mitigating MPI in DSP. An objective is to effectively mitigate MPI with minimal architectural modifications and with low complexity and, thus, to enable a friendly implementation of DSPs.

[0013] These and other objectives are achieved by the solutions of this disclosure as described in the independent claims. Advantageous implementations are further defined in the dependent claims.

[0014] According to a first aspect, a device for mitigating MPI in a direct-detection receiver within an intensity-modulation optical transmission system is provided. The device includes an interleaver, a filter, an equalizer and a deinterleaver. The interleaver is configured to: receive one or more input blocks of symbols, each input block comprising a number N of symbols, wherein N is an integer number, and wherein the one or more input blocks and the respective N symbols are received in sequential order; arrange the received symbols into one or more even blocks of symbols and into one or more odd blocks of symbols, each even block comprising N different even symbols of the received sequentially ordered symbols, and each odd block comprising N different odd symbols of the sequentially ordered symbols; and provide to the filter, in a parallel manner, the one or more even blocks of symbols and the one or more odd blocks of symbols.

[0015] The equalizer is configured to process one or more even blocks of symbols and one or more odd blocks of symbols after being filtered by the filter. Further, the deinterleaver is configured to: receive from the equalizer, in a parallel manner, one or more even blocks of symbols and one or more odd blocks of symbols after being processed by the equalizer; arrange the received one or more even blocks of symbols and the received one or more odd blocks of symbols processed by the equalizer into one or more output blocks of symbols, each of the output blocks comprising N symbols, and wherein the one or more output symbols are output in a same sequential order as the symbols are received by the interleaver; and provide the one or more output blocks as an output.

[0016] In this disclosure, the terms even symbol an odd symbol refer to the order in which a symbol is received, irrespective of a value of the symbol.

[0017] As the interleaver is placed before the filter, first even N symbols can be provided to the filter in a first lane, first N odd symbols can be provided in a second lane, and so on. After the symbols are filtered by the filter and subsequently processed by the equalizer, the deinterleaver can effectively reverse the effect of the even-odd interleaver and the processed symbols are arranged again in the sequential (correct) sequence in which the input symbols are received by the interleaver. Due to this architectural change, the filter and the equalizer are able to mitigate interference from every second symbol, thereby suppressing both high-frequency and low- frequency noise components. Consequently, low-frequency interference mitigation and high- frequency noise suppression are achieved without increasing the memory of the filter and the equalizer.

[0018] In an implementation form of the first aspect, arranging the received symbols into the one or more even blocks of symbols and into the one or more odd blocks of symbols, includes: choosing first N even symbols of the received sequentially ordered symbols and arranging them in a first even block; choosing next N even symbols of the received sequentially ordered symbols and arranging them in a next even block; choosing first N odd symbols of the received sequentially ordered symbols and arranging them in a first odd block; and choosing next N odd symbols of the received sequentially ordered symbols and arranging them in a next odd block.

[0019] In an implementation form of the first aspect, arranging the received one or more even blocks of symbols and the received one or more odd blocks of symbols processed by the equalizer into the one or more output blocks of symbols includes: combining the received even symbols and the received odd symbols processed by the equalizer in the same sequential order as the symbols are received by the interleaver; choosing first N symbols of the combined sequentially ordered symbols and arranging them into a first output block; and choosing next N symbols of the combined sequentially ordered symbols and arranging them into a next output block.

[0020] In an implementation form of the first aspect, the device is further configured to enable or disable the interleaver and the deinterleaver based on link conditions.

[0021] That is, the interleaver and the deinterleaver can be turned on and off, optionally bypassed. When they are turned off, the conventional DSP architecture is revived. This is beneficial because the device can operate in a conventional manner when there is no MPI or when there is low MPI in an optical link, without the need to implement further architectural modifications in the device. Thereby, the device has a flexible design.

[0022] In an implementation form of the first aspect, the filter includes a single-tap noise-whitening filter.

[0023] In an implementation form of the first aspect, the equalizer includes one or more MLSE blocks and / or one or more MAP blocks.

[0024] By using conventional filters and conventional MLSE / MAP blocks, there is no additional increase in the computational complexity. Moreover, the device may be fully compatible with existing technologies and implementations.

[0025] According to a second aspect, a method for a device for mitigating MPI in a direct-detection receiver within an intensity-modulation optical transmission system is provided. The method includes: receiving, with an interleaver, one or more input blocks of symbols, each input block comprising a number N of symbols, wherein N is an integer number, and wherein the one or more input blocks and the respective N symbols are received in sequential order; arranging, with the interleaver, the received symbols into one or more even blocks of symbols and into one or more odd blocks of symbols, each even block comprising N different even symbols of the received sequentially ordered symbols, and each odd block comprising N different odd symbols of the sequentially ordered symbols; providing to a filter, with the interleaver, in a parallel manner, the one or more even blocks of symbols and the one or more odd blocks of symbols.

[0026] Further, the method comprises: processing, with an equalizer, the one or more even blocks of symbols and the one or more odd blocks of symbols after being filtered by the filter; receiving from the equalizer, with a deinterleaver in a parallel manner, the one or more even blocks of symbols and the one or more odd blocks of symbols after being processed by the equalizer; arranging, with the deinterleaver, the received one or more even blocks of symbols and the received one or more odd blocks of symbols processed by the equalizer into one or more output blocks of symbols, each of the output blocks comprising N symbols, wherein the one or more output symbols are output in a same sequential order as the symbols are received by the interleaver; and providing, with the deinterleaver, the one or more output blocks as an output.

[0027] In an implementation form of the second aspect, the arranging the received symbols into the one or more even blocks of symbols and into the one or more odd blocks of symbols, includes: choosing first N even symbols of the received sequentially ordered symbols and arranging them in a first even blocks; choosing next N even symbols of the received sequentially ordered symbols and arranging them in a next even block; choosing first N odd symbols of the received sequentially ordered symbols and arranging them in a first odd block; and choosing next N odd symbols of the received sequentially ordered symbols and arranging them in a next odd block.

[0028] In an implementation form of the second aspect, the arranging the received one or more even blocks of symbols and the received one or more odd blocks of symbols processed by the equalizer into the one or more output blocks of symbols includes: combining the received even symbols and the received odd symbols processed by the equalizer in the same sequential order as the symbols are received by the interleaver; choosing first N symbols of the combined sequentially ordered symbols and arranging them into a first output block; and choosing next N symbols of the combined sequentially ordered symbols and arranging them into a next output block.

[0029] In an implementation form of the second aspect, the method further comprises enabling or disabling the interleaver and the deinterleaver based on link conditions.

[0030] That is, the interleaver and the deinterleaver can be turned on and off, optionally bypassed. When they are turned off, the conventional DSP architecture is revived. This is beneficial because a conventional operation is achieved when there is no MPI or when there is low MPI in an optical link, without the need to implement further modifications.

[0031] In an implementation form of the second aspect, the filter includes a single tap noise-whitening filter.

[0032] In an implementation form of the second aspect, the equalizer includes one or more MLSE blocks and / or one or more MAP blocks.

[0033] By using conventional filters and conventional MLSE / MAP blocks, there is no additional increase in the computational complexity.

[0034] The method according to the second aspect comprises the features of the corresponding implementation forms of the device of the second aspect.

[0035] According to a third aspect, a computer program is provided. The computer program includes instructions which, when the program is executed by a computer, cause the computer to carry out the method according to the second aspect and its implementation forms.

[0036] The method according to the second aspect and the computer program according to the third aspect and their implementation forms provide the same advantages and effects as described above for the device of the first aspect and its respective implementation forms.

[0037] It has to be noted that all devices, elements, units and means described in the present application could be implemented in the software or hardware elements or any kind of combination thereof. All steps which are performed by the various entities described in the present application as well as the functionalities described to be performed by the various entities are intended to mean that the respective entity is adapted to or configured to perform the respective steps and functionalities. Even if, in the following description of specific embodiments, a specific functionality or step to be performed by external entities is not reflected in the description of a specific detailed element of that entity which performs that specific step or functionality, it should be clear for a skilled person that these methods and functionalities can be implemented in respective software or hardware elements, or any kind of combination thereof.

[0038] BRIEF DESCRIPTION OF DRAWINGS

[0039] The above described aspects and implementation forms will be explained in the following description of specific embodiments in relation to the enclosed drawings, in which:

[0040] FIG. 1 schematically depicts a device for mitigating MPI in a direct-detection receiver within an intensity-modulation optical transmission system, according to this disclosure;

[0041] FIG. 2 schematically depicts an example for an implementation of the device for mitigating MPI in a direct-detection receiver within an intensity-modulation optical transmission system, according to this disclosure;

[0042] FIG. 3 schematically depicts a device for mitigating MPI in a direct-detection receiver within an intensity-modulation optical transmission system, according to this disclosure;

[0043] FIG. 4 shows a method for a device for mitigating MPI in a direct-detection receiver within an intensity-modulation optical transmission system, according to this disclosure; and

[0044] FIG. 5 shows an example of a conventional DSP block processing architecture. DETAILED DESCRIPTION OF EMBODIMENTS

[0045] FIG. 1 shows an exemplary embodiment of a device 100 for mitigating MPI in a receiver, according to this disclosure. The receiver may be a direct-detection receiver within an intensity-modulation optical transmission system.

[0046] In this exemplary embodiment, the device 100 comprises an interleaver 110, a filter 120, an equalizer 130, and a deinterleaver 140.

[0047] The device 100 may be implemented in, or may be part of, a DSP architecture in a receiver, or a transmitter or a transceiver.

[0048] The device 100 according to this disclosure may comprise a processor or processing circuitry (not shown) configured to perform, conduct or initiate the various operations of the device 100 described herein. The processing circuitry may comprise hardware and / or the processing circuitry may be controlled by software. The hardware may comprise analog circuitry or digital circuitry, or both analog and digital circuitry. The digital circuitry may comprise components such as application-specific integrated circuits (ASICs), field-programmable arrays (FPGAs), digital signal processors (DSPs), or multi-purpose processors. The device 100 may further comprise memory circuitry, which stores one or more instruction(s) that can be executed by the processor or by the processing circuitry, for example under control of the software. For instance, the memory circuitry may comprise a non-transitory storage medium storing executable software code which, when executed by the processor or the processing circuitry, causes the various operations of the device 100 to be performed. The processing circuitry may comprise one or more processors and a non-transitory memory connected to the one or more processors. The non-transitory memory may carry executable program code which, when executed by the one or more processors, causes the device 100 to perform, conduct or initiate the operations or methods described herein.

[0049] The interleaver 110 according to this disclosure may comprise a processor or processing circuitry (not shown) configured to perform, conduct or initiate the various operations of the interleaver 110 described herein. The processing circuitry may comprise hardware and / or the processing circuitry may be controlled by software. The hardware may comprise analog circuitry or digital circuitry, or both analog and digital circuitry. The digital circuitry may comprise components such as application-specific integrated circuits (ASICs), field- programmable arrays (FPGAs), digital signal processors (DSPs), or multi-purpose processors. The interleaver 110 may further comprise memory circuitry, which stores one or more instruction(s) that can be executed by the processor or by the processing circuitry, for example under control of the software. For instance, the memory circuitry may comprise a non-transitory storage medium storing executable software code which, when executed by the processor or the processing circuitry, causes the various operations of the interleaver 110 to be performed. The processing circuitry may comprise one or more processors and a non-transitory memory connected to the one or more processors. The non-transitory memory may carry executable program code which, when executed by the one or more processors, causes the interleaver 110 to perform, conduct or initiate the operations or methods described herein.

[0050] The deinterleaver 140 according to this disclosure may comprise a processor or processing circuitry (not shown) configured to perform, conduct or initiate the various operations of the deinterleaver 140 described herein. The processing circuitry may comprise hardware and / or the processing circuitry may be controlled by software. The hardware may comprise analog circuitry or digital circuitry, or both analog and digital circuitry. The digital circuitry may comprise components such as application-specific integrated circuits (ASICs), field- programmable arrays (FPGAs), digital signal processors (DSPs), or multi-purpose processors. The deinterleaver 140 may further comprise memory circuitry, which stores one or more instruction(s) that can be executed by the processor or by the processing circuitry, for example under control of the software. For instance, the memory circuitry may comprise a non-transitory storage medium storing executable software code which, when executed by the processor or the processing circuitry, causes the various operations of the deinterleaver 140 to be performed. The processing circuitry may comprise one or more processors and a non-transitory memory connected to the one or more processors. The non-transitory memory may carry executable program code which, when executed by the one or more processors, causes the deinterleaver 140 to perform, conduct or initiate the operations or methods described herein.

[0051] Referring to FIG, 1, the interleaver 110 is configured to receive one or more input blocks of symbols. For example, in a digital implementation on a clocked device, e.g. an ASIC, the interleaver is configured to receive at each clock cycle one or more input blocks of symbols. In FIG. 1, four exemplary blocks 101-1, 101-2, 101-3, 101-4, are depicted; however, this is not limiting in this disclosure. Each input block 101-1, 101-2, 101-3, 101-4 comprises a number N of symbols, wherein N is an integer number and N > 0.

[0052] Then, the interleaver 110 is configured to receive the one or more input blocks 101-1, 101-2, 101-3, 101-4 and, accordingly, the respective N symbols in each input block 101-1, 101-2, 101-3, 101-4, in sequential order.

[0053] The symbols received by the interleaver 110 may comprise, or may be, symbols corrupted by noise and distortion, or may comprise signal samples.

[0054] Further, the interleaver 110 is configured to arrange the received symbols into one or more even blocks of symbols 112-1, 112-2 and into one or more odd blocks of symbols 113-1, 113-2.

[0055] Each even block 112-1, 112-2 comprises N different even symbols of the received sequentially ordered symbols, and each odd block 113-1, 113-2 comprises N different odd symbols of the sequentially ordered symbols. Just as an example and not as a limitation, FIG. 1 depicts two exemplary even blocks 112-1, 112-2 and two exemplary odd blocks 113-1, 113-2; however, a total number of odd blocks of symbols 113 and a total number of even blocks of symbols 112 can be determined based on a total number of the input symbols received by the interleaver 110.

[0056] Next, the interleaver 110 is configured to provide to the filter 120, in a parallel manner, the one or more even blocks of symbols 112-1, 112-2 and the one or more odd blocks of symbols 113-1, 113-2.

[0057] The filter 120 is configured to receive the one or more even blocks of symbols 112-1, 112-2 and the one or more odd blocks of symbols 113-1, 113-2 from the interleaver, and the filter 120 is configured to filter each of the even and odd symbols in the received one or more even blocks 112-1, 112-2 and the one or more odd blocks of symbols 113-1, 113-2. In other words, the filter 120 is configured to filter the one or more even blocks of symbols 112-1, 112-2 and the one or more odd blocks of symbols 113-1, 113-2. Further, the filter is configured to provide to the equalizer 130, in a parallel manner, the filtered one or more even blocks of symbols 122-1, 122-2 and the filtered one or more odd blocks of symbols 123-1, 123-2.

[0058] The equalizer 130 is configured to process the one or more even blocks of symbols 122-1, 122-2 and the one or more odd blocks of symbols 123-1, 123-2 after being filtered by the filter (e.g., the filtered even and odd blocks). Further, the equalizer 130 may be configured to provide the processed one or more even blocks of symbols 132-1, 132-2 and the processed one or more odd blocks of symbols 133-1, 133-2 to the deinterleaver 140, in a parallel manner.

[0059] The deinterleaver 140 is configured to receive from the equalizer 130, in a parallel manner, the processed one or more even blocks of symbols 132-1, 132-2 and the processed one or more odd blocks of symbols 133-1, 133-2.

[0060] Next, the deinterleaver 140 is configured to arrange the received one or more even blocks of symbols 132-1, 132-2 and the received one or more odd blocks of symbols 133-1, 133-2 processed by the equalizer into one or more output blocks of symbols 141-1, 141-2, 141-3, 141-4.

[0061] Each of the output blocks 141-1, 141-2, 141-3, 141-4 comprises N symbols, wherein the one or more output symbols are output (or arranged) in a same sequential order as the symbols are received by the interleaver 110. That is, the output symbols are arranged in the same sequential order of the input symbols.

[0062] In other words, the deinterleaver 140 arranges the one or more even symbols and the one or more odd symbols that have been filtered and subsequently processed by the equalizer 130, in the same order in which the input symbols were received by the interleaver 110.

[0063] The deinterleaver 140 is further configured to provide the one or more output blocks 141-1, 141-2, 141-3, 141-4, and thus the output symbols, as an output.

[0064] Arranging the received symbols into the one or more even blocks of symbols 112-1, 112-2 and into the one or more odd blocks of symbols 113-1, 113-2, comprises the steps explained in the following, and that are performed by the interleaver 110. The interleaver 110 is configured to choose first N even symbols of the received sequentially ordered symbols in the one or more input blocks 101-1, 101-2, 101-3, 101-4, and to arrange them in a first even block 112-1.

[0065] Next, the interleaver 110 is configured to choose next N even symbols of the received sequentially ordered symbols in the one or more input blocks 101-1, 101-2, 101-3, 101-4, and to arrange them in a next even block 112-2. The interleaver 110 is configured to repeat this step until all the even input symbols are chosen and arranged into one of the even blocks 112.

[0066] Then, the interleaver 110 is configured to choose first N odd symbols of the received sequentially ordered symbols in the one or more input blocks 101-1, 101-2, 101-3, 101-4, and to arrange them into a first odd block 113-1.

[0067] The interleaver 110 is further configured to choose next N odd symbols of the received sequentially ordered symbols in the one or more input blocks 101-1, 101-2, 101-3, 101-4, and to arrange them in a next odd block 113-2. The interleaver 110 is configured to repeat this step until all the odd input symbols are chosen and arranged into one of the odd blocks 112.

[0068] Arranging the received one or more even blocks of symbols 132-1, 132-2 and the received one or more odd blocks of symbols 133-1, 133-2 processed by the equalizer 130 into the one or more output blocks of symbols 141-1, 141-2, 141-3, 141-4 comprises the steps explained in the following as performed by the deinterleaver 140.

[0069] The deinterleaver 140 is configured to combine (or arrange) the received even symbols and the received odd symbols processed by the equalizer 130, e.g., the symbols in the received one or more even blocks of symbols 132-1, 132-2 and the received one or more odd blocks of symbols 133-1, 133-2, in the same sequential order as the symbols are received by the interleaver 110.

[0070] Then, the deinterleaver 140 is configured to choose first N symbols of the combined sequentially ordered symbols and to arranged them into a first output block 141-1.

[0071] Next, the deinterleaver 140 is configured to choose next N symbols of the combined sequentially ordered symbols, and to arrange them into a next output block 141-2, 141-3, 141-4. The deinterleaver 140 is configured to repeat this step until all the symbols are chosen and arranged into an output block 141 in the same sequential order in which the input symbols were received by the interleaver 110.

[0072] In this exemplary embodiment, the filter 120 may comprise a single-tap noise-whitening filter.

[0073] The equalizer 130 may comprise one or more MLSE blocks and / or one or more MAP blocks. That is, the equalizer 130 may comprise one or more MLSE / MAP blocks. Further, the equalizer 130 may comprise, or may be, a BCJR equalizer.

[0074] In this exemplary embodiment, as the interleaver 110 is placed before the noise-whitening filter, the first even N symbols may be provided to the filter 120 in a first lane, first N odd symbols may be provided to a second lane, and so on. The following noise-whitening filtering and equalization can be performed, and the resulting symbols after being equalized and filtered are provided to the deinterleaver 140, which reverses the effect of the interleaver 110, so that and the processed symbols are again in the input sequence. Due to this architectural change, the filter 120 and the MLSE / MAP equalizer 130 may be able to mitigate interference from every second symbol, thereby suppressing both high frequency and low frequency noise components.

[0075] In other words, the exemplary embodiment of the device 100 according to FIG. 1 can effectively suppress the low frequency interference term generated by MPI as well as high frequency noise enhanced by MMSE based FFE employing only a single memory MLSE / MAP, e.g., effectively mitigates MPI without increasing complexity of the DSP architecture.

[0076] FIG. 2 shows an exemplary implementation of the exemplary embodiment of the device 100 according to FIG. 1. Same elements are labelled with the same reference signs, and may be implemented likewise.

[0077] In the exemplary device 100 according to FIG. 2, four input blocks of symbols 101 are depicted, each comprising N symbols. The four input blocks 101 and the respective N symbols may be received by the interleaver 110 in sequential order. That is, the first input block 101 (depicted as a first arrow from top to bottom at the left side of the interleaver 110) may comprise N symbols, which can be enumerated from 0 to N-l; the second input block 101 (second arrow from top to bottom) may comprise the next N to 2*N-1 symbols, and so on. Thus, in this example, the interleaver 110 may receive a total number of 4*N symbols.

[0078] Even though only four parallel lanes are depicted in FIG. 1 and FIG. 2, the number of parallel lanes depend on a ratio of symbol rate to an ASIC clock rate, which may be larger than 100 for existing DSPs architectures.

[0079] The interleaver 110 may receive the input blocks of symbols 101, may further arrange them into one or more even blocks of symbols 112 and into one or more odd blocks of symbols 113, and may provide them to the filter 120 in a parallel manner.

[0080] The example according to FIG. 2 depicts that the first even block 112 (the first line from top to bottom between the interleaver 110 and the filter 120) comprises the first N even symbols of the total of 4*N symbols received by the interleaver 110, e.g., the symbols enumerated as 0, 2, 4, ..., 2*N-2, and the second even block 112 (third line from top to bottom between the interleaver 110 and the filter 120) comprises the next N even symbols of the total of 4*N symbols received by the interleaver 110, e.g., the symbols enumerated as 2*N, 2*N+2, . . . , 4*N- 2.

[0081] Similarly, the first odd block 113 (second line from top to bottom between the interleaver 110 and the filter 120) comprises the first N odd symbols of the total of 4*N symbols received by the interleaver 110, e.g., the symbols enumerated as 1, 3, 5, ..., 2*N-1, and the second odd block 113 (last line from top to bottom between the interleaver 110 and the filter 120) comprises the next N even symbols of the total of 4*N symbols received by the interleaver 110, e.g., the symbols enumerated as 2*N+1, 2*N+3, ..., 4*N-1.

[0082] Then, the filter 120 may receive the two exemplary even blocks of symbols 112 and the two exemplary odd blocks of symbols 113 in a parallel manner.

[0083] In this example, the filter 120 may comprise a single-tap whitening-noise filter. The effect of the single tap filter as filtering each of the even blocks of symbols 112 and each of the two exemplary odd blocks of symbols 113 that are received in parallel is depicted with the four blocks (from top to bottom) shown in FIG. 2. The filter 120 may then filter each of the even and odd symbols comprised in the received even blocks 112 and odd blocks 113, respectively. Further, the filter may provide to the equalizer 130 a filtered even block 122 corresponding to each received even block 122 and a filtered odd block 123 corresponding to each received odd block 123.

[0084] In the example according to FIG. 2, the equalizer 130 may comprise one or more MLSE / MAP blocks, and may be configured to process the filtered even blocks 122 and the filtered odd blocks 123, thereby generating a processed even block 132 corresponding to each of the received filtered even blocks 122, and a processed odd block 133 corresponding to each of the received filtered odd blocks 123.

[0085] The processed even blocks 132 of symbols and the processed odd blocks 133 may be provided by the equalizer 130 to the deinterleaver 140.

[0086] Then, the deinterleaver 140 may combine the symbols in the received processed even blocks 132 and the received processed blocks 133, and may arrange them into one or more output blocks of symbols 141.

[0087] In this example, four output blocks of symbols 141 are depicted. Each of the four blocks of symbols 141 may comprise N symbols that are arranged in the same sequential order as the input 4*N symbols received by the interleaver 140.

[0088] That is, the first output block of symbols 141 (first line from top to bottom at the right side of the deinterleaver 140) comprises the first N processed symbols (e.g., the symbols after being filtered and equalized) enumerated as 0, 1, 2, . . ., N-l. The second output block of symbols 141 (second line from top to bottom at the right side of the deinterleaver 140) comprises the next N processed symbols, enumerated as N, N+l, N+2, . . . 2*N-1. The third output block of symbols 141 (third line from top to bottom at the right side of the deinterleaver 140) comprises the next N processed symbols, enumerated as 2*N, 2*N+1, 2*N+2, ... 3*N-1, and the fourth output block 141 (fourth line from top to bottom at the right side of the deinterleaver 140) comprises the next N symbols, enumerated as 3*N, 3*N+1, 3*N+1, ..., 4*N-1. FIG. 3 shows an exemplary embodiment of a device 100 for mitigating MPI in a receiver, according to this disclosure, which builds on the device 100 shown in FIG. 1. Same elements are labelled with the same reference signs, and may be implemented likewise.

[0089] Hereinafter, only the differences between FIG. 1 and FIG. 3 are explained. The device 100 according to FIG. 3 further comprises a controller 350, configured to enable or disable both the interleaver 110 and the deinterleaver 140 based on link conditions. That is, the device 100 may control the operation of the interleaver 110 and the deinterleaver 140 by turning them on or off.

[0090] The controller 350 according to this disclosure may comprise a processor or processing circuitry (not shown) configured to perform, conduct or initiate the various operations of the controller 350 described herein. The processing circuitry may comprise hardware and / or the processing circuitry may be controlled by software. The hardware may comprise analog circuitry or digital circuitry, or both analog and digital circuitry. The digital circuitry may comprise components such as application-specific integrated circuits (ASICs), field-programmable arrays (FPGAs), digital signal processors (DSPs), or multi-purpose processors. The controller 350 may further comprise memory circuitry, which stores one or more instruction(s) that can be executed by the processor or by the processing circuitry, for example under control of the software. For instance, the memory circuitry may comprise a non-transitory storage medium storing executable software code which, when executed by the processor or the processing circuitry, causes the various operations of the controller 350 to be performed. The processing circuitry may comprise one or more processors and a non-transitory memory connected to the one or more processors. The non-transitory memory may carry executable program code which, when executed by the one or more processors, causes the controller 350 to perform, conduct or initiate the operations or methods described herein.

[0091] That the interleaver 110 is turned on or enabled refers to the features performed by the interleaver 110 of the device 100 disclosed above for the exemplary embodiment according to FIG. 1 and for the example according to FIG. 2. Similarly, that the deinterleaver 140 is turned on or enabled refers to the features performed by the deinterleaver 140 of the device 100 disclosed above for the exemplary embodiment according to FIG. 1 and for the example according to FIG. 2. The details are not repeated again. That the interleaver 110 and the deinterleaver 140 are turned off or disabled, comprises the following: the interleaver 110 may be configured to receive the one or more input blocks of symbols, exemplary blocks 101-1, 101-2, 101-3, 101-4, each input block 101-1, 101-2, 101-3, 101-4 comprising the number N of symbols. The one or more input blocks 101-1, 101-2, 101-3, 101-4 and the respective N symbols in each input block 101-1, 101-2, 101-3, 101-4 may be received by the interleaver 110 in sequential order.

[0092] Then, the interleaver 110 may be configured to provide to the filter 120, in a parallel manner, the received one or more input blocks 101-1, 101-2, 101-3, 101-4.

[0093] In other words, the interleaver 110 does not arrange the received symbols into the one or more even and odd symbols and, thus, the one or more blocks 112-1, 112-2, 113-1, 113-2 provided to the filter 120 may be the same as the input blocks 101-1, 101-2, 101-3, 101-4.

[0094] Then, the filter 120 may be configured to filter the blocks 112-1, 112-2, 113-1, 113-2 received from the interleaver 110, and may provide the one or more filtered blocks of symbols 122-1, 122-2, 123-1, 123-2 to the equalizer 130, wherein the filtered blocks of symbols 122-1, 122-2, 123-1, 123-2 and the respective symbols may be arranged in the same sequential order in which the one or more input blocks 101-1, 101-2, 101-3, 101-4 are received by the interleaver 110.

[0095] The equalizer 130 may be configured to process the filtered one or more blocks of symbols 122-1, 122-2, 123-1, 123-2, and may process them. Then, the equalizer 130 may provide the one or more processed blocks 132-1, 132-2, 133-1, 133-2 to the deinterleaver 140.

[0096] In this exemplary embodiment, the processed blocks of symbols 132-1, 132-2, 133-1, 133-2 and the respective symbols may be arranged in the same sequential order in which the one or more input blocks 101-1, 101-2, 101-3, 101-4 are received by the interleaver 110.

[0097] Then, the deinterleaver 140 may be configured to provide one or more output blocks 141-1, 141-2, 141-3, 141-4 as an output, wherein each of the one or more output blocks 141-1, 141-2, 141-3, 141-4 may be equal to, or may be the same as, the respective one or more blocks 132-1, 132-2, 133-1, 133-2 after being processed by the equalizer 130. Each of the output blocks 141-1, 141-2, 141-3, 141-4 may comprise N symbols, and the one or more output blocks 141-1, 141-2, 141-3, 141-4 as well as the corresponding symbols may be output in the same sequential order in which the input symbols are received by the interleaver 110.

[0098] In other words, as the deinterleaver is note enabled, it does not combine the received one or more processed blocks of symbols 132-1, 132-2, 133-1, 133-2.

[0099] Turning off the interleaver 110 and the deinterleaver 140 leads to a conventional DSP architecture. This is beneficial in systems in which no MPI or only a low MPI mitigation is needed. Moreover, the device 110 may be fully compatible with existing technologies and can be easily integrated into them.

[0100] As disclosed above, the controller 350 is configured to enable or disable the interleaver 110 and the deinterleaver 140 based on one or more link conditions. Additionally or alternatively, the controller 350 is configured to enable or disable the interleaver 110 and the deinterleaver 140 based on one or more coefficients of the filter 120.

[0101] That the interleaver 110 and the deinterleaver 140 are enabled or disabled based on one or more link conditions refers to the presence of MPI over a link. If the link is affected by MPI, the interleaver 110 and the deinterleaver 140 are activated. Otherwise, if MPI is absent or negligible, the interleaver 110 and the deinterleaver 140 are bypassed.

[0102] In order to decide whether turn on or off the interleaver 110 and the deinterleaver 140, post filter coefficients a and [J can be determined. That is, a manner to detect the presence of MPI is to estimate the coefficients of a virtual 2-tap whitening filter of the type 1 + aD + pD2, where D is a delay. Note that said filter is not implemented, but only the coefficients a and [J are calculated.

[0103] In case that the magnitude of the [J coefficient is large, the interleaver 110 and the deinterleaver 140 may be turned on. Otherwise, the interleaver 110 and the deinterleaver 140 may be turned off. As it has been explained above in this disclosure, when the interleaver 110 and the deinterleaver 140 are turned on or enabled, N even symbols may go to the first parallel processing lane of the filter 120, N odd symbols may go to the second one, and so on. Consequently, the noise-whitening filter 120 and the MLSE / MAP equalizer 130 may be capable of mitigating inter-symbol interference from every second data symbol. Thereby, the device 100 according to the exemplary embodiment of FIG. 1 and FIG. 3 enables to mathematically implement equation (1): where a is a coefficient of the filter 120, and D is a delay, e.g., D is a dummy variable whose exponent represents the tap delay, and can be expressed as z-1, where z is a dummy variable of the conventional z-transform.

[0104] Notably, equation (1) is equivalent to a combination of low pass and high pass filters in a cascade, whereas only a single post-filter coefficient and a single memory of MLSE / MAP blocks equalizer 130 are used.

[0105] The exemplary embodiments of the device 100 according to this disclosure according to FIG. 1 and FIG. 3 as well as the example according to FIG. 2 may be implemented in high-speed optical transceivers where optical MPI can be encountered. This comprises optical transceivers for datacenter intraconnects, 5G / 6G front-haul optical transceivers, and other short to medium reach high-speed optical transceivers.

[0106] FIG. 4 shows an exemplary embodiment of a method 400 for a device 100 for mitigating MPI in a direct-detection receiver within an intensity-modulation optical transmission system. The method 400 may be performed by the exemplary embodiments of the device 100 according to FIG. 1 and FIG. 3 disclosed above. The device 100 comprises an interleaver 110, a filter 120, an equalizer 130, and a deinterleaver 140.

[0107] The method 400 comprises a step 401 of receiving, with the interleaver 110, one or more input blocks of symbols 101-1, 101-2, 101-3, 101-4, each input block comprising a number N of symbols, where N is an integer number, and where the one or more input blocks 101-1, 101-2, 101-3, 101-4 and the respective N symbols are received in sequential order. Then, the method 400 comprises a step 402 of arranging, with the interleaver 110, the received symbols into one or more even blocks of symbols 112-1, 112-2 and into one or more odd blocks of symbols 113-1, 113-2. Each even block 112-1, 112-2 comprises N different even symbols of the received sequentially ordered symbols, and each odd block 113-1, 113-2 comprises N different odd symbols of the sequentially ordered symbols.

[0108] Further, in step 403, the method 400 comprises providing to the filter 120, with the interleaver 110, in a parallel manner, the one or more even blocks of symbols 112-1, 112-2 and the one or more odd blocks of symbols 113-1, 113-2.

[0109] The method 400 further comprises a step 404 of processing, with the equalizer 130, one or more even blocks of symbols 122-1, 122-2 and one or more odd blocks of symbols 123-1, 123-2 after being filtered by the filter 120.

[0110] Then, the method 400 comprises a step 405 of receiving from the equalizer 130, with the deinterleaver 140 in a parallel manner, one or more even blocks of symbols 132-1, 132-2 and one or more odd blocks of symbols 133-1, 133-2 after being processed by the equalizer 130.

[0111] In step 406, the method 400 comprises arranging, with the deinterleaver 140, the received one or more even blocks of symbols 132-1, 132-2 and the received one or more odd blocks of symbols 133-1, 133-2 processed by the equalizer 130 into one or more output blocks of symbols 141-1, 141-2, 141-3, 141-4. Each of the output blocks 141-1, 141-2, 141-3, 141-4 comprises N symbols, and the one or more output symbols are output in a same sequential order as the symbols are received by the interleaver 110.

[0112] Further, in step 407, the method 400 comprises providing, with the deinterleaver 140, the one or more output blocks 141-1, 141-2, 141-3, 141-4 as an output.

[0113] The method 400 may further comprise actions according to the exemplary embodiments of the device 100 according to FIG. 1 and FIG. 3. Hence, the method 400 achieves the same advantages as the device 100 disclosed above.

[0114] This disclosure further provides a computer program comprising instructions for carrying out, when the program is executed by a computer, the method 400. The computer program may be included in a computer readable medium of a computer program product. The computer readable medium may comprise essentially any memory, such as a ROM (Read-Only Memory), a PROM (Programmable Read-Only Memory), a 15 EPROM (Erasable PROM), a Flash memory, an EEPROM (Electrically Erasable PROM), or a hard disk drive.

[0115] The present disclosure has been described in conjunction with various embodiments as examples as well as implementations. However, other variations can be understood and effected by those persons skilled in the art and practicing the claimed matter, from the studies of the drawings, this disclosure and the independent claims. In the claims as well as in the description the word "comprising" does not exclude other elements or steps and the indefinite article "a" or "an" does not exclude a plurality. A single element or other unit may fulfill the functions of several entities or items recited in the claims. The mere fact that certain measures are recited in the mutual different dependent claims does not indicate that a combination of these measures cannot be used in an advantageous implementation.

Claims

CLAIMS1. A device (100) for mitigating multipath interference, MPI, in a direct-detection receiver within an intensity-modulation optical transmission system, the device (100) comprising: an interleaver (110) configured to: receive one or more input blocks of symbols (101-1, 101-2, 101-3, 101-4), each input block (101-1, 101-2, 101-3, 101-4) comprising a number N of symbols, wherein N is an integer number, and wherein the one or more input blocks (101-1, 101-2, 101-3, 101-4) and the respective N symbols are received in sequential order; arrange the received symbols into one or more even blocks of symbols (112-1, 112-2) and into one or more odd blocks of symbols (113-1, 113-2), each even block (112-1, 112-2) comprising N different even symbols of the received sequentially ordered symbols, and each odd block (113-1, 113-2) comprising N different odd symbols of the sequentially ordered symbols; provide to a filter (120), in a parallel manner, the one or more even blocks of symbols (112-1, 112-2) and the one or more odd blocks of symbols (113-1, 113-2); an equalizer (130) configured to process one or more even blocks of symbols (122-1, 122-2) and one or more odd blocks of symbols (123-1, 123-2) after being filtered by the filter; and a deinterleaver (140) configured to: receive from the equalizer, in a parallel manner, one or more even blocks of symbols (132-1, 132-2) and one or more odd blocks of symbols (133-1, 133-2) after being processed by the equalizer; arrange the received one or more even blocks of symbols (132-1, 132-2) and the received one or more odd blocks of symbols (133-1, 133-2) processed by the equalizer into one or more output blocks of symbols (141-1, 141-2, 141-3, 141-4), each of the output blocks (141-1, 141-2, 141-3, 141-4) comprising N symbols, wherein the one or more output symbols are output in a same sequential order as the symbols are received by the interleaver (110); and provide the one or more output blocks (141-1, 141-2, 141-3, 141-4) as an output.

2. The device (100) according to claim 1, wherein arranging the received symbols into the one or more even blocks of symbols (112-1, 112-2) and into the one or more odd blocks of symbols (113-1, 113-2), comprises: choosing first N even symbols of the received sequentially ordered symbols and arranging them in a first even block (112-1); choosing next N even symbols of the received sequentially ordered symbols and arranging them in a next even block (112-2); choosing first N odd symbols of the received sequentially ordered symbols and arranging them in a first odd block (113-1); and choosing next N odd symbols of the received sequentially ordered symbols and arranging them in a next odd block (113-2).

3. The device (100) according to one of the preceding claims, wherein arranging the received one or more even blocks of symbols (132-1, 132-2) and the received one or more odd blocks of symbols (133-1, 133-2) processed by the equalizer (130) into the one or more output blocks of symbols (141-1, 141-2, 141-3, 141-4) comprises: combining the received even symbols and the received odd symbols processed by the equalizer (130) in the same sequential order as the symbols are received by the interleaver (no); choosing first N symbols of the combined sequentially ordered symbols and arranging them into a first output block (141-1); and choosing next N symbols of the combined sequentially ordered symbols and arranging them into a next output block (141-2, 141-3, 141-4).

4. The device (100) according to one of the preceding claims, wherein the device (100) is further configured to enable or disable the interleaver (110) and the deinterleaver (140) based on link conditions.

5. The device (100) according to one of the preceding claims, wherein the filter (120) comprises a single tap noise whitening filter.

6. The device (100) according to one of the preceding claims, wherein the equalizer (130) comprises one or more Maximum Likelihood Sequence Estimation, MLSE, blocks and / or one or more Maximum Aposteriori Probability, MAP, blocks.

7. A method (400) for a device (100) for mitigating multipath interference, MPI, in a direct- detection receiver within an intensity-modulation optical transmission system, the method (400) comprising: receiving (401), with an interleaver (110), one or more input blocks of symbols (101-1, 101-2, 101-3, 101-4), each input block comprising a number N of symbols, wherein N is an integer number, and wherein the one or more input blocks (101-1, 101-2, 101-3, 101-4) and the respective N symbols are received in sequential order; arranging (402), with the interleaver (110), the received symbols into one or more even blocks of symbols (112-1, 112-2) and into one or more odd blocks of symbols (113-1, 113-2), each even block (112-1, 112-2) comprising N different even symbols of the received sequentially ordered symbols, and each odd block (113-1, 113-2) comprising N different odd symbols of the sequentially ordered symbols; providing (403) to a filter (120), with the interleaver (110), in a parallel manner, the one or more even blocks of symbols (112-1, 112-2) and the one or more odd blocks of symbols (113-1, 113-2); processing (404), with an equalizer, one or more even blocks of symbols (122-1, 122-2) and one or more odd blocks of symbols (123-1, 123-2) after being filtered by the filter (120); receiving (405) from the equalizer (130), with a deinterleaver (140), in a parallel manner, one or more even blocks of symbols (132-1, 132-2) and one or more odd blocks of symbols (133-1, 133-2) after being processed by the equalizer (130); arranging (406), with the deinterleaver (140), the received one or more even blocks of symbols (132-1, 132-2) and the received one or more odd blocks of symbols (133-1, 133-2) processed by the equalizer (130) into one or more output blocks of symbols (141-1, 141-2, 141-3, 141-4), each of the output blocks (141-1, 141-2, 141-3, 141-4) comprising N symbols, wherein the one or more output symbols are output in a same sequential order as the symbols are received by the interleaver (110); and providing (407), with the deinterleaver (140), the one or more output blocks (141-1, 141-2, 141-3, 141-4) as an output.

8. A computer program comprising instructions which, when the program is executed by a computer, cause the computer to carry out the method (400) according to claim 7.

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