Method and apparatus for channel decoder in a wireless communication system

Abstract

The disclosure relates to a 5G or 6G communication system for supporting a higher data transmission rate. Embodiments herein disclose methods and systems for parallelizing operations for decoding polar codes and reducing the latency, complexity, and power consumption in the domain of channel coding for beyond 5G networks. Embodiments herein disclose methods and systems for identifying the right number of decoding variables selected from a plurality of pre-defined discrete decoding variables for an Error Correcting Code (ECC) before the decoding process starts, where the method helps in saving significant amount of power.

Description

METHOD AND APPARATUS FOR CHANNEL DECODER IN A WIRELESS COMMUNICATION SYSTEM

[0001] Embodiments disclosed herein relate to the field of decoding technique for a data communication channel in a wireless network, and more particularly related to methods and systems to select an optimal set of decoder cores for a channel decoder in the wireless network.

[0002] Considering the development of wireless communication from generation to generation, the technologies have been developed mainly for services targeting humans, such as voice calls, multimedia services, and data services. Following the commercialization of 5G (5th generation) communication systems, it is expected that the number of connected devices will exponentially grow. Increasingly, these will be connected to communication networks. Examples of connected things may include vehicles, robots, drones, home appliances, displays, smart sensors connected to various infrastructures, construction machines, and factory equipment. Mobile devices are expected to evolve in various form-factors, such as augmented reality glasses, virtual reality headsets, and hologram devices. In order to provide various services by connecting hundreds of billions of devices and things in the 6G (6th generation) era, there have been ongoing efforts to develop improved 6G communication systems. For these reasons, 6G communication systems are referred to as beyond-5G systems.

[0003] 6G communication systems, which are expected to be commercialized around 2030, will have a peak data rate of tera (1,000 giga)-level bit per second (bps) and a radio latency less than 100μsec, and thus will be 50 times as fast as 5G communication systems and have the 1 / 10 radio latency thereof.

[0004] In order to accomplish such a high data rate and an ultra-low latency, it has been considered to implement 6G communication systems in a terahertz (THz) band (for example, 95 gigahertz (GHz) to 3THz bands). It is expected that, due to severer path loss and atmospheric absorption in the terahertz bands than those in mmWave bands introduced in 5G, technologies capable of securing the signal transmission distance (that is, coverage) will become more crucial. It is necessary to develop, as major technologies for securing the coverage, Radio Frequency (RF) elements, antennas, novel waveforms having a better coverage than Orthogonal Frequency Division Multiplexing (OFDM), beamforming and massive Multiple-input Multiple-Output (MIMO), Full Dimensional MIMO (FD-MIMO), array antennas, and multiantenna transmission technologies such as large-scale antennas. In addition, there has been ongoing discussion on new technologies for improving the coverage of terahertz-band signals, such as metamaterial-based lenses and antennas, Orbital Angular Momentum (OAM), and Reconfigurable Intelligent Surface (RIS).

[0005] Moreover, in order to improve the spectral efficiency and the overall network performances, the following technologies have been developed for 6G communication systems: a full-duplex technology for enabling an uplink transmission and a downlink transmission to simultaneously use the same frequency resource at the same time; a network technology for utilizing satellites, High-Altitude Platform Stations (HAPS), and the like in an integrated manner; an improved network structure for supporting mobile base stations and the like and enabling network operation optimization and automation and the like; a dynamic spectrum sharing technology via collision avoidance based on a prediction of spectrum usage; an use of Artificial Intelligence (AI) in wireless communication for improvement of overall network operation by utilizing AI from a designing phase for developing 6G and internalizing end-to-end AI support functions; and a next-generation distributed computing technology for overcoming the limit of UE computing ability through reachable super-high-performance communication and computing resources (such as Mobile Edge Computing (MEC), clouds, and the like) over the network. In addition, through designing new protocols to be used in 6G communication systems, developing mechanisms for implementing a hardware-based security environment and safe use of data, and developing technologies for maintaining privacy, attempts to strengthen the connectivity between devices, optimize the network, promote softwarization of network entities, and increase the openness of wireless communications are continuing.

[0006] It is expected that research and development of 6G communication systems in hyper-connectivity, including person to machine (P2M) as well as machine to machine (M2M), will allow the next hyper-connected experience. Particularly, it is expected that services such as truly immersive eXtended Reality (XR), high-fidelity mobile hologram, and digital replica could be provided through 6G communication systems. In addition, services such as remote surgery for security and reliability enhancement, industrial automation, and emergency response will be provided through the 6G communication system such that the technologies could be applied in various fields such as industry, medical care, automobiles, and home appliances.

[0007] Channel coding is one of the important blocks in the cellular transmitter-receiver (Tx-Rx) chain that determines the latency and reliability of the link. The decoders used, specifically in the cellular receiver chain often operate iteratively or sometimes based on a bit-by-bit list decoding process, leading to higher latency and power consumption. For example, the decoders of turbo and low-density

[0008] parity-check (LDPC) codes operate iteratively, which are used as channel coding schemes in the 3GPP defined fourth generation (4G) long term evolution (LTE) and 5G new radio NR) cellular technologies, respectively, for data channels in both uplink (UL) and downlink (DL) directions. Successive cancellation list (SCL) decoder is a list size based decoder, which is used for decoding polar codes in 5G NR UL and DL control channels. The SCL decoder with list size L, decodes bit-by-bit, considering L simultaneous paths in the process till the decoding ends, and can be viewed as L decoder cores running in parallel. Similarly, the recently discovered polarization-adjusted convolutional (PAC) codes, which are being considered for beyond 5G and 6G technologies, also use a list-based decoder, similar to that of SCL, with an additional convolutional operation.

[0009] In general, an iterative decoder is a class of decoders used in digital communication systems which refines its estimate of the transmitted data through multiple iterations. These decoders progressively exchange information between different parts in a decoding process, to perform error correction in a fading communication channel. Some examples of iterative decoder are, such as turbo decoder, LDPC decoder and so on.

[0010] Further, a Turbo decoder is used in digital communication systems, for error correction. mostly used for decoding encoded data transmitted over fading channels in a wireless communication system. Further, the turbo decoders exchange information in an iterative manner. A turbo decoder combines results of two or more decoders that work on slightly different versions of a received signal. A The first decoder (often a soft-input, soft-output decoder) processes the received signal and produces soft outputs (probabilities or log-likelihood ratios) for information bits. An interleaver rearranges sequence of bits received to create a different version of the data, which is sent to the second decoder. The second decoder works on the interleaved data, and again generates soft outputs, which are passed back to the first decoder. This exchange continues in iterations, where each of the first decoder and the second decoder refines its estimate based on the feedback from the other.

[0011] An LDPC decoder is an Error correcting code (ECC) decoder, used to correct errors through soft decision decoding and hard decision decoding, in messages that have been transmitted over a fading communication channel. LDPC codes are a class of linear block codes, and their decoding relies on a sparse parity-check matrix. The LDPC decoder works by way of iteratively passing messages between a plurality of variable nodes (bits) and a plurality of check nodes (parity constraints). The decoder initiates decoding by making an initial estimate of the received bits (typically the received value itself), and then iterates to improve the estimate. This process is repeated multiple times, where each node refines its message based on the information it gets from its neighbors. After a significant number of iterations, the decoder should converge to a codeword that satisfies the parity-check matrix (i.e., the errors are corrected).

[0012] Polar codes have been proposed as capacity achieving codes. The Polar codes are based on the concept of channel polarization, wherein each bit of the Polar codes is made to be transmitted either via a noiseless channel or an extremely noisy channel. In the polar codes, polarization is achieved through polar transform. The 3rd Generation Partnership Project (3GPP) uses the polar codes for controlling and broadcasting data transmissions in a 5G New radio (NR), Downlink control information (DCI) via Physical downlink control channel (PDCCH), Master information block (MIB) via Physical broadcast channel (PBCH), and Uplink control information (UCI) via Physical uplink control channel (PUCCH) or Physical uplink shared channel (PUSCH).

[0013] The Polar codes are discussed in 5G NR, and considered for small data lengths in the 5G NR. The polar encoding has a structure such that, at any intermediate node, if an inverse polar transform of the respective length is applied, the information bits, that are attached as leaf nodes to that intermediate node, can be obtained.

[0014] The widely used decoder for the polar codes is successive cancellation list (SCL) decoder, known for its best performance. The SCL decoder is sequential in nature, wherein the bits are decoded sequentially one after the other, making the latency higher for decoding large code lengths.

[0015] The SCL decoder suffers from latency and complexity. The sequential operation of successive cancellation list decoder used for the polar codes adds latency to a system (or communication system). Further, list size used for SCL decoding is of concern. Therefore, for achieving a target Block error rates (BLER), a smaller list size is sufficient at high Signal-to-noise ratio (SNR), and a large list size may be required for low SNR conditions. The existing technologies do not address this issue.

[0016] FIG. 1 is a binary representation of the SCL decoder as a binary tree. The SCL decoder is represented as a binary tree with depth , wherein the roots of the tree shall receive log-likelihood ratios (LLRs), corresponding to the bits transmitted after encoding. At each node (if the node is not a leaf node), proceed to the left child where the hard decision bits are decoded, then move to the parent node, and finally proceed to the right child, using the hard decisions from the left child. At every node (if the node is a leaf node), make a hard decision of the bit, and go to the parent node. At each leaf node, two paths emerge for the bit being either 0 or 1. The SCL techniques keeps track of L paths at a time, and prunes the paths with large penalty (based on the LLR values). Traversing till the leaf node for obtaining hard decision for each information bit, makes the SCL decoder sequential and complex. Methods to avoid such exhaustive tree traversals are required in reducing the complexity and latency of the SCL decoder, and also parallelize.

[0017] FIG.2 is an example block diagram of a traditional SCL decoder with L decoder cores among which the decoder cores with CRC check success are used for decoding information bits.

[0018] Hence, there is a need in the art for solutions which will overcome the above mentioned drawback(s), among others.

[0019] The principal object of embodiments herein is to disclose methods and systems for providing an optimal set of decoder cores to a channel decoder for performing an Error Correcting Code (ECC) decoding in digital communication.

[0020] Another object of embodiments herein is to provide at least one optimal list size of Successive Cancellation (SC) decoder cores for a Successive Cancellation List (SCL) decoding.

[0021] Another object of embodiments herein is to provide at least one optimal set of depth levels for successive cancellation or successive cancellation list based decoding.

[0022] Another object of embodiments herein is to provide at least one optimal set of a plurality of iteration numbers for an iterative decoding.

[0023] Another object of embodiments herein is to parallelize operations for decoding polar codes and its variants, and reduce the latency, complexity, and power consumption in the domain of channel coding for the wireless networks.

[0024] Another object of embodiments herein is to determine at least one link abstraction metric Received bit information Rate (RBIR) corresponding to an effective Signal to Noise ratio (SNR) for selecting an optimal set of decoder cores or list size or iteration number or depth level for an ECC decoding.

[0025] Another object of embodiments herein is to determine the list size required for any list decoder such as successive cancellation list decoding for polar and list decoding for polar variant codes.

[0026] Another object of embodiments herein is to determine the iteration size required for any iterative decoder such as turbo, LDPC decoders, and so on.

[0027] Embodiments herein disclose a method for selecting an optimal set of decoding variables in a channel decoder for decoding at least one an Error Correcting Code in digital communication. The method includes receiving, by a receiver in a wireless network, a plurality of channel-inputs of a fading channel, wherein the channel-inputs comprising at least one: a code rate or modulation order or modulation and coding scheme index (MCS), LLRs, and a plurality of Signal to noise ratios (SNRs). The method further comprises, determining, by the receiver, a plurality of a first type link-abstraction metrics based on the plurality of channel-inputs. Further, the method comprises, comparing, by the receiver, the plurality of determined first type link-abstraction metrics with a plurality of pre-defined first type link-abstraction metrics. The method further comprises, identifying, by the receiver, the optimal set of decoding variables from a plurality of pre-defined discrete decoding variables, based on the comparison. The identified optimal set of decoding variable has one determined first type link-abstraction metric closest to one pre-defined first type link-abstraction metric.

[0028] Embodiments herein disclose, a receiver in a wireless communication network comprising a decoding variable identifier engine, a decoder, a processor, and a memory. The decoding variable identifier engine coupled with the decoder, the processor, and the memory. The decoding variable identifier engine is configured to receive, a plurality of channel-inputs comprising at least a code rate or modulation order or modulation and coding scheme index (MCS), LLRs and a plurality of Signal to noise ratios (SNRs). Further, the decoding variable identifier engine is configured to determine, a plurality of a first type link-abstraction metrics based on the plurality of channel-inputs. The decoding variable identifier engine further is configured to compare, the plurality of the determined first type link-abstraction metrics with a plurality of pre-defined first type link-abstraction metrics. Further, the decoding variable identifier engine is configured to identify, an optimal set of decoding variables from a plurality of pre-defined discrete decoding variables based on the comparison for decoding at least an Error Correcting Code in digital communication. The identified optimal set of decoding variables having one determined first type link-abstraction metric, closest to one first type pre-defined link-abstraction metric.

[0029] These and other aspects of the embodiments herein will be better appreciated and understood when considered in conjunction with the following description and the accompanying drawings. It should be understood, however, that the following descriptions, while indicating at least one embodiment and numerous specific details thereof, are given by way of illustration and not of limitation. Many changes and modifications may be made within the scope of the embodiments herein without departing from the scope thereof, and the embodiments herein include all such modifications.

[0030] Aspects of the disclosure are to address at least the above-mentioned problems and / or disadvantages and to provide at least the advantages described below. Accordingly, an aspect of the disclosure is to provide efficient communication methods in a wireless communication system.

[0031] Embodiments herein are illustrated in the accompanying drawings, throughout which like reference letters indicate corresponding parts in the various figures. The embodiments herein will be better understood from the following description with reference to the following illustratory drawings. Embodiments herein are illustrated by way of examples in the accompanying drawings, and in which:

[0032] FIG. 1 is an example binary representation of a SCL decoder as a binary tree, according to existing arts;

[0033] FIG. 2 depicts an example block diagram of a traditional SCL decoder with L decoder cores, according to existing arts;

[0034] FIG. 3 depicts a block diagram of a system for performing reduction in number of ECC decoding variables during an ECC decoding, according to embodiments as disclosed herein;

[0035] FIG. 4A depicts a block diagram of a system configured to select a plurality of decoding variables from a plurality of pre-defined discrete decoding variables for ECC decoding, according to embodiments as disclosed herein;

[0036] FIG. 4B depicts an example block diagram of a system configured to select a plurality of decoding variables (decoder cores) from a pre-defined discrete set of decoding variables for the ECC decoding in order to decode at least one of: a plurality of polar codes, a plurality of polar variant codes, a plurality of turbo codes, a plurality of LDPC codes and so on, according to embodiments as disclosed herein;

[0037] FIG. 5A depicts an example intermediate (early) decoding module in a decoder engine, according to embodiments as disclosed herein;

[0038] FIG. 5B depicts an example flow chart depicting a process of performing an intermediate (early) decoding in the decoder engine, according to embodiments as disclosed herein;

[0039] FIG. 6A depicts an example intermediate decoding module operation, according to embodiments as disclosed herein;

[0040] FIG. 6B depicts an example flow chart of a process for performing instant decoding at an intermediate node in the decoder engine, wherein the decoder engine, according to embodiments as disclosed herein;

[0041] FIG. 7A depicts an example intermediate decoding module in a decoder engine, wherein the decoder engine is an SCL decoder engine, wherein the intermediate decoding module can be located at or before a root node in the SCL decoder engine, according to embodiments as disclosed herein;

[0042] FIG. 7B, FIG. 7C, and FIG. 7D are an example flowchart illustrating a process of performing intermediate decoding in an SCL decoder engine, according to embodiments as disclosed herein.

[0043] FIG. 8A is an example flow diagram depicting a method for selecting a reduced number of decoding variables, according to embodiments as disclosed herein;

[0044] FIG. 8B depicts an example flow diagram of a method for selecting, a reduced number of decoding variables, from a plurality of SNRs, wherein each SNR achieves a target second type target link abstraction metrics, according to embodiments as disclosed herein;

[0045] FIG. 9A depicts an example flow diagram of a method for selecting a reduced list-size of a plurality of decoder cores, based on at least an RBIR of fading channel matching with RBIR threshold and achieving a target BLER, according to embodiments as disclosed herein;

[0046] FIG. 9B depicts a block diagram illustrating a RBIR threshold for a list size obtained by identifying the SNR corresponding to the target BLER, according to embodiments as disclosed herein;

[0047] FIG. 10 A depicts a block diagram of a method for an RBIR-based list size and iteration number identification for respectively a list-based decoding and an iterative decoding in an LTE, a 5G NR, and beyond 5G systems, according to embodiments as disclosed herein;

[0048] FIG. 10B depicts an example 5G NR transmitter-receiver chain for selecting a reduced number of decoding variables for ECC decoding, according to embodiments as disclosed herein;

[0049] FIG. 11 illustrates a BLER performance as a function SNR with various iteration numbers for iterative LDPC decoder, and list sizes for list-based polar decoder in AWGN channel (for example)

[0050] FIG. 12 illustrates a 5G NR LDPC Codes with PDSCH Tx-Rx in which performance comparison between proposed ULIP and traditional fixed iteration decoders, for different MCS indices, using TDL-A channel with DS = 30 ns, fD =100Hz.

[0051] FIG. 13 illustrates LTE Turbo Codes with PDSCH Tx-Rx in which performance comparison between proposed ULIP and traditional fixed iteration decoders, for different MCS indices, using EPA-5Hz channel.

[0052] FIG. 14 illustrates the 5G NR Polar Codes with PDCCH Tx-Rx in which performance comparison between proposed ULIP and traditional fixed list size decoders, for different code rates, using TDL-A channel with DS = 30 ns, fD =100Hz.

[0053] FIG. 15 illustrates PAC Codes with 5G NR PDCCH Tx-Rx in which performance comparison between proposed ULIP and traditional fixed list size decoders, for different code rates, using TDL-A channel with DS = 30 ns, fD =100Hz. respectively.

[0054] FIG. 16 illustrates the BLER performance of SC decoder with decoding at different depth levels in AWGN channel, for N =1024, and code rate of 1 / 2.

[0055] FIG. 17 illustrates performance comparison between proposed RBIR-AFSC and traditional SC decoders, for different code rates, using TDL-A channel.

[0056] FIG. 18 illustrates the performance comparison of proposed RBIR-AFSC with varying Dmin, using TDL-A channel with DS = 30 ns, fD =100Hz, and code rate of 1 / 2.

[0057] FIG. 19 illustrates a structure of a user equipment (UE) according to embodiments disclosed herein.

[0058] FIG. 20 illustrates a structure of a base station (BS) according to embodiments disclosed herein.

[0059] Aspects of the disclosure are to address at least the above-mentioned problems and / or disadvantages and to provide at least the advantages described below. Accordingly, an aspect of the disclosure is to provide a terminal and a communication method thereof in a wireless communication system.

[0060] The embodiments herein and the various features and advantageous details thereof are explained more fully with reference to the non-limiting embodiments that are illustrated in the accompanying drawings and detailed in the following description. Descriptions of well-known components and processing techniques are omitted so as to not unnecessarily obscure the embodiments herein. The examples used herein are intended merely to facilitate an understanding of ways in which the embodiments herein may be practiced and to further enable those of skill in the art to practice the embodiments herein. Accordingly, the examples should not be construed as limiting the scope of the embodiments herein.

[0061] For the purposes of interpreting this specification, the definitions (as defined herein) will apply and whenever appropriate the terms used in singular will also include the plural and vice versa. It is to be understood that the terminology used herein is for the purposes of describing particular embodiments only and is not intended to be limiting. The terms "comprising", "having" and "including" are to be construed as open-ended terms unless otherwise noted.

[0062] The words / phrases "exemplary", "example", "illustration", "in an instance", "and the like", "and so on", "etc.", "etcetera", "e.g.," , "i.e.," are merely used herein to mean "serving as an example, instance, or illustration." Any embodiment or implementation of the present subject matter described herein using the words / phrases "exemplary", "example", "illustration", "in an instance", "and the like", "and so on", "etc.", "etcetera", "e.g.,", "i.e.," is not necessarily to be construed as preferred or advantageous over other embodiments.

[0063] Embodiments herein may be described and illustrated in terms of blocks which carry out a described function or functions.　These blocks, which may be referred to herein as managers, units, modules, hardware components or the like, are physically implemented by analog and / or digital circuits such as logic gates, integrated circuits, microprocessors, microcontrollers, memory circuits, passive electronic components, active electronic components, optical components, hardwired circuits and the like, and may optionally be driven by a firmware. The circuits may, for example, be embodied in one or more semiconductor chips, or on substrate supports such as printed circuit boards and the like.　The circuits constituting a block may be implemented by dedicated hardware, or by a processor (e.g., one or more programmed microprocessors and associated circuitry), or by a combination of dedicated hardware to perform some functions of the block and a processor to perform other functions of the block.　Each block of the embodiments may be physically separated into two or more interacting and discrete blocks without departing from the scope of the disclosure.　Likewise, the blocks of the embodiments may be physically combined into more complex blocks without departing from the scope of the disclosure.

[0064] It should be noted that elements in the drawings are illustrated for the purposes of this description and ease of understanding and may not have necessarily been drawn to scale. For example, the flowcharts / sequence diagrams illustrate the method in terms of the steps required for understanding of aspects of the embodiments as disclosed herein. Furthermore, in terms of the construction of the device, one or more components of the device may have been represented in the drawings by conventional symbols, and the drawings may show only those specific details that are pertinent to understanding the present embodiments so as not to obscure the drawings with details that will be readily apparent to those of ordinary skill in the art having the benefit of the description herein. Furthermore, in terms of the system, one or more components / modules which comprise the system may have been represented in the drawings by conventional symbols, and the drawings may show only those specific details that are pertinent to understanding the present embodiments so as not to obscure the drawings with details that will be readily apparent to those of ordinary skill in the art having the benefit of the description herein.

[0065] The accompanying drawings are used to help easily understand various technical features and it should be understood that the embodiments presented herein are not limited by the accompanying drawings. As such, the present disclosure should be construed to extend to any modifications, equivalents, and substitutes in addition to those which are particularly set out in the accompanying drawings and the corresponding description. Usage of words such as first, second, third etc., to describe components / elements / steps is for the purposes of this description and should not be construed as sequential ordering / placement / occurrence unless specified otherwise.

[0066] The embodiments herein achieve methods and systems for parallelizing operations for decoding polar codes.

[0067] Referring now to the drawings, and more particularly to FIGs. 3 through 18, where similar reference characters denote corresponding features consistently throughout the figures, there are shown embodiments.

[0068] FIG. 3 depicts a block diagram of a system (400A) for performing reduction in number of decoding variables (e.g., decoder cores) for an ECC decoding, according to embodiments as disclosed herein. The system (400A) comprises a transmitter (402) and a receiver (404). In an embodiment herein, the transmitter (402) includes an encoder unit (412), a CRC checking unit (414), a modulation mapping unit (416), a processor (418), a memory (420), and a communication module (422). The processor (418) is coupled with the encoder unit (412), the CRC checking unit (414), the modulation mapping unit (416), the memory (420), and the communication module (422).

[0069] In an example embodiment herein, the encoder unit (412) can be a polar encoder unit, which can implement polar codes for generating encoded data using at least a polar transformation. Further, in an example embodiment herein, the encoder unit (412) can generate polarization adjusted convolutional (PAC) codes, wherein the PAC codes are a variant of polar codes, for 5G usage, 6G Applications (for example). Further, in an example embodiment herein, the encoder unit (412) can implement turbo codes for generating encoded data in 4G Applications. Furthermore, in an example embodiment herein, the encoder unit (412) can implement LDPC codes for generating encoded data in 5G and 6G Applications. In an embodiment herein, the CRC checking unit (414) can detect error in the data generated from the encoder unit (412). In an embodiment herein, an encoded data transmitted by the transmitter (402) includes an ECC encoded data with a CRC check. In an embodiment herein, the modulation mapping unit (416) can perform at least phase modulation of the ECC encoded data for facilitating data transmission over a physical medium.

[0070] In an embodiment herein, the receiver (404) can comprise a reference signal analyzer engine (432), a Log likelihood ratio (LLR) generation engine (434), a decoding variable identifier engine (436), a decoder engine (438), a processor (440), a memory (442) and a communication module (444).

[0071] In an example embodiment herein, the transmitter (402) can be at least a user equipment, a network node and so on in a wireless communication network. Further, in an example embodiment herein, the receiver (404) can be at least a user equipment, a network node and so on, in the wireless communication network. In an embodiment herein, the network node of at least one of the transmitter (402) and the receiver (404) can be, for example, but not limited to a gNB, an eNB, a new radio (NR) trans-receiver or the like. In an embodiment herein, the transmitter and the receiver (404) can be a portable mobile device such as an electronic equipment with communication facility designed to serve as a medium for facilitating virtual interaction with a network. Further, the UE can be operated by an authenticated user is a portable electronic device, such as a portable computer, a computing device, a laptop, a smart phone, a desktop computer, a notebook, a Device-to-Device (D2D) device, a vehicle to everything (V2X) device, a foldable phone, a smart TV, a tablet, an immersive device, and an internet of things (IoT) device etc. The UE further, can include functionality for communicating with the network through the communication module (444). In an example embodiment, the UE can be a Smart Phone (iPhone, Android phone, Windows phone), a conventional web-enabled portable computers, a tablet computer or another device capable of communicating through the communication module (444) to connect internet or any other conventional network. In an embodiment herein, the communication modules (422, 444) can include an electronic circuit specific to a standard that enables wired or wireless communication.

[0072] In an example embodiment herein, the communication modules (422, 444) may include at least one of the Internet, a wired network (a Local Area Network (LAN), a Controller Area Network (CAN), a Universal Asynchronous Receiver / Transmitter (UART), a bus network, Ethernet and so on), a wireless network (a Wi-Fi network, a cellular network, a Wi-Fi Hotspot, Bluetooth, Zigbee and so on using Wireless Application Protocol), a direct interconnection, and so on.

[0073] In an embodiment herein, the communication modules (422, 444) can be configured for communicating internally between internal hardware components of the transmitter (402) and the receiver (404) and with a network (not shown). In an embodiment herein, the network can be at least a wired network and a wireless network, wherein the wireless network can be for example, but not limited to a fourth generation (4G) network, a fifth generation (5G) network, a 6G network, an Open Radio Access Network (ORAN) or the like.

[0074] In an embodiment herein, the processors (418, 440) can include analog and / or digital circuits such as logic gates, integrated circuits, microprocessors, microcontrollers, memory circuits, passive electronic components, active electronic components, optical components, hardwired circuits and the like, and may optionally be driven by firmware.

[0075] The processors (418, 440) may further, include one or a plurality of processors. The one or the plurality of processors may be a general-purpose processor, such as a central processing unit (CPU), an Application processor (AP), or the like, a graphics-only processing unit such as a graphics processing unit (GPU), a visual processing unit (VPU), and / or an AI-dedicated processor such as a neural processing unit (NPU). The processors (418, 440) may include multiple cores and is configured to execute the instructions stored in the memories (420, 442).

[0076] Further, the processors (418, 440) are configured to execute instructions stored in the memories (420, 442) and to perform various processes. The memories (420, 442) can also store instructions to be executed by the processors (418, 440). The memories (420, 442) may include non-volatile storage elements. Examples of such non-volatile storage elements may include magnetic hard discs, optical discs, floppy discs, flash memories, or forms of electrically programmable memories (EPROM) or electrically erasable and programmable (EEPROM) memories. In addition, the memories (420, 442) may, in some examples, be considered a non-transitory storage medium. The term "non-transitory" may indicate that the storage medium is not embodied in a carrier wave or a propagated signal. However, the term "non-transitory" should not be interpreted that the memories (420, 442) is non-movable. In certain examples, a non-transitory storage medium may store data that can, over time, change (e.g., in Random Access Memory (RAM) or cache).

[0077] In an embodiment herein, the reference signal analyzer engine (432) of the receiver (404) can acquire a reference signal carrying a plurality of ECC encoded data through at least one fading channel medium, from the transmitter (402). In an example embodiment herein, the plurality of ECC encoded data can be, for example, a plurality of polar encoded data, a plurality of PAC encoded data, a plurality of turbo code encoded data, a plurality of LDPC encoded data and so on.

[0078] In an example embodiment herein, each of the plurality of ECC encoded codes are attached with a cyclic redundancy check (CRC) code for enabling the receiver (404) to select a plurality of decoder cores for a decoding mechanism. Further, in an example embodiment herein, each of the plurality of polar encoded data are phase modulated by such as a Quadrature Phase Shift Keying (QPSK) modulator present with the transmitter (402). In an embodiment herein, the reference signal analyzer engine (432) further can analyze the plurality of ECC encoded data (bits) in order to detect coding pattern of a plurality of the encoded data received through the fading channel.

[0079] In an example embodiment herein, the reference signal analyzer engine (432) can derive a plurality of channel-inputs to feed thereof to the decoding variable identifier engine (436). In an embodiment herein, the plurality of channel-inputs can comprise, a plurality of Signal to noise ratios (SNRs), a plurality of Effective Signal to noise ratios (ESNRs), a plurality of code rates or modulation order or modulation and coding scheme index (MCS), LLRs, a plurality of first type Link abstraction metrics such as without limitation, a plurality of Received bit information rates (RBIRs), a plurality of exponential effective SNR mapping (EESM), and a plurality of mean mutual information per bit (MMIB). Further, the plurality of channel-inputs can comprise a plurality of Channel (Intermediate) LLRs, and a histogram of channel LLRs. In an embodiment herein, the LLR generation engine (434) can generate, from the plurality of ECC encoded bits, the plurality of Channel (Intermediate) LLRs and the histogram of channel LLRs (or intermediate LLRs). Further, the LLR generation engine (434) can identify the LLR-pattern of the plurality of LLRs identifiable through negative LLRs and positive LLRs from the histogram of channel LLRs. Further, the LLR generation engine (434) can generate mean, median, mode, difference between min and max and so on for the plurality of LLRs. In an embodiment herein, based on the plurality of channel-inputs of the fading channel, an optimal set of decoding variables can be decided adaptively by the decoding variable identifier engine (436) before decoding a signal received from the transmitter (402).

[0080] In an example embodiment herein, the optimal set of decoding variables include an optimal set of list size of a plurality of decoder cores in a Successive cancellation list (SCL) based decoding, an optimal set of list size of the plurality of decoder cores in a list-based decoding, an optimal depth level in a list-based decoding, and an optimal set of a plurality of optimal iteration numbers in an iterative decoding and so on. In an embodiment herein, the optimal set of list size of the plurality of decoder cores is used to determine the number of decoding paths pursued in the list-based decoding. The optimal set of depth level is used to determine depth at which instantaneous decoding is performed in a binary tree search based list-decoding. The optimal set of a plurality of iteration numbers is used to determine number of iterations used in the decoding procedure.

[0081] In an embodiment herein, the reference signal analyzer engine (432) can obtain a plurality of pre-defined first type link abstraction metrics from an information noise model (such as without limitation an AWGN (Additive White Gaussian Noise) model, and so on), where the information noise model is generated by the processor (440). In an embodiment herein, the processor (440) can generate the information noise model from a plurality of a second type target link-abstraction metrics, and the plurality of SNRs. The plurality of second type target link-abstraction metrics can be a plurality of Block error rates (BLERs) corresponding to the fading channel. In an example embodiment herein, the plurality of pre-defined first type link abstraction metrics include a plurality of pre-defined Received bit information rates (RBIRs), a plurality of exponential effective SNR mapping (EESM), and a plurality of mean mutual information per bit (MMIB).

[0082] In an embodiment herein, based on at least one parameter or a function of at least one parameter (such as, but not limited to, channel LLRs, effective or received SNR, code rate or modulation order or modulation and coding scheme index (MCS), LLRs, RBIR, and so on), for each received LLR stream, the decoding variable identifier engine (436) can identify the optimal set (optimal list) of the plurality of decoder cores. Further, the decoding variable identifier engine (436) can identify the depth level, at which an intermediate or an early decoding can be done. Furthermore, decoding variable identifier engine (436) can identify, a plurality of reduced iteration numbers for an iterative decoding. The early decoding reduces the number of edge traversals significantly, so as to result in huge savings in terms of computations, and power. In an example embodiment herein, the early decoding is performed to reduce the number of edge traversals in a Successive Cancellation (SC), a Successive Cancellation List (SCL) decoding or in any list based decoding, and iterative decoding. At high SNR, the hard decisions is directly made based on the received or channel LLRs and then applying the inverse polar transform is sufficient to decode the codeword. Based on one or many function of a plurality of channel-inputs, and utilizing the structure of polar codes, hard decisions can be made on intermediate nodes of a binary decoding tree to apply the inverse polar transform, and to obtain the information bits. In an example embodiment herein, the plurality of channel-inputs can be, Channel (Received) LLRs (intermediate LLRs), histogram of channel, LLRs or intermediate LLRs (distinguishable from negative to positive LLRs, identify patterns), function of channel / received / intermediate LLRs (for example, mean, median, mode, difference between min and max, etc.)), received SNR / Effective SNR (to have a threshold), code rate (given a code rate), or modulation order or modulation and coding scheme index (MCS), link abstraction metrics (RBIR or EESM (to have a threshold), and so on. One metric means max ((min(LLR>0)) - max((LLR<0))) corresponding to decoding failure cases, wherein the one metric decodes the maximum gap between the positive and negative LLRs observed for unsuccessful decodes. Here, the LLR corresponds to channel LLRs at root level and intermediate LLRs at other depth levels. Along with the mean (abs(channel LLRs)) that acts as a metric for identification of signal strength. This avoids the traversal of binary tree till the leaf nodes for decoding the information bits.

[0083] In an embodiment herein, the decoder engine (438) can comprise a plurality of pre-defined discrete set of decoder cores, wherein the pre-defined discrete set of decoder cores are configured based on at least one of: the plurality of code rates or modulation order or modulation and coding scheme index (MCS), the plurality of LLRs, and the plurality of SNRs, of the fading channel.

[0084] In an embodiment herein, the decoding variable identifier engine (436) can obtain the plurality of channel-inputs from the reference signal analyzer engine (432) and select a reduced list (optimal set) of decoder cores of a channel decoder (herein the decoding engine (438)), from the pre-defined discrete set of decoder cores for the SCL decoding of at least one of: the plurality of polar codes and the plurality of polar variant codes. In an embodiment herein, the decoding variable identifier engine (436) can further determine an optimal path depth size of decode cores from the pre-defined discrete set of decoder cores for the decoding. The optimal list of the decoder cores is used as decoding paths for the decoding. In an embodiment herein, the decoding variable identifier engine (436) can identify the optimal list-size of the decoder cores from the pre-defined discrete set of decoder cores by identifying the set of unused codes from the pre-defined discrete set of decoder cores. In an embodiment herein, the decoder core identifier engine (436) can turn off a successive set of decoder cores from the pre-defined discrete set of decoder cores, and identify as unused decoder cores based on the optimal list of the decoder cores.

[0085] FIG. 4A depicts an example block diagram of a system (400B) configured to select an optimal set of decoding variables (list size of decoder cores) from the pre-defined discrete set of decoding variables for SCL decoding in order to decode at least one of: the plurality of polar codes, and the plurality of polar variant codes, according to embodiments as disclosed herein.

[0086] At block 452, a decoding variable identifier engine (436) of the receiver (404) can receive the plurality of channel-inputs from the reference signal analyzer engine (432) of the receiver (404). The decoding variable identifier engine (436) facilitates selection of a reduced list-size of decoder cores from the pre-defined discrete set of decoder cores. In an embodiment herein, the pre-defined discrete set of decoder cores are configured by the decoder engine (438) based on at least one of: the plurality of code rates, or modulation order or modulation and coding scheme index (MCS), the plurality of LLRs, and the plurality of SNRs, of the fading channel. In an embodiment herein, the plurality of channel-inputs are generated from the reference signal of a fading channel input to the reference signal analyzer engine (432), wherein the input signal carries at least a plurality of polar codes. In an embodiment herein, the plurality of channel-inputs comprise a plurality of Signal to noise ratios (SNRs), a plurality of Effective Signal to noise ratios (ESNRs), a plurality of code rates or modulation order or modulation and coding scheme index (MCS), LLRs, a plurality of first type Link abstraction metrics such as without limitation, a plurality of Received bit information rates (RBIRs), a plurality of exponential effective SNR mapping (EESM), and a plurality of mean mutual information per bit (MMIB). Further, the plurality of channel-inputs comprise a plurality of Channel (Intermediate) LLRs, and a histogram of channel LLRs.

[0087] At block 454, the decoder engine (438) of the receiver (404) can obtain a list-size of a plurality of decoder cores detected based on the plurality of channel-inputs and the plurality of LLRs.

[0088] At block 456, the decoder engine (438) can keep only decoder cores and turn off all the remaining decoder cores in the pre-defined discrete set of decoder cores. In an embodiment herein, the decoder engine (438) can make hard decisions to decode the transmitted codeword using the plurality of LLRs as obtained by the decoder engine (438). Further, in an embodiment herein, the decoder core identifier engine (436) can determine information bits indicating the optimal list-size for the receiver, wherein the optimal list-size of the decoder cores are used as optimal decoding code-words for decoding, where is the maximum list of decoder cores.

[0089] The decoder engine (438) can produce codewords, while keeping only decoder cores active and turns off rest of the decoder cores.

[0090] At block 458, the codewords, are fed to a CRC checking engine (486), wherein the CRC checking engine (486) can give information on a plurality of encoded bits which passes CRC check. In an embodiment herein, from codewords, at least one codeword corresponding to CRC check success is used for abstracting information bits.

[0091] FIG. 4B depicts an example block diagram of a system (400C) configured to select a plurality of decoding variables (any of optimal list size or optimal depth level or optimal iteration numbers of decoder cores) from the pre-defined discrete set of decoding variables for the ECC decoding in order to decode at least one of: the plurality of polar codes, the plurality of polar variant codes, the plurality of turbo codes, the plurality of LDPC codes and so on, according to embodiments as disclosed herein. In an embodiment the system (400C) comprises components such as the decoding variable identifier engine (436), the decoder engine (4384) with a discrete set of a plurality of decoding variables and a CRC checking engine (462). Working functionality of the components of the system (400C) are similar to the system (400B) as depicted for SCL decoding. Hence, we are not repeating the same operation in the patent disclosure. The decoder engine (438) of the receiver (404) can obtain an optimal set of decoding variables , based on the plurality of channel-inputs and the plurality of LLRs. In an example embodiment herein, the optimal set of decoding variables include at least one of, the set of an optimal list size of a plurality of decoder cores in a Successive cancellation list (SCL) based decoding, the set of an optimal depth level in a list based decoding, and the set of a plurality of optimal iteration numbers in an iterative decoding.

[0092] Further, the decoder engine (438) can keep only decoder cores (decoding variables) and turn off all the remaining decoder cores in the pre-defined discrete set of decoder cores. Further, in an embodiment herein, the decoder core identifier engine (436) can determine information bits indicating the optimal set of decoding variables for decoding by the receiver, wherein the optimal set of the decoding variables are used as optimal decoding code-words for decoding, where is the maximum number of decoding variables.

[0093] The decoder engine (438) can produce codewords, while keeping only decoder cores active and turns off rest of the decoder cores. FIG. 5A depicts an example intermediate (early) decoding module in the decoder engine (438), according to embodiments as disclosed herein. An intermediate decoding module (520) can be at or before the root node in the decoder engine (438). The input to the intermediate decoding module (520) can be one / many / function of the parameters from the code rate, or modulation order or modulation and coding scheme index (MCS), the channel LLRs, the received bit information rate (RBIR), the received SNR ( RX 10 SNR), the effective SINR, and so on. The output of the intermediate decoding module (520) (early decoding block) can be depth level for instant hard decision decoding, depth level can vary from root to leaf nodes, and so on.

[0094] FIG. 5B is a flow chart (500B) depicting a process of performing an intermediate (early) decoding in the SC decoder, according to embodiments as disclosed herein.

[0095] At step 502, the process includes configuring, by the processor (440), the intermediate decoding module within the decoder engine (438) with the plurality of parameters such as, at, such as code rate or modulation order or modulation and coding scheme index (MCS), the channel LLRs, the received bit information rate (RBIR), the received SNR (RX SNR), the effective SINR, and so on.

[0096] In an embodiment herein, the decoder engine (438) is an SC decoder engine. In an example embodiment herein, the intermediate decoding module comprises of a decoder list-size identifier and the SC decoder engine. In an embodiment herein, depth level, can be provided to the SC decoder engine, wherein the SC decoder engine is a decoder engine of length .

[0097] At step 504, the process includes configuring, by the intermediate decoding module, I number of intermediate nodes at depth d. In an embodiment herein, is the number of intermediate nodes present at depth and is initialized as

[0098] At step 506, the process includes calculating, by the intermediate decoding module, hard decisions based on sign of intermediate LLR For an intermediate nodes present at depth d.

[0099] At step 508, the process includes, performing by the intermediate decoding module, inverse polar transformation on intermediate bits and obtaining information bits.

[0100] At step 510, the process includes identifying intermediate decoding module presence of number of wrongly decoded frozen bit positions, F (identified) (if any).

[0101] In an embodiment herein, at step 512, the process includes, determining by the intermediate decoding module, if there are any wrongly decoded frozen bit positions (i.e., ), followed by a step 514, of at least one of: -performing by the intermediate decoding module a flip to the wrongly decoded frozen bits and a matrix is applied on the information to get bits at depth , when F>0.

[0102] At step 518, the process include checking by the intermediate decoding module if, N information bits are decoded, when F<0. In an embodiment herein, if there are no wrongly decoded frozen bit positions, and if all the information bits are decoded, the decoding process is stopped.

[0103] At step 516, the process include traversing by the intermediate decoding module back to parent and perform regular SC decoding till (i+1)th intermediate node at depth d is reached, when all N information bits are not decoded.

[0104] Furthermore, in an example embodiment herein, the decoder engine (438) is an iterative decoder engine. In an example embodiment herein, further, the intermediate decoding module comprises of a decoding variable identifier (436) engine and the iterative decoder engine. In an embodiment herein, an optimal set of a plurality of iterative numbers (n), can be provided to the iterative decoder engine, wherein the iterative decoder engine is a decoder engine of length .

[0105] FIG. 6A depicts an example intermediate decoder engine (630) (early decoder engine), according to embodiments as disclosed herein. In an example embodiment herein, the early decoder engine shall indicate a flag that indicates whether to do the instant decoding or not. Say, 1 indicates to do instant decoding and 0 indicates not to do instant decoding. Further, in an example embodiment herein, intermediate decoding is performed by an iterative decoder engine.

[0106] FIG. 6B depicts a flow chart of a process (600B) for performing instant decoding at the intermediate node in the decoder engine (438), wherein the decoder engine in a SC decoder engine, according to embodiments as disclosed herein.

[0107] At step 602, the process includes, configuring the plurality of intermediate LLRs, at each intermediate node, other than a root node and each leaf node. In case of instant decoding, decoder engine (438) takes hard decisions on the intermediate node based on the sign of the LLRs. In an embodiment herein, a function of intermediate LLRs is provided as the input to the early decoding block at each intermediate node (i.e., a node other than the root and leaf nodes).

[0108] At step 604, the process includes identifying, by the intermediate decoding module, that the instant decode is required based on the flag indicating whether to do the instant decoding or not.

[0109] At step 606, the process includes performing at least one of: calculating by the intermediate decoding module hard decisions on the intermediate nodes, when an instant decode is required, and continuing regular SC deciding and traversing to left child node by the intermediate decoding module, when an instant decode is not required.

[0110] At step 608, the process includes performing the inverse polar transformation on intermediate bits and obtaining information bits by the intermediate decoding module.

[0111] At step 610, the process includes identifying the intermediate decoding module number (N) of wrongly decoded frozen bit positions.

[0112] At step 612, the process includes checking, by the intermediate decoding module, N>0.

[0113] At step 614, the process includes, performing at least one of: a flip to the wrongly decoded frozen bits, when N>0 is determined and traversing back to parent node and continuing SC decoding, when N<0 is determined at step 618.

[0114] At step 616, the process includes applying G Matrix on information bits to obtain bits at depth d by the intermediate decoding module. At step 620, the process includes continuing regular SC deciding and traversing to left child node.

[0115] Therefore, a function of intermediate LLRs is provided as the input to the early decoding block at each intermediate node (i.e., a node other than the root and leaf nodes). If there is a flag to indicate to perform instant decoding, hard decisions are calculated. The inverse polar transform is taken, and information bits are obtained. The number of wrongly decoded frozen bit positions, are identified (if any). If there are any wrongly decoded frozen bit positions, the wrongly decoded frozen bit positions are flipped, and a matrix is applied on the information to get bits at depth . Then or if there are no wrongly decoded frozen bit positions, traverse back to the parent node, and continue SC decoding. If there is no flag indicating to perform instant decoding, regular SC decoding is continued, and traverse is done to the left child node.

[0116] In an example embodiment herein, a decoder engine performing instant decoding based on an optimal set of a plurality of iteration numbers follows a similar process, as depicted above.

[0117] FIG. 7A depicts an example intermediate decoding module (750) (early decoder engine) in a SCL decoder engine, wherein the intermediate decoding module (750) can be located at or before the root node in the SCL decoder engine, according to embodiments as disclosed herein. The input to the early decoder engine can be function(s) of one or many parameters such as, code rate or modulation order or modulation and coding scheme index (MCS), channel LLRs, received bit information rate (RBIR), received SNR (RX SNR), effective SINR, and so on. The output of the early decoder engine is depth level for instant hard decision decoding, herein the depth level can vary from root to leaf nodes. Further, for an SCL decoder engine, once a depth, is identified, embodiments propose to find the lists and their corresponding path metrics of SCL decoder engine using the below method. At a first intermediate node at depth , the default and the first path (list) shall be the one with the wrongly decoded frozen bits flipped and the path metric shall be the summation of absolute values of LLRs corresponding to flipped LLR bits. As this will be the default path, embodiments herein can initiate the path metric as zero. For second path, embodiments herein shall flip the least reliable bit, and add path metric as the absolute of the LLR value corresponding to the least reliable bit. The LLR value of least reliable bit can be found using G matrix and the LLR values corresponding to intermediate LLRs. At second intermediate node at depth , embodiments herein again split the paths into 2, making the number of paths 2 fold, by flipping the least reliable bit. The LLR value of the least reliable bit can be found using G matrix and the LLR values corresponding to intermediate LLRs. On reaching the last intermediate node at depth d, embodiments herein again split the paths into 2, by flipping the least reliable bit. If number of paths obtained, , we flip a total of least reliable bits, one at a time. The LLR value of least reliable bits can be found using G matrix and the LLR values corresponding to intermediate LLRs. Further, an intermediate decoding module is present for an iterative decoder engine for performing intermediate decoding at or before root node.

[0118] FIG. 7B depicts an example flowchart (700B) for a process of performing intermediate decoding in an SCL decoder engine, according to embodiments as disclosed herein.

[0119] At step 702, the process includes, configuring, by the processor (440), the intermediate decoding module with function(s) of one or more plurality of the parameters such as code rate or modulation order or modulation and coding scheme index (MCS), channel LLRs, received bit information rate (RBIR), received SNR (RX SNR), effective SINR, and so on.

[0120] At step 704, the process includes initializing, by the intermediate decoding module, L path metrics with 0 and obtaining M number of intermediate nodes at depth d. In an embodiment herein, a depth level is provided to the SCL decoder engine with L paths. L path metrics are initialized with 0. The number of intermediate nodes at depth d (M) are obtained. i=1 is initialized, wherein (i=1)<M. The number of paths (P) are initialized to zero.

[0121] At step 706, the process includes, calculating, by the intermediate decoding module, at depth d, hard decisions at intermediate node I, initialize i=1(<M).

[0122] At step 708, the process includes, performing, by the intermediate decoding module inverse polar transformations at intermediate node I and obtaining information bits.

[0123] At step 710, the process includes, identifying, by the intermediate decoding module, number of wrongly decoded frozen bit positions, N. In an aspect.

[0124] At step 712, the process includes, checking, by the intermediate decoding module, presence of the number of wrongly decoded frozen bit positions (N>0),

[0125] At step 714, the process includes, performing, by the intermediate decoding module, a flip to the wrongly decoded frozen bit positions and diverge into paths.

[0126] At step 716, the process includes, evaluating by the intermediate decoding module, If, i<M, followed by at step 718, where the process includes, at least one of - evaluating by the intermediate decoding module, If, i=M, and P<L, when i>M.

[0127] At least one of event comprises at least one of: applying by the intermediate decoding module G Matrix on information bits to get corrected intermediate bits, when i<M, and performing by the intermediate decoding module a flip to a least reliable bit, when i<M.

[0128] At step 720, the process includes performing by the intermediate decoding module, a flip to L-P least reliable bits, one at a time for j=1 to L-P, when the i=M, and P<L condition is satisfied for i>M.

[0129] At step 722, the process includes, obtaining by the intermediate decoding module, a path metric as summation of absolute values of LLRs corresponding to j least reliable bits, for j=1 to L-P.

[0130] At step 724, the process includes, updating by the intermediate decoding module, Path metric with addition of absolute value of LLR corresponding to j least reliable bits, for j=1 to L-P.

[0131] At step 726, the process includes, applying by the intermediate decoding module, G Matrix on information bits to get corrected intermediate bits at depth d.

[0132] At step 728, the process includes, picking by the intermediate decoding module, a path with CRC check as success.

[0133] At step 730, the process includes, applying by the intermediate decoding module, G Matrix on information bits to get corrected intermediate bits, when the condition i<M is satisfied.

[0134] At step 732, the process includes, updating by the intermediate decoding module, path metric (P).

[0135] At step 734, the process includes, performing by the intermediate decoding module, a flip to a least reliable bit, when the condition i<M is satisfied.

[0136] At step 736, the process includes, obtaining by the intermediate decoding module, LLR value of the least reliable bit using inverse polar transform and intermediate LLRs.

[0137] At step 738, the process includes, updating by the intermediate decoding module, Path metric with addition of absolute value of LLR corresponding to least reliable bit.

[0138] At step 740, the process includes, applying by the intermediate decoding module, G Matrix on information bits to get corrected intermediate bits at depth d.

[0139] At step 742, the process includes, updating by the intermediate decoding module, the path metric (P) as 2P, for both the events, occurred for the condition i<M.

[0140] At step 744, the process includes, checking by the intermediate decoding module, if, P<L.

[0141] At step 746, the process includes, performing by the intermediate decoding module, at least one of: traversing back till next intermediate node at depth d, using regular SCL decoding, and Prune away P-L Paths.

[0142] Therefore, in aspect, if i is not less than M and if (i-M and P<L), the L-P least reliable bits are flipped one at a time for j=1 to L-P. The path metric is obtained as a summation of absolute values of LLRs corresponding to j least reliable bits, for j=1 to L-P. The path metric is updated with the addition of absolute values of LLRs corresponding to j least reliable bits, for j=1 to L-P. The G matrix is applied on the information bits to get corrected intermediate bits at depth d. The path with CRC check is picked as success.

[0143] Further, if i is less than M, a G matrix is applied on the information bits to get corrected intermediate bits at depth d and the path metric is updated as the same. Further, if i is less than M, the least reliable bit is flipped. The LLR value of the least reliable bit is obtained using inverse polar transform and intermediate LLRs. The path metric is updated with addition of absolute value of LLR corresponding to the lest reliable bit. The G matrix is applied on the information bits to get corrected intermediate bits at depth d. Subsequently, P is multiplied by 2. If P<L, traverse back till the next intermediate node at depth d, using regular SCL decoding, and i is incremented by 1. If P is not less than L, P-L paths are pruned away, traverse back till the next intermediate node at depth d, using regular SCL decoding, and i is incremented by 1.

[0144] Further, embodiments herein can decide to perform intermediate or early termination of the decoding, during the decoding procedure. Based on one / many / function of the parameters (channel LLRs, effective or received SNR, Code rate, or modulation order or modulation and coding scheme index (MCS), RBIR), for each received LLR stream, the receiver can identify the depth level, at which intermediate or early termination can be done. This also includes the case of terminating the decoding at root level, which is equivalent to terminating the decoding procedure before it starts. 10% BLER is the typical operating region of most of the devices in cellular technology (for example). At this region, 10% of the times, SCL decoding is going to fail. All the failed decoding packets follow certain pattern in terms of received SNR, RBIR, and histogram of LLRs given the code rate. At each depth level, including the root node, based on one / many / function of the following parameters, the receiver make a decision whether to continue the decoding procedure further or terminate. The parameters are,

[0145] - Channel / Received LLRs / Intermediate LLRs

[0146] - Histogram of channel LLRs or intermediate LLRs (Distinguishable from negative to positive LLRs, identify patterns)

[0147] - Function of channel / received / intermediate LLRs; for example, Mean, median, mode, difference between min and max, etc.

[0148] - Received SNR / Effective SNR

[0149] - Code rate or modulation order or modulation and coding scheme index (MCS) (Given a code rate)

[0150] - Link abstraction metrics: RBIR or EESM (To have a threshold)

[0151] The proposed method avoids the running of decoder unnecessarily, when the decoder engine (438) is going to be unsuccessful.

[0152] The proposed method discloses an early termination process at the root level. Using a function of parameters (such as code rate or modulation order or modulation and coding scheme index (MCS), channel LLRs, RBIR effective or Rx SNR), the early termination process provides the flag to indicate termination or continuing of the SCL decoding process.

[0153] The proposed method discloses the early termination block at depth levels greater than zero. Using a function of intermediate LLRs, the early termination process provides the flag to indicate termination or continuing of the SCL decoding process.

[0154] Based on one / many / function of the parameters (channel LLRs, effective or received SNR, Code rate, or modulation order or modulation and coding scheme index (MCS), RBIR), for each received LLR stream, the proposed method can identify the list size, using which SCL decoding can be done. This reduces the number of lists maintained for a given decoding, resulting in huge savings in terms of computations, and thus, saving the power. In SCL decoding, list size decides the number of paths to be pursued for decoding. It is observed that at low SNR, a large list sizes help in improving the BLER performance, while at high SNR, smaller list sizes will be sufficient to achieve the required BLER. Based on one / many / function of the following parameters, embodiments herein adaptively decide the list size before decoding each received signal. This helps in huge power saving, by turning off the decoder cores, that are not required to be run.

[0155] FIG. 8A is a flow diagram (800A) depicting a method for selecting an optimal set of decoding variables of a plurality of decoder cores, for the ECC decoding, according to embodiments as disclosed herein.

[0156] At step 802, the method comprises receiving, by the decoding variable identifier engine (436) of the receiver (404), the plurality of channel-inputs, from the reference signal analyzer engine (432). In an embodiment herein, the plurality of channel-inputs includes a plurality of Signal to noise ratios (SNRs), the plurality of Effective Signal to noise ratios (ESNRs), the plurality of code rates or modulation order or modulation and coding scheme index (MCS), LLRs, the plurality of first type Link abstraction metrics such as without limitation, a plurality of Received bit information rates (RBIRs), a plurality of exponential effective SNR mapping (EESM), and a plurality of mean mutual information per bit (MMIB). Further, the plurality of channel-inputs can comprise a plurality of Channel (Intermediate) LLRs, and a histogram of channel LLRs. In an embodiment herein, a channel-inputs analyzer engine can receive an input signal of at least a plurality of polar codes through a fading channel, in order to generate the plurality of the channel-inputs by analyzing the input signal.

[0157] At step 804, the method comprises determining, by the decoding variable identifier engine (436), the plurality of the first type link-abstraction metrics based on the plurality of channel-inputs. In an embodiment herein, the plurality of the first type link-abstraction metrics include at least one of: the plurality of RBIR for the fading channel, a plurality of EESM for the fading channel, and the plurality of MMIB for the fading channel.

[0158] At step 806, the method comprises comparing, by the decoding variable identifier engine (436), the plurality of determined first type link-abstraction metrics with the plurality of pre-defined first type link-abstraction metrics. In an embodiment herein, the plurality of pre-defined first type link-abstraction metrics include at least one of: the plurality of pre-defined RBIR for the fading channel, the plurality of EESM for the fading channel, and the plurality of pre-defined MMIB for the fading channel.

[0159] At step 808, the method comprises, identifying, by the decoding variable identifier engine (436), the reduced number of the plurality of decoder variables from a pre-defined discrete decoding variables based on the comparison for performing at least an ECC decoding. The identified reduced number (optimal set) of the plurality of decoding variables has one determined first type link-abstraction metric closest to one pre-defined first type link-abstraction metric. In an embodiment herein, the decoding variable identifier engine (436) can obtain, from the processor (440), the information noise model corresponding to the fading channel, for determining the plurality of the first type pre-defined link-abstraction metrics. In an embodiment herein, the information noise model generates a first look up table with, a plurality of a second type target link-abstraction metrics, the plurality of SNRs and the pre-defined discrete decoding variables. In an example embodiment herein, the reduced number of decoding variables are an optimal set of list size of a plurality of decoder cores in a Successive cancellation list (SCL) based decoding, an optimal set of depth level in a list based decoding, and an optimal set of a plurality of optimal iteration numbers in an iterative decoding. Further, in an example embodiment herein, the optimal depth level from the pre-defined discrete set of depth levels is selected by the receiver (404) for decoding at least, a plurality of polar codes and polar variant codes or codes with list-based decoding algorithms with list size greater than or equal to 1, wherein the optimal depth level is used for instantaneous decoding in the decoding tree.

[0160] FIG. 8B depicts a flow diagram 800B of a method for selecting, the reduced number (optimal set) of decoder variables, with the plurality of SNRs, wherein each SNR achieving the target second type target link abstraction metric, according to embodiments as disclosed herein.

[0161] At step 812, the method comprises, obtaining by the decoding variable identifier engine (436), the information noise model (such as an AWGN model and so on) with the first look up table comprising, corresponding to the fading channel, the plurality of the second type target link abstraction metrics, the plurality of SNRs and the pre-defined discrete set of decoder cores. In an embodiment herein, the information noise model is generated by the processor (440). In an example embodiment herein, the plurality of the second type target link-abstraction metrics can be a plurality of target BLERs for the fading channel.

[0162] At step 814, the method comprises determining, by the decoding variable identifier engine (436), the plurality of the first type pre-defined link abstraction metrics from the first look up table. In an embodiment herein, the plurality of pre-defined first type link abstraction metrics include at least one of, the plurality of pre-defined RBIR for the fading channel, the plurality of pre-defined EESM for the fading channel, and the plurality of MMIB for the fading channel.

[0163] At step 816, the method comprises generating, by the processor (440), a second look up table (second LUT) from the first look up table (first LUT), wherein the second look up table (second LUT) includes the plurality of the first type pre-defined link-abstraction metrics and the plurality of SNRs.

[0164] At step 818, the method comprises, identifying, by the receiver (404), in the first LUT, the plurality of SNRs corresponding to the plurality of second type target link-abstraction metrics form the first LUT.

[0165] At step 820, the method comprises, mapping, by the receiver (404), in the second LUT, a single SNR of the plurality of SNRs to a corresponding first type pre-defined link-abstraction metric, in order to select one or more SNRs of plurality of SNRs of a fading channel. In an embodiment herein, the selected one or more SNRs determines the optimal list-size of the plurality of decoder cores.

[0166] In an embodiment herein, the receiver (404) can identify a decodability status of the optimal set of decoding variables based on value of a first type determined link-abstraction metric corresponding to the optimal set of decoding variables that is close to the first type pre-defined link abstraction metric, wherein the decidability status is "decodable". Further, in an embodiment herein, the receiver (404) can identify a decodability status of the optimal set of decoding variables based on value of the first type determined link-abstraction metric corresponding to the optimal set of decoding variables is far away from the first type pre-defined link-abstraction metrics, wherein the decodability status of the decoding core is "not decodable".

[0167] FIG. 9A depicts a flow diagram (900A) of an example method for selecting an optimal set of the plurality of decoding variables, based on at least an RBIR of a fading channel, the RBIR is matching with a RBIR threshold and achieving a target BLER, according to embodiments as disclosed herein. In an embodiment herein, the optimal set of the plurality of decoding variables includes at least, an optimal set of list size of a plurality of decoder cores in a Successive cancellation list (SCL) based decoding, an optimal set of depth level in a list based decoding, and an optimal set of iteration numbers in an iterative decoding and so on.

[0168] At step 902, the method comprises receiving, by the receiver (404), the data with at least, one code rate R, or modulation order or / and modulation and coding scheme index (MCS), LLRs with the plurality of reference signals of a fading channel. Further, in an example embodiment herein, the receiver (404), receives the data of a fading channel with one of a modulation order, or modulation and coding scheme index (MCS). In an embodiment herein, the decoding variable identifier engine (436) shall maintain a discrete set of at least one of, list sizes, iteration numbers, depth levels possible (e.g. , L indicates any of the list sizes,iteration numbers,depth

[0169] levels) and the corresponding RBIR thresholds to obtain a target BLER, for all possible modulation schemes and code rates. The RBIR is a fading in-sensitive metric that can map the instantaneous SNR observed in a real time fading channel to the BLER.

[0170] At step 904, the method comprises obtaining, by the receiver (404), the RBIR with the plurality of reference signal. In an embodiment herein, for a real time fading channel scenario, the receiver 404 obtains a RBIR metric for transmission, using the reference signals transmitted along with the data and obtain the reference signal positions in the frequency grid from the transmitter. Further, the receiver (404) obtains an instantaneous SNR on all the reference signal positions. The RBIR is obtained using mutual information on each reference signal tone within a transmission, which is a function of the instantaneous SNR on that tone. In an embodiment herein, RBIR for the plurality of reference signals of the fading channel is obtained using equations (1a), (1b),

[0171]

[0172]

[0173] where, is the number of demodulation reference signals (DMRS) in the grid.

[0174] is the mutual information of jth DMRS symbol in the grid, wherein, the MI is obtained using a look up table, and m is the modulation order.

[0175] is the adjusting factor required for each coding rate to minimize the MI modelling error between the predicted and the observed BLER of a system.

[0176] At step 906, the method comprises comparing, by the receiver (404), the obtained RBIR to the plurality of RBIR thresholds for the at least one of: different list sizes, different depth levels and different iteration numbers, of the code rate R, or modulation order or modulation and coding scheme index (MCS). In an embodiment herein, the obtained RBIR is compared with the RBIR thresholds, (e.g. )to identify the at least one of list size, iteration numbers, depth level, that can provide the target BLER.

[0177] At step 908, the method comprises selecting, by the receiver (404), the at least one of the optimal set of list size, the optimal set of iteration numbers and the optimal set of depth levels for which the RBIR is closest to the RBIR threshold, which provides the target BLER.

[0178] At step 910, the method comprises, feeding by a decoder core identifier engine (436) of the receiver (404) the selected at least the optimal list size, the optimal depth level and the optimal iteration numbers to at least, a decoder engine (438) of the receiver (404), for decoding at least a plurality of polar codes, and a plurality of polar variant codes, wherein the decoder engine is an ECC decoder engine. In an embodiment herein, the decoding variable identifier engine (436) feeds an obtained optimal list size (or optimal depth level or iteration number), (e.g say, ) to the ECC decoder engine for decoding the data. In an embodiment herein, the ECC decoder engine shall keep only decoder cores and turn off all the remaining decoder cores.

[0179] At step 912, the method comprises, evaluating by the ECC decoder engine if CRC check is successful. In an embodiment herein, the ECC decoder engine shall produce codewords, from which a codeword corresponding to CRC check success shall be used for abstracting information bits

[0180] In an embodiment herein, the decoding variable identifier engine (436) sends to the decoder engine (438), the optimal number of the decoder cores via front haul, for enabling decoding, using bits, wherein indicating maximum number of decoding variables for the decoder. In an example embodiment herein, the decoding is performed for of the at least, a polar code and polar variant code, a turbo code, a Low density parity check code (LDPC) code, a concatenated polar code, and a code with list-based decoding algorithms and so on. Further, the decoder engine (438) receive the optimal number of the decoder cores along with a plurality of channel LLRs.

[0181] At step 914, the method comprises obtaining by the ECC decoder engine decoded information bits, when the CRC check is successful.

[0182] At step 916, the method comprises identifying by the ECC decoder engine, decoding failure, when the CRC check is not successful.

[0183] In an embodiment herein, a pseudo technique for an ECC decoder engine with CRC check, to select an optimal set of a plurality of decoding variables (optimal list-size, optimal depth level, optimal iteration number) for the plurality of decoder cores is mentioned below.

[0184] In an embodiment herein, for optimal depth level identification, the pseudo technique includes,

[0185] Initialization: Set DM = log2N and DAdap (optimal depth)=DM (Maximum depth).

[0186] Nodes at depth level Di are represented as and hard decisions at are represented as .

[0187] Choose Dmin : minimum depth level for decoding, implementation, choice, min 0, 1, 2..,M - 1.

[0188] Assign a trial and error based obtained adjusting factor, cod, for the considered code rate, or modulation order or modulation and coding scheme index (MCS).

[0189] For a real-time 5G NR UL transmission, obtain the DMRS locations in the received grid.

[0190] Calculate instantaneous SNR, on each DMRS tone using a formula {1, 2, ..,NDMRS}, wherein multipath fading channel for a DMRS frequency tone n, and noise power observed at the receiver.

[0191] Calculate RBIR using and cod as given in equation (1a).

[0192] for i → M-1 to min do

[0193] if RBIR,Di-1 < RBIR ≤ RBIR, Di then

[0194] DAdap = Di;

[0195] end if

[0196] end for

[0197] In an embodiment herein, method for a fast decoding (power saving decoding) with the identified depth DAdap, includes,

[0198] for j → 0 to 2DAdap - 1 do

[0199] Take hard decisions, on intermediate LLRs at node , based on the sign, using a SC decoding mechanism.

[0200] Apply inverse polar transform of length ,

[0201] on hard decisions, and obtains leaf node bits wherein N is the code length.

[0202] In an embodiment herein, frozen bit correction is performed using,

[0203] count = 0

[0204] for

[0205] if k is frozen bit position & then

[0206]

[0207] count = count +1

[0208] end if

[0209] end for

[0210] if count

[0211]

[0212] end if

[0213] end for

[0214] In an embodiment herein, a method to identify the optimal set of list size of the plurality of decoding variables and the optimal set of iteration numbers of the plurality of decoding variables include,

[0215] Initialization: Define {K1,K2,K3, ..,KM} as discrete set of possible iteration numbers / list sizes for the decoding engine i.e., iteration number for LDPC and turbo, and list size for polar and PAC. Set adaptive iteration number / list size as KAdap = KM.

[0216] Denote code rate of the transmission as R.

[0217] Assign a trial and error simulation based obtained adjusting factor, cod, for the considered code rate R.

[0218] For R, obtain RBIR thresholds, RBIR, Ki Ki {K1,K2,K3, ..,KM}.

[0219] For a real-time 4G LTE and 5G NR DL / UL transmission, obtain the RS locations in the received grid, i.e., CRS for 4G LTE and DMRS for 5G NR.

[0220] Calculate estimated SNR, on each frequency tone using equation {1, 2, ..,NRS}, wherein channel estimate, and noise power observed at the receiver.

[0221] Calculate RBIR using and cod as given in equation (1b).

[0222] for i → M- 1 to 1 do

[0223] if RBIR,Ki-1 < RBIR ≤ RBIR, Ki then

[0224] KAdap = Ki;

[0225] end if

[0226] end for

[0227] if Polar / PAC codes then,

[0228] Run the polar and PAC decoders with list size, L = KAdap, i.e., run the decoder with KAdap decoder cores, and turn off the remaining KM - KAdap cores.

[0229] else if Turbo / LDPC codes then

[0230] Run the decoder for I = KAdap iterations and terminate.

[0231] end if

[0232] In an embodiment herein, a technique to obtain the RBIR threshold include the following steps,

[0233] The adaptive list identifier shall maintain a discrete set of list sizes possible: and the corresponding RBIR thresholds to obtain a target BLER.

[0234] RBIR thresholds stored in the decoding variable identifier engine (436) are obtained using the below two look up tables (LUTs) (FIG. 9B), offline using a AWGN model.

[0235] LUT-a: RBIR vs SNR for the modulation schemes supported

[0236] E.g.: RBIR vs SNR LUT for QPSK, with PDCCH / PUCCH

[0237] LUT-b: SNR vs BLER for , for all possible code rates and modulation schemes.

[0238] Obtain a Look up table (LUT-a), of RBIR / EESM / MMIB with respect to SNR under AWGN channel conditions for any one code rate among all possible code rates within a modulation scheme.

[0239] Modulations schemes:

[0240] QPSK for control (PDCCH, PUCCH)

[0241] QPSK, 16 QAM, 64 QAM, 256 QAM for data (PDSCH, PUSCH)

[0242] Obtain LUT2, of BLER with respect to SNR for different code rates under AWGN channel, with different list sizes, chosen such as .

[0243] In an embodiment herein, the decoding variable identifier engine (436) in the receiver )404) shown in maintains at least one of: a discrete set of iteration numbers and list sizes {K1,K2,K3, ..,KM}, to be used by the decoding engine (438). The step-by-step procedure for predicting the right iteration number and list size, in a real time fading environment is given below, with the objective of achieving a target BLER.

[0244] 1) Firstly, the decoding variable identifier engine (436) obtains a LUT of RBIR-SNR (LUTRBIR-SNR, AWGN) for LTE / NR DL / UL data and control transmissions, using the respective decoding engines for at least of list based decoding and iterative decoding, in AWGN channel for all modulation schemes using Monte Carlo simulations. The RBIR is calculated using the instantaneous estimated SNR on each RS tone (using equation (1b)) in the transmission, with cod = 1. The LUTRBIR-SNR, AWGN remains the same for all possible code rates within a modulation scheme.

[0245] 2) Similarly, obtain LUTs of SNR-BLER mapping for LTE / NR DL / UL data and control transmissions, using the respective decoders, corresponding to all the iteration numbers / list sizes in the set {K1,K2,K3, ..,KM}, respectively, for all possible code rates, in AWGN channel. An SNR-BLER LUT with iteration number / list size Ki will be referred as LUTSNR-BLER, AWGN, Ki. We use these LUTs and LUTRBIR-SNR, AWGN, to calculate the RBIR thresholds for each iteration number / list size. These LUTs are independent of channel fading conditions and have one-to-one mapping among RBIRSNR- BLER.

[0246] RBIR threshold for an iteration number / list size Ki, denoted by RBIR, Ki, is obtained by identifying the SNR corresponding to target BLER from LUTSNR-BLER, AWGN,Ki, and then mapping it to a corresponding RBIR in LUTRBIR-SNR, AWGN. It can be noted that RBIR,Ki < RBIR, Kj, if Ki > Kj, as with the increased iteration number / list size, the considered decoder can attain the target BLER at lower SNR, corresponding to a lower RBIR threshold.

[0247] For a real time fading channel LTE / 5G NR DL / UL, transmission at a given code rate, we calculate the RBIR using instantaneous estimated SNR on RS tones as given in equation (1(b). The obtained RBIR is then compared with the RBIR thresholds, RBIR,Ki Ki {K1,K2,K3, ..,KM}, to identify the iteration number / list size, KAdap that can provide the target BLER. In an embodiment herein, the decoding variable identifier engine (436) can maintain a set of depth levels: {D0,D1,D2, ..,DM}, to be used by the decoding engine (438), for fast decoding, where D0 represents the root level, and DM = log2N represents the leaf node level in a binary tree representation of an SC decoding, with N being the polar encoded length. The step-by-step procedure for predicting the right depth level from this set before employing the decoding engine (438), in a real time fading environment is given below, with the objective of achieving a target BLER, wherein the decoding engine is an SC decoding engine.

[0248] Firstly, obtain a look up table (LUT) of RBIR-SNR (LUTRBIR-SNR,AWGN) for NR UL transmissions in an AWGN channel for all modulation schemes using Monte Carlo simulations. RBIR is calculated using the instantaneous SNR on each DMRS tone in the transmission as explained in (1a), with cod = 1. Note that the LUTRBIR-SNR, AWGN remains the same for all possible code rates within a modulation scheme.

[0249] Similarly, obtain LUTs of SNR-BLER mapping for DL transmissions corresponding to depth levels of the SC decoding engine, {D0,D1,D2, ..,DM}, respectively, for all possible code rates, or modulation order or modulation and coding scheme index (MCS), in AWGN channel. An SNR-BLERLUT with depth level Di will be referred as LUTSNR-BLER, AWGN,Di . We use these LUTs and LUTRBIR-SNR, AWGN, to calculate the RBIR thresholds for each depth level. Note that, these LUTs are independent of channel fading conditions and have one-to-one mapping among RBIR-SNR-BLER.

[0250] RBIR threshold ( RBIR,Di) for a depth level Di, denoted by is obtained by identifying the SNR corresponding to the target BLER from LUTSNR-BLER, AWGN,Di, and then mapping it to a corresponding RBIR in LUTRBIR-SNR, AWGN. It can be noted that RBIR,Di < RBIR,Dj, if Di > Dj, as with the increased depth level, the SC decoding engine can attain the target BLER at lower SNR, corresponding to a lower RBIR threshold.

[0251] For a real time fading channel 5G NR UL transmission at a given code rate, or modulation order or modulation and coding scheme index (MCS), we calculate the RBIR using instantaneous SNR on DMRS tones using equation (1b). The obtained RBIR is then compared with the RBIR thresholds, RBIR,Di Di {D0,D1,D2, ..,DM}, to identify the adaptive depth level (DAdap) that can provide the target BLER.

[0252] We keep a minimum depth level, Dmin for decoding early to minimize the decoding failures due to insufficient refinement of LLRs at early depth levels. The identified adaptive depth level DAdap in the above procedure is fed to the SC decoder along with the channel LLRs, before the channel decoding procedure starts. The proposed method of RBIR-based depth identification is easy to implement at the receiver given its LUT based implementation adding near-zero complexity.

[0253] With the identified depth level DAdap, the decoding engine (438) (herein the SC decoding engine) then proceeds with fast decoding at all the intermediate nodes at DAdap, and decodes all the bits attached to the leaf nodes, corresponding to them in parallel. In the proposed fast decoding, when an intermediate node v is encountered at depth DAdap, it immediately calculates the hard decisions on the intermediate node, using the LLRs, and applies the inverse polar transform of length on them to recover the local codeword.

[0254]

[0255] Further, any wrongly decoded frozen bits are checked by the receiver (404) in the local codeword and flip them. We then correct the hard decisions of intermediate node by applying polar transform on the corrected local codeword.

[0256] The various actions in method 500B, 600B, 700B, 800A-800B, and 900 A, may be performed in the order presented, in a different order or simultaneously. Further, in some embodiments, some actions listed in FIG. 5B, FIG. 6B, FIG. 7B, FIG.s 8A-8B, and FIG. 9A may be omitted.

[0257] FIG. 10A depicts a block diagram of a method for an RBIR-based list size and iteration number identification for respectively a list-based decoding and an iterative decoding in an LTE, a 5G NR, and beyond 5G systems.

[0258] At block 1012, the decoding variable identifier engine (436) of the receiver (404), calculates MI and RBIR upon receiving input of a fading channel comprising, instantaneous estimated SNR on reference signals (5G NR DMRS / LTE Cell specific reference signal (CRS)).

[0259] At block 1014, the decoding variable identifier engine (436) of the receiver (404), identifies the optimal iteration number, the optimal list size and the depth level, based on the calculated RBIR of the fading channel. In an embodiment herein, the decoding variable identifier engine (436) contains a plurality of pre-defined discrete list sizes and iteration numbers of decoder cores and code rate, or modulation order or modulation and coding scheme index (MCS) based RBIR thresholds corresponding to the plurality of pre-defined discrete list sizes and iteration numbers, to identify an optimal set of decoder cores. The RBIR with respect to an optimal set of decoder cores meets a target BLER.

[0260] FIG. 10B depicts a 5G NR transmitter-receiver chain for selecting a reduced number of decoding variables for ECC decoding, according to embodiments as disclosed herein.

[0261] At block 1002, CRC attachment is performed by the transmitter (402) for a plurality of information bits.

[0262] At block 1004, ECC encoding is performed by the transmitter (404) for the plurality of CRC attached information bits.

[0263] At block 1006, modulation mapping is performed by the transmitter (404) for the plurality of ECC encoded CRC attached information bits.

[0264] At block 1008, Orthogonal Frequency Division Multiplexing (OFDM) is performed for transmission of the plurality of ECC encoded CRC attached information bits.

[0265] At block 1010, the plurality of ECC encoded CRC attached information bits are transmitted through a communication channel used for digital communication of encoded data.

[0266] At block 1012, the receiver (404) receives the plurality of ECC encoded CRC attached information bits.

[0267] At block 1014, the receiver (404) generates LLR from the plurality of ECC encoded CRC attached information bits, by channel estimation and equalization.

[0268] At block 1016, the receiver (404) calculates RBIR from the received data.

[0269] At block 1018, an optimal set of a plurality of decoding variables are identified by the receiver (404).

[0270] At block 1020, ECC encoding is performed by the receiver (404), using the identified optimal set of a plurality of decoding variables.

[0271] At block 1022, the receiver (404) is performed CRC check and removal of the CRC and retrieved the information bits.

[0272] Embodiments herein disclose, a system and a method for selecting a reduced list-size of a plurality of decoder cores from a pre-defined discrete set of decoder cores, wherein the proposed system can be used for early decoding in at least a plurality of polar codes. The proposed solution can be used early decoding in polar codes, when used within any of the following channel transmissions:

[0273] - DCI via PDCCH

[0274] ▷ Target BLER of 0.1%

[0275] ▷ Modulation scheme of QPSK

[0276] - Downlink data via PDSCH

[0277] ▷ Target BLER of 10%

[0278] ▷ Modulation scheme of QPSK and 16-QAM, if supported for smaller block lengths.

[0279] - UCI via PUCCH

[0280] ▷ Target BLER of 0.1%

[0281] ▷ Modulation scheme of QPSK

[0282] - UCI or uplink data via PUSCH

[0283] ▷ Target BLER of 10%

[0284] ▷ Modulation scheme of QPSK and 16-QAM, if supported for smaller block lengths.

[0285] Further, the proposed system using link abstraction metric (RBIR / MMIB / EESM / effective SINR) along with the code rate, or modulation order or modulation and coding scheme index (MCS) can also be further used for identifying aggregation level and PDCCH candidate within blind decoding of PDDCH. In blind decoding, a receiver does an exhaustive search over all possible aggregation levels and the PDCCH candidates to decode the DCI from PDCCH. In an example embodiment herein, if a Maximum number of candidates to blindly decode ~ 44, which uses a polar decoder upto ~44 times. In an embodiment herein, for a given list size of SCL decoding, a receiver can maintain the LUT1 with RBIR vs SNR and LUT2 with SNR vs BLER for all code rates, or modulation order or modulation and coding scheme index (MCS). In an embodiment herein, at the receiver, when the blind decoding process starts for control data decoding, RBIR can be calculated using the DMRS of PDCCH, for all the candidates and the aggregation levels. The RBIR can be used to map to BLER using LUT1 and LUT2 in the order. In an embodiment herein, except for the RBIR of the right aggregation level and the candidate number, rest of the metrics calculated would correspond to non-DMRS transmissions. Hence, with the right aggregation level and candidate number, the mapping will correspond to that of target BLER. Further, in an embodiment herein, once the UE maps to target BLER, UE can proceed with decoding the control data. This will help in saving huge power, consumed for running SCL decoder unnecessarily in the additional aggregation level and candidates. In an example embodiment herein, Polarization adjusted convolutional (PAC) codes, a variant of polar codes are also decoded using an adaptive list-size of decoder cores obtained from the proposed system.

[0286] One of the decoding technique used for decoding PAC codes is list-decoder, implementation similar to that of SCL decoder, with an additional convolutional block.

[0287] The proposed adaptive list identifier can be used in list-decoder of PAC codes as well, replacing the SCL with that of list-decoder.

[0288] Embodiments herein disclose methods and systems for parallelizing the operations of a Polar decoder and reducing the latency, complexity, and power consumption is of key interest, in the domain of channel coding for beyond 5G networks (such as, but not limited to, 6G). Embodiments herein disclose methods and systems for identifying a right list size of SCL decoding can help in saving significant amount of power.

[0289] Embodiments herein, disclose an early decoding which can be performed at or before a root node in a SCL decoding. The method of early decoding comprises receiving by a decoder list-size identifier engine, a plurality of channel-inputs generated for a plurality of reference signals of a fading channel, wherein the plurality of reference signals comprises a plurality of polar coded data. In an example embodiment herein, the plurality of channel-inputs are generated by a reference signal analyzer unit. In an embodiment herein, the plurality of channel-inputs can be one of a function or many / function of the parameters such as without limitation code rate, or modulation order or modulation and coding scheme index (MCS), channel LLRs, received bit information rate (RBIR), received SNR (RX SNR), effective SINR, and so on. The method of early decoding can provide depth level for instant hard decision decoding, wherein the depth level can vary from root to leaf nodes, and so on.

[0290] Embodiments herein, depict the decoding variable identifier engine (436). The decoding variable identifier engine (436) can be located before the SCL decoder engine, wherein the input to the decoding variable identifier engine (436) can be a function of one or more parameters from the code rate, the modulation order or the MCS, channel LLRs, RBIR, Rx or effective SNR, and so on. The decoding variable identifier engine (436) can provide the output by analysing the channel LLRs and provide an output of the list size, wherein the list size can be used for achieving the target BLER. The decoding variable identifier engine (436) shall maintain a look up table of the input parameters versus the list size required for decoding based on pre obtained simulation results. The proposed metric in LUT can be a function of the code rate, the modulation order or the MCS, channel LLRs, Rx or effective SINR, RBIR, and so on.

[0291] Embodiments herein disclose, a Memory management unit (MMU) or the radio unit of the receiver (404) sending the optimal set of a plurality of decoding variables of a channel decoder to at least a distributed unit (DU) of the receiver via front haul, for enabling decoding of the at least, a plurality of polar codes and a plurality of polar variant codes using bits, wherein indicating maxima of the decoding variable of the decoder. The decoder engine (436) of the receiver (404), can receive the optimal set of a plurality of decoding variables along with a plurality of channel LLRs, from the DU.

[0292] Embodiments herein describes systems and methods for determining list size required for any list decoder such as successive cancellation list (SCL) decoding or CRC-Aided SCL (CA-SCL) for polar and any other list decoding for polar variant or pre-transformed polar codes such as polarization-adjusted convolutional (PAC) codes. The list size is selected adaptively before the decoding procedure starts. In an embodiment herein, the list size is determined by one or many or function of the following parameters,

[0293] Channel LLRs, Intermediate LLRs, Received SNR / SINR, Effective SNR / SINR, Received bit information rate (RBIR) or exponential effective SNR mapping (EESM) or mean mutual information per bit (MMIB), Code rate, the modulation order or the MCS.

[0294] Embodiments herein, disclose a receiver (UE or BS) (404), shall obtain look up tables as below,

[0295] LUT 1: Received SNR / SINR, Effective SNR / SINR, received bit information rate (RBIR), mean mutual information bit (MMIB) with respect to each transmit SNR, under AWGN channel conditions.

[0296] LUT 2: Block error rate with respect to each transmit SNR for all possible code rates, the modulation order or the MCS, and the pre-defined discrete list sizes such as {L1, L2, L3, ..., LN} under AWGN channel condition.

[0297] Wherein, the receiver (UE or BS) (404), shall calculate the received SNR / SINR, Effective SNR / SINR, received bit information rate (RBIR), mean mutual information bit (MMIB), before channel decoding. In an embodiment the receiver shall obtain the SNR from LUT1.

[0298] In an embodiment herein, using the SNR from LUT1, the receiver shall obtain the right list size from LUT2, for target BLER requirement such as 10% for data channels and 1% for control channel.

[0299] Embodiments herein disclose, an adaptive list identification block, which is created in a Matrix Management Unit (MMU) (not shown) for list decoder of polar and polar variant codes, that uses a function of one or many of code rate, the modulation order or the MCS, channel LLRs, effective SINR, RBIR / EESM / MMIB metrics as the inputs, and outputs the adaptive list size parameter, , for list decoding of polar and polar code variants, based on the channel conditions.

[0300] Embodiments herein disclose the MMU sends the adaptive list size parameter, , to a Distributed unit (DU) (not shown) via front-haul, when polar coded or any polar variant such as PAC (polarization-adjusted convolutional) coded transmissions are to be decoded, using log2(LMax) bits, where LMax is the maximum list size of the list decoder.

[0301] Embodiments herein disclose, the DU gives the adaptive list size parameter, , to the list decoder such as successive cancellation list decoder for polar codes or list decoder for polar variant codes along with the channel LLRs.

[0302] Embodiments herein disclose, the list decoder can be successive cancellation list or simple list decoder with list size L, where L codeword candidates and decoding paths are considered in the process of decoding.

[0303] Embodiments herein disclose, the list decoder of polar and polar variant codes in the DU turns off the unused decoder cores based on the adaptive list size parameter, , received from the MMU.

[0304] Embodiments herein disclose, the list decoder of polar and polar variant codes in the DU can pause the computations of L- decoding paths, upon receiving the adaptive list size parameter,

[0305] Embodiments herein disclose, the adaptive list identification module which will maintain discrete list sizes: {L1, L2, L3, ..., LN }, their corresponding RBIR thresholds: { (RBIR,L1), (RBIR,L2), ...., (RBIR,LN)}, for different code rates, the modulation order or the MCS.

[0306] Embodiments herein disclose, the adaptive list identification module which maintains adjusting factors { _(cod,1), _(cod,2), ..., _(cod,M)} corresponding to all the M code rates, the modulation order or the MCS.

[0307] Embodiments herein disclose, the adaptive list identification module which calculates the RBIR / EESM / MMIB / effective SINR of any transmission using SINR on reference signals or reference signals and data symbols combined.

[0308] Embodiments herein disclose, the adaptive list identification module which compares the RBIR / EESM / MMIB / effective SINR to pre-defined thresholds corresponding to all the set of list sizes in {L_1, L_2, L_3, ....,_N}, obtained for a target BLER, using AWGN simulation results.

[0309] Embodiments herein disclose, the adaptive list identification module which identifies the list size that has RBIR / EESM / MMIB / effective SINR threshold close to that of the ongoing transmission, such that the current transmission can be decoded successfully.

[0310] Embodiments herein disclose, the adaptive list identification module which identifies decodability status using the RBIR / EESM / MMIB / effective SINR threshold and sends the least list size to the DU, when identifies that the codeword is not decodable.

[0311] Embodiments herein disclose, the adaptive list identification module which is applicable to both hardware and software implementations of the decoder.

[0312] FIG. 11 illustrates a BLER performance as a function SNR with various iteration numbers for iterative LDPC decoder, and list sizes for list-based polar decoder in AWGN channel (for example).

[0313] In practical cellular system implementations, all the receiver techniques at both BS and UE are designed and optimized to meet the set target BLER, denoted as BLERTarget. We simulated and observed that the required I and L of the decoders vary as a function of SNR, to meet the target BLER, as shown in FIG. 11. The notation "a" of the FIG. 11 shows the BLER performance of 5G NR LDPC codes, with code rate of 1 / 3, as a function of SNR, and The notation "b" of the FIG. 11 shows that of 5G NR polar codes of encoded length N = 128, with code rate of 1 / 4, for additive white Gaussian noise (AWGN) channel. From The notation "a" of FIG. 11, we can observe that for achieving the target BLER of 10%, I = 2 is sufficient around SNR 4.43 dB, whereas, I = 10 is required at an SNR of 0.21 dB, for 5G NR LDPC codes

[0314] Similarly, L = 2 is sufficient for 5G NR polar codes at an SNR of 4 dB, whereas, L = 32 is required to operate at an SNR of 2.65 dB, for obtaining a target BLER of 0.1%. It is important to note that choosing the right iteration number / list size helps in reducing the power consumption of the decoding process significantly. Even further, having a common method applicable to all the decoders makes it easier for implementation in real time systems. Thus, we propose to identify the iteration number / list size in these decoder types by opportunistically utilizing the time-varying and frequency-selective channel conditions, by capturing them through a link abstraction metric called RBIR, that maps the observed SNR to the BLER of the system.

[0315] FIG. 12 illustrates a 5G NR LDPC Codes with PDSCH Tx-Rx in which performance comparison between proposed ULIP and traditional fixed iteration decoders, for different MCS indices, using TDL-A channel with DS = 30 ns, fD =100Hz.

[0316] The notation "a" of FIG. 12 plots the BLER as a function of SNR for 5G NR LDPC codes with the proposed ULIP choosing the iteration number adaptively among {2,4,6,8,10}, and the traditional fixed iteration decoder withI= 10 for different modulation schemes indicated as MCS index

[0017] , for TDL-A channel with DS = 30 ns and fD= 100 Hz

[0014] . We observe that the BLER decreases with the increase in SNR for all the MCS indices, for both proposed ULIP and fixed-iteration decoder methods, respectively. We also observe that the BLER performance of the proposed ULIP matches exactly with that of fixed-iteration decoder, without any loss, for all the MCS indices, and at all the ranges of SNR.

[0317] The notation "b" of FIG. 12 shows the average adaptive iteration number required with the proposed ULIP as a function of SNR, for all the MCS indices, considered in The notation "a" of FIG. 12. We observe that it reduces with the increase in SNR, as opposed to the fixed iteration number ofI= 10, for all the MCS indices. Further, at SNR corresponding to the target BLER of 10%, we observe that the average iteration numbers required for the adaptive LDPC decoder with the proposed ULIP are only 4.53, 4.9, and 5.36, respectively, for the MCS indices {5,12,17}, corresponding to QPSK, 16-QAM, and 64-QAM modulation schemes, respectively.

[0318] FIG. 13 illustrates LTE Turbo Codes with PDSCH Tx-Rx in which performance comparison between proposed ULIP and traditional fixed iteration decoders, for different MCS indices, using EPA-5Hz channel.

[0319] Similarly, FIG. 13 shows the BLER and average adaptive iteration number of turbo codes with the proposed ULIP, choosing the iteration number adaptively among {2,4,6,8,10}, and fixed iteration decoder with I = 10, for EPA-5 Hz. From the notation "a" FIG. 13, we observe that the BLER performance of the turbo decoder with the proposed ULIP matches exactly with that of fixed-iteration turbo decoder, without any loss, for all the MCS indices, and at all the ranges of SNR. The reduction in average iteration number with the proposed ULIP can be observed from the notation "b" of FIG. 13.

[0320] FIG. 14 illustrates the 5G NR Polar Codes with PDCCH Tx-Rx in which performance comparison between proposed ULIP and traditional fixed list size decoders, for different code rates, using TDL-A channel with DS = 30 ns, fD =100Hz.

[0321] The notation "a" of the FIG. 14 plots the BLER as a function of SNR for 5G NR polar codes with the proposed ULIP choosing the list size adaptively among {2,4,8,16,32}, and the traditional fixed list size decoder withL= 32, for different code rates, using TDL-A channel with DS = 30 ns and fD= 100 Hz. We observe that the BLER decreases with the increase in SNR for all the code rates {1 / 2,1 / 3,1 / 4}, for both proposed and fixed-list decoder methods, respectively. We also observe that the BLER performance of the proposed ULIP matches exactly with that of fixed-list size decoder, without any loss, for all the code rates, and at all the ranges of SNR.

[0322] The notation "b" of the FIG. 14 shows the average adaptive list size required with the proposed ULIP as a function of SNR, for all the code rates, considered in Fig. 14. We observe that it reduces with the increase in SNR, as opposed to the fixed list size ofL= 32, for all the code rates. Further, at SNR corresponding to the target BLER of 0.1% [7], we observe that the average list sizes required for the proposed ULIP are only 2.7, 2.69, and 2.49, respectively, for the code rates {1 / 2,1 / 3,1 / 4}.

[0323] FIG. 15 illustrates PAC Codes with 5G NR PDCCH Tx-Rx in which performance comparison between proposed ULIP and traditional fixed list size decoders, for different code rates, using TDL-A channel with DS = 30 ns, fD =100Hz. respectively. Similarly, The notation "a" of the FIG. 15 shows the BLER and average adaptive list size of PAC codes with the proposed ULIP choosing the list size adaptively among {2,4,8,16,32}. From The notation "a" of the FIG. 15, we observe that the BLER performance of the PAC decoder with the proposed ULIP matches exactly with that of fixed list size PAC decoder, without any loss, for all the code rates, and at all the ranges of SNR. Whereas, the reduction in the average list size of the PAC decoder with the proposed ULIP can be observed from The notation "b" of the FIG. 15.

[0324] FIG. 16 illustrates the BLER performance of SC decoder with decoding at different depth levels in AWGN channel, for N =1024, and code rate of 1 / 2.

[0325] FIG. 16 shows the BLER performance of the 5G NR polar codes of length N = 1024, with code rate of 1 / 2, as a function of SNR, decoded using SC decoder for additive white Gaussian noise (AWGN) channel, at various depth levels. The notation SC(Di) refers to the performance when decoded at depth level i, where, i = 0 represents the root level. For decoding at a depth level, Di, we hard-quantize the LLRs, apply an inverse sub-polar transform and then correct the wrongly decoded frozen bits. We can observe that for achieving the target BLER of 10%, which is typically the operating BLER for 3GPP data transmissions

[0010] , SC(D10) is required below SNR 2.45 dB, whereas, SC(D0) is sufficient above an SNR of 11.05 dB. It is important to note that choosing the right depth level decreases the decoding latency significantly, given the reduced number of edge traversals and computations with intermediate node decoding. Thus, we need a method to identify the right depth level for an SC decoder that meets the requirement of target BLER in real time systems based on varying channel conditions. We observed that the depth level for obtaining a target BLER is a function of SNR. It is studied and proved in the literature that the link abstraction metrics such as RBIR work pretty well in estimating the system BLER given an observed SNR in real time fading systems. Thus, we choose RBIR, which is relatively simple and easy to implement, in identifying the depth level adaptively for fast SC decoding.

[0326] FIG. 17 illustrates performance comparison between proposed RBIR-AFSC and traditional SC decoders, for different code rates, using TDL-A channel.

[0327] The notation "a" of the FIG. 17 plots the BLER as a function of SNR for the proposed RBIR-AFSC decoder with Dmin = 8 and traditional SC decoders, for code rates of {3 / 4,1 / 2,1 / 3,1 / 4}, respectively, with their corresponding adjusting factors, cod, for TDL-A channel with DS = 30 ns and fD = 100 Hz. The adjusting factors shown in the figure are obtained for each code rate by trial and error simulation analysis [8], that ensure no loss in BLER performance. We observe that the BLER decreases with the increase in SNR for all the code rates, for both RBIR-AFSC and SC decoder methods, respectively. We also observe that the BLER performance of the proposed RBIRAFSC decoder matches exactly with that of traditional SC, without any loss, for all the code rates, and at almost all the ranges of SNR.

[0328] The notation "a" of Fig. 17 shows the average latency calculated using,

[0329]

[0330] The notation "b" of the FIG. 17 shows the average latency calculated using (5), with the proposed RBIR-AFSC decoder and the traditional SC decoder, as a function of SNR, for all the code rates, considered in Fig. 6a. We observe that the latency of the proposed RBIR-AFSC decoder reduces with the increase in SNR, as opposed to that of the traditional SC decoder, for all the code rates. Further, at SNR corresponding to the target BLER of 10%, we observe that the average latency of the proposed RBIR-AFSC decoder is reduced by around 53.21%, for a code rate of 3 / 4.

[0331] FIG. 18 illustrates the performance comparison of proposed RBIR-AFSC with varying Dmin, using TDL-A channel with DS = 30 ns, fD =100Hz, and code rate of 1 / 2.

[0332] Fig. 18 shows the average latency with the proposed RBIRAFSC decoder as a function of SNR, for a code rate of with varying values of Dmin. We observe that the average latency of the proposed RBIR-AFSC decoder decreases with the increase in SNR, for all the values of Dmin ranging from 0 to 9. For the case of Dmin = 10 which corresponds to the leaf level decoding and is equivalent to the traditional SC decoding, the latency remains constant and high, irrespective of SNR. However, choosing a lower value of Dmin can cause some degradation in BLER performance, due to the insufficient refinement of LLRs at some intermediate nodes, resulting in failure of the recovery of the local codewords, and thus the decoding failure.

[0333] FIG. 19 illustrates a structure of a user equipment (UE) according to embodiments disclosed herein.

[0334] As shown in FIG. 19, the UE according to an embodiment may include a transceiver 1910, a memory 1920, and a processor 1930. The transceiver 1910, the memory 1920, and the processor 1930 of the UE may operate according to a communication method of the UE described above. However, the components of the UE are not limited thereto. For example, the UE may include more or fewer components than those described above. In addition, the processor 1930, the transceiver 1910, and the memory 1920 may be implemented as a single chip. Also, the processor 1930 may include at least one processor. Furthermore, the UE of FIG. 19 corresponds to a UE according to embodiments of the disclosure.

[0335] The transceiver 1910 collectively refers to a UE receiver and a UE transmitter, and may transmit / receive a signal to / from a base station or a network entity. The signal transmitted or received to or from the base station or a network entity may include control information and data. The transceiver 1910 may include a RF transmitter for up-converting and amplifying a frequency of a transmitted signal, and a RF receiver for amplifying low-noise and down-converting a frequency of a received signal. However, this is only an example of the transceiver 1910 and components of the transceiver 1910 are not limited to the RF transmitter and the RF receiver.

[0336] Also, the transceiver 1910 may receive and output, to the processor 1930, a signal through a wireless channel, and transmit a signal output from the processor 1930 through the wireless channel.

[0337] The memory 1920 may store a program and data required for operations of the UE. Also, the memory 1920 may store control information or data included in a signal obtained by the UE. The memory 1920 may be a storage medium, such as read-only memory (ROM), random access memory (RAM), a hard disk, a CD-ROM, and a DVD, or a combination of storage media.

[0338] The processor 1930 may control a series of processes such that the UE operates as described above. For example, the transceiver 1910 may receive a data signal including a control signal transmitted by the base station or the network entity, and the processor 1930 may determine a result of receiving the control signal and the data signal transmitted by the base station or the network entity.

[0339] FIG. 20 illustrates a structure of a base station (BS) according to embodiments disclosed herein.

[0340] As shown in FIG. 20, the base station according to an embodiment may include a transceiver 2010, a memory 2020, and a processor 2030. The transceiver 2010, the memory 2020, and the processor 2030 of the base station may operate according to a communication method of the base station described above. However, the components of the base station are not limited thereto. For example, the base station may include more or fewer components than those described above. In addition, the processor 2030, the transceiver 2010, and the memory 2020 may be implemented as a single chip. Also, the processor 2030 may include at least one processor. Furthermore, the base station of FIG. 20 corresponds to a base station according to embodiments of the disclosure.

[0341] The transceiver 2010 collectively refers to a base station receiver and a base station transmitter, and may transmit / receive a signal to / from a terminal (UE) or a network entity. The signal transmitted or received to or from the terminal or a network entity may include control information and data. The transceiver 2010 may include a RF transmitter for up-converting and amplifying a frequency of a transmitted signal, and a RF receiver for amplifying low-noise and down-converting a frequency of a received signal. However, this is only an example of the transceiver 2010 and components of the transceiver 2010 are not limited to the RF transmitter and the RF receiver.

[0342] Also, the transceiver 2010 may receive and output, to the processor 2030, a signal through a wireless channel, and transmit a signal output from the processor 2030 through the wireless channel.

[0343] The memory 2020 may store a program and data required for operations of the base station. Also, the memory 2020 may store control information or data included in a signal obtained by the base station. The memory 2020 may be a storage medium, such as read-only memory (ROM), random access memory (RAM), a hard disk, a CD-ROM, and a DVD, or a combination of storage media.

[0344] The processor 2030 may control a series of processes such that the base station operates as described above. For example, the transceiver 2010 may receive a data signal including a control signal transmitted by the terminal, and the processor 2030 may determine a result of receiving the control signal and the data signal transmitted by the terminal.

[0345] The embodiments disclosed herein can be implemented through at least one software program running on at least one hardware device and performing network management functions to control the network elements. The elements include blocks which can be at least one of a hardware device, or a combination of hardware device and software module.

[0346] The embodiments disclosed herein describe method and systems for reducing number of decoder cores for SCL decoder. Therefore, it is understood that the scope of the protection is extended to such a program and in addition to a computer readable means having a message therein, such computer readable storage means contain program code means for implementation of one or more steps of the method, when the program runs on a server or mobile device or any suitable programmable device. The method is implemented in at least one embodiment through or together with a software program written in e.g., Very high speed integrated circuit Hardware Description Language (VHDL) another programming language, or implemented by one or more VHDL or several software modules being executed on at least one hardware device. The hardware device can be any kind of portable device that can be programmed. The device may also include means which could be e.g., hardware means like e.g., an ASIC, or a combination of hardware and software means, e.g., an ASIC and an FPGA, or at least one microprocessor and at least one memory with software modules located therein. The method embodiments described herein could be implemented partly in hardware and partly in software. Alternatively, the invention may be implemented on different hardware devices, e.g., using a plurality of CPUs.

[0347] The foregoing description of the specific embodiments will so fully reveal the general nature of the embodiments herein that others can, by applying current knowledge, readily modify and / or adapt for various applications such specific embodiments without departing from the generic concept, and, therefore, such adaptations and modifications should and are intended to be comprehended within the meaning and range of equivalents of the disclosed embodiments. It is to be understood that the phraseology or terminology employed herein is for the purpose of description and not of limitation. Therefore, while the embodiments herein have been described in terms of embodiments and examples, those skilled in the art will recognize that the embodiments and examples disclosed herein can be practised with modification within the scope of the embodiments as described herein.

Claims

1.A method performed by a receiver (404), the method comprises:receiving a plurality of channel-inputs of a fading channel, wherein the plurality of channel-inputs comprises at least one of: a code rate or modulation order or modulation and coding scheme index (MCS), LLRs, and a plurality of Signal to noise ratios (SNRs);determining a plurality of a first type link-abstraction metrics based on the plurality of channel-inputs;comparing the plurality of determined first type link-abstraction metrics with a plurality of pre-defined first type link-abstraction metrics; andidentifying the optimal set of decoding variables before the decoding procedure starts from a plurality of pre-defined discrete decoding variables, based on the comparison, wherein the identified optimal set of decoding variable has one determined first type link-abstraction metric closest to one pre-defined first type link-abstraction metric.2.The method of claim 1, wherein the method comprises:generating an information noise model with a first look up table, wherein the first look up table includes, correlation among a plurality of a second type target link-abstraction metrics, the plurality of SNRs and the plurality of pre-defined discrete decoding variables, corresponding to the fading channel;determining the plurality of the pre-defined first type link-abstraction metrics from the information noise model; andgenerating a second look up table (LUT) from the first look up table (LUT), wherein the second look up table comprises correlation between the plurality of the pre-defined first type link-abstraction metrics and the plurality of SNRs,wherein the plurality of second type target link-abstraction metrics includes a plurality of target block error rates (BLERs) of the information noise model.3.The method of claim 1, wherein identifying, the optimal set of decoding variables, comprises:identifying the plurality of SNRs corresponding to the plurality of second type target link-abstraction metrics, from the first LUT; andmapping a single SNR of the identified plurality of SNRs to a corresponding pre-defined first type link-abstraction metric of the second LUT, wherein the single SNR is relative to the first type link-abstraction metric closest to the pre-defined first type link-abstraction metric.4.The method of claims 1, wherein the plurality of the first type link-abstraction metrics at least one of: a plurality of Received bit information rate (RBIR) for the fading channel, a plurality of exponential effective SNR (EESM) for the fading channel, or a plurality of mean mutual information per bits (MMIB) for the fading channel,wherein the plurality of the first type pre-defined link-abstraction metrics include at least one of: a plurality of pre-defined Received bit information rate (RBIR) for the fading channel, a plurality of pre-defined exponential effective SNR (EESM) for the fading channel, or a plurality of pre-defined mean mutual information per bits (MMIB) for the fading channel.5.The method of claim 1, wherein the optimal set of decoding variables is at least one of: an optimal set of list size of a plurality of decoder cores in a Successive cancellation list (SCL) based decoding, an optimal set of list size of a plurality of decoder cores in a list-based decoding, an optimal set of an optimal depth level in a successive cancellation and successive-cancellation list based decoding, or an optimal set of a plurality of optimal iteration numbers in an iterative decoding,wherein the optimal set of list size is used to determine number of decoding paths pursued in the list-based decoding, the set of an optimal depth level is used to determine depth at which instantaneous decoding is performed in a binary tree search based list-decoding, and the plurality of iteration numbers is used to determine number of iterations used in a decoding procedure,wherein, the set of optimal list size of list-based decoding, the set of the optimal depth level for the binary tree search based list-decoding decoding, and the optimal set of iteration numbers for iterative decoding are applicable to be used in at least one of: logic based decoder implementation and a hardware based decoder implementation, andwherein, the set of optimal list size of list-based decoding, the set of the optimal depth level for the binary tree search based list-decoding decoding, and the optimal set of iteration numbers for iterative decoding are applicable to be used in at least one of: logic based decoder implementation and a hardware based decoder implementation.6.The method of claim 1, wherein a plurality of signal-inputs comprises at least one of: a plurality of channel Log Likelihood ratios (LLRs) corresponding to the code rate, a plurality of intermediate LLRs corresponding to the code rate, a plurality of effective SNRs, and a plurality of Signal to interference and noise ratios (SINRs).7.The method of claim 1, wherein the method comprises:determining the set of optimal decoding variables opportunistically, from the plurality of pre-defined discrete decoding parameters for decoding at least one of: a polar code, a polar variant code, a turbo code, a Low density parity check code (LDPC) code, a concatenated polar code, a code with list-based decoding technique, and a code for iterative decoding technique, wherein the set of optimal decoding variables are used to identify, a plurality of optimal decoding paths for decoding the error correcting code.8.The method of claim 1, wherein the method comprises feeding by a decoding variable identifier engine (436) of the receiver (404), the optimal set of decoding variables, identified from the plurality of pre-defined discrete decoding variables, to a decoder of the receiver (404) for performing a decoding mechanism with the optimal set of decoding variables.9.The method of claim 1, wherein decoding of the Error Correcting Code in digital communication comprises:identifying an optimal set of decoding variables from the plurality of pre-defined discrete decoding variables, for performing the decoding;identifying a successive unused decoding variables from the plurality of pre-defined discrete decoder variables, based on the optimal set of the decoding variables;turning off a successive number of operations corresponding to the identified successive unused decoding variables, based on the optimal set of the decoding variables; anddecoding at least, the Error Correcting Code with Log2Xmaxinformation bits for the optimal set of decoding variables.10.The method of claim 1, wherein the method comprises configuring by the receiver (404) a plurality of adjusting factors for determining the plurality of first type link-abstraction metrics, wherein the plurality of adjusting factors minimizes error between an observed link-abstraction metric and the determined plurality of first type link-abstraction metrics.11.The method of claim 1, wherein the method comprises at least one of:identifying a decodability status of the optimal set of decoding variables based on value of a first type determined link-abstraction metric corresponding to the optimal set of decoding variable that is close to the first type pre-defined link-abstraction metric, wherein the decidability status is "decodable"; andidentifying a decodability status of the optimal set of decoding variables based on value of the first type determined link-abstraction metric corresponding to the optimal set of decoding variables is far away from the first type pre-defined link-abstraction metrics, wherein the decodability status of the decoding core is "not decodable".12.The method of claim 1, wherein the method comprises:sending by the decoding variable identifier unit or a radio unit of the receiver (404), the optimal set of the decoding variables to at least a decoder unit (DU) of the receiver via front haul, for enabling decoding operation using Log2XMaxbits, wherein XMaxindicating maximum value of the optimal set of decoding variables; andreceiving by the decoder unit (DU) of the receiver, the optimal set of the decoding variables along with a plurality of channel LLRs, wherein the DU is at least, a successive cancellation list decoder, a list decoder with list-based decoding technique, and an iterative decoder.13.A method performed by a receiver, the method comprising:receiving a channel-input with at least one code rate, corresponding to a plurality of reference signals, from a fading channel;determining a received bit information rate (RBIR), from the plurality of reference signals;mapping the determined RBIR to an information noise model comprising information on a plurality of RBIRs of the fading channel and a plurality of Signal to noise ratios (SNRs) corresponding to the RBIRs, to obtain an effective SNR from the information noise model, wherein the effective SNR corresponds to an RBIR of the noise model which is close to the determined RBIR; andmapping the effective SNR with a target BLER of the information noise model, to select the optimal set of decoding variables corresponding to the effective SNR, for decoding at least an Error Correcting Code in digital communication,wherein the fading channel is at least, at least one of a Physical downlink shared Channel (PDSCH), a Physical uplink shared Channel (PUSCH), a Physical downlink control channel (PDCCH), a Physical uplink control channel (PUCCH); andthe at least one RBIR of the fading channel is determined by using at least, a plurality of demodulation reference signals (DMRSs) in a frequency grid, mutual of information of each DMRS in the frequency grid, an adjusting factor for minimizing error between an observed RBIR and the determined RBIR.14.A receiver (404) in a wireless communication system, comprising:a decoding variable identifier engine (436);a decoder engine (438),a processor (440); anda memory (442);wherein the decoding variable identifier unit (436) is, coupled with the decoder engine (438), the processor (440), and the memory (442), configured to:receive, a plurality of channel-inputs comprising at least a code rate, MCS or modulation order, channel LLRs and a plurality of Signal to noise ratios (SNRs);determine, a plurality of a first type link-abstraction metrics based on the plurality of channel-inputs;compare, the plurality of the determined first type link-abstraction metrics with a plurality of pre-defined first type link-abstraction metrics; andidentify, an optimal set of decoding variables from a plurality of pre-defined discrete decoding variables based on the comparison for decoding at least a correcting code in digital communication, wherein the identified optimal set of decoding variables having one determined first type link-abstraction metric, closest to one first type pre-defined link-abstraction metric.15.A receiver (404) in a wireless communication system, comprising:a decoding variable identifier engine (436);a decoder engine (438),a processor (440); anda memory (442);wherein the decoding variable identifier unit (436) is, coupled with the decoder engine (438), the processor (440), and the memory (442), configured to:receive a channel-input with at least one code rate, corresponding to a plurality of reference signals, from a fading channel;determine a received bit information rate (RBIR), from the plurality of reference signals;map the determined RBIR to an information noise model comprising information on a plurality of RBIRs of the fading channel and a plurality of Signal to noise ratios (SNRs) corresponding to the RBIRs, to obtain an effective SNR from the information noise model, wherein the effective SNR corresponds to an RBIR of the noise model which is close to the determined RBIR; andmap the effective SNR with a target BLER of the information noise model, to select the optimal set of decoding variables corresponding to the effective SNR, for decoding at least an Error Correcting Code in digital communication,wherein the fading channel is at least, at least one of a Physical downlink shared Channel (PDSCH), a Physical uplink shared Channel (PUSCH), a Physical downlink control channel (PDCCH), a Physical uplink control channel (PUCCH); andthe at least one RBIR of the fading channel is determined by using at least, a plurality of demodulation reference signals (DMRSs) in a frequency grid, mutual of information of each DMRS in the frequency grid, an adjusting factor for minimizing error between an observed RBIR and the determined RBIR.

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