Data transmission device

Abstract

A data transmission device according to one embodiment of the present invention, comprises: a plurality of data driving devices; and a host having an input / output port electrically connected to the plurality of data driving devices through a first lane and a second lane, and a main controller using the first lane and the second lane so as to control that a data packet is transmitted to the plurality of data driving devices, wherein the main controller divides, into a first data packet and a second data packet, the data packet transmitted to the first through nth data driving devices, and uses the first lane and the second lane so as to simultaneously transmit each of the divided first data packet and second data packet to the first data driving device.

Description

data transmission device

[0001] The present invention relates to a data transmission device.

[0002] Signage is a display system installed on the exterior of a building or location to deliver advertisements or information. Signage is used to deliver a variety of information and advertisements through large screens, billboards, LED displays, and other means.

[0003] For example, signage can include digital signage, interactive displays, projection mapping, menu boards, wayfinding signage, electronic billboards, video walls, open-frame displays, human care signage, transparent displays, etc.

[0004] Users increasingly demand content like high-definition video and large data volumes. Conventional signage, with a frame data transmission speed of 40 Mbps, cannot support GS data resolutions of up to 16 bits and frame rates of 120 Hz or higher, posing numerous challenges when displaying high-definition video or transmitting large amounts of data.

[0005] To solve this problem, conventional signage is being replaced with differential communication, but this has the problem that not only does the logic size of the circuit increase by more than 10 times, but the current consumption also increases.

[0006] The purpose of the present invention is to provide a data transmission device having a daisy chained SPI structure composed of a double rate SPI with the same number of SPI terminals.

[0007] In addition, the present invention aims to provide a data transmission device in which a Master of a Daisy Chain communicates with a Host using mini-LVDS and a lower daisy chain can use a structure of Double rate SPI.

[0008] According to one embodiment of the present invention, a data transmission device includes a data processing device having a plurality of data driving devices; an input / output port electrically connected to the plurality of data driving devices through a first lane and a second lane; and a main controller controlling the transmission of the data packet to the plurality of data driving devices using the first lane and the second lane; wherein the main controller divides the data packet transmitted to the first to n-th data driving devices into a first data packet and a second data packet, and simultaneously transmits the divided first data packet and the second data packet to the first data driving device using the first lane and the second lane, respectively.

[0009] In addition, the main controller may determine whether the data packet is divided based on a Write Command / Read Command recognized in the data packet, and may transmit the data packet to the first data driving device through at least one of the first lane and the second lane based on the determined result, or transmit the first data packet or the second data packet to the first data driving device.

[0010] In addition, the main controller may include, when the write command is recognized in the data packet, dividing the data packet into the first data packet and the second data packet, transmitting the first data packet to the first data driving device using the first lane, and simultaneously transmitting the second data packet to the first data driving device using the second lane.

[0011] In addition, the main controller may include, when the read command is recognized in the data packet, transmitting the data packet to the first data driving device using the first lane without splitting the data packet, and transmitting a “0” bit to the first data driving device using the second lane.

[0012] Additionally, the main controller may include, when dividing the data packet into at least one or more, dividing the data packet into the number of lanes connected to the input / output ports of the data processing device.

[0013] In addition, the first data driving device may include a first input unit electrically connected to the first lane and the second lane to receive a clock signal, a data packet, a first data packet, and a second data packet; a first register to store the clock signal, the data packet, the first data packet, and the second data packet input through the first input unit, and to shift and transmit the clock signal, the data packet, the first data packet, and the second data packet by a predetermined bit; a first controller to analyze the clock signal, the data packet, the first data packet, and the second data packet input through the first input unit, and to obtain information or data of an identifier for the data packet, the first data packet, and the second data packet based on the analyzed result; and a first output unit to output the clock signal, the data packet, the first data packet, and the second data packet received from the first register.

[0014] In addition, the first controller may analyze the data packet, the first data packet, and the second data packet to determine an ID among the header parts thereof, and if the ID is determined to be its own ID, may include receiving data related to its own ID.

[0015] In addition, the first controller may analyze the data packet, the first data packet, and the second data packet to determine an ID among the header parts thereof, and if the ID is determined to be an ID other than the own ID, bypass data related to the other ID.

[0016] In addition, the first judgment unit may include receiving the data packet, the first data packet and the second data packet, input through the first input unit, analyzing the header part and the data part of each of them, and checking whether there is an error based on the analyzed result, and if it is determined as a result of the analysis that there is an error, generating a specific signal and transmitting the specific signal to the first output unit.

[0017] The first judgment unit may include checking the first start bit of the first data packet provided through the first lane and the first start bit of the second data packet provided through the second lane, and if the first start bit of the first data packet is “1” and the first start bit of the second data packet is “0”, determining that it is the read command, and transmitting the data packet using the first lane based on the judgment result.

[0018] In addition, according to another embodiment of the present invention, a data transmission device includes a first data driving device to an n-th data driving device; and a data processing device electrically connected to the first data driving device to the n-th data driving device through at least one lane; wherein the data processing device is connected to the first data driving device in a low-voltage differential signal transmission method, that is, M-LVDS (Mini Low-Voltage Differential Signaling), to transmit a differential data signal, and the first data driving device is connected to the second data driving device to the n-th data driving device in a daisy chain type SPI (Serial Peripheral Interface) structure to transmit a data packet.

[0019] In addition, the first data driving device may be connected to the host with a single lane, which is one lane, and may be connected to the second data driving device to the n-th data driving device with two lanes, which is a double lane.

[0020] In addition, the first data driving device includes an RX unit that receives a differential data signal and a differential clock signal from the host and transmits the differential data signal as digital serial data; a conversion unit that receives the digital serial data from the RX unit one bit at a time based on the differential clock signal and converts the digital serial data into a digital parallel data packet in a parallel format and transmits the converted digital serial data; and a controller that receives the digital parallel data packet from the conversion unit and divides it into at least one.

[0021] In addition, the controller may include a division unit that receives the digital parallel data packet from the conversion unit, divides the digital parallel data packet into a first data packet and a second data packet based on a preset criterion, transmits the divided first data packet using a first lane, and transmits the divided second data packet using a second lane; and a selection unit that selects a first path or a second path according to a VD signal provided from the data processing device, and transmits the first data packet and the second data packet to the first path or the second path based on a selection result.

[0022] Additionally, the controller may include selecting the first path when the logic value of the VD signal provided from the data processing device is “0”, and selecting the second path when the logic value of the VD signal is “1”.

[0023] A data transmission device according to an embodiment of the present invention has a daisy chained SPI structure composed of double rate SPIs with the same number of SPI terminals, thereby increasing the SPI frame data rate without additional cost.

[0024] In addition, the data transmission device according to an embodiment of the present invention can perform high-speed communication without additional cost by having the master of the daisy chain communicate with the host using mini-LVDS and the lower daisy chain using a double rate SPI structure.

[0025] In addition, a data transmission device according to an embodiment of the present invention can reduce the complexity of the communication circuit and current consumption issues by using a structure in which a master of a daisy chain communicates with a host using mini-LVDS, and a lower daisy chain uses a double rate SPI, but only uses the RX of the mini-LVDS and eliminates the TX of the mini-LVDS.

[0026] FIG. 1 is a block diagram showing a data transmission device according to one embodiment of the present invention.

[0027] FIG. 2 is a block diagram showing a data processing device and a data driving device according to one embodiment of the present invention.

[0028] FIG. 3 is a diagram illustrating a first controller according to an embodiment of the present invention.

[0029] FIG. 4 is a diagram for explaining a light command and a read command according to an embodiment of the present invention.

[0030] FIG. 5 is a diagram for explaining a stream of data packets in a daisy chain type SPI (Serial Peripheral Interface) structure according to an embodiment of the present invention and data being transmitted to pixels during one frame based on the stream.

[0031] FIG. 6 and FIG. 7 are diagrams for explaining data transmission using the first lane in the case of a lead according to an embodiment of the present invention.

[0032] FIGS. 8 and 9 are diagrams for explaining idea assignment according to an embodiment of the present invention.

[0033] FIG. 10 is a diagram showing a data transmission device according to another embodiment of the present invention.

[0034] Figures 11 and 12 are diagrams showing a data processing device and a data driving device according to one embodiment of the present invention.

[0035] FIGS. 13 to 17 are diagrams for explaining the transmission of data provided to a conversion unit to a controller according to another embodiment of the present invention.

[0036] The advantages and features of the present invention, and the methods for achieving them, will become clearer with reference to the embodiments described in detail below together with the accompanying drawings. The present invention is not limited to the embodiments disclosed below, but may be implemented in various different forms. The embodiments are provided solely to ensure that the disclosure of the present invention is complete and to fully inform those skilled in the art of the scope of the invention, and the present invention is defined solely by the scope of the claims.

[0037] The shapes, sizes, ratios, angles, numbers, etc. disclosed in the drawings for explaining embodiments of the present invention are illustrative, and the present invention is not limited to the details depicted in the drawings. Throughout the specification, the same reference numerals designate substantially the same components. Furthermore, in describing the present invention, detailed descriptions of related known technologies will be omitted if they are deemed to unnecessarily obscure the gist of the present invention.

[0038] In the specification, when “comprises,” “includes,” “has,” and “consists of,” other parts may be added unless “only” is used. When a component is expressed in the singular, it may be interpreted as plural unless otherwise explicitly stated.

[0039] When interpreting a component, it is interpreted as including the error range even if there is no separate explicit description.

[0040] When the positional relationship and interconnectedness between two components are described as ‘on’, ‘above’, ‘below’, ‘next to’, ‘connect, couple’, crossing, intersecting, etc., one or more other components may be interposed between the components unless there is a mention of ‘directly’ or ‘directly’.

[0041] When the temporal relationship is explained with phrases such as ‘after’, ‘following’, ‘next to’, or ‘before’, it may not be continuous on the time axis unless ‘right away’ or ‘directly’ is used.

[0042] Although first, second, etc. may be used to distinguish components, the function or structure of these components is not limited by the ordinal number or component name attached to the front of the component.

[0043] The following embodiments may be partially or fully combined or combined with one another, enabling various technically feasible interconnections and operations. Each embodiment may be implemented independently of the other, or may be implemented together in a related manner.

[0044] Hereinafter, various embodiments of the present invention will be described in detail with reference to the attached drawings.

[0045] FIG. 1 is a block diagram showing a data transmission device according to an embodiment of the present invention, and FIG. 2 is a block diagram showing a data processing device (100) and a data driving device according to an embodiment of the present invention.

[0046] Referring to FIGS. 1 and 2, a data transmission device according to an embodiment of the present invention may include a data processing device (100) and a plurality of data driving devices. The data processing device may be referred to as a host, a field-programmable gate array (FPGA), or a display controller. The data driving devices may be referred to as driver integrated circuits. Here, the plurality of data driving devices (200) may include a first data driving device (210a1) to an n-th data driving device (210an). The first data driving device (210a1) to the n-th data driving device (210an) may be sequentially connected. Here, SCLK represents a clock signal. SDI1 represents the first serial input data (Seral Data Input 1), SDI2 represents the second serial input data (Seral Data Input 2), SDO1 represents the first serial output data (Serial Data Output), and SDO2 represents the second serial output data (Serial Data Output2). The data processing device (100) and each of the plurality of data driving devices (200) may be connected in a daisy chain manner. For example, the data processing device (100) may be connected to the first data driving device (210a1) in a daisy chain manner, the first data driving device (210a1) may be connected to the second data driving device (210a2) in a daisy chain manner, ..., the n-1th data driving device (210an-1) may be connected to the nth data driving device (210an) in a daisy chain manner.

[0047] As described above, each of the data processing device (100) and the plurality of data driving devices (200) may have a daisy chain type SPI (Serial Peripheral Interface) structure.

[0048] Each of the data processing device (100) and the plurality of data driving devices (200) may be a semiconductor integrated circuit or a package packaging a semiconductor integrated circuit, but is not limited thereto.

[0049] A data processing device (100) may include a main controller (10) capable of generating a data packet or clock signal, a clock port (11) for outputting a clock signal, and an input / output port (12) capable of inputting and outputting data packets. Here, the clock port (11) may be referred to as a clock pin, and the input / output port (12) may be referred to as an input / output pin.

[0050] The clock port (11) is electrically connected to a clock line and can transmit a clock signal to the first data driving device (210a1) using the clock line.

[0051] The input / output port (12) is electrically connected to the first lane and the second lane, and can transmit a data packet to the first data driving device (210a1) to the nth data driving device (210an) using at least one of the first lane and the second lane. Here, the data packet can include a header part and a data part.

[0052] The main controller (10) can transmit a write command / read command to the first data driving device (210a1) using the header part. For example, the write command can be defined as Write=0xF0, and the read command can be defined as Read=0xAF.

[0053] The main controller (10) can determine whether to split a data packet based on a write command / read command, and can transmit the data packet or the split data packet to the first data drive device (210a1) using at least one of the first lane and the second lane based on the determined result.

[0054] For example, when a write command is recognized, the main controller (10) may divide a data packet into at least one, and transmit each of the divided data packets to the first data driving device (210a1) through the first lane and the second lane. The main controller (10) may divide one data packet into a first data packet and a second data packet based on a preset reference range to reduce the size of the data. Each of the first data packet and the second data packet may have substantially the same data size. The first data packet may be referred to as first serial input data (Seral Data Input 1) and may be expressed as SDI1. The second data packet may be referred to as second serial input data (Seral Data Input 2) and may be expressed as SDI2.

[0055] When a write command is recognized, the main controller (10) can synchronize a first data packet to a clock signal and transmit it to the first data driving device (210a1) using the first lane, and synchronize a second data packet to a clock signal and transmit it to the first data driving device (210a1) using the second lane. It is not limited thereto, and the first data packet can be transmitted to the first data driving device (210a1) via the second lane, or the second data packet can be transmitted to the first data driving device (210a1) via the first lane.

[0056] As described above, when a write command is recognized, the data processing device (100) simultaneously transmits the first data packet and the second data packet, which are divided, to the first data driving device (210a1) using the first lane and the second lane for a preset time of one frame, thereby increasing the transmission speed by approximately two times and enabling faster transmission of large amounts of data.

[0057] In FIG. 1 and FIG. 2, the division of a data packet into a first data packet and a second data packet is described, but is not limited thereto.

[0058] When the main controller (10) divides a data packet into at least one or more, it can divide it based on the number of lanes connected to the input / output port (12) of the host (100). That is, if the number of lanes connected to the input / output port (12) is n, the main controller (10) can divide the data packet into n based on this. For example, if the number of lanes connected to the input / output port (12) is 4, the data processing device (100) can divide the data packet into the first data packet to the fourth data packet based on this.

[0059] Accordingly, when a write command is recognized, the data processing device (100) simultaneously transmits the divided first data packet to the fourth data packet to the first data driving device (210a1) using the first to fourth lanes connected to each of the four input / output ports (12), thereby increasing the transmission speed by approximately four times and enabling faster transmission of large amounts of data.

[0060] In contrast, when a read command is recognized, the main controller (10) can transmit the data packet to the first data driving device (210a1) using the first lane without splitting the data packet. When a read command is recognized, the main controller (10) can fix the “0” bit to the second lane and transmit it to the first data driving device (210a1).

[0061] Each of the plurality of data driving devices may include an input unit, an output unit, a register, and a controller. For example, the first data driving device (210a1) includes a first input unit (21a), a first output unit (21c), a first register (21b), and a first controller (21), the second data driving device (210a2) includes a second input unit, a second output unit, a second register, and a second controller, ..., the n-1th data driving device includes an n-1th input unit, an n-1th output unit, an n-1th register, and an n-1th controller, and the nth data driving device (210an) includes an nth input unit, an nth output unit, an nth register, and an nth controller. Hereinafter, the operations of the input unit, the output unit, the register, and the controller configured in each of the plurality of data driving devices are substantially the same. Hereinafter, for convenience of explanation, the first data driving device (210a1) will be described as the basis.

[0062] The first input unit (21a) is electrically connected to the clock line, the first lane, and the second lane, and can be electrically connected to the clock port (11) of the data processing device (100) and the input / output port (12) of the data processing device (100) through these.

[0063] The first input unit (21a) can receive a clock signal, a data packet, and a first data packet and a second data packet, which are divided data packets, from the data processing device (100) under the control of the first controller (21).

[0064] For example, the first input unit (21a) can receive a clock signal through a clock line under the control of the first controller (21), and input a data packet using the first lane and the second lane, or can input the first data packet and the second data packet simultaneously.

[0065] The first input unit (21a) can provide the received clock signal, data packet, first data packet and second data packet to the first register (21b) or the first controller (21) under the control of the first controller (21).

[0066] The first register (21b) stores, under the control of the first controller (21), a clock signal, a data packet, a first data packet, and a second data packet input through the first input unit (21a), and can simultaneously shift the data by a predetermined number of bits and transmit it to the first output unit (21c).

[0067] The first controller (21) can process a clock signal, data packet, first data packet, and second data packet received through the first input unit (21a).

[0068] The first controller (21) can analyze the input data packet or the input first data packet and second data packet, and obtain information or data of an identifier for the data packet, the first data packet, and the second data packet based on the analyzed result.

[0069] The first controller (21) can analyze information about an identifier from a data packet input through the first input unit (21a) or from the first and second data packets input, and obtain information about an identifier for the first data driving device (210a1) based on the data packet. The first controller (21) can analyze data from a data packet input through the first input unit (21a) or from the first and second data packets input, and obtain data included in the data packet input or data included in the first and second data packets based on the data packet.

[0070]

[0071] The second data driving device (210a2) to the nth data driving device (210an) may have substantially the same operation and function as the first data driving device (210a1) described above, so a detailed description thereof will be omitted.

[0072] FIG. 3 is a diagram illustrating a first controller according to an embodiment of the present invention. FIG. 4 is a diagram illustrating a light command and a read command according to an embodiment of the present invention.

[0073] Referring to FIG. 3, the first controller (21) may include a first judgment unit (21-1), a first coupling unit (21-2), and a first setting unit (21-3).

[0074] The first judgment unit (21-1) can receive data packets input through the first input unit (21a), the first data packet and the second data packet, analyze the header part and the data part of each of them, and check for errors based on the analyzed results. For example, if the first judgment unit (21-1) determines that there is an error as a result of analyzing the data packets, the header part and the data part of each of the first data packet and the second data packet, it can generate a specific signal. Here, the specific signal can be a high fix.

[0075] When a specific signal is generated, the first judgment unit (21-1) can output the generated specific signal through the first output unit (21c). When the specific signal is output through the first output unit (21c), the second data driving unit (210a2) to the n-th data driving unit (210an) sequentially connected to the first data driving unit (210a1) can sequentially bypass the specific signal. Accordingly, the specific signal can be input to the data processing unit (100) after sequentially bypassing the second data driving unit (210a2) to the n-th data driving unit (210an).

[0076] The first judgment unit (21-1) may not provide the data packet in which an error occurred, the first data packet in which an error occurred, or the second data packet in which an error occurred to the first register (21b).

[0077] In contrast, if the first judgment unit (21-1) determines that there is no error as a result of analyzing the header part and data part of each of the data packet, the first data packet and the second data packet, the first judgment unit (21-1) can transmit the checked data packet, the checked first data packet and the checked second data packet to at least one of the first register (21b) and the first combination unit (21-2).

[0078] In addition, the first judgment unit (21-1) can receive a data packet or a first data packet and a second data packet input through the first input unit (21a), analyze the header part of each of them, and determine whether it is a write command or a read command based on the analyzed result.

[0079] As shown in (a) and (b) of FIG. 4, the first judgment unit (21-1) can analyze the start bit of the data packet provided through the first lane and the second lane.

[0080] For example, the first judgment unit (21-1) can determine that if the bit of the start (8 bits) is 1111000, it is a write command, and if the bit of the start (8 bits) is 10101111, it is a read command.

[0081] The first judgment unit (21-1) checks the first start bit of the first data packet provided through the first lane and the first start bit of the second data packet provided through the second lane, and if the first start bit of the first data packet is “1” and the first start bit of the second data packet is “1”, the SIF light operation can be performed in dual lanes (or double lanes).

[0082] In contrast, the first judgment unit (21-1) checks the first start bit of the first data packet provided through the first lane and the first start bit of the second data packet provided through the second lane, and if the first start bit of the first data packet is “1” and the first start bit of the second data packet is “0”, the SIF read operation can be performed in a single lane (or one lane).

[0083] The first judgment unit (21-1) analyzes the header part to determine whether it is a write command or a read command, and based on this, the lane for inputting and outputting data can be set to dual lane or single lane.

[0084] For example, if the first judgment unit (21-1) determines that the header part is a write command, it can utilize dual lanes to transmit or receive a large amount of data within a limited time. Here, dual lanes can be interpreted to mean that both the first lane and the second lane can be used. Dual lanes can be referred to as two lanes or double lanes. If the first judgment unit (21-1) determines that the header part is a write command, it can transmit or receive the first data packet and the second data packet through the dual lanes.

[0085] For example, if the first judgment unit (21-1) determines that the header part is a read command, it can utilize a single lane without transmission speed restrictions. Here, a single lane can be interpreted to mean that only one of the first lane and the second lane can be used. A single lane can be referred to as one lane. If the first judgment unit (21-1) determines that the header part is a read command, it can transmit or receive a data packet through a single lane. This is to compensate for restrictions on the number of data lanes, such as a connector, which is an input / output port (12) input to a data processing device (100).

[0086] For example, the data processing device (100) experiences many problems in transmitting the first data packet and the second data packet fed back from the first lane and the second lane of the plurality of data driving devices connected in a daisy chain through the limited port or connector of the host (100). Considering this, if the first judgment unit (21-1) determines that the command is a read command with relatively less time constraints, it can use a single lane rather than a dual lane.

[0087] In the case of a write command, the first combining unit (21-2) can receive the checked first data packet and the checked second data packet from the first judgment unit (21-1) and combine them into one data packet.

[0088] For example, the first combining unit (21-2) may synchronize each of the checked first data packet and the checked second data packet to the rising or falling of the clock signal, while shifting at least one clock signal for the checked second data packet and sequentially combining them to create one data packet. This is not limited thereto, and combinations may be performed in various ways.

[0089] Although the present invention describes checking for errors in the first data packet and the second data packet and then combining them, it is not limited thereto, and errors may be checked after first combining the first data packet and the second data packet.

[0090] When the first combining unit (21-2) combines into one data packet, it can provide it to the first acquiring unit (21-3).

[0091] The first acquisition unit (21-3) can analyze a data packet combined into one together with a clock signal and acquire information or data of an identifier for the data packet based on the analyzed result.

[0092] For example, the first acquisition unit (21-3) can analyze identifier information about an identifier from a data packet input through the first combination unit (21-2) and, based on this, acquire identifier information about the first data driving device (210a1).

[0093] For example, the first acquisition unit (21-3) can load data corresponding to its own ID based on the result of analyzing the data packet together with the clock signal.

[0094] FIG. 5 is a diagram for explaining a stream of data packets in a daisy chain type SPI (Serial Peripheral Interface) structure according to an embodiment of the present invention and data being transmitted to pixels during one frame based on the stream.

[0095] Referring to FIG. 5, a data packet may include a header part and a data part.

[0096] The header part can include a start (START), a command (CMD), and an address (ADDR). For example, the header part can be expressed as [START], [CMD=WRITE, READ], [ADDR=0x10].

[0097] Start consists of 8 bits and can signal the start of the SPI interface. For example, Start can be expressed as Start & Reset[7:0]. Here, the start of the first data packet, which is a data packet segment, can consist of 4 bits, and the start of the second data packet can consist of 4 bits.

[0098] A command (CMD) can consist of 4 bits. For example, a command (CMD) can be expressed as CMD[3:0]. A command (CMD) can indicate a control command, Config register write / read, GS data write, Trim Data Write, etc., but is not limited thereto.

[0099] The address (ADDR) consists of 8 bits and can represent an option or address of a command (CMD). For example, the address (ADDR) can be expressed as ADDR[7:0].

[0100] A Data Part may include an ID, DATA, and EOD or EOC. For example, a Data Part may be expressed as [ID=0x01], [DATA=0xABCD], [EOD], or [EOC].

[0101] The ID consists of 4 bits and can be a daisy-chained ID number. The ID can be expressed as ID [3:0]. A detailed explanation of ID assignment will be provided later.

[0102] Data can be composed of 16 / 48 bits, depending on the command (CMD). For example, data can be expressed as DATA[47:0].

[0103] The End of Data (EOD) consists of four bits and can signal the end of data. For example, EOD can be expressed as EOD [1:0].

[0104] The End of Command (EOC) consists of 4 bits and can signal the end of a command (CMD). For example, EOC can be expressed as EOC [1:0].

[0105] As illustrated in FIG. 5, the first data driving device (210a1), under the control of the first controller (21), if it is determined to be a read command, can provide a 0 bit to the second data packet using the second lane and transmit the start, command, address, ID, blank data, etc. to the first data packet transmitted to the first lane in synchronization with the clock signal.

[0106] Referring to FIG. 5, the data transmission device can transmit data packets serially from the host (100) to the first data driving device (210a1) or from the n-1th data driving device to the nth data driving device (210an) using lanes. For convenience of explanation, the first data driving device (210a1) to the third data driving device will be described here.

[0107] At least one lane can utilize a buffer or First-In-First-Out (FIFO) to ensure smooth transmission of data packets in a Serial Peripheral Interface (SPI) structure.

[0108] The data processing device (100) can transmit at least one data packet serially. For example, the data processing device (100) can sequentially transmit a header part and at least one data part serially.

[0109] By having the data processing device (100) transmit data packets serially to multiple data driving devices, each of the multiple data driving devices can analyze the header part and sequentially load its own ID and corresponding data.

[0110] When the first data packet and the second data packet are transmitted simultaneously through the first lane and the second lane, respectively, the first data driving device (210a1) can analyze the header part and the data part of each of the first data packet and the second data packet and load its own ID and related data until an EOD is detected.

[0111] When the first data packet and the second data packet are serially transmitted from the first data driver (210a1) through the first lane and the second lane, respectively, the second data driver (210a2) can analyze the header part and the data part of each of the updated first data packet and the second data packet and load its own ID and corresponding data until an EOD is detected.

[0112] The third data driving device, which is the last, can analyze the header part and the data part of each of the first data packet and the second data packet when the first data packet and the second data packet are serially transmitted from the second data driving device (210a2) through the first lane and the second lane, respectively, and load its own ID and corresponding data until the EOC is detected.

[0113] The data processing device (100) can, under the control of the main controller (10), continuously transmit data parts equal to the number of registered data driving devices when the IDs of the first data driving device (210a1) to the third data driving device are registered.

[0114] For example, as illustrated in FIG. 5, the data processing device (100) can transmit a GS data signal to the first data driving device (210a1) to the third data driving device (210a3) for one frame under the control of the main controller (10).

[0115] For example, the data processing device (100) stores identification information indicating that it will continuously transmit GS data signals (e.g., continuously transmit 48 bits, 16 bits each for RGB) in the header part under the control of the main controller (10), and can continuously transmit data parts to the first data driving device (210a1) to the third data driving device as many times as the number of registered data driving devices.

[0116] The data processing device (100) can continuously transmit data parts for one pixel to the first data driving device (210a1) to the third data driving device during one frame under the control of the main controller (10).

[0117] Here, in the data part, EOD can be included in the data part transmitted to the pixel preceding the last pixel. In the data part, EOC can be included in the data part transmitted to the last pixel.

[0118] For example, the host (100) may, under the control of the main controller (10), continuously transmit data parts for the first data driving device (210a1) to the third data driving device to pixel 1 during one frame, then continuously transmit data parts for the first data driving device (210a1) to the third data driving device to pixel 2, and then continuously transmit data parts for the first data driving device (210a1) to the third data driving device to pixel n. However, this is not limited thereto.

[0119] FIG. 6 and FIG. 7 are diagrams for explaining data transmission using the first lane in the case of a lead according to an embodiment of the present invention.

[0120] As shown in FIGS. 6 and 7, the data transmission device can transmit data using the first lane when it is a lead, and fix the second lane to low.

[0121] The data processing device (100) can transmit a header part of a data packet such as an 8-bit start [ex, 10101111], a 4-bit read command [ex, 1011], and an 8-bit address [7:0], and a data part such as a 4-bit first ID [ex, 0001], 48-bit (or 16-bit) data (D1), 4-bit EOD, 4-bit second ID [ex, 0010], 48-bit (or 16-bit) data (D2), 4-bit EOD, 4-bit third ID [ex, 0011], 48-bit (or 16-bit) data (D3), and 4-bit EOC.

[0122] If the first data drive device (210a1, D-IC#1) determines that its ID (ID=1) is the first ID [ex, 0001], it can receive 48-bit (or 16-bit) data (D1) related to it and bypass data related to other IDs.

[0123] If the second data drive (210a2, D-IC#2) determines that its own ID (ID=2) is the second ID [ex, 0010], it can receive 48-bit (or 16-bit) data (D2) related to it and bypass data related to other IDs.

[0124] If the third data drive (210a3, D-IC#3) determines that its own ID (ID=3) is the third ID [ex, 0011], it can receive 48-bit (or 16-bit) data (D3) related to it and bypass data related to other IDs.

[0125] FIGS. 8 and 9 are diagrams for explaining idea assignment according to an embodiment of the present invention.

[0126] Referring to FIGS. 8 and 9, the data processing device (100) can transmit IDs as many as the number of data driving devices (200) in the address transmission section under the control of the main controller (10). For example, if there are three data driving devices (200), the data processing device (100) can transmit start, command, address 1 (ID1=1), address 2 (ID1=2), address 3 (ID1=3)-ID_STOP (8'hFF).

[0127] Each of the plurality of data driving devices (200) can initiate ID Assign when an ID Assign command is transmitted in the command. For example, each of the plurality of data driving devices can initiate ID Assign when it receives “1101” in the ID Assign Command.

[0128] For example, if the address MSB[7] is 0, the first data driving device (210a1, D-IC#1) can register the address [3:0] as its ID, and check the MSB as 1 (MSB[7]=1) and transmit it to the second data driving device (210a2, D-IC#2). After the ID Assignment is completed, the first data driving device (210a1, D-IC#1) can pass the ID input thereafter.

[0129] The second data driver (210a2, D-IC#2) can pass if the input address MSB is 1 and wait for the next address MSB. The second data driver (210a2, D-IC#2) can wait until the address MSB is 0.

[0130] When the address MSB[7] is 0, the second data driving device (210a2, D-IC#2) can register the address [3:0] as its ID and check the MSB as 1 (MSB[7]=1) and transmit it to the third data driving device (210a3, D-IC#3). When the ID Assignment is completed, the second data driving device (210a2, D-IC#2) can pass the ID that is input thereafter.

[0131] The third data driver (210a3, D-IC#3) can pass if the input address MSB is 1 and wait for the next address MSB. The third data driver (210a3, D-IC#3) can wait until the address MSB is 0.

[0132] When the address MSB[7] is 0, the third data driving device (210a3, D-IC#3) can register the address [3:0] as its ID and check the MSB as 1 (MSB[7]=1) and pass it to the next data driving device. When the ID Assignment is completed, the third data driving device (210a3, D-IC#3) can pass the ID that is input thereafter.

[0133] The data processing device (100) or data driving device (210) can terminate ID Assign when an address of 8'FF is input.

[0134] FIG. 10 is a diagram showing a data transmission device according to another embodiment of the present invention, and FIGS. 11 and 12 are diagrams showing a data processing device and a data driving device according to one embodiment of the present invention.

[0135] Referring to FIGS. 10 to 12, a data transmission device according to an embodiment of the present invention may include a data processing device (300) and a plurality of data driving devices (400). Here, the plurality of data driving devices (400) may include a first data driving device (410a1) to an n-th data driving device (410an). The first data driving device (410a1) to the n-th data driving device (410an) may be sequentially connected.

[0136] Here, SCLK represents a clock signal. SDI1 represents the first serial input data (Seral Data Input 1), SDI2 represents the second serial input data (Seral Data Input 2), SDO1 represents the first serial output data (Serial Data Output), and SDO2 represents the second serial output data (Serial Data Output2). CLKP represents a positive (+) clock signal (Clock Positive), CLKM represents a negative (-) clock signal (Clock Negative), DATP represents a positive (+) data signal (Data Positive), DATM represents a negative (-) data signal (Data Negative), and LD represents a load signal.

[0137] Each of the data processing device (300) and the plurality of data driving devices (400) may be connected in a daisy chain manner. For example, the data processing device (300) may be connected to the first data driving device (410a1) in a daisy chain manner, the first data driving device (410a1) may be connected to the second data driving device (410a2) in a daisy chain manner, …, the n-1th data driving device may be connected to the nth data driving device (410an) in a daisy chain manner.

[0138] The first data drive unit (410a1) may be connected to the data processing unit (300) using a low-voltage differential signal transmission method called M-LVDS (Mini Low-Voltage Differential Signaling). The first data drive unit (410a1, D-IC#1) may be referred to as a master data drive unit. The first data drive unit (410a1, D-IC#1) may be connected to the data processing unit (300) in a single lane.

[0139] And the first data driving device (410a1, D-IC#1) may have a daisy chain type SPI (Serial Peripheral Interface) structure with multiple data driving devices.

[0140] Each of the host (300) and the plurality of data driving devices (400) may be a semiconductor integrated circuit or a package packaging a semiconductor integrated circuit, but is not limited thereto.

[0141] The data processing device (300) may include a main controller (41) capable of generating a differential data signal or a differential clock signal, and a mini differential port capable of inputting and outputting a differential clock signal and a differential data signal. Here, the mini differential port may be referred to as a mini differential pin or a mini LVDS port.

[0142] The mini differential port is electrically connected to a single lane, and can transmit a differential clock signal and a differential data signal to the first data driver (410a1) using the single lane. The differential clock signal may include a positive (+) clock signal and a negative (-) clock signal. A positive (+) clock signal (Clock Positive) indicates a state higher than a reference voltage when transmitting a clock signal, and a negative (-) clock signal (Clock Negative) indicates a state lower than the reference voltage when transmitting a clock signal. The differential data signal may include a positive (+) data signal and a negative (-) data signal. A positive (+) data signal (Data Positive) transmits a data bit value and indicates a state higher than a reference voltage, and a negative (-) data signal (Data Negative) transmits a data bit value and indicates a state lower than the reference voltage. The differential data signal may include a header part and a data part.

[0143] The first data drive device (410a1) may include an RX unit (42), a conversion unit (43), and a controller (41).

[0144] The RX unit (42) can receive a differential data signal and a differential clock signal from the data processing device (300). For example, the differential data signal may be DATP / DATM in the form of a mini LVDS, and the differential clock signal may be CLKP / CLKM in the form of a mini LVDS.

[0145] When the RX unit (42) receives a differential data signal and a differential clock signal, it can filter them in the input buffer. That is, the RX unit (42) can filter the differential data signal and the differential clock signal and match the electrical characteristics.

[0146] The RX unit (42) can recover the differential clock signal to accurately synchronize the differential data signal and the differential clock signal, and extract the bit value by sampling the differential data signal based on the differential clock signal.

[0147] The RX unit (42) can verify the integrity of the differential data signal using an error detection code.

[0148] The RX unit (42) can output a differential data signal as digital serial data. That is, the RX unit (42) can transmit digital serial data to the conversion unit (43).

[0149] The conversion unit (43) can receive digital serial data from the RX unit (42) one bit at a time based on a differential clock signal. The conversion unit (43) can buffer the received digital serial data. That is, the conversion unit (43) can temporarily store the received digital serial data in a buffer or register.

[0150] The conversion unit (43) collects digital serial data in a preset bit width (e.g., 4 bits, 8 bits, 16 bits, 32 bits), and when a certain number of bits are collected, converts the digital serial data into a data packet in a parallel format and transmits it to the controller (41). For example, the conversion unit (43) can convert digital serial data into a digital parallel data packet in a parallel format of 4 bits each, and transmit it to the controller (41). Here, the digital parallel data packet can be interpreted as data packed in a parallel format of 4 bits each of digital serial data.

[0151] The controller (41) can receive a digital parallel data packet in a parallel format from the conversion unit (43) and divide the digital parallel data packet into at least one based on a preset standard. The controller (41) can divide the digital parallel data packet into a first data packet and a second data packet.

[0152] Since digital parallel data packets are essentially the same as dividing data packets as described above, they are omitted here.

[0153] The controller (41) may be referred to as a logic top.

[0154] The controller (41) can select the first path or the second path according to the VD signal provided from the data processing device (300), and transmit the first data packet and the second data packet to the first path or the second path based on the selected result. The VD (mini LVDS Valid Data) signal is a valid data signal and can be used to indicate the validity of data transmission. The VD signal can be referred to as an LVDS Interface selection signal. For example, the data processing device can maintain the VD signal until data is transmitted to all data driving devices of the corresponding daisy after data input. Here, the VD signal is not used as a reset concept. The protocol can be continuously maintained until EOC comes.

[0155] LVDS_DATA_EN can send an Enable signal to the RX section (42) when the VD signal (VD Interface) is applied from the controller (41), which is the logic top, and can be Disabled when the command is finished. That is, the controller (41) can disable the Enable of LVDS_CLK_EN when all buffered data is transmitted.

[0156] At this time, the IP of the RX unit (42) may not be controlled to eliminate the wakeup time.

[0157] Here, the first path may be a path transmitted from the data processing device (300) to a plurality of data driving devices through the data processing device (300), the SPI interface, and the first controller (21, see FIG. 1), and the second path may be a path transmitted from the data processing device (300) to the first data driving device (410a1), which is a master data driving device, through the data processing device (300), the mini LVDS interface, the RX unit (42), the conversion unit (43), and the controller (41), and transmitted to the remaining data driving devices except for the first data driving device (410a1).

[0158] The controller (41) may include a division unit (41-1) and a selection unit (41-2).

[0159] The division unit (41-1) can receive a digital parallel data packet in a parallel format from the conversion unit (43) and divide the digital parallel data packet into at least one based on a preset standard. The controller (41) can divide the digital parallel data packet into a first data packet and a second data packet. For example, the controller (41) can divide data packets transmitted in 4-bit chunks each through the conversion unit (43) into two each to form a first data packet and a second data packet.

[0160] The splitter (41-1) can transmit the first data packet to the selector (41-2) using the first lane, and can transmit the second data packet to the selector (41-2) using the second lane.

[0161] The selection unit (41-2) can select the first path or the second path according to the VD signal provided from the data processing device (300), and transmit the first data packet and the second data packet to the first path or the second path based on the selection result.

[0162] For example, if the logic value of the VD signal provided from the data processing (300) is “0”, the controller (41) can select a first path and transmit the first data packet and the second data packet using the selected first path. If the logic value of the VD signal provided from the host (300) is “1”, the controller (41) can select a second path and transmit the first data packet and the second data packet using the selected second path.

[0163] When the logic value of the VD signal is “0”, the selection unit (41-2) can transmit the first data packet provided through the first path to the second data driving device (410a2) using the first lane in synchronization with the clock signal, and can transmit the second data packet provided through the first path to the second data driving device (410a2) using the second lane in synchronization with the clock signal.

[0164] When the logic value of the VD signal is “1”, the selection unit (41-2) can transmit the first data packet provided through the second path to the second data driving device (410a2) using the first lane in synchronization with the clock signal, and can transmit the second data packet provided through the second path to the second data driving device (410a2) using the second lane in synchronization with the clock signal.

[0165] The first data driver used as input by the Mini-LVDS described above can have a data buffer as large as the maximum number of daisy chains. For example, if the number of daisy chains is 12, 48 bits x 12 can be used.

[0166] At this time, it is desirable for the dummy clock to be larger than (input data bit x 4) for stable operation.

[0167] FIGS. 13 to 17 are diagrams illustrating the transmission of data provided to a conversion unit to a controller according to another embodiment of the present invention. FIG. 13 illustrates a transmission protocol of a header part, FIG. 14 illustrates a transmission protocol of a data part for 48 bits, FIG. 15 illustrates a transmission protocol of a data part for 16 bits, FIG. 16 illustrates a transmission protocol of a command, and FIG. 17 illustrates a transmission protocol of ID Assign.

[0168] Referring to FIGS. 13 to 17, the header part may include a start, a command (CMD), an address (ADDR), and a stop. For example, the header part may be expressed as [START], [CMD=WRITE, READ], [ADDR=0x10], and [STOP]. The header part may be referred to as a header packet.

[0169] Start consists of 8 bits and can signal the start of the SPI interface. For example, Start can be expressed as Start & Reset [8T]. The start of the first data packet into which the data packet is divided can consist of 4 bits, and the start of the second data packet can consist of 4 bits.

[0170] The command (CMD) can be composed of 4 bits. For example, the command (CMD) can be expressed as CMD[3T]. The command (CMD) can indicate a control command, Config register write / read, GS data write, Trim Data Write, etc., but is not limited thereto. The command (CMD) of the first data packet into which the data packet is divided can be composed of 2 bits, and the command (CMD) of the second data packet can be composed of 2 bits.

[0171] The address (ADDR) consists of 8 bits and can represent an option (Option) or address of a command (CMD). For example, the address (ADDR) can be expressed as ADDR[8T]. The address (ADDR) of the first data packet into which the data packet is divided can consist of 4 bits, and the address (ADDR) of the second data packet can consist of 4 bits.

[0172] STOP can be used when sending the header part and the data part on the next VD signal. That is, since LVDS can separate the header part and the data part, STOP may be needed to separate them.

[0173] The header part transmits a total of 24 bits including start, command, address, and stop, and then adds a 4-bit dummy bit to transmit to the controller as a total of 28T. 28T can be expressed as 14 clocks. Here, dual can represent both edges of the clock signal.

[0174] In this way, the conversion unit adds a 4-bit dummy and transmits it to the controller, so that the controller that receives the header part can process the data more stably.

[0175] Additionally, the conversion unit can convert digital serial data into digital parallel data packets in a 4-bit parallel format. This is to facilitate easier division into a first data packet and a second data packet when the controller divides the digital parallel data packets transmitted in 4-bit increments into two.

[0176] Accordingly, the division unit can transmit the total Total 96+16T (dual) to the controller by multiplying the 24-bit and 4-bit dummy by 4. The conversion unit adds a 16-bit dummy and transmits it to the controller, so that the controller that receives the header part can process the data more stably.

[0177] A data part may include an ID, DATA, and EOD (or EOC). For example, a data part may be expressed as ID[4T], DATA[47:0], EOD[], and EOC.

[0178] The ID consists of 8 bits and can be a daisy chained ID number. The ID can be expressed as ID [4T]. The ID of the first data packet into which the data packet is divided can consist of 2 bits, and the ID of the second data packet can consist of 2 bits.

[0179] Data can be composed of 16 / 48 bits, depending on the command (CMD). For example, data can be expressed as DATA[47:0]. The data of the first data packet into which the data packet is divided can be composed of 24 bits, and the data of the second data packet can be composed of 24 bits.

[0180] EOD consists of 4 bits.

[0181] EOC consists of 4 bits and can be expressed as 1010. EOC or STOP can be used to transmit the data part of Daisy and send the data part on the next VD signal.

[0182] When there are 10 data drive units, the data part can be transmitted to the controller as a total of 560T by multiplying 56 bits including ID, data, and EOD (or EOC) by 10 and adding a 16-bit dummy.

[0183] In this way, the conversion unit adds a 16-bit dummy and transmits it to the controller, so that the controller that receives the data part can process the data more stably.

[0184] The logic top controller must receive the data signals transmitted quickly from the converter, so it may take time to convert them to SCLKO for transmission over dual-lane SPI. Since the controller operates more slowly than the converter, it needs a clock to match the slow operation, so the converter can additionally transmit a dummy blank clock.

[0185] As described above, the controller receives data transmitted quickly from the conversion unit, and since it takes a lot of time to process it, the conversion unit can additionally transmit a dummy blank clock. The data part for 16 bits illustrated in FIG. 15, the transmission protocol of the command illustrated in FIG. 16, and the transmission protocol of the ID Assign illustrated in FIG. 17 also allow the conversion unit to additionally transmit a dummy blank clock to the controller for the same reason.

[0186] As described above, the data transmission device according to the embodiment of the present invention has a Daisy Chained SPI structure composed of a Double Rate SPI with the same number of SPI terminals, thereby increasing the SPI frame data rate without additional cost.

[0187] In addition, the data transmission device according to an embodiment of the present invention can perform high-speed communication without additional cost by using the Master of the Daisy Chain to communicate with the Host using mini-LVDS and the lower daisy chain using the structure of Double rate SPI.

[0188] In addition, a data transmission device according to an embodiment of the present invention can reduce the complexity of the communication circuit and the current consumption problem by using the Master of the Daisy Chain to communicate with the Host using mini-LVDS and using the lower daisy chain in the structure of Double rate SPI, but using only the RX of the Mini-LVDS and eliminating the TX of the Mini-LVDS.

[0189] Since the content of the specification described in the problem to be solved, the means for solving the problem, and the effect described above does not specify the essential features of the claim, the scope of the claim is not limited by the matters described in the content of the specification.

[0190] Since the content of the specification described in the problem to be solved, the means for solving the problem, and the effect described above does not specify the essential features of the claim, the scope of the claim is not limited by the matters described in the content of the specification.

[0191] While the embodiments of the present invention have been described in more detail with reference to the attached drawings, the present invention is not necessarily limited to these embodiments, and various modifications may be implemented without departing from the scope of the technical spirit of the present invention. Accordingly, the embodiments disclosed in the present invention are intended to illustrate rather than limit the technical spirit of the present invention, and the scope of the technical spirit of the present invention is not limited by these embodiments. Therefore, it should be understood that the embodiments described above are illustrative in all respects and not restrictive.

Claims

1. Multiple data drive devices; and A data processing device comprising an input / output port electrically connected to the plurality of data driving devices through a first lane and a second lane, and a main controller controlling the transmission of the data packet to the plurality of data driving devices using the first lane and the second lane; The above main controller, The data packet transmitted to the first data driving device to the nth data driving device is divided into a first data packet and a second data packet, A data transmission device that simultaneously transmits the divided first data packet and the second data packet to the first data driving device using the first lane and the second lane, respectively.

2. In paragraph 1, The above main controller, A data transmission device that, when a write command / read command is recognized in the data packet, determines whether the data packet is divided based on this, and transmits the data packet to the first data driving device through at least one of the first lane and the second lane based on the determined result, or transmits the first data packet or the second data packet to the first data driving device.

3. In paragraph 2, The above main controller, When the write command is recognized in the data packet, the data packet is divided into the first data packet and the second data packet, A data transmission device that transmits the first data packet to the first data driving device using the first lane, and simultaneously transmits the second data packet to the first data driving device using the second lane.

4. In paragraph 2, The above main controller, When the Read Command is recognized in the above data packet, the data packet is not split, A data transmission device that transmits the data packet to the first data driving device using the first lane and transmits a “0” bit to the first data driving device using the second lane.

5. In paragraph 1, The above main controller, A data transmission device that divides the above data packet into at least one or more data packets, the number of lanes connected to the input / output ports of the data processing device being divided.

6. In paragraph 1, The above first data driving device, A first input section electrically connected to the first lane and the second lane and receiving a clock signal, a data packet, a first data packet, and a second data packet; A first register that stores the clock signal, the data packet, the first data packet and the second data packet input through the first input unit, and transmits the clock signal, the data packet, the first data packet and the second data packet by shifting them by a predetermined number of bits; A first controller that analyzes the clock signal, the data packet, the first data packet and the second data packet input through the first input unit, and obtains information or data of an identifier for the data packet, the first data packet and the second data packet based on the analyzed result; and A data transmission device comprising: a first output unit that outputs the clock signal received from the first register, the data packet, the first data packet, and the second data packet.

7. In paragraph 6, The above first controller, A data transmission device that analyzes the above data packet, the first data packet, and the second data packet to determine an ID among the header parts thereof, and if the ID is determined to be the user's ID, receives data related to the user's ID.

8. In paragraph 7, The above first controller, A data transmission device that analyzes the above data packet, the first data packet, and the second data packet to determine an ID among the header parts thereof, and if the ID is determined to be another ID other than the own ID, bypasses data related to the other ID.

9. In paragraph 6, The above first judgment section, The data packet, the first data packet and the second data packet input through the first input unit are provided, the header part and the data part of each of them are analyzed, and the presence or absence of an error is checked based on the analyzed result. A data transmission device that generates a specific signal and transmits the specific signal to the first output unit when the analysis result determines that there is an error.

10. In paragraph 6, The above first judgment section, A data transmission device that checks the first start bit of the first data packet provided through the first lane and the first start bit of the second data packet provided through the second lane, and if the first start bit of the first data packet is "1" and the first start bit of the second data packet is "0", determines that it is the read command, and transmits the data packet using the first lane based on the determination result.

11. First data driving device to nth data driving device; and A data processing device electrically connected to the first data driving device to the nth data driving device through at least one lane; The above data processing device, The first data drive device is connected to the M-LVDS (Mini Low-Voltage Differential Signaling) low-voltage differential signal transmission method to transmit differential data signals. The above first data driving device, A data transmission device that transmits data packets by being connected to the second data driving device to the nth data driving device in a daisy chain SPI (Serial Peripheral Interface) structure.

12. In paragraph 11, The above first data driving device, Connected to the above host as a single lane, A data transmission device connected to the second data driving device or the nth data driving device with two lanes, that is, a double lane.

13. In paragraph 11, The above first data driving device, An RX unit that receives a differential data signal and a differential clock signal from the host and transmits the differential data signal as digital serial data; A conversion unit that receives the digital serial data from the RX unit one bit at a time based on the differential clock signal, converts the digital serial data into a digital parallel data packet in parallel form, and transmits the converted digital serial data; and A data transmission device including a controller that receives the digital parallel data packet from the conversion unit and divides it into at least one.

14. In paragraph 13, The above controller, Receive the digital parallel data packet from the above conversion unit, divide the digital parallel data packet into a first data packet and a second data packet based on a preset standard, A splitter that transmits the split first data packet using a first lane and transmits the split second data packet using a second lane; and A data transmission device comprising a selection unit that selects a first path or a second path according to a VD signal provided from the data processing device, and transmits the first data packet and the second data packet to the first path or the second path based on the selection result.

15. In paragraph 14, The above controller, If the logic value of the VD signal provided from the data processing device is “0”, the first path is selected, A data transmission device that selects a second path when the logic value of the above VD signal is “1”.

Images