Array substrate, display panel, and display device

Abstract

Provided in the embodiments of the present disclosure are an array substrate, a display panel, and a display device. The array substrate comprises: a base; a plurality of gate lines, which are located on one side of the base and extend in a first direction; a plurality of data lines, which are located on the same side of the base as the gate lines and extend in a second direction, the second direction intersecting with the first direction; and a plurality of sub-pixel electrodes, which are located on the same side of the base as the gate lines, wherein at least one sub-pixel electrode among the plurality of sub-pixel electrodes comprises: two first sub-pixel electrodes sequentially arranged in the first direction, and a second sub-pixel electrode located between the two first sub-pixel electrodes; the light emission brightness of the region where the second sub-pixel electrodes are located is greater than that of the region where the first sub-pixel electrodes are located; and each sub-pixel electrode comprises at least a first slit extending in the first direction, the first slit passing through a central region of the sub-pixel electrode.

Description

Array substrate, display panel, and display device Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, and in particular to an array substrate, a display panel, and a display device. Background Art

[0002] The name UV2A comes from the multiplication of ultraviolet (UV) light and the VA method of the liquid crystal panel. This technology can precisely manipulate the alignment of liquid crystal molecules through ultraviolet light, greatly improving the light transmittance.

[0003] The key to UV2A lies in its use of a special polymer material as an alignment film, precisely controlling the tilt of liquid crystal molecules along the direction of ultraviolet light. This accuracy is measured in picometers (one trillionth of a meter). UV2A's advantage lies in its simple LCD panel structure, free of protrusions and slits. This "dream of LCD technicians" was explored as early as 30 years ago. Today, thanks to the availability of new materials, production equipment, and a refined processing process, this dream has become a reality. This simple LCD panel structure not only improves production efficiency but also offers numerous advantages in image quality.

[0004] Summary of the Invention

[0005] The present disclosure provides an array substrate, a display panel, and a display device. The array substrate includes:

[0006] substrate;

[0007] A plurality of gate lines are located on one side of the substrate and extend along a first direction;

[0008] a plurality of data lines, located on the same side of the substrate as the gate lines, extending along a second direction, the second direction intersecting the first direction;

[0009] a plurality of sub-pixel electrodes, each located on the same side of the substrate as the gate line, wherein at least one of the plurality of sub-pixel electrodes comprises: two first sub-pixel electrodes arranged sequentially along a first direction, and a second sub-pixel electrode located between the two first sub-pixel electrodes; and a light output luminance of a region where the second sub-pixel electrode is located is greater than a light output luminance of a region where the first sub-pixel electrode is located;

[0010] The sub-pixel electrode at least includes a first slit extending along the first direction, and the first slit passes through a central area of ​​the sub-pixel electrode.

[0011] In a possible implementation manner, the first slit is located on the first sub-pixel electrode.

[0012] In a possible implementation, the first slit includes: a plurality of first sub-slits extending along the first direction and arranged along the second direction.

[0013] In a possible implementation, the second sub-pixel electrode includes: a plurality of electrode pattern blocks arranged along the second direction, and an electrode connecting portion connecting adjacent pattern blocks;

[0014] The first sub-slit further includes: a first sub-slit portion and a second sub-slit portion extending along the first direction and arranged along the first direction; the first sub-slit portion and the second sub-slit portion are located on different sides of the electrode connecting portion.

[0015] In a possible implementation manner, the first sub-pixel electrode further includes: a first sub-pixel electrode portion, and a second sub-pixel electrode portion;

[0016] The first sub-pixel electrode portion is spaced between two adjacent first sub-slit portions in the second direction; and the second sub-pixel electrode portion is spaced between two adjacent second sub-slit portions in the second direction.

[0017] In a possible implementation manner, one end of the first sub-slit portion away from the electrode connecting portion is a closed structure; and one end of the second sub-slit portion away from the electrode connecting portion is a closed structure.

[0018] In a possible implementation, the sub-pixel electrode further includes: a second slit extending along the second direction, and an extension line of the second slit passes through a central area of ​​the sub-pixel electrode.

[0019] In a possible embodiment, the electrode pattern block includes: a first pattern portion extending along the second direction, and two second pattern portions connected to the first pattern portion; the two second pattern portions are respectively located on both sides of the first pattern portion along the first direction;

[0020] The second slit is located between the first pattern portion and the second pattern portion.

[0021] In a possible implementation manner, the electrode pattern block further includes: a pattern connecting portion located between the first pattern portion and the second pattern portion; the first pattern portion and the second pattern portion are electrically connected via the pattern connecting portion.

[0022] In a possible embodiment, two pattern connecting portions are provided between the first pattern portion and the second pattern portion, and the two pattern connecting portions are respectively located at two end positions of the outer edge of the second pattern portion along the second direction, and connect the second pattern portion and the first pattern portion at the end positions;

[0023] The second slit is located between two of the pattern connecting portions.

[0024] In a possible embodiment, a pattern connecting portion is provided between the first pattern portion and the second pattern portion, wherein the pattern connecting portion is connected to a middle position of an outer edge of the second pattern portion along the second direction, and connects the second pattern portion and the first pattern portion at the middle position;

[0025] The second slit is located between the first pattern portion and the second pattern portion and located on both sides of the pattern connecting portion along the second direction.

[0026] In a possible implementation, the array substrate further includes: a first common trace located on one side of the gate line, and a transfer electrode; an orthographic projection of the transfer electrode on the substrate and an orthographic projection of the first common trace on the substrate have an overlapping area;

[0027] The array substrate further includes a pixel circuit; the pixel circuit includes a first transistor, a second transistor, and a third transistor.

[0028] The first transistor includes: a first transistor control electrode, a first transistor first electrode, and a first transistor second electrode; the second transistor includes: a second transistor control electrode, a second transistor first electrode, and a second transistor second electrode; the third transistor includes: a third transistor control electrode, a third transistor first electrode, and a third transistor second electrode;

[0029] The control electrode of the first transistor multiplexes with the gate line, the first electrode of the first transistor multiplexes with the data line; the second electrode of the first transistor is electrically connected to the second sub-pixel electrode;

[0030] The control electrode of the second transistor reuses the gate line, the first electrode of the second transistor reuses the first electrode of the first transistor; the second electrode of the second transistor is electrically connected to the first sub-pixel electrode;

[0031] The control electrode of the third transistor reuses the gate line, the first electrode of the third transistor reuses the second electrode of the second transistor; and the second electrode of the third transistor is electrically connected to the switching electrode.

[0032] In a possible implementation manner, the orthographic projection of the second sub-pixel electrode on the substrate overlaps with the orthographic projections of the gate line and the first common line on the substrate.

[0033] In a possible implementation, the array substrate further includes: a pixel circuit; the pixel circuit includes: a first transistor, a second transistor, a third transistor, and a first signal line;

[0034] The first transistor includes: a first transistor control electrode, a first transistor first electrode, and a first transistor second electrode; the second transistor includes: a second transistor control electrode, a second transistor first electrode, and a second transistor second electrode; the third transistor includes: a third transistor control electrode, a third transistor first electrode, and a third transistor second electrode;

[0035] The control electrode of the first transistor multiplexes with the gate line, the first electrode of the first transistor multiplexes with the data line; the second electrode of the first transistor is electrically connected to the second sub-pixel electrode;

[0036] The control electrode of the second transistor reuses the gate line, the first electrode of the second transistor reuses the first electrode of the first transistor; the second electrode of the second transistor is electrically connected to the first sub-pixel electrode;

[0037] The control electrode of the third transistor multiplexes with the gate line, the first electrode of the third transistor multiplexes with the second electrode of the second transistor; and the second electrode of the third transistor multiplexes with the first signal line.

[0038] An embodiment of the present disclosure further provides a display panel, which includes the array substrate provided in the embodiment of the present disclosure, and also includes an opposite substrate arranged opposite to the array substrate; the opposite substrate includes: a common electrode layer.

[0039] An embodiment of the present disclosure further provides a display device, which includes the display panel provided by the embodiment of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] Figure 1 is a schematic diagram of the sub-pixel distribution of 1P4D;

[0041] FIG2A is a schematic top view of an array substrate according to an embodiment of the present disclosure;

[0042] FIG2B is a schematic diagram of a single film layer of the gate line layer in FIG2A ;

[0043] FIG2C is a schematic diagram of a single film layer of the data line layer in FIG2A ;

[0044] FIG2D is a schematic diagram of a single film layer of the active layer in FIG2A;

[0045] FIG2E is a schematic diagram of a single film layer of the first insulating layer in FIG2A ;

[0046] FIG2F is a schematic diagram of a single film layer of the pixel electrode layer in FIG2A ;

[0047] FIG2G is a schematic diagram of the black matrix layer corresponding to FIG2A ;

[0048] FIG2H is a schematic diagram of light effects corresponding to FIG2A ;

[0049] FIG2I is a schematic diagram of an equivalent circuit corresponding to FIG2A ;

[0050] FIG3A is a second schematic top view of an array substrate provided in an embodiment of the present disclosure;

[0051] FIG3B is a schematic diagram of a single film layer of the pixel electrode layer in FIG2A ;

[0052] FIG3C is a schematic diagram of light effects corresponding to FIG3A ;

[0053] FIG4A is a third schematic top view of an array substrate provided in an embodiment of the present disclosure;

[0054] FIG4B is a schematic diagram of a single film layer of the pixel electrode layer in FIG4A ;

[0055] FIG5A is a fourth schematic top view of an array substrate provided in an embodiment of the present disclosure;

[0056] FIG5B is a schematic diagram of a single film layer of the gate line layer in FIG5A;

[0057] FIG5C is a schematic diagram of a single film layer of the data line layer in FIG5A ;

[0058] FIG5D is a schematic diagram of a single film layer of the active layer in FIG5A;

[0059] FIG5E is a schematic diagram of a single film layer of the first insulating layer in FIG5A ;

[0060] FIG5F is a schematic diagram of a single film layer of the pixel electrode layer in FIG5A ;

[0061] FIG5G is a schematic diagram of an equivalent circuit corresponding to FIG5A ;

[0062] FIG6 is a fifth schematic top view of an array substrate provided in an embodiment of the present disclosure;

[0063] FIG7 is a sixth schematic top view of an array substrate provided in an embodiment of the present disclosure;

[0064] FIG8 is a seventh schematic top view of an array substrate provided in an embodiment of the present disclosure;

[0065] FIG9 is a schematic diagram of various crosstalk images. DETAILED DESCRIPTION

[0066] In order to make the purpose, technical solutions and advantages of the embodiments of the present disclosure more clear, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the drawings of the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, not all of the embodiments. Based on the described embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure.

[0067] Unless otherwise defined, the technical or scientific terms used in this disclosure should have the usual meanings understood by persons of ordinary skill in the field to which this disclosure belongs. The words "first", "second" and similar terms used in this disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. Words such as "include" or "comprise" mean that the elements or objects appearing before the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Words such as "connect" or "connected" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the object being described changes, the relative positional relationship may also change accordingly.

[0068] As used herein, "about" or "approximately the same" is inclusive of the stated value and means within an acceptable range of deviation for the particular value as determined by one of ordinary skill in the art taking into account the measurement in question and the errors associated with the measurement of the particular quantity (i.e., the limitations of the measurement system). For example, "approximately the same" can mean that the difference relative to the stated value is within one or more standard deviations, or within ±30%, 20%, 10%, 5%.

[0069] In the accompanying drawings, the thickness of layers, films, panels, regions, etc. are exaggerated for clarity. Exemplary embodiments are described herein with reference to cross-sectional views that are schematic representations of idealized embodiments. As such, deviations from the shapes of the figures are to be expected as a result of, for example, manufacturing techniques and / or tolerances. Thus, the embodiments described herein should not be construed as limited to the specific shapes of the regions as shown herein, but rather include deviations in shape that result from, for example, manufacturing. For example, a region illustrated or described as flat may typically have rough and / or nonlinear features. Furthermore, sharp corners illustrated may be rounded. Thus, the regions illustrated in the figures are schematic in nature, and their shapes are not intended to illustrate the precise shape of the regions and are not intended to limit the scope of the claims.

[0070] In order to keep the following description of the embodiments of the present disclosure clear and concise, the present disclosure omits detailed descriptions of known functions and known components.

[0071] Compared with the UV2A pixel design, ultra-fine photo-alignment (SUVA) is an upgraded version of UV2A, as shown in Figure 1, where Figure 1 shows the SUVA pixel design of 1P4D (one sub-pixel contains 4 domains). Compared with the UV2A pixel design, the SUVA pixel design can effectively reduce the dark lines of the pixel, but the transmittance of the SUVA alignment is significantly improved for the 4-domain alignment, while the number of dark lines increases for the 8-domain alignment, and the transmittance improvement is insufficient.

[0072] In view of this, an embodiment of the present disclosure provides an array substrate, as shown in FIG. 2A to FIG. 2F , comprising:

[0073] Substrate 1;

[0074] A plurality of gate lines 2 are located on one side of the substrate 1 and extend along a first direction X;

[0075] A plurality of data lines 3 are located on the same side of the substrate 1 as the gate lines 2 and extend along a second direction Y, which intersects the first direction X;

[0076] A plurality of sub-pixel electrodes 4 are located on the same side of the substrate 1 as the gate line 2, at least one of the plurality of sub-pixel electrodes 4 includes: two first sub-pixel electrodes 41 arranged sequentially along the first direction X, and a second sub-pixel electrode 42 located between the two first sub-pixel electrodes 41, optionally, the two first sub-pixel electrodes 41 in the same sub-pixel electrode 4 are electrically connected; and the light output brightness of the region where the second sub-pixel electrode 42 is located is greater than the light output brightness of the region where the first sub-pixel electrode 41 is located;

[0077] The sub-pixel electrode 4 at least includes a first slit F1 extending along the first direction X, and the first slit F1 passes through the central area of ​​the sub-pixel electrode 4 .

[0078] In the embodiment of the present disclosure, the sub-pixel electrode 4 includes: two first sub-pixel electrodes 41, and a second sub-pixel electrode 42 located between the two first sub-pixels 41; the light output brightness of the area where the second sub-pixel electrode 42 is located is greater than the light output brightness of the area where the first sub-pixel electrode 41 is located; the sub-pixel electrode 4 includes at least a first slit F1 extending along the first direction X, and the first slit F1 passes through the central area of ​​the sub-pixel electrode 4, that is, by setting the brighter second sub-pixel electrode 42 between the two darker first sub-pixel electrodes 41 in a 1P8D structure design, and adding the first slit F1 extending along the first direction X to the sub-pixel electrode 4, which roughly coincides with the position of the sub-pixel horizontal dark stripes, the design of the pixel structure forming dark stripes in the light orientation can be compressed, the proportion of dark stripes can be reduced, and the liquid crystal efficiency can be improved. At the same time, the 1P8D pixel design is adopted to improve color deviation.

[0079] In addition, in the embodiment of the present disclosure, a 1P8D structure is designed by setting the brighter second sub-pixel electrode 42 between the two darker first sub-pixel electrodes 41, that is, the brighter second sub-pixel 42 is located in the middle and the darker first sub-pixels 41 are set on both sides. Due to voltage suppression, longitudinal crosstalk will not occur.

[0080] In the liquid crystal display panel, various wirings are densely arranged, and there is a large coupling capacitance, which leads to various crosstalk problems. The type of crosstalk is closely related to the row flip / column flip / dot flip of the liquid crystal display panel. As shown in Figure 9, crosstalk problems include horizontal crosstalk, vertical crosstalk, etc. Among them, horizontal crosstalk is related to the coupling capacitance between the data line and the common electrode; and vertical crosstalk, on the one hand, is related to the coupling capacitance between the data line and the pixel electrode, and on the other hand, it is also related to the transistor leakage current Ioff.

[0081] In the conventional 8Domain sub-pixel design, dark pixels are not bright at low grayscales, and only bright pixels are bright. In the disclosed embodiment, by setting the brighter second sub-pixel 42 in the middle of the sub-pixel 4, the distance between the brighter second sub-pixel 42 and the data line can be made farther, and the coupling capacitance Cpd between the sub-pixel electrode and the data line is approximately 0. Therefore, when the image changes at low grayscales, pixels of different grayscales on both sides are unlikely to be affected by the different voltages of the data lines on both sides, so it is difficult for longitudinal crosstalk (i.e., vertical crosstalk) to occur, thereby improving the problem of longitudinal crosstalk. In other words, the setting method of setting the brighter second sub-pixel 42 in the middle of the sub-pixel 4 has good longitudinal crosstalk performance at low grayscales.

[0082] It should be noted that brighter means more backlight is transmitted, and darker means less backlight is transmitted. That is, when different voltages are applied to different areas, the voltage difference formed with the common electrode of the opposite substrate is different. The greater the pressure difference, the stronger the ability to drive the liquid crystal to rotate, the more backlight is transmitted, and the brighter the area is. Conversely, the smaller the pressure difference, the weaker the ability to drive the liquid crystal to rotate, the less backlight is transmitted, and the darker the area is.

[0083] Specifically, the array substrate may further include a pixel circuit, and the brightness of the area where the second sub-pixel electrode 42 is located is greater than the brightness of the area where the first sub-pixel 41 is located. It can be understood that under the drive of the pixel circuit, the brightness of the second sub-pixel 42 is greater than the brightness of the first sub-pixel 41.

[0084] It should be noted that, since the main difference between the structure shown in FIG3A and the structure shown in FIG2A lies in the difference in the sub-pixel electrode pattern, the array substrate corresponding to FIG3A mainly shows the pattern of the sub-pixel electrode layer shown in FIG3B , and the patterns of the gate line layer, data line layer, active layer, first insulating layer, and black matrix layer corresponding to FIG3A can be seen in FIG2B-FIG2E , and are no longer repeated in the embodiments of the present disclosure; the remaining drawings are similar.

[0085] Figure 2H is a light effect diagram of the pixel structure corresponding to Figure 2A, and Figure 3C is a light effect diagram of the pixel structure corresponding to Figure 3A. By comparing the light effect diagrams of Figures 2H and 3C, it can be seen that the pixel structure of Figure 2A can make the dark lines of the structure thinner and increase the transmittance compared to Figure 3A; in the structure of Figure 3A, there is a dark line that bends in the middle position of the electrode pattern block P0, and the effect of improving the transmittance is not as good as the structure shown in Figure 2A.

[0086] In one possible embodiment, as shown in FIG2F , the first slit F1 is located in the first sub-pixel electrode 41 . This adapts to the position where the pixel structure may produce horizontal dark stripes in the sub-pixel center area, reduces the proportion of dark stripes, and improves liquid crystal efficiency.

[0087] In one possible embodiment, as shown in FIG2F , the first slit F1 includes: a plurality of first sub-slits F11 extending along the first direction X and arranged along the second direction Y. In another possible embodiment, as shown in FIG2G , the first slit F1 includes: two first sub-slits F11 extending along the first direction X and arranged along the second direction Y. In this way, while reducing the proportion of dark lines, the impact on the sub-pixel electrode 4 during normal display is reduced. Optionally, three or more first slits can be provided in this case, and the slits can be straight, wavy, or broken line-shaped, etc., which is not limited here.

[0088] In one possible embodiment, as shown in FIG2F , the second sub-pixel 42 electrode includes: a plurality of electrode pattern blocks P0 arranged along the second direction Y, and an electrode connection portion P1 connecting adjacent pattern blocks P0. The first sub-slit F11 also includes: a first sub-slit portion FA and a second sub-slit portion FB extending along the first direction X and arranged along the first direction X. The first sub-slit portion FA and the second sub-slit portion FB are located on different sides of the electrode connection portion P1. For example, as shown in FIG2G , the first sub-slit portion FA is located to the left of the electrode connection portion P1, and the second sub-slit portion FB is located to the right of the electrode connection portion P1. In other words, the first sub-slit F11 is disconnected at the location of the second sub-pixel electrode 42 to avoid affecting the structure of the second sub-pixel electrode 42.

[0089] In one possible embodiment, as shown in FIG2F , the first subpixel electrode 41 further includes: a first subpixel electrode portion 41A and a second subpixel electrode portion 41B; the first subpixel electrode portion 41A is spaced between two adjacent first sub-slit portions FA in the second direction Y; and the second subpixel electrode portion 41B is spaced between two adjacent second sub-slit portions FB in the second direction Y. Optionally, the portion of the first subpixel electrode 41 located between the two first sub-slit portions FA may serve as the first subpixel electrode portion 41A, and the portion of the first subpixel electrode 41 located between the two second sub-slit portions FB may serve as the second subpixel electrode portion 41B.

[0090] In one possible embodiment, as shown in FIG2F , the end of the first sub-slit portion FA away from the electrode connection portion P1 is closed, and the end of the second sub-slit portion F2 away from the electrode connection portion P1 is also closed. This prevents the first sub-pixel electrode 41 from being broken in the second direction Y when the first slit F1 penetrates the first sub-pixel electrode 41 in the first direction X, thereby preventing the display from being interrupted.

[0091] In one possible implementation, referring to Figures 2F, 3B, 4B, 6, 7, and 8, the sub-pixel electrode 4 further includes a second slit F2 extending along the second direction Y, with the extension of the second slit F2 passing through the central region of the sub-pixel electrode 4. In the disclosed embodiment, the sub-pixel electrode 4 further includes a second slit F2 extending along the second direction Y, with the extension of the second slit F2 passing through the central region of the sub-pixel electrode 4 and substantially coinciding with the position of the longitudinal dark stripe of the sub-pixel. This can compress the design of the pixel structure forming dark stripes in the second direction Y when light is aligned, reduce the proportion of dark stripes in the second direction Y, improve liquid crystal efficiency, and simultaneously improve color shift by adopting a 1P8D pixel design.

[0092] In one possible embodiment, as shown in FIG2F , an electrode pattern block P0 includes: a first pattern portion P01 extending along the second direction Y, and two second pattern portions P02 connected to the first pattern portion P01. Optionally, the orthographic projection of the first pattern portion P01 on the substrate 1 may be a vertical bar, and the orthographic projection of the second pattern portion P02 on the substrate 1 may be a triangle. The two second pattern portions P02 are respectively located on either side of the first pattern portion P01 along the first direction X. A second slit F2 is located between the first pattern portion P01 and the second pattern portion P02. Optionally, as shown in FIG2G , each second pattern portion P02 may form a second slit F2 extending along the second direction Y between the first pattern portion P01 and the second pattern portion P02. Thus, an electrode pattern block P0 may have two second slits F2.

[0093] In a possible embodiment, referring to FIG2F , the electrode pattern block P0 further includes: a pattern connecting portion P03 located between the first pattern portion P01 and the second pattern portion P02. For example, in combination with FIG2G , the pattern connecting portion P03 is located at the end of the second pattern portion P02; the first pattern portion P01 and the second pattern portion P02 are electrically connected via the pattern connecting portion P03.

[0094] In a possible embodiment, as shown in Figure 2F, there are two pattern connecting portions P03 between the first pattern portion P01 and the second pattern portion P02. The two pattern connecting portions P03 are respectively located at the two end positions of the outer edge of the second pattern portion P02 along the second direction Y, and connect the second pattern portion P02 and the first pattern portion P01 at the end positions; the second slit F2 is located between the two pattern connecting portions P03.

[0095] In a possible embodiment, referring to Figures 3A and 3B, a pattern connecting portion P03 is provided between the first pattern portion P01 and the second pattern portion P02. The pattern connecting portion P03 is connected to the middle position of the outer edge of the second pattern portion P02 along the second direction Y, and connects the second pattern portion P02 and the first pattern portion P01 at the middle position; the second slit F2 is located between the first pattern portion P01 and the second pattern portion P02, and on both sides of the pattern connecting portion P03 along the second direction Y.

[0096] In one possible embodiment, as shown in FIG2F , the two second pattern portions P02 are symmetrical about the first pattern portion P01. In another possible embodiment, as shown in FIG5B , the orthographic projection of the second pattern portion P02 on the substrate 1 is a triangle. Alternatively, the orthographic projection of the second pattern portion P02 on the substrate 1 is a right triangle, with the two second pattern portions P02 of the right triangle arranged with their hypotenuses facing each other; alternatively, the second pattern portion P02 of the right triangle is arranged with its hypotenuse facing the second gap F2.

[0097] In one possible embodiment, as shown in FIG. 2F , the second gaps F2 of two adjacent electrode pattern blocks P0 are not connected. This allows the two second pattern portions P02 on the left and right sides of the same electrode pattern block P0 to be electrically connected at their upper and lower ends, ensuring that the two second pattern portions P02 in the same electrode pattern block P0 have good connectivity even when the second gaps F2 are provided.

[0098] In one possible embodiment, as shown in FIG2F , the orthographic projection of the electrode pattern block P0 on the substrate 1 comprises a rhombus. The angle formed between one side of the rhombus and the first direction X may be 30° to 60°, specifically, for example, 45°; the angle formed between another side of the rhombus and the first direction X may be 130° to 160°, specifically, for example, 145°. In one possible embodiment, as shown in FIG2F , one diagonal line of the rhombus may be parallel to the first direction X, and the other diagonal line may be parallel to the second direction Y.

[0099] In one possible embodiment, the width of the diamond-shaped electrode pattern block P0 in the first direction X may be one-fifth to four-fifths of the width of the sub-pixel electrode 4 in the first direction X. In one possible embodiment, the width of the diamond-shaped electrode pattern block P0 in the first direction X may be one-half of the width of the sub-pixel electrode 4 in the first direction X. In one possible embodiment, the length of the diamond-shaped electrode pattern block P0 in the second direction Y may be one-fifth to four-fifths of the width of the sub-pixel electrode 4 in the second direction Y. In one possible embodiment, the length of the diamond-shaped electrode pattern block P0 in the second direction Y may be one-quarter of the length of the sub-pixel electrode 4 in the second direction Y. In one possible embodiment, the length of the diamond-shaped electrode pattern block P0 in the second direction Y may be one-half of the length of the sub-pixel electrode 4 in the second direction Y. In one possible embodiment, the length of the diamond-shaped electrode pattern block P0 in the second direction Y may be equal to the length of the sub-pixel electrode 4 in the second direction Y.

[0100] In a possible implementation, the four corners of the rhombus may all be right angles, as shown in FIG2F .

[0101] In a possible embodiment, as shown in FIG. 2F , the first sub-pixel electrode 41 may be a pattern complementary to the pattern of the second sub-pixel electrode 42 , that is, in the sub-pixel electrode 4 , the pattern of the second sub-pixel electrode 42 is removed, resulting in the pattern of two first sub-pixel electrodes 41 .

[0102] In one possible embodiment, at least one electrode pattern block P0 is distributed in the same sub-pixel electrode 4. That is, the area of ​​the electrode pattern block P0 can be relatively small, and one or more electrode pattern blocks P0 can be distributed in one sub-pixel electrode 4, as shown in Figures 2A, 3A, 4A, 5A, and 6. In one possible embodiment, referring to Figure 2A, two electrode pattern blocks P0 can be distributed in one sub-pixel electrode P; in one possible embodiment, referring to Figure 7, one electrode pattern block P0 can be distributed in one sub-pixel electrode P.

[0103] In another possible embodiment, at least one electrode pattern block P0 is distributed in two adjacent sub-pixel electrodes 4, that is, the area of ​​the electrode pattern block P0 can be larger, and a portion of an electrode pattern block P0 can be distributed in one sub-pixel electrode 4, that is, one electrode pattern block P0 can be respectively in multiple sub-pixel electrodes 4, as shown in Figure 8.

[0104] In a possible embodiment, referring to FIG8 , the electrode pattern block P0 includes: a first sub-pattern block PX1 distributed along the second direction Y, and a second sub-pattern block PX2; the orthographic projection of the first sub-pattern block PX1 on the substrate 1 is a triangle, and the orthographic projection of the second sub-pattern block PX2 on the substrate 1 is a triangle; the orthographic projection of the second sub-pattern block PX2 of a second sub-pixel electrode 42 on the substrate 1 is combined with the orthographic projection of the first sub-pattern block PX1 of an adjacent second sub-pixel electrode 42 on the substrate 1 to form a rhombus; in the same second sub-pixel electrode 42, the first sub-pattern block PX1 and the second sub-pattern block PX2 are distributed relative to each other at a vertex angle.

[0105] In a possible embodiment, with reference to FIG. 2A to FIG. 2F and FIG. 2I , where FIG. 2I may be an equivalent circuit diagram corresponding to FIG. 2A , the array substrate further includes: a first common trace 51 located on one side of the gate line 2, and a transfer electrode PC; an orthographic projection of the transfer electrode PC on the substrate 1 overlaps with an orthographic projection of the first common trace 51 on the substrate 1;

[0106] The array substrate further includes a pixel circuit; the pixel circuit includes a first transistor T1, a second transistor T2, and a third transistor T3; the first transistor T1 includes a first transistor control electrode T1A, a first transistor first electrode T1B, and a first transistor second electrode T1C; the second transistor T2 includes a second transistor control electrode T2A, a second transistor first electrode T2B, and a second transistor second electrode T2C; the third transistor T3 includes a third transistor control electrode T3A, a third transistor first electrode T3B, and a third transistor second electrode T3C;

[0107] The first transistor control electrode T1A is multiplexed with the gate line 2, the first transistor first electrode T1B is multiplexed with the data line 3; the first transistor second electrode T1C is electrically connected to the second sub-pixel electrode 42;

[0108] The control electrode T2A of the second transistor reuses the gate line 2, the first electrode T2B of the second transistor reuses the first electrode T1B of the first transistor; the second electrode T2C of the second transistor is electrically connected to the first sub-pixel electrode 41;

[0109] The control electrode T3A of the third transistor reuses the gate line 2 , the first electrode T3B of the third transistor reuses the second electrode T2C of the second transistor; the second electrode T3C of the third transistor is electrically connected to the first common wiring 51 through the switching electrode PC.

[0110] In a possible embodiment, in combination with Figures 2A to 2F and Figure 2I, the array substrate further includes: a second common wiring 52 located on the other side of the gate line 2; the pixel circuit further includes: a first liquid crystal capacitor Cpx1, a second liquid crystal capacitor Cpx2, a first capacitor C1, and a second capacitor C2, wherein the first liquid crystal capacitor Cpx1 can be formed by the first sub-pixel electrode 41 and the common electrode layer of the opposite substrate, the second liquid crystal capacitor Cpx2 can be formed by the second sub-pixel electrode 42 and the common electrode layer of the opposite substrate, the first capacitor C1 can be formed by the first sub-pixel electrode 41 and the second common wiring 52, and the second capacitor C2 can be formed by the second sub-pixel electrode 42 and the first sub-common wiring 51.

[0111] In the embodiment of the present invention, the first sub-pixel electrode 41 can be electrically connected to the gate line 2 and the data line 3 through the first transistor T1, the second sub-pixel electrode 42 can be electrically connected to the gate line 2 and the data line 3 through the second transistor T2, and the second electrode T3C of the third transistor is electrically connected to the first common wiring 51. Part of the charge in the second capacitor C2 corresponding to the second sub-pixel electrode P2 can be released to the first common wiring 51 through the third transistor T3, thereby making the brightness of the first sub-pixel electrode 41 greater than the brightness of the second sub-pixel electrode 42, so that different light and dark pixels are provided in the same sub-pixel electrode 4, and realizing an 8-domain display effect.

[0112] In one possible embodiment, as shown in Figures 2A-2F , the orthographic projection of the transfer electrode PC on the substrate 1 overlaps with the orthographic projection of the first common trace 51 on the substrate 1, and also overlaps with the orthographic projection of the second electrode T3C of the third transistor on the substrate 1. The second electrode T3C of the third transistor is electrically connected to the first common trace 51 in the overlapping region through a third via K3 via the transfer electrode PC. The third via K3 can be a semi-via design, partially exposing the first common trace 51 and partially exposing the second electrode T3C of the third transistor. At the third via K3, the transfer electrode PC partially contacts the first common trace 51 and partially contacts the second electrode T3C of the third transistor, thereby electrically connecting the first common trace 51 to the second electrode T3C of the third transistor via the transfer electrode PC. Specifically, the semi-via design of the third via K3 can form a stepped structure within the third via K3, which serves to drain the alignment liquid and prevent the appearance of moiré patterns on the image.

[0113] In a possible embodiment, as shown in FIG2B , the first common routing line 51 and the second common routing line 52 can be made of the same layer and material as the gate line 2 . Thus, the first common routing line 51 and the second common routing line 52 are formed at the same time as the gate line 2 , which can simplify the manufacturing process of the array substrate.

[0114] In a possible implementation, as shown in FIG. 2F , the transfer electrode PC may be made of the same layer and material as the sub-pixel electrode 4 , so that the transfer electrode PC is formed at the same time as the sub-pixel electrode 4 , thereby simplifying the manufacturing process of the array substrate.

[0115] In a possible embodiment, as shown in Figure 2B, the array substrate may further include: a third common routing group extending along the second direction Y, the third common routing group including: two third common routing lines 53, the two third common routing lines 53 of the same third common routing group are projected on the substrate 1 and are located on both sides of the projected data line 3 on the substrate 1.

[0116] In one possible embodiment, referring to Figures 2A to 2F , the orthographic projection of the second sub-pixel electrode 42 on the substrate 1 overlaps with the orthographic projections of the gate line 2 and the first common wiring 51 on the substrate 1. Optionally, the second sub-pixel electrode 42 may include a pixel extension portion P04. Optionally, the orthographic projection of the pixel extension portion P04 on the substrate 1 may overlap with the orthographic projections of the gate line 2 and the first common wiring 51 on the substrate 1. The pixel extension portion P04 may protrude from the sub-pixel electrode, overlap with the orthographic projection of the second electrode T1C of the first transistor, and be electrically connected in the overlapping region, thereby realizing an electrical connection between the first transistor T1 and the second sub-pixel electrode 42.

[0117] In a possible implementation, referring to FIG. 5A to FIG. 5G , FIG. 5G may be an equivalent pixel circuit diagram corresponding to FIG. 5A , and the array substrate further includes: a pixel circuit; the pixel circuit includes: a first transistor T1 , a second transistor T2 , a third transistor T3 , and a first signal line 6 ;

[0118] The first transistor T1 includes: a first transistor control electrode T1A, a first transistor first electrode T1B, and a first transistor second electrode T1C; the second transistor T2 includes: a second transistor control electrode T2A, a second transistor first electrode T2B, and a second transistor second electrode T2C; the third transistor T3 includes: a third transistor control electrode T3A, a third transistor first electrode T3B, and a third transistor second electrode T3C;

[0119] The first transistor control electrode T1A is multiplexed with the gate line 2, the first transistor first electrode T1B is multiplexed with the data line 3; the first transistor second electrode T1C is electrically connected to the second sub-pixel electrode 42;

[0120] The control electrode T2A of the second transistor reuses the gate line 2, the first electrode T2B of the second transistor reuses the first electrode T1B of the first transistor; the second electrode T2C of the second transistor is electrically connected to the first sub-pixel electrode 41;

[0121] The control electrode T3A of the third transistor multiplexes with the gate line 2 , the first electrode T3B of the third transistor multiplexes with the second electrode T2C of the second transistor; and the second electrode T1C of the third transistor multiplexes with the first signal line 6 .

[0122] In a possible embodiment, referring to Figures 5A to 5G, the array substrate further includes: a first common routing line 51 located on one side of the gate line 2, and a second common routing line 52 located on the other side of the gate line 2; the pixel circuit further includes: a first liquid crystal capacitor Cpx1, a second liquid crystal capacitor Cpx2, a first capacitor C1, and a second capacitor C2, wherein the first liquid crystal capacitor Cpx1 can be formed by the first sub-pixel electrode 41 and the common electrode layer of the opposing substrate, the second liquid crystal capacitor Cpx2 can be formed by the second sub-pixel electrode 42 and the common electrode layer of the opposing substrate, the first capacitor C1 can be formed by the first sub-pixel electrode 41 and the second common routing line 52, and the second capacitor C2 can be formed by the second sub-pixel electrode 42 and the first sub-common routing line 51.

[0123] In the embodiment of the present invention, the first sub-pixel electrode 41 can be electrically connected to the gate line 2 and the data line 3 through the first transistor T1, the second sub-pixel electrode 42 can be electrically connected to the gate line 2 and the data line 3 through the second transistor T2, and the second electrode T3C of the third transistor is electrically connected to the first signal line 6. Part of the charge in the second capacitor C2 corresponding to the second sub-pixel electrode 42 can be released to the first signal line 6 through the third transistor T3, thereby making the brightness of the first sub-pixel electrode P1 greater than the brightness of the second sub-pixel electrode 42, so that different light and dark pixels are achieved in the same sub-pixel electrode 4, and realizing an 8-domain display effect.

[0124] In one possible embodiment, as shown in FIG5A to FIG5G , the orthographic projection of the first signal line 6 on the substrate 1 passes through the central area of ​​the orthographic projection of the electrode pattern block P0 on the substrate 1. In this way, the transmittance of the display panel can be improved by having fewer dark lines.

[0125] In a possible embodiment, as shown in FIG. 2A to FIG. 2G , the array substrate may be provided with a gate line layer as shown in FIG. 2B , a data line layer as shown in FIG. 2C , an active layer as shown in FIG. 2D , a first insulating layer as shown in FIG. 2E , and a sub-pixel electrode layer as shown in FIG. 2F in sequence on one side of the substrate 1;

[0126] The active layer may include an active pattern 71 corresponding to the transistor;

[0127] The first insulating layer may have a first via hole K1 , a second via hole K2 , and a third via hole K3 ; the first insulating layer may be a first passivation layer or an organic organic layer.

[0128] Based on the same inventive concept, an embodiment of the present disclosure further provides a display panel, which includes the array substrate provided in the embodiment of the present disclosure, and also includes an opposite substrate arranged opposite to the array substrate; the opposite substrate includes: a common electrode layer.

[0129] Specifically, the counter substrate may include a counter substrate and a common electrode layer located on the side of the counter substrate facing the array substrate. Specifically, the counter substrate may also include a black matrix layer as shown in FIG2G , and the black matrix layer may include a black matrix pattern 81 and black matrix openings.

[0130] Based on the same inventive concept, an embodiment of the present disclosure further provides a display device, which includes a display panel provided by the embodiment of the present disclosure.

[0131] Although the preferred embodiments of the present invention have been described, those skilled in the art may make additional changes and modifications to these embodiments once they have learned the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the present invention.

[0132] Obviously, those skilled in the art may make various changes and modifications to the embodiments of the present invention without departing from the spirit and scope of the embodiments of the present invention. Thus, if such changes and modifications of the embodiments of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is intended to include such changes and modifications.

Claims

1. An array substrate, wherein: include: substrate; A plurality of gate lines are located on one side of the substrate and extend along a first direction; a plurality of data lines, located on the same side of the substrate as the gate lines, extending along a second direction, the second direction intersecting the first direction; a plurality of sub-pixel electrodes, each located on the same side of the substrate as the gate line, wherein at least one of the plurality of sub-pixel electrodes comprises: two first sub-pixel electrodes arranged sequentially along a first direction, and a second sub-pixel electrode located between the two first sub-pixel electrodes; and a light output luminance of a region where the second sub-pixel electrode is located is greater than a light output luminance of a region where the first sub-pixel electrode is located; The sub-pixel electrode at least includes a first slit extending along the first direction, and the first slit passes through a central area of ​​the sub-pixel electrode.

2. The array substrate according to claim 1, wherein: The first slit is located at the first sub-pixel electrode.

3. The array substrate according to claim 1 or 2, wherein: The first slit includes: a plurality of first sub-slits extending along the first direction and arranged along the second direction.

4. The array substrate according to claim 3, wherein: The second sub-pixel electrode includes: a plurality of electrode pattern blocks arranged along the second direction, and an electrode connecting portion connecting adjacent pattern blocks; The first sub-slit further includes: a first sub-slit portion and a second sub-slit portion extending along the first direction and arranged along the first direction; the first sub-slit portion and the second sub-slit portion are located on different sides of the electrode connecting portion.

5. The array substrate according to claim 4, wherein: The first sub-pixel electrode further includes: a first sub-pixel electrode portion, and a second sub-pixel electrode portion; The first sub-pixel electrode portion is spaced between two adjacent first sub-slit portions in the second direction; the second sub-slit portion is spaced between two adjacent second sub-slit portions in the second direction. Second sub-pixel electrode portion.

6. The array substrate according to claim 4 or 5, wherein: One end of the first sub-slit portion away from the electrode connecting portion is a closed structure; and one end of the second sub-slit portion away from the electrode connecting portion is a closed structure.

7. The array substrate according to any one of claims 4 to 6, wherein: The sub-pixel electrode further includes a second slit extending along the second direction, and an extension line of the second slit passes through a central area of ​​the sub-pixel electrode.

8. The array substrate according to claim 7, wherein: The electrode pattern block includes: a first pattern portion extending along the second direction, and two second pattern portions connected to the first pattern portion; the two second pattern portions are respectively located on both sides of the first pattern portion along the first direction; The second slit is located between the first pattern portion and the second pattern portion.

9. The array substrate according to claim 8, wherein: The electrode pattern block further includes: a pattern connecting portion located between the first pattern portion and the second pattern portion; the first pattern portion and the second pattern portion are electrically connected via the pattern connecting portion.

10. The array substrate according to claim 9, wherein: There are two pattern connecting portions between the first pattern portion and the second pattern portion, the two pattern connecting portions are respectively located at two end positions of the outer edge of the second pattern portion along the second direction, and connect the second pattern portion and the first pattern portion at the end positions; The second slit is located between two of the pattern connecting portions.

11. The array substrate according to claim 9, wherein: A pattern connecting portion is provided between the first pattern portion and the second pattern portion, the pattern connecting portion is connected to a middle position of an outer edge of the second pattern portion along the second direction, and connects the second pattern portion and the first pattern portion at the middle position; The second slit is located between the first pattern portion and the second pattern portion and located on both sides of the pattern connecting portion along the second direction.

12. The array substrate according to any one of claims 1 to 11, wherein: The array substrate further includes: a first common wiring located on one side of the gate line, and a switching electrode; an orthographic projection of the switching electrode on the substrate and an orthographic projection of the first common wiring on the substrate have an overlapping area; The array substrate further includes a pixel circuit; the pixel circuit includes a first transistor, a second transistor, and a third transistor. The first transistor includes: a first transistor control electrode, a first transistor first electrode, and a first transistor second electrode; the second transistor includes: a second transistor control electrode, a second transistor first electrode, and a second transistor second electrode; the third transistor includes: a third transistor control electrode, a third transistor first electrode, and a third transistor second electrode; The control electrode of the first transistor multiplexes with the gate line, the first electrode of the first transistor multiplexes with the data line; the second electrode of the first transistor is electrically connected to the second sub-pixel electrode; The control electrode of the second transistor reuses the gate line, the first electrode of the second transistor reuses the first electrode of the first transistor; the second electrode of the second transistor is electrically connected to the first sub-pixel electrode; The control electrode of the third transistor reuses the gate line, the first electrode of the third transistor reuses the second electrode of the second transistor; and the second electrode of the third transistor is electrically connected to the switching electrode.

13. The array substrate according to claim 12, wherein: The orthographic projection of the second sub-pixel electrode on the substrate overlaps with the orthographic projections of the gate line and the first common wiring on the substrate.

14. The array substrate according to any one of claims 1 to 11, wherein: The array substrate further includes: a pixel circuit; the pixel circuit includes: a first transistor, a second transistor, a third transistor, and a first signal line; The first transistor includes: a first transistor control electrode, a first transistor first electrode, and a first transistor second electrode; the second transistor includes: a second transistor control electrode, a second transistor first electrode, and a second transistor second electrode; the third transistor includes: a third transistor control electrode, a third transistor first electrode, and a third transistor second electrode; The control electrode of the first transistor multiplexes with the gate line, the first electrode of the first transistor multiplexes with the data line; the second electrode of the first transistor is electrically connected to the second sub-pixel electrode; The control electrode of the second transistor reuses the gate line, the first electrode of the second transistor reuses the first electrode of the first transistor; the second electrode of the second transistor is electrically connected to the first sub-pixel electrode; The control electrode of the third transistor multiplexes with the gate line, the first electrode of the third transistor multiplexes with the second electrode of the second transistor; and the second electrode of the third transistor multiplexes with the first signal line.

15. A display panel, wherein: The invention comprises the array substrate according to any one of claims 1 to 14, and further comprises an opposite substrate arranged opposite to the array substrate; the opposite substrate comprises: a common electrode layer.

16. A display device, wherein: Comprising the display panel as claimed in claim 15.

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