Display panel and display device

Abstract

The present application discloses a display panel and a display device. A partition structure comprises a first partition layer and a second partition layer; the minimum opening area of each second sub-opening in the second partition layer is larger than the minimum opening area of each first sub-opening in the first partition layer; a first light-emitting layer and a charge generation layer are partitioned at the partition structure; a second electrode layer is continuously arranged at the partition structure; and the opening area of the side of each first sub-opening away from the substrate is larger than the opening area of the side of said first sub-opening close to the substrate.

Description

Display panel and display device Technical Field

[0001] The present application relates to the field of display technology, and in particular to a display panel and a display device. Background Art

[0002] Organic Light-Emitting Diode (OLED) devices offer broad application prospects due to their low power consumption, fast response speed, and wide viewing angle. OLED display technology is currently widely used in a variety of electronic products, ranging from small devices like smart bracelets, smart watches, smartphones, and tablets to large devices like laptops, desktop computers, and televisions. To further improve the efficiency and lifespan of OLED devices, tandem display technology has emerged. Tandem devices offer higher brightness, longer lifespan, and lower power consumption, and are currently experiencing strong market demand.

[0003] At present, a charge generation layer is often added to stacked OLED devices to improve device performance. However, the charge generation layer has a strong ability to generate and separate electrons, which can easily lead to the phenomenon of stealing light between adjacent pixels. Generally, the stealing light phenomenon between adjacent pixels is avoided by isolating the charge generation layer. However, when isolating the charge generation layer, it is easy to cause a short circuit between the charge generation layer and the cathode at the isolation point. SUMMARY OF THE INVENTION

[0004] Embodiments of the present application provide a display panel and a display device, which can reduce the probability of hidden light in the display panel and reduce the probability of short circuit between the charge generation layer and the second electrode layer.

[0005] An embodiment of the present application provides a display panel, comprising:

[0006] substrate;

[0007] A first electrode layer is provided on one side of the substrate, wherein the first electrode layer comprises a plurality of first electrodes arranged at intervals;

[0008] a pixel definition layer, disposed on a side of the first electrode layer away from the substrate, the pixel definition layer comprising: a plurality of pixel openings disposed corresponding to the first electrodes and a first opening disposed between adjacent pixel openings;

[0009] a partition structure disposed between the substrate and the pixel definition layer and corresponding to the first opening; the partition structure comprising: a first partition layer and a second partition layer stacked together, the second partition layer being located between the substrate and the first partition layer, the first partition layer comprising a first sub-opening corresponding to the first opening, the second partition layer comprising a second sub-opening corresponding to the first sub-opening, the minimum opening area of ​​the second sub-opening being greater than the minimum opening area of ​​the first sub-opening, and the second sub-opening being connected to the first opening through the first sub-opening;

[0010] A first light-emitting layer is provided on a side of the pixel definition layer away from the substrate and is disconnected at the partition structure;

[0011] a charge generation layer, disposed on a side of the first light-emitting layer away from the pixel definition layer and disconnected from the partition structure;

[0012] a second light-emitting layer, disposed on a side of the charge generation layer away from the first light-emitting layer;

[0013] a second electrode layer, disposed on a side of the second light-emitting layer away from the substrate, the second electrode layer being continuously disposed at the partition structure;

[0014] The opening area of ​​the first sub-opening at a side away from the substrate is larger than the opening area of ​​the first sub-opening at a side close to the substrate.

[0015] In accordance with the above-mentioned purpose of the present application, an embodiment of the present application further provides a display device, wherein the display device includes a display panel, and the display panel includes:

[0016] substrate;

[0017] A first electrode layer is provided on one side of the substrate, wherein the first electrode layer comprises a plurality of first electrodes arranged at intervals;

[0018] a pixel definition layer, disposed on a side of the first electrode layer away from the substrate, the pixel definition layer comprising: a plurality of pixel openings disposed corresponding to the first electrodes and a first opening disposed between adjacent pixel openings;

[0019] a partition structure disposed between the substrate and the pixel definition layer and corresponding to the first opening; the partition structure comprising: a first partition layer and a second partition layer stacked together, the second partition layer being located between the substrate and the first partition layer, the first partition layer comprising a first sub-opening corresponding to the first opening, the second partition layer comprising a second sub-opening corresponding to the first sub-opening, the minimum opening area of ​​the second sub-opening being greater than the minimum opening area of ​​the first sub-opening, and the second sub-opening being connected to the first opening through the first sub-opening;

[0020] A first light-emitting layer is provided on a side of the pixel definition layer away from the substrate and is disconnected at the partition structure;

[0021] a charge generation layer, disposed on a side of the first light-emitting layer away from the pixel definition layer and disconnected from the partition structure;

[0022] a second light-emitting layer, disposed on a side of the charge generation layer away from the first light-emitting layer;

[0023] a second electrode layer, disposed on a side of the second light-emitting layer away from the substrate, the second electrode layer being continuously disposed at the partition structure;

[0024] The opening area of ​​the first sub-opening at a side away from the substrate is larger than the opening area of ​​the first sub-opening at a side close to the substrate. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] The following detailed description of the specific embodiments of the present application in conjunction with the accompanying drawings will make the technical solutions and other beneficial effects of the present application apparent.

[0026] FIG1 is a schematic structural diagram of a display panel in the related art;

[0027] FIG2 is an equivalent circuit diagram of a light emitting device in the related art;

[0028] FIG3 is another equivalent circuit diagram of a light emitting device in the related art;

[0029] FIG4 is a schematic structural diagram of a display panel provided in an embodiment of the present application;

[0030] FIG5 is a schematic diagram of an enlarged structure of point A in FIG4 provided in an embodiment of the present application;

[0031] FIG6 is a schematic diagram showing parameters of a partition structure in a display panel provided in an embodiment of the present application;

[0032] FIG7 is a schematic diagram of the structure of the first light-emitting layer and the second light-emitting layer in the display panel provided in an embodiment of the present application;

[0033] FIG8 is another enlarged structural diagram of point A in FIG4 provided in an embodiment of the present application;

[0034] FIG9 is another enlarged structural schematic diagram of point A in FIG4 provided in an embodiment of the present application. Modes for Carrying Out the Invention

[0035] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the embodiments described are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without making creative efforts are within the scope of protection of this application.

[0036] The disclosure below provides many different embodiments or examples for realizing different structures of the present application. In order to simplify the disclosure of the present application, the components and settings of specific examples are described below. Of course, they are merely examples and are not intended to limit the present application. In addition, the present application may repeat reference numbers and / or reference letters in different examples, and such repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the various embodiments and / or settings discussed. In addition, the present application provides examples of various specific processes and materials, but those of ordinary skill in the art will appreciate the application of other processes and / or the use of other materials.

[0037] In conjunction with Figures 1, 2 and 3, the display panel provided by the related art includes an OLED light-emitting device, and the OLED light-emitting device includes an anode 1, a hole transport layer 2 arranged on the anode 1, a first light-emitting layer 3 arranged on the hole transport layer 2, an n-type charge generation layer 4 arranged on the first light-emitting layer 3, a p-type charge generation layer 5 arranged on the n-type charge generation layer 4, a second light-emitting layer 6 arranged on the p-type charge generation layer 5, and a cathode layer 7 arranged on the second light-emitting layer 6; since the n-type charge generation layer 4 has a strong ability to generate and separate electrons, it is easy to conduct This causes the phenomenon of stealth lighting between adjacent pixels. Therefore, in the related art, an undercut structure is often used to isolate the n-type charge generation layer 4 between adjacent pixels to reduce the probability of stealth lighting. For example, the suspended part in the undercut structure is prepared as a side waist-shaped structure with an inverted trapezoid, which is more conducive to isolating the first light-emitting layer 3 and the n-type charge generation layer 4. However, the isolation process is also prone to short-circuiting between the n-type charge generation layer 4 and the cathode layer 7, thereby making the second light-emitting layer 6 unable to play its due light-emitting effect, reducing the light-emitting efficiency and affecting the display effect of the display panel.

[0038] 4 and 5 , an embodiment of the present application provides a display panel, which includes a substrate 10 , a first electrode layer 620 , a pixel definition layer 20 , a partition structure 30 , a first light-emitting layer 41 , a charge generation layer 50 , a second light-emitting layer 42 and a second electrode layer 61 .

[0039] The first electrode layer 620 is disposed on the substrate 10 , and the first electrode layer 620 includes a plurality of first electrodes 62 disposed at intervals.

[0040] The pixel definition layer 20 is disposed on a side of the first electrode layer 620 away from the substrate 10 . The pixel definition layer 20 includes a plurality of pixel openings 202 corresponding to the first electrodes 62 and a first opening 201 disposed between adjacent pixel openings 202 .

[0041] The partition structure 30 is arranged between the substrate 10 and the pixel definition layer 20, and is arranged corresponding to the first opening 201. The partition structure 30 includes a first partition layer 31 and a second partition layer 32 arranged in a stacked manner. The second partition layer 32 is located between the substrate 10 and the first partition layer 31. The first partition layer 31 includes a first sub-opening 311 arranged corresponding to the first opening 201. The second partition layer 32 includes a second sub-opening 321 arranged corresponding to the first sub-opening 311. The minimum opening area of ​​the second sub-opening 321 is larger than the minimum opening area of ​​the first sub-opening 311. The second sub-opening 321 is connected to the first opening 201 through the first sub-opening 311.

[0042] The first light emitting layer 41 is disposed on a side of the pixel definition layer 20 away from the substrate 10 and is disconnected at the partition structure 30 .

[0043] The charge generation layer 50 is disposed on a side of the first light emitting layer 41 away from the pixel definition layer 20 and is disconnected from the partition structure 30 .

[0044] The second light-emitting layer 42 is provided on a side of the charge generation layer 50 away from the first light-emitting layer 41 .

[0045] The second electrode layer 61 is disposed on a side of the second light emitting layer 42 away from the substrate 10 , and the second electrode layer 61 is continuously disposed at the partition structure 30 .

[0046] Furthermore, the opening area of ​​the first sub-opening 311 at the side away from the substrate 10 is larger than the opening area of ​​the first sub-opening 311 at the side close to the substrate 10 .

[0047] During the implementation and application process, the embodiment of the present application designs the opening area of ​​the first sub-opening 311 of the first partition layer 31 so that the opening area of ​​the first sub-opening 311 on the side away from the substrate 10 is larger than the opening area of ​​the first sub-opening 311 on the side close to the substrate 10. The charge generation layer 50 can be isolated, and the second light-emitting layer 42 is located on the side of the charge generation layer 50 away from the first light-emitting layer 41, while the second electrode layer 61 continuously covers the side of the second light-emitting layer 42 away from the substrate 10. In addition, on the basis of solving the problem of stealing light, the probability of short circuit between the charge generation layer 50 and the second electrode layer 61 can also be reduced, thereby improving the yield rate and display effect of the display panel.

[0048] In one embodiment of the present application, the second light-emitting layer is continuously provided at the partition structure.

[0049] In one embodiment of the present application, the angle between the inner wall of the first sub-opening and the first direction is less than 90°, the first direction is the direction in which the center of the first sub-opening is close to the inner wall of the first sub-opening, and the first direction is parallel to the substrate.

[0050] In one embodiment of the present application, the inner wall of the first sub-opening includes multiple sub-surfaces, and the angle between the sub-surface on the side away from the center of the first sub-opening and the first direction is smaller than the angle between the sub-surface on the side close to the center of the first sub-opening and the first direction.

[0051] In one embodiment of the present application, the plurality of sub-surfaces include a first sub-surface close to a center side of the first sub-opening and a second sub-surface away from a center side of the first sub-opening, and the first sub-surface is connected to the second sub-surface;

[0052] The first light-emitting layer includes a first recess provided on a side of the first sub-surface close to the center of the first sub-opening, and a second recess provided at a junction of the first sub-surface and the second sub-surface.

[0053] In one embodiment of the present application, the charge generation layer includes a first sub-portion located in the first sub-opening, a second sub-portion located on a side of an inner wall of the first sub-opening away from the substrate, and a third sub-portion located on a side of the second sub-portion away from the center of the first sub-opening;

[0054] Wherein, the first sub-portion and the second sub-portion are spaced apart in the first recess;

[0055] The second sub-portion and the third sub-portion are connected, or the second sub-portion and the third sub-portion are spaced apart in the second recess.

[0056] In one embodiment of the present application, the second light-emitting layer includes a third recess and a fourth recess, the third recess and the first recess are aligned along a second direction, and the fourth recess and the second recess are aligned along the second direction, and the second direction is the direction in which the substrate is close to the pixel definition layer.

[0057] In one embodiment of the present application, the second electrode layer continuously covers the third recess and the fourth recess.

[0058] In one embodiment of the present application, an angle between an inner wall of the first sub-opening and the first direction is greater than or equal to 10° and less than or equal to 70°.

[0059] In one embodiment of the present application, the sum of the thickness of the first partition layer and the thickness of the second partition layer is greater than or equal to the sum of the thickness of the first light-emitting layer and the thickness of the charge generation layer, and less than or equal to the sum of the thickness of the first light-emitting layer, the thickness of the charge generation layer, and the thickness of the second light-emitting layer.

[0060] In one embodiment of the present application, the partition structure further includes a third partition layer, which is disposed between the second partition layer and the substrate and is stacked with the second partition layer.

[0061] Specifically, please continue to refer to Figures 1 and 2. The display panel includes a substrate 10, a driving circuit layer 70 arranged on the substrate 10, a pixel definition layer 20 arranged on the side of the driving circuit layer 70 away from the substrate 10, and a light-emitting device layer arranged on the side of the pixel definition layer 20 away from the driving circuit layer 70.

[0062] In one embodiment, the display panel further includes a light extraction layer and an encapsulation layer, which are not shown in the figure, and are arranged on a side of the light emitting device layer away from the pixel definition layer 20 .

[0063] In one embodiment, the driving circuit layer 70 includes a buffer layer 71 disposed on the substrate 10, a first insulating layer 72 disposed on the buffer layer 71, a second insulating layer 73 disposed on the first insulating layer 72, a first gate insulating layer 74 disposed on the second insulating layer 73, a second gate insulating layer 75 disposed on the first gate insulating layer 74, a first organic planarizing layer 76 disposed on the second gate insulating layer 75, and a second organic planarizing layer 77 disposed on the first organic planarizing layer 76; further, the driving circuit layer 70 also includes a thin film transistor 78 disposed on the substrate 10, the thin film transistor 78 including an active layer disposed on the first insulating layer 72 and covered by the second insulating layer 73, a first gate disposed on the second insulating layer 73 and covered by the first gate insulating layer 74, a first gate disposed on the first gate insulating layer 74, and a second organic planarizing layer 77 disposed on the first organic planarizing layer 76. A second gate on the gate insulating layer 74 and covered by the second gate insulating layer 75, a source and a drain arranged on the second gate insulating layer 75 and covered by the first organic flat layer 76; in addition, the driving circuit layer 70 also includes a light-shielding layer arranged between the active layer and the substrate 10 and a signal line connected to the light-shielding layer and used to provide a stable voltage for the light-shielding layer, and the light-shielding layer is located on the buffer layer 71 and covered by the first insulating layer 72, the signal line is located on the second gate insulating layer 75 and passes through the second gate insulating layer 75, the first gate insulating layer 74, the second insulating layer 73 and the first insulating layer 72 to overlap with the light-shielding layer; further, the driving circuit layer 70 also includes a switching line arranged on the first organic flat layer 76 and overlapped with the drain, and the switching line is used to connect the drain with the light-emitting device layer to realize signal transmission.

[0064] The light-emitting device layer includes a first electrode layer 620 arranged on the second organic planar layer 77, and the first electrode layer 620 includes a plurality of first electrodes 62. The pixel definition layer 20 is arranged on the second organic planar layer 77, and the pixel definition layer 20 includes a plurality of pixel openings 202. One pixel opening 202 is arranged corresponding to one first electrode 62, and the first electrode 62 can be connected to the drain.

[0065] In the embodiment of the present application, the light-emitting device layer is a stacked light-emitting device, that is, the light-emitting device layer has multiple light-emitting layers, which can effectively improve the luminous efficiency and life of the light-emitting device layer.

[0066] In one embodiment, the light-emitting device layer also includes a first light-emitting layer 41 arranged on the pixel definition layer 20, a charge generation layer 50 arranged on the side of the first light-emitting layer 41 away from the pixel definition layer 20, a second light-emitting layer 42 arranged on the side of the charge generation layer 50 away from the first light-emitting layer 41, and a second electrode layer 61 arranged on the side of the second light-emitting layer 42 away from the charge generation layer 50.

[0067] It should be noted that the first light-emitting layer 41 may include a hole injection layer, a hole transport layer and a first organic light-emitting layer stacked in sequence in the direction from the first electrode 62 to the second electrode layer 61, and the second light-emitting layer 42 may include a second organic light-emitting layer, an electron transport layer and an electron injection layer stacked in sequence in the direction from the first electrode 62 to the second electrode layer 61; wherein the first organic light-emitting layer and the second organic light-emitting layer are arranged corresponding to multiple pixel openings 202, and the hole injection layer, the hole transport layer, the electron transport layer and the electron injection layer can cover the side of the pixel definition layer 20 away from the driving circuit layer 70.

[0068] Furthermore, a first opening 201 is defined in the pixel definition layer 20 , and the first opening 201 is located between adjacent pixel openings 202 .

[0069] In an embodiment of the present application, the display panel also includes a partition structure 30 arranged on the side of the driving circuit layer 70 away from the substrate 10, and the partition structure 30 can be arranged on the same layer as the first electrode 62, that is, the partition structure 30 is located on the surface of the second organic flat layer 77 away from the first organic flat layer 76, and the partition structure 30 is arranged corresponding to the first opening 201.

[0070] The partition structure 30 includes a first partition layer 31 and a second partition layer 32 that are stacked, and the second partition layer 32 is located between the first partition layers 31; wherein, the first partition layer 31 includes a first sub-opening 311 corresponding to the first opening 201, and the second partition layer 32 includes a second sub-opening 321 corresponding to the first opening 201, the minimum opening area of ​​the second sub-opening 321 is larger than the minimum opening area of ​​the first sub-opening 311, and the second sub-opening 321 is connected to the first opening 201 through the first sub-opening 311; that is, the inner wall of the first sub-opening 311 protrudes from the inner wall of the second sub-opening 321 to form an undercut structure at the first sub-opening 311 and the second sub-opening 321, that is, an undercut structure surrounding the first sub-opening 311 and the second sub-opening 321 is formed in the partition structure 30.

[0071] In which, the opening area of ​​the first sub-opening 311 on the side away from the substrate 10 is larger than the opening area of ​​the first sub-opening 311 on the side close to the substrate 10; further, the angle between the inner wall 310 of the first sub-opening 311 and the first direction X is less than 90°, the first direction X is the direction in which the center of the first sub-opening 311 is close to the inner wall 310 of the first sub-opening 311, and the first direction X is parallel to the substrate 10; in one embodiment, the inner wall 310 of the first sub-opening 311 is in the shape of a side waist of a right trapezoid.

[0072] The first light-emitting layer 41 and the charge generation layer 50 are both disconnected at the partition structure 30, while the second light-emitting layer 42 and the second electrode layer 61 are both continuously arranged at the partition structure 30; that is, in the embodiment of the present application, the inner wall 310 of the first partition layer 31 is designed so that the opening area of ​​the first sub-opening 311 away from the substrate 10 is larger than the opening area of ​​the first sub-opening 311 close to the substrate 10, that is, the angle between the inner wall 310 of the first sub-opening 311 and the first direction X is less than 90°, which can not only isolate the charge generation layer 50, but also make the second light-emitting layer 42 and the second electrode layer 61 continuously cover the side of the charge generation layer 50 away from the substrate 10, and further, on the basis of solving the phenomenon of stealing light, the probability of short circuit between the charge generation layer 50 and the second electrode layer 61 can be reduced, thereby improving the yield rate and display effect of the display panel.

[0073] It should be noted that, in the embodiment of the present application, the charge generation layer 50 includes at least an n-type charge generation layer. Since the n-type charge generation layer is formed by doping an electron transport material with an n-dopant (n dopant), it has a higher electron mobility. Therefore, in the embodiment of the present application, the n-type charge generation layer is isolated to improve the phenomenon of adjacent pixel elements in the display panel being brightly lit.

[0074] In one embodiment, the charge generation layer 50 includes an n-type charge generation layer, and the second light-emitting layer 42 includes a p-type charge generation layer located between the n-type charge generation layer and the second organic light-emitting layer. In this embodiment, the n-type charge generation layer is isolated.

[0075] In another embodiment, the charge generation layer 50 includes an n-type charge generation layer and a p-type charge generation layer. In this embodiment, both the n-type charge generation layer and the p-type charge generation layer are isolated.

[0076] Please refer to Figures 4, 5 and 6. In one embodiment, the angle c between the inner wall 310 of the first sub-opening 311 and the first direction X is greater than or equal to 10° and less than or equal to 70°; further preferably, the angle c between the inner wall 310 of the first sub-opening 311 and the first direction X is greater than or equal to 50° and less than or equal to 60°.

[0077] Furthermore, the sum of the thickness a of the first isolation layer 31 and the thickness b of the second isolation layer 32 is greater than or equal to the sum of the thickness of the first light-emitting layer 41 and the thickness of the charge generation layer 50, and is less than or equal to the sum of the thickness of the first light-emitting layer 41, the thickness of the charge generation layer 50, and the thickness of the second light-emitting layer 42; thereby, the first light-emitting layer 41 and the charge generation layer 50 can be effectively isolated, and the second light-emitting layer 42 and the second electrode layer 61 can be avoided from being isolated, which effectively ensures that on the basis of improving the phenomenon of stealing light between adjacent pixels, the probability of short circuit between the charge generation layer 50 and the second electrode layer 61 is also reduced.

[0078] 4 , 5 , and 7 , in one embodiment, the light-emitting device layer includes a first pixel, a second pixel, and a third pixel, wherein the first light-emitting layer 41 includes a first light-emitting sublayer 411 corresponding to the first pixel, a second light-emitting sublayer 412 corresponding to the second pixel, and a third light-emitting sublayer 413 corresponding to the third pixel; the second light-emitting layer 42 includes a fourth light-emitting sublayer 421 corresponding to the first pixel, a fifth light-emitting sublayer 422 corresponding to the second pixel, and a sixth light-emitting sublayer 423 corresponding to the third pixel; and the thickness of the first light-emitting sublayer 411 is greater than the thickness of the second light-emitting sublayer 412, the thickness of the second light-emitting sublayer 412 is greater than the thickness of the third light-emitting sublayer 413, and the thickness of the fourth light-emitting sublayer 421 is greater than the thickness of the fifth light-emitting sublayer 422. The thickness of the fifth light-emitting sublayer 422 is greater than the thickness of the sixth light-emitting sublayer 423; therefore, in an embodiment of the present application, in order to isolate the first pixel, the third pixel and the charge generation layer 50 corresponding to the third pixel, the sum of the thickness a of the first isolation layer 31 and the thickness b of the second isolation layer 32 needs to be greater than or equal to the sum of the thickness of the first light-emitting sublayer 411 corresponding to the first pixel and the thickness of the charge generation layer 50. At the same time, in order to avoid isolation of the first pixel, the third pixel and the second light-emitting layer 42 corresponding to the third pixel, the sum of the thickness a of the first isolation layer 31 and the thickness b of the second isolation layer 32 needs to be less than or equal to the sum of the thickness of the third light-emitting sublayer 413 corresponding to the third pixel, the thickness of the charge generation layer 50, and the thickness of the sixth light-emitting sublayer 423.

[0079] In one embodiment, the first pixel is a red pixel, the second pixel is a green pixel, and the third pixel is a blue pixel.

[0080] In one embodiment, the thickness b of the first partition layer 31 is greater than or equal to 0.01 microns and less than or equal to 0.2 microns, and the distance d from one end of the inner wall 310 of the first sub-opening 311 close to the center of the first sub-opening 311 to the side wall of the first opening 201 along the first direction X is greater than or equal to 0.1 microns, so as to reduce the impact of process precision deviation on the formation of the partition structure 30.

[0081] In one embodiment, the partition structure 30 also includes a third partition layer 33 arranged between the second partition layer 32 and the substrate 10 and stacked with the second partition layer 32, and the third partition layer 33 is located at the bottom of the second sub-opening 321 and does not penetrate the third partition layer 33. In one embodiment, the second sub-opening 321 can pass through part of the third partition layer 33. Since the partition structure 30 needs to be etched to form the second opening 301 and the bottom cut structure, in the embodiment of the present application, a third partition layer 33 is added between the second partition layer 32 and the driving circuit layer 70 as an etching stop layer to avoid damage to the driving circuit layer 70 during the etching process.

[0082] In one embodiment, the material of the first isolation layer 31 is the same as the material of the third isolation layer 33, and the material of the first isolation layer 31 is different from the material of the second isolation layer 32. The etching selectivity between the materials can be used to obtain an undercut structure. For example, the material of the first isolation layer 31 and the material of the third isolation layer 33 can include silicon oxide, and the material of the second isolation layer 32 can include silicon nitride.

[0083] In one embodiment of the present application, please refer to Figures 4 and 5. In this embodiment, the inner wall 310 of the first sub-opening 311 is a plane, and the first light-emitting layer 41 is separated on the side of the inner wall 310 of the first sub-opening 311 close to the center of the first sub-opening 311, and a depression is formed; then the charge generation layer 50 is separated at the depression, that is, it is also separated on the side of the inner wall 310 of the first sub-opening 311 close to the center of the first sub-opening 311.

[0084] Among them, the second light-emitting layer 42 and the second electrode layer 61 both continuously cover the side of the inner wall 310 of the first sub-opening 311 close to the first sub-opening 311 and the inner wall 310 of the first sub-opening 311, and the second light-emitting layer 42 is separated between the second electrode layer 61 and the charge generation layer 50, which can effectively avoid short circuit between the second electrode layer 61 and the charge generation layer 50.

[0085] In another embodiment of the present application, please refer to Figures 4 and 8, the inner wall 310 of the first sub-opening 311 includes multiple sub-surfaces, and the angle between the sub-surface on the side away from the center of the first sub-opening 311 and the first direction X is smaller than the angle between the sub-surface on the side close to the center of the first sub-opening 311 and the first direction X; that is, the inner wall 310 of the first sub-opening 311 is formed with multiple sub-surfaces with different slope angles, and the slope angles of the multiple sub-surfaces increase along the direction of the inner wall of the first sub-opening 311 close to the center of the first sub-opening 311.

[0086] Specifically, the plurality of sub-surfaces include a first sub-surface 3101 close to the center of the first sub-opening 311 and a second sub-surface 3102 away from the center of the first sub-opening 311 . The first sub-surface 3101 is connected to the second sub-surface 3102 .

[0087] Among them, the first light-emitting layer 41 includes a first recess 4101 arranged on the center side of the first sub-surface 3101 close to the first sub-opening 311, and a second recess 4102 arranged at the connection between the first sub-surface 3101 and the second sub-surface 3102, and the first light-emitting layer 41 is separated at the first recess 4101, and the first light-emitting layer 41 is continuously arranged at the second recess 4102.

[0088] The charge generation layer 50 includes a first sub-portion 51 located in the first sub-opening 311, a second sub-portion 52 located on the side of the inner wall 310 of the first sub-opening 311 away from the substrate 10, and a third sub-portion 53 located on the side of the second sub-portion 52 close to the center away from the first sub-opening 311; wherein, the first sub-portion 51 and the second sub-portion 52 are spaced apart at the first recess 4101, and the second sub-portion 52 and the third sub-portion 53 are connected.

[0089] It is understandable that the embodiment of the present application is described by taking two sub-surfaces as an example, and the number of sub-surfaces can also be more, such as three, four or five.

[0090] The second light-emitting layer 42 includes a third recess 4201 and a fourth recess 4202. The third recess 4201 and the first recess 4101 are aligned along the second direction Y, and the fourth recess 4202 and the second recess 4102 are aligned along the second direction Y. The second direction Y is the direction in which the substrate 10 approaches the pixel definition layer 20. The second electrode layer 61 continuously covers the third recess 4201 and the fourth recess 4202.

[0091] As mentioned above, in the implementation of the present application, the inner wall 310 of the first sub-opening 311 is designed so that the inner wall 310 of the first sub-opening 311 forms multiple sub-surfaces with different slope angles, thereby allowing the first light-emitting layer 41 and the second light-emitting layer 42 to form a concave and convex morphology above the inner wall 310 of the first sub-opening 311, thereby increasing the extension path of the second electrode layer 61 at the inner wall 310 of the first sub-opening 311, and increasing the resistance of the second electrode layer 61 at the inner wall 310 of the first sub-opening 311, thereby reducing the probability of short circuit between the second electrode layer 61 and the charge generation layer 50.

[0092] In another embodiment of the present application, please refer to Figures 4 and 9. The difference between this embodiment and the embodiment shown in Figure 8 is that the second sub-portion 52 and the third sub-portion 53 are spaced apart at the second recess 4102, that is, in addition to being isolated at one end of the inner wall 310 of the first sub-opening 311 close to the center of the first sub-opening 311, the charge generation layer 50 can also be isolated again above the inner wall 310 of the first sub-opening 311, and the number of times it is isolated again can be determined according to the number of sub-surfaces, which is not limited here.

[0093] As mentioned above, in the implementation of the present application, the inner wall 310 of the first sub-opening 311 is designed so that the inner wall 310 of the first sub-opening 311 forms multiple sub-surfaces with different slope angles, thereby allowing the first light-emitting layer 41 and the second light-emitting layer 42 to form a concave and convex film above the inner wall 310 of the first sub-opening 311, thereby increasing the extension path of the second electrode layer 61 at the inner wall 310 of the first sub-opening 311, and increasing the resistance of the second electrode layer 61 at the inner wall 310 of the first sub-opening 311, so as to reduce the probability of short circuit between the second electrode layer 61 and the charge generation layer 50; in addition, in this embodiment, the charge generation layer 50 can be further isolated above the inner wall 310 of the first sub-opening 311, thereby further reducing the probability of short circuit between the second electrode layer 61 and the charge generation layer 50, thereby improving the light extraction efficiency and display effect of the display panel.

[0094] In addition, an embodiment of the present application further provides a display device, which includes the display panel described in the above embodiment.

[0095] It can be understood that, since the display device includes the display panel described in the above embodiment, the display device has the same beneficial effects as the display panel described in the above embodiment, which will not be described in detail here.

[0096] In the above embodiments, the description of each embodiment has its own focus. For parts that are not described in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0097] The above is a detailed introduction to a display panel and a display device provided in the embodiments of the present application. Specific examples are used herein to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the technical solutions and core ideas of the present application. Ordinary technicians in this field should understand that they can still modify the technical solutions recorded in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. These modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A display panel comprising: substrate; A first electrode layer is provided on one side of the substrate, wherein the first electrode layer comprises a plurality of first electrodes arranged at intervals; a pixel definition layer, disposed on a side of the first electrode layer away from the substrate, the pixel definition layer comprising: a plurality of pixel openings disposed corresponding to the first electrodes and a first opening disposed between adjacent pixel openings; a partition structure disposed between the substrate and the pixel definition layer and corresponding to the first opening; the partition structure comprising: a first partition layer and a second partition layer stacked together, the second partition layer being located between the substrate and the first partition layer, the first partition layer comprising a first sub-opening corresponding to the first opening, the second partition layer comprising a second sub-opening corresponding to the first sub-opening, the minimum opening area of ​​the second sub-opening being greater than the minimum opening area of ​​the first sub-opening, and the second sub-opening being connected to the first opening through the first sub-opening; A first light-emitting layer is provided on a side of the pixel definition layer away from the substrate and is disconnected at the partition structure; a charge generation layer, disposed on a side of the first light-emitting layer away from the pixel definition layer and disconnected from the partition structure; a second light-emitting layer, disposed on a side of the charge generation layer away from the first light-emitting layer; a second electrode layer, disposed on a side of the second light-emitting layer away from the substrate, the second electrode layer being continuously disposed at the partition structure; The opening area of ​​the first sub-opening at a side away from the substrate is larger than the opening area of ​​the first sub-opening at a side close to the substrate.

2. The display panel according to claim 1, wherein The second light-emitting layer is continuously disposed at the partition structure.

3. The display panel according to claim 1, wherein: An angle between the inner wall of the first sub-opening and a first direction is less than 90°, the first direction is a direction in which the center of the first sub-opening is close to the inner wall of the first sub-opening, and the first direction is parallel to the substrate.

4. The display panel according to claim 3, wherein: The inner wall of the first sub-opening includes a plurality of sub-surfaces, and the angle between the sub-surface away from the center of the first sub-opening and the first direction is smaller than the angle between the sub-surface close to the center of the first sub-opening and the first direction.

5. The display panel according to claim 3, wherein: The plurality of sub-surfaces include a first sub-surface close to a center side of the first sub-opening and a second sub-surface away from a center side of the first sub-opening, and the first sub-surface is connected to the second sub-surface; The first light-emitting layer includes a first recess provided on a side of the first sub-surface close to the center of the first sub-opening, and a second recess provided at a junction of the first sub-surface and the second sub-surface. The display panel according to claim 5 , wherein: The charge generation layer includes a first sub-portion located in the first sub-opening, a second sub-portion located on a side of an inner wall of the first sub-opening away from the substrate, and a third sub-portion located on a side of the second sub-portion away from the center of the first sub-opening; Wherein, the first sub-portion and the second sub-portion are spaced apart in the first recess; The second sub-portion and the third sub-portion are connected, or the second sub-portion and the third sub-portion are spaced apart in the second recess.

7. The display panel according to claim 5, wherein: The second light-emitting layer includes a third recess and a fourth recess, the third recess and the first recess are aligned along a second direction, and the fourth recess and the second recess are aligned along the second direction, where the second direction is the direction in which the substrate approaches the pixel definition layer.

8. The display panel according to claim 7, wherein: The second electrode layer continuously covers the third recess and the fourth recess.

9. The display panel according to claim 3, wherein: An included angle between an inner wall of the first sub-opening and the first direction is greater than or equal to 10° and less than or equal to 70°.

10. The display panel according to claim 1, wherein The sum of the thickness of the first partition layer and the thickness of the second partition layer is greater than or equal to the sum of the thickness of the first light-emitting layer and the thickness of the charge generation layer, and less than or equal to the sum of the thickness of the first light-emitting layer, the thickness of the charge generation layer, and the thickness of the second light-emitting layer.

11. The display panel according to claim 1, wherein: The partition structure further includes a third partition layer, which is disposed between the second partition layer and the substrate and stacked with the second partition layer.

12. A display device, comprising a display panel, wherein the display panel comprises: substrate; A first electrode layer is provided on one side of the substrate, wherein the first electrode layer comprises a plurality of first electrodes arranged at intervals; a pixel definition layer, disposed on a side of the first electrode layer away from the substrate, the pixel definition layer comprising: a plurality of pixel openings disposed corresponding to the first electrodes and a first opening disposed between adjacent pixel openings; a partition structure disposed between the substrate and the pixel definition layer and corresponding to the first opening; the partition structure comprising: a first partition layer and a second partition layer stacked together, the second partition layer being located between the substrate and the first partition layer, the first partition layer comprising a first sub-opening corresponding to the first opening, the second partition layer comprising a second sub-opening corresponding to the first sub-opening, the minimum opening area of ​​the second sub-opening being greater than the minimum opening area of ​​the first sub-opening, and the second sub-opening being connected to the first opening through the first sub-opening; A first light-emitting layer is provided on a side of the pixel definition layer away from the substrate and is disconnected at the partition structure; a charge generation layer, disposed on a side of the first light-emitting layer away from the pixel definition layer and disconnected from the partition structure; a second light-emitting layer, disposed on a side of the charge generation layer away from the first light-emitting layer; a second electrode layer, disposed on a side of the second light-emitting layer away from the substrate, the second electrode layer being continuously disposed at the partition structure; The opening area of ​​the first sub-opening at a side away from the substrate is larger than the opening area of ​​the first sub-opening at a side close to the substrate.

13. The display device according to claim 12, wherein: The second light-emitting layer is continuously disposed at the partition structure.

14. The display device according to claim 12, wherein: An angle between the inner wall of the first sub-opening and a first direction is less than 90°, the first direction is a direction in which the center of the first sub-opening is close to the inner wall of the first sub-opening, and the first direction is parallel to the substrate.

15. The display device according to claim 14, wherein The inner wall of the first sub-opening includes a plurality of sub-surfaces, and the angle between the sub-surface away from the center of the first sub-opening and the first direction is smaller than the angle between the sub-surface close to the center of the first sub-opening and the first direction.

16. The display device according to claim 14, wherein: The plurality of sub-surfaces include a first sub-surface close to a center side of the first sub-opening and a second sub-surface away from a center side of the first sub-opening, and the first sub-surface is connected to the second sub-surface; The first light-emitting layer includes a first recess provided on a side of the first sub-surface close to the center of the first sub-opening, and a second recess provided at a junction of the first sub-surface and the second sub-surface.

17. The display device according to claim 16, wherein: The charge generation layer includes a first sub-portion located in the first sub-opening, a second sub-portion located on a side of an inner wall of the first sub-opening away from the substrate, and a third sub-portion located on a side of the second sub-portion away from the center of the first sub-opening; Wherein, the first sub-portion and the second sub-portion are spaced apart in the first recess; The second sub-portion and the third sub-portion are connected, or the second sub-portion and the third sub-portion are spaced apart in the second recess.

18. The display device according to claim 16, wherein: The second light-emitting layer includes a third recess and a fourth recess, the third recess and the first recess are aligned along a second direction, and the fourth recess and the second recess are aligned along the second direction, where the second direction is the direction in which the substrate approaches the pixel definition layer.

19. The display device according to claim 18, wherein The second electrode layer continuously covers the third recess and the fourth recess.

20. The display device according to claim 14, wherein An included angle between an inner wall of the first sub-opening and the first direction is greater than or equal to 10° and less than or equal to 70°.

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