Display panel and manufacturing method therefor, and display device

Abstract

A display panel and a manufacturing method therefor, and a display device. The display panel comprises a substrate, a pixel definition layer, a light-emitting functional layer and a partition structure. The pixel definition layer is located on one side of the substrate. The pixel definition layer is provided with a plurality of pixel openings, and the plurality of pixel openings include a first pixel opening and a second pixel opening arranged adjacent to each other. The light-emitting functional layer is located on the side of the pixel definition layer away from the substrate. The light-emitting functional layer comprises a first light-emitting layer, a charge generation layer and a second light-emitting layer which are sequentially stacked in a direction moving away from the substrate. The partition structure is located between the first pixel opening and the second pixel opening. In the light-emitting functional layer, at least the charge generation layer is disconnected at the partition structure. The surface of the partition structure away from the substrate is closer to the substrate than the surface of the pixel definition layer away from the substrate, or the surface of the partition structure away from the substrate is flush with the surface of the pixel definition layer away from the substrate. The display panel is used for displaying an image.

Description

Display panel, method for manufacturing display panel, and display device

[0001] This application claims priority to Chinese patent application No. 202410370695.6, filed on March 28, 2024, the entire contents of which are incorporated herein by reference. Technical Field

[0002] The present disclosure relates to the field of display technology, and in particular to a display panel, a method for manufacturing a display panel, and a display device. Background Art

[0003] With the continuous development of display technology, display devices have become increasingly ubiquitous in people's lives. Organic Light-Emitting Diode (OLED) display panels, due to their advantages such as self-luminescence, low power consumption, wide viewing angle, fast response speed, and high contrast, are widely used in display devices such as mobile phones, televisions, and laptops. Summary of the Invention

[0004] In one aspect, a display panel is provided, including a substrate, a pixel definition layer, a light-emitting functional layer, and a partition structure.

[0005] The pixel definition layer is located on one side of the substrate and is provided with a plurality of pixel openings, wherein the plurality of pixel openings include a first pixel opening and a second pixel opening which are adjacently arranged.

[0006] The light-emitting functional layer is located on a side of the pixel definition layer away from the substrate. The light-emitting functional layer includes a first light-emitting layer, a charge generation layer and a second light-emitting layer stacked in sequence in a direction away from the substrate.

[0007] The partition structure is located between the first pixel opening and the second pixel opening. In the light-emitting functional layer, at least the charge generation layer is disconnected at the partition structure.

[0008] The partition structure is away from the surface of the substrate and closer to the substrate than the surface of the pixel definition layer is away from the substrate; or the partition structure is away from the surface of the substrate and flush with the surface of the pixel definition layer is away from the substrate.

[0009] In some embodiments, the display panel further includes a first dielectric layer, and the first dielectric layer is located between the partition structure and the substrate.

[0010] An opening is provided on a surface of the first dielectric layer away from the substrate, and at least a portion of the partition structure is located in the opening.

[0011] In some embodiments, the first dielectric layer is farther away from the surface of the substrate and closer to the substrate than the partition structure is farther away from the surface of the substrate.

[0012] In some embodiments, a side of the partition structure close to the first pixel opening is provided with an undercut structure; and / or a side of the partition structure close to the second pixel opening is provided with an undercut structure.

[0013] The undercut structure is located in the opening, and a distance is provided between the undercut structure and a sidewall of the opening.

[0014] In the light-emitting functional layer, at least the charge generation layer is disconnected at the undercut structure.

[0015] In some embodiments, an undercut structure is provided on a side of the partition structure close to one of the first pixel opening and the second pixel opening.

[0016] A side of the partition structure close to the other of the first pixel opening and the second pixel opening is at least partially in contact with a sidewall of the opening.

[0017] In some embodiments, a side of the partition structure close to the other of the first pixel opening and the second pixel opening is partially overlapped on a surface of the first dielectric layer away from the substrate.

[0018] In some embodiments, the portion of the partition structure overlapping the surface of the first dielectric layer remote from the substrate includes a first side surface proximate to the other of the first pixel opening and the second pixel opening. The first side surface and the surface of the first dielectric layer remote from the substrate form a first angle, the first angle being toward the opening and being acute.

[0019] In some embodiments, the partition structure has a closed loop shape surrounding the first pixel opening or the second pixel opening.

[0020] In some embodiments, the display panel further comprises a common electrode layer, the common electrode layer being located on a side of the second light-emitting layer away from the substrate, and the common electrode layer being continuous at the partition structure.

[0021] In some embodiments, the partition structure is disposed around the first pixel opening or the second pixel opening, and the partition structure has at least one gap.

[0022] In some embodiments, the display panel further comprises a common electrode layer, the common electrode layer being located on a side of the second light-emitting layer away from the substrate, the common electrode layer being disconnected at the partition structure and continuous at the at least one notch.

[0023] In some embodiments, the partition structure includes a plurality of block-shaped partition portions, and the plurality of partition portions are spaced apart and arranged around the first pixel opening or the second pixel opening.

[0024] In some embodiments, the partition structure comprises a negative photosensitive material.

[0025] In some embodiments, the slope of the sidewall of the opening close to the undercut structure is greater than the slope of the sidewall of the opening away from the undercut structure.

[0026] In some embodiments, a depth of the opening is less than a thickness of the first dielectric layer.

[0027] In another aspect, a method for preparing a display panel is provided, comprising the following steps:

[0028] A partition structure is formed on the substrate.

[0029] A pixel definition layer is formed on the substrate having the partition structure. The pixel definition layer has a plurality of pixel openings, including a first pixel opening and a second pixel opening disposed adjacent to each other, with the partition structure positioned between the first pixel opening and the second pixel opening. The partition structure is distal to the substrate surface and closer to the substrate than the surface of the pixel definition layer distal to the substrate; alternatively, the partition structure is distal to the substrate surface and flush with the surface of the pixel definition layer distal to the substrate.

[0030] A light-emitting functional layer is formed on a side of the pixel definition layer away from the substrate. The light-emitting functional layer includes a first light-emitting layer, a charge generation layer, and a second light-emitting layer stacked in sequence in a direction away from the substrate. In the light-emitting functional layer, at least the charge generation layer is disconnected at the partition structure.

[0031] In some embodiments, before forming the partition structure on the substrate, the method further includes the following steps:

[0032] A first dielectric layer is formed on the substrate.

[0033] An opening is formed on a surface of the first dielectric layer away from the substrate.

[0034] Wherein, at least a portion of the partition structure is located in the opening.

[0035] In some embodiments, forming a partition structure on the substrate includes the following steps:

[0036] A partition layer is formed on a side of the first dielectric layer away from the substrate.

[0037] Exposure treatment is performed on the target area of ​​the partition layer to form a partition structure.

[0038] Part of the target area overlaps with the opening and has a distance from the sidewall of the opening; another part of the target area is located outside the opening and close to the other of the first pixel opening and the second pixel opening.

[0039] In some embodiments, the material of the barrier layer includes a negative photosensitive material.

[0040] In another aspect, a display device is provided, comprising the display panel according to any one of the above embodiments and a cover plate, wherein the cover plate is disposed on the light-emitting side of the display panel. BRIEF DESCRIPTION OF THE DRAWINGS

[0041] To more clearly illustrate the technical solutions of the present disclosure, the following briefly introduces the drawings required for use in some embodiments of the present disclosure. Obviously, the drawings described below are only drawings of some embodiments of the present disclosure, and those skilled in the art can also derive other drawings based on these drawings. Furthermore, the drawings described below are schematic diagrams and are not intended to limit the actual dimensions of the products, actual processes of the methods, actual timing of signals, and the like involved in the embodiments of the present disclosure.

[0042] FIG1 is a structural diagram of a display device according to some embodiments;

[0043] FIG2 is a cross-sectional view of the display device in FIG1 along section line BB;

[0044] FIG3 is a structural diagram of a display panel according to some embodiments;

[0045] FIG4 is a partial plan view of a structure of a display panel according to some embodiments;

[0046] FIG5A is a diagram illustrating a film structure of a pixel layer of a display panel according to some embodiments;

[0047] FIG5B is another film layer structure diagram of a pixel layer of a display panel according to some embodiments;

[0048] FIG6 is a diagram illustrating another film layer structure of a pixel layer of a display panel according to some embodiments;

[0049] FIG7 is another structural diagram of a display panel according to some embodiments;

[0050] FIG8 is another structural diagram of a display panel according to some embodiments;

[0051] FIG9 is a structural diagram of a partition structure of a display panel according to some embodiments;

[0052] FIG10 is another structural diagram of a partition structure of a display panel according to some embodiments;

[0053] FIG11 is another structural diagram of a partition structure of a display panel according to some embodiments;

[0054] FIG12A is another structural diagram of a partition structure of a display panel according to some embodiments;

[0055] FIG12B is another structural diagram of a partition structure of a display panel according to some embodiments;

[0056] FIG12C is another structural diagram of a partition structure of a display panel according to some embodiments;

[0057] FIG13A is another structural diagram of a partition structure of a display panel according to some embodiments;

[0058] FIG13B is another structural diagram of a partition structure of a display panel according to some embodiments;

[0059] FIG13C is a structural diagram of another partition structure of a display panel according to some embodiments;

[0060] FIG14A is another partial plan view of the structure of a display panel according to some embodiments;

[0061] FIG14B is another partial plan view of a display panel according to some embodiments;

[0062] FIG15 is another partial plan view of a display panel according to some embodiments;

[0063] FIG16 is another partial plan view of a display panel according to some embodiments;

[0064] FIG17 is a cross-sectional view of a display panel according to some embodiments;

[0065] FIG18 is a flow chart of a method for manufacturing a display panel according to some embodiments;

[0066] FIG19 is a structural diagram corresponding to step S1 in the method for manufacturing a display panel in the embodiment shown in FIG18 ;

[0067] FIG20 is a structural diagram corresponding to step S2 in the method for manufacturing a display panel in the embodiment shown in FIG18 ;

[0068] FIG21 is a structural diagram corresponding to step S3 in the method for manufacturing a display panel in the embodiment shown in FIG18 ;

[0069] FIG22 is a structural diagram corresponding to step S0 in the method for manufacturing a display panel in the embodiment shown in FIG18 ;

[0070] FIG. 23 is another structural diagram corresponding to step S1 in the method for manufacturing a display panel in the embodiment shown in FIG. 18 . DETAILED DESCRIPTION

[0071] The following will be combined with the accompanying drawings to clearly and completely describe the technical solutions in some embodiments of the present disclosure. Obviously, the embodiments described are only some embodiments of the present disclosure, not all embodiments. Based on the embodiments provided by the present disclosure, all other embodiments obtained by ordinary technicians in this field are within the scope of protection of the present disclosure.

[0072] Unless the context requires otherwise, throughout the specification and claims, the term "comprise" and its other forms, such as the third person singular form "comprises" and the present participle form "comprising", are to be interpreted as open and inclusive, that is, "including, but not limited to". In the description of the specification, the terms "one embodiment", "some embodiments", "exemplary embodiments", "example", "specific example" or "some examples" are intended to indicate that the particular features, structures, materials or characteristics associated with the embodiment or example are included in at least one embodiment or example of the present disclosure. The schematic representation of the above terms does not necessarily refer to the same embodiment or example. In addition, the particular features, structures, materials or characteristics may be included in any one or more embodiments or examples in any appropriate manner.

[0073] In the following, the terms "first" and "second" are used for descriptive purposes only and should not be understood to indicate or imply relative importance or implicitly specify the number of the technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the embodiments of the present disclosure, unless otherwise specified, "plurality" means two or more.

[0074] When describing some embodiments, the expressions "coupled" and "connected" and their derivatives may be used. The term "connected" should be understood in a broad sense. For example, "connection" can be a fixed connection, a detachable connection, or an integral connection; it can be directly connected or indirectly connected through an intermediate medium. The term "coupled" indicates, for example, that two or more components are in direct physical or electrical contact. The term "coupled" or "communicatively coupled" may also refer to two or more components that are not in direct contact with each other, but still cooperate or interact with each other. The embodiments disclosed herein are not necessarily limited to the contents of this document.

[0075] “At least one of A, B and C” has the same meaning as “at least one of A, B or C” and both include the following combinations of A, B and C: A only, B only, C only, the combination of A and B, the combination of A and C, the combination of B and C, and the combination of A, B and C.

[0076] “A and / or B” includes the following three combinations: A only, B only, and a combination of A and B.

[0077] As used herein, the term "if" is optionally interpreted to mean "when" or "upon" or "in response to determining" or "in response to detecting," depending on the context. Similarly, the phrases "if it is determined that" or "if [stated condition or event] is detected" are optionally interpreted to mean "upon determining" or "in response to determining" or "upon detecting [stated condition or event]" or "in response to detecting [stated condition or event]," depending on the context.

[0078] The use of "adapted to" or "configured to" herein is intended to be open and inclusive language that does not exclude devices adapted or configured to perform additional tasks or steps.

[0079] Additionally, the use of “based on” is meant to be open and inclusive, as a process, step, calculation, or other action “based on” one or more stated conditions or values ​​may, in practice, be based on additional conditions or values ​​beyond those stated.

[0080] As used herein, "about," "substantially," or "approximately" includes the stated value and an average value that is within an acceptable range of deviation from the particular value as determined by one of ordinary skill in the art taking into account the measurements in question and the errors associated with the measurement of the particular quantity (i.e., the limitations of the measurement system).

[0081] As used herein, "parallel", "perpendicular", and "equal" include the situations described and situations similar to the situations described, and the range of the similar situations is within an acceptable deviation range, wherein the acceptable deviation range is as determined by a person of ordinary skill in the art taking into account the measurement in question and the errors associated with the measurement of the specific quantity (i.e., the limitations of the measurement system). For example, "parallel" includes absolute parallelism and approximate parallelism, wherein the acceptable deviation range of approximate parallelism can be, for example, a deviation within 5°; "perpendicular" includes absolute perpendicularity and approximate perpendicularity, wherein the acceptable deviation range of approximate perpendicularity can also be, for example, a deviation within 5°. "Equal" includes absolute equality and approximate equality, wherein the acceptable deviation range of approximate equality can be, for example, that the difference between the two equals is less than or equal to 5% of either one.

[0082] It will be understood that when a layer or element is referred to as being on another layer or substrate, it can be directly on the other layer or substrate, or intervening layers may be present therebetween.

[0083] Exemplary embodiments are described herein with reference to cross-sectional and / or plan views that are idealized exemplary drawings. In the drawings, the thickness of layers and the area of ​​regions are exaggerated for clarity. Therefore, variations in shape relative to the drawings due to, for example, manufacturing techniques and / or tolerances are contemplated. Therefore, the exemplary embodiments should not be construed as limited to the shapes of the regions shown herein, but rather include deviations in shape due to, for example, manufacturing. For example, an etched region shown as a rectangle will typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to illustrate the actual shape of regions of the device and are not intended to limit the scope of the exemplary embodiments.

[0084] For the convenience of the following description, an XYZ coordinate system is established. The third direction Z is the thickness direction of the display device, the XY plane is perpendicular to the Z direction, and the first direction X intersects the second direction Y. For example, the first direction X and the second direction Y are perpendicular to each other.

[0085] It should be noted that, for example, 91 / 9 appearing in the drawings of the present disclosure indicates that the component is both 9 and 91, and other similar numbers appearing in the drawings also follow the above description.

[0086] As shown in FIG. 1 , some embodiments of the present disclosure provide a display device 100 .

[0087] Exemplarily, the display device 100 may be any device that displays images, whether in motion (e.g., video) or stationary (e.g., still images), and whether textual or electronic. More specifically, it is contemplated that the embodiments described may be implemented in or associated with a variety of electronic devices, such as, but not limited to, mobile phones, wireless devices, personal data assistants (PDAs), handheld or portable computers, GPS receivers / navigators, cameras, MP4 video players, video cameras, game consoles, watches, clocks, calculators, television monitors, flat-panel displays, computer monitors, automotive displays (e.g., speedometer displays), navigation systems, cockpit controls and / or displays, camera view displays (e.g., displays for rearview cameras in vehicles), electronic photographs, electronic billboards or signs, projectors, architectural structures, packaging, and aesthetic structures (e.g., displays for images of a piece of jewelry). FIG1 illustrates the display device 100 as a mobile phone.

[0088] For example, the display device 100 may be an electroluminescent display device or a photoluminescent display device. If the display device 100 is an electroluminescent display device, the electroluminescent display device may be an organic light-emitting diode (OLED) or a quantum dot electroluminescent display device (QLED). If the display device 100 is a photoluminescent display device, the photoluminescent display device may be a quantum dot photoluminescent display device.

[0089] The following uses an organic light-emitting diode (OLED) display device 100 as an example to schematically illustrate some embodiments of the present disclosure. However, the implementation methods of the present disclosure include but are not limited to this, and any other display device can also be considered as long as the same technical concept is applied.

[0090] In some embodiments, as shown in FIG2 , FIG2 is a cross-sectional view of the display device 100 along the section line BB in FIG1 . The display device 100 includes a display panel 10 and a cover plate 20 . The cover plate 20 is disposed on the light-emitting side of the display panel 10 .

[0091] The cover plate 20 can isolate the display panel 10 from the external environment and provide protection for the display panel 10 .

[0092] Illustratively, the cover plate 20 may be a single-layer cover plate, or may be a multi-layer cover plate 20 laminated together by adhesive.

[0093] Exemplarily, the cover plate 20 may be a silicate glass cover plate, for example, curved glass or ultra-thin glass.

[0094] The cover plate 20 may also be a flexible polymer film cover plate, for example, transparent polyimide, PET or polyurethane.

[0095] The cover plate 20 may also be a combination of the above-mentioned flexible polymer films, or a combination of a flexible polymer film and silicate glass.

[0096] In some embodiments, the display device 100 may further include a circuit board (not shown in the figure). The circuit board is electrically connected to the display panel 10 and is configured to drive the display panel 10 to display images.

[0097] Illustratively, the circuit board includes but is not limited to a PCB (Printed Circuit Board) and an FPC (Flexible Printed Circuit Board).

[0098] In some embodiments, the display device 100 may further include an under-screen camera and an under-screen fingerprint sensor, so that the display device 100 can realize a variety of different functions such as taking photos, recording videos, fingerprint recognition, or face recognition. This disclosure does not impose any restrictions on this, and adaptive design can be performed according to actual needs.

[0099] The display panel 10 is described in detail below.

[0100] In some embodiments, as shown in FIG3 , which is a structural diagram of a display panel 10 according to some embodiments, the display panel 10 may be a rectangular structure.

[0101] It should be noted that the aforementioned "rectangular structure" means that the shape of the boundary of the display panel 10 is rectangular as a whole, but is not limited to a standard rectangle. That is, the "rectangle" here includes not only the shape of a standard rectangle, but also, taking into account process conditions, shapes similar to rectangles. For example, as shown in FIG3 , the long and short sides of the rectangle are curved at each intersection (i.e., corner G), i.e., the corner G is smooth, so that the shape of the boundary of the display panel 10 in a plan view is a rounded rectangle.

[0102] In other embodiments, the display panel 10 may be a circular structure, or other shapes with corners.

[0103] In the following, some embodiments of the present disclosure are schematically described by taking the display panel 10 as a rectangular structure as an example. However, the embodiments of the present disclosure include but are not limited to this. The shape of the display panel 10 may also be any other shape.

[0104] In some embodiments, referring to FIG. 3 , the display panel 10 has a display area AA for displaying images, and a peripheral area AN located on at least one side of the display area AA.

[0105] For example, the peripheral area AN is located at one side of the display area AA.

[0106] For another example, the peripheral area AN is located on two opposite sides of the display area AA.

[0107] For another example, as shown in FIG3 , the peripheral area AN surrounds the display area AA.

[0108] It should be noted that the specific configuration of the peripheral area AN is related to the specific design of the display panel 10 and can be designed according to actual needs. It is only used as an example here and is not intended to limit the present disclosure.

[0109] In some embodiments, please continue to refer to FIG. 3 . A plurality of sub-pixels 9 are disposed in the display area AA of the display panel 10 . The sub-pixels 9 are the smallest light-emitting units in the display area AA.

[0110] For example, the multiple sub-pixels 9 within the display area AA of the display panel 10 can emit light of the same color. The display panel 10 may further include a color filter layer disposed on the light-emitting side of the multiple sub-pixels 9. For example, the multiple sub-pixels 9 may all emit light of a color such as white, red, green, or blue. In this case, the colored light emitted by the sub-pixels 9 remains the same color after passing through the color filter layer, or is converted into light of another color and emitted. Thus, when the multiple sub-pixels 9 emit light of the same color, the display panel 10 can achieve multi-color light emission.

[0111] Alternatively, multiple sub-pixels 9 within the display area AA of the display panel 10 emit light of different colors. For example, the multiple sub-pixels 9 include red sub-pixels that emit red light, green sub-pixels that emit green light, and blue sub-pixels that emit blue light, thereby realizing multi-color light output of the display panel 10.

[0112] In some embodiments, please continue to refer to FIG. 2 , the display panel 10 includes a substrate 1 , a driving layer 2 , a pixel layer D, and an encapsulation layer 8 , which are stacked in sequence.

[0113] The pixel layer D is used to provide a plurality of sub-pixels 9 within the display area AA of the display panel 10 . The plurality of sub-pixels 9 include a first sub-pixel 91 and a second sub-pixel 92 that are adjacently provided.

[0114] It should be noted that “a first sub-pixel 91 and a second sub-pixel 92 that are adjacently arranged” means that no other sub-pixel 9 is arranged between the first sub-pixel 91 and the second sub-pixel 92 .

[0115] The driving layer 2 is used to drive the plurality of sub-pixels 9 in the pixel layer D to emit light.

[0116] The encapsulation layer 8 is used to encapsulate the pixel layer D, thereby protecting the pixel layer D from corrosion caused by external water and oxygen.

[0117] For example, the first sub-pixel 91 can be a red sub-pixel emitting red light, a green sub-pixel emitting green light, or a blue sub-pixel emitting blue light. The second sub-pixel 92 can also be a red sub-pixel emitting red light, a green sub-pixel emitting green light, or a blue sub-pixel emitting blue light.

[0118] It is understandable that the colors of the light emitted by the first sub-pixel 91 and the second sub-pixel 92 may be the same. For example, the first sub-pixel 91 and the second sub-pixel 92 may both be red sub-pixels that emit red light.

[0119] For another example, the first sub-pixel 91 and the second sub-pixel 92 may both be green sub-pixels that emit green light.

[0120] For another example, the first sub-pixel 91 and the second sub-pixel 92 may both be blue light sub-pixels that emit blue light.

[0121] The colors of the light emitted by the first sub-pixel 91 and the second sub-pixel 92 may also be different. For example, the first sub-pixel 91 may be a red sub-pixel that emits red light, and the second sub-pixel 92 may be a green sub-pixel that emits green light or a blue sub-pixel that emits blue light.

[0122] For another example, the first sub-pixel 91 may be a green sub-pixel that emits green light, and the second sub-pixel 92 may be a red sub-pixel that emits red light or a blue sub-pixel that emits blue light.

[0123] For another example, the first sub-pixel 91 may also be a blue sub-pixel that emits blue light, and the second sub-pixel 92 may also be a red sub-pixel that emits red light or a green sub-pixel that emits green light.

[0124] For example, the material used to form the substrate 1 may include an inorganic material, for example, a glass material such as soda-lime glass, quartz glass, or sapphire glass.

[0125] The material used to form the substrate 1 may also include an organic material, for example, one or more of polymethyl methacrylate, polyvinyl alcohol, polyvinylphenol, polyethersulfone, polyimide, polyamide, polyacetal, polycarbonate, polyethylene terephthalate, and polyethylene naphthalate.

[0126] The material used to form the substrate 1 may also include both organic materials and inorganic materials.

[0127] For example, a plurality of pixel driving circuits may be provided in the driving layer 2. The pixel driving circuits are electrically connected to the sub-pixels 9 (e.g., the first sub-pixel 91 and the second sub-pixel 92), and the sub-pixels 9 (e.g., the first sub-pixel 91 and the second sub-pixel 92) may emit light under the drive of the pixel driving circuits.

[0128] The pixel driving circuit may include a thin film transistor (TFT) and a storage capacitor.

[0129] Exemplarily, the encapsulation layer 8 may include an inorganic encapsulation layer and an organic encapsulation layer.

[0130] The pixel layer D is described in detail below.

[0131] In some embodiments, referring to FIG. 2 , the pixel layer D of the display panel 10 includes a pixel electrode layer 4, a light-emitting functional layer 6, and a common electrode layer 7 sequentially stacked along a third direction Z. The pixel electrode layer 4 and the common electrode layer 7 can provide carriers such as electrons and holes to the light-emitting functional layer 6, so that the light-emitting functional layer 6 emits light.

[0132] A plurality of pixel electrodes 41 are provided in the pixel electrode layer 4 , and the light-emitting functional layer 6 includes a plurality of light-emitting portions 6 a . Each light-emitting portion 6 a overlaps with a pixel electrode 41 in the third direction Z.

[0133] The common electrode layer 7 may serve as a common electrode for a plurality of sub-pixels 9 (e.g., a first sub-pixel 91 and a second sub-pixel 92 ) within the pixel layer D. Each sub-pixel 9 (e.g., the first sub-pixel 91 or the second sub-pixel 92 ) within the pixel layer D may include a stacked pixel electrode 41 and a common electrode, and a light-emitting portion 6 a located between the pixel electrode 41 and the common electrode.

[0134] For example, referring to FIG. 2 , the pixel electrode layer 4 may be closer to the driving layer 2 than the common electrode layer 7 .

[0135] Exemplarily, one of the pixel electrode 41 and the common electrode can serve as the anode of the sub-pixel 9 (e.g., the first sub-pixel 91 and the second sub-pixel 92), and the other can serve as the cathode of the sub-pixel 9 (e.g., the first sub-pixel 91 and the second sub-pixel 92).

[0136] For example, the pixel electrode 41 may serve as an anode of the sub-pixel 9 (eg, the first sub-pixel 91 and the second sub-pixel 92 ), and the common electrode may serve as a cathode of the sub-pixel 9 (eg, the first sub-pixel 91 and the second sub-pixel 92 ).

[0137] Exemplarily, the material used to form the pixel electrode 41 may include a metal material, such as any one or more of magnesium (Mg), silver (Ag), copper (Cu), aluminum (Al), titanium (Ti), and molybdenum (Mo).

[0138] The material used to form the pixel electrode 41 may also include an alloy material of the above-mentioned metal materials, such as aluminum-neodymium alloy (AlNd) or molybdenum-niobium alloy (MoNb).

[0139] Exemplarily, the pixel electrode 41 may be a single-layer structure.

[0140] Alternatively, the pixel electrode 41 may have a multi-layer composite structure. For example, the pixel electrode 41 may have a Ti / Al / Ti structure. In another example, the pixel electrode 41 may have a stacked structure formed by a metal material and a transparent conductive material, such as ITO / Ag / ITO, Mo / AlNd / ITO, etc.

[0141] Exemplarily, the material used to form the common electrode layer 7 may include any one or more of magnesium (Mg), silver (Ag), aluminum (Al), and the like.

[0142] The material used to form the common electrode layer 7 may also include any one of magnesium (Mg), silver (Ag), aluminum (Al), etc., or an alloy made of several of them.

[0143] The material used to form the common electrode layer 7 may also include a transparent conductive material, such as indium tin oxide (ITO).

[0144] In some embodiments, as shown in FIG4 and in combination with FIG2 , FIG4 is a partial planar structural diagram of a display panel 10 according to some embodiments. The display panel 10 further includes a pixel definition layer (PDL) 5, which is located between the pixel electrode layer 4 and the light-emitting functional layer 6. A plurality of pixel openings K are formed in the pixel definition layer (PDL) 5. The pixel openings K are arranged corresponding to the pixel electrodes 41, and each pixel opening K exposes at least a portion of a pixel electrode 41. The light-emitting portion 6a in the light-emitting functional layer 6 is arranged in the pixel opening K and is electrically connected to the pixel electrode 41 and the common electrode layer 7, respectively.

[0145] By exposing at least a portion of the area of ​​a pixel electrode 41 through each pixel opening K, the pixel definition layer (PDL) 5 can effectively define the actual effective area of ​​the pixel electrode 41 (i.e., the area where the pixel electrode 41 is directly electrically connected to the light-emitting portion 6a in the light-emitting functional layer 6), thereby defining the light-emitting region and light-emitting area of ​​the sub-pixel 9.

[0146] For example, referring to FIG. 4 , the pixel definition layer (PDL) 5 may cover the edge of the pixel electrode 41 , and the pixel opening K may expose a portion of the inner region of the pixel electrode 41 .

[0147] For example, the material for forming the pixel definition layer (PDL) 5 may include an organic material, such as polyimide, acryl, or polyethylene terephthalate.

[0148] For example, referring to FIG. 4 , the plurality of pixel openings K within the pixel definition layer 5 include a first pixel opening K1 and a second pixel opening K2 disposed adjacent to each other. The first pixel opening K1 is disposed correspondingly to the pixel electrode 41 within the first sub-pixel 91 and exposes at least a portion of the pixel electrode 41 within the first sub-pixel 91. The second pixel opening K2 is disposed correspondingly to the pixel electrode 41 within the second sub-pixel 92 and exposes at least a portion of the pixel electrode 41 within the second sub-pixel 92.

[0149] It should be noted that “the first pixel opening K1 and the second pixel opening K2 are adjacently arranged” means that no other pixel opening K is arranged between the first pixel opening K1 and the second pixel opening K2 .

[0150] 5A and 5B , both of which are film structure diagrams of the pixel layer D of the display panel 10 according to some embodiments, the light-emitting functional layer 6 in the pixel layer D includes a light-emitting layer 61 .

[0151] For example, referring to FIG. 5A , the display panel 10 may be a QLED display panel. Based on the display panel 10 being a QLED display panel, the light-emitting layer 61 may include a quantum dot layer (QDL). For example, the quantum dot layer (QDL) may include quantum dot particles, which may be interconnected via surface modification groups.

[0152] Alternatively, referring to FIG. 5B , the display panel 10 may also be an OLED display panel. Based on the OLED display panel, the light-emitting layer 61 may include an organic light-emitting layer (EML). For example, the organic light-emitting layer EML may include a host material and a guest material, wherein the guest material may be a fluorescent dopant or a phosphorescent dopant.

[0153] The following uses an OLED display panel as an example to schematically illustrate some embodiments of the present disclosure. However, the implementation methods of the present disclosure include but are not limited to this. Any other type of display panel can also be considered as long as the same technical concept is applied.

[0154] In some embodiments, please continue to refer to Figure 5B, the light-emitting functional layer 6 also includes one or more of a hole injection layer (HIL), a hole transport layer (HTL), an electron blocking layer (EBL), a hole blocking layer (HBL), an electron transport layer (ETL) and an electron injection layer (EIL).

[0155] For example, the material for forming the hole injection layer (HIL) may include an oxide. The material for forming the hole injection layer (HIL) may also include an organic material.

[0156] For example, the material for forming the hole transport layer (HTL) may include aromatic amines, dimethylfluorene, or carbazole materials having hole transport properties.

[0157] Exemplarily, the material for forming the electron transport layer (ETL) may include an aromatic heterocyclic compound.

[0158] Exemplarily, a material for forming the electron injection layer (EIL) may include an alkali metal or a metal and a compound thereof.

[0159] In some embodiments, please continue to refer to FIG. 5B , the light-emitting functional layer 6 in the pixel layer D may include a single light-emitting layer 61 .

[0160] In some other embodiments, as shown in FIG6 , which is a film structure diagram of a pixel layer D of a display panel 10 according to some embodiments, the light-emitting functional layer 6 in the pixel layer D may include multiple light-emitting layers 61 .

[0161] For example, please continue to refer to FIG. 6 , the light-emitting functional layer 6 may include two light-emitting layers 61 , namely a first light-emitting layer 61 a and a second light-emitting layer 61 b ​​.

[0162] The second light-emitting layer 61 b ​​may be closer to the common electrode layer 7 than the first light-emitting layer 61 a , and the common electrode layer 7 may be located on a side of the second light-emitting layer 61 b ​​away from the substrate 1 .

[0163] In the following, some embodiments of the present disclosure are schematically described by taking the light-emitting functional layer 6 including two light-emitting layers 61 as an example.

[0164] Continuing with Figure 6 , the light-emitting functional layer 6 further includes a charge generation layer (CGL) 62 located between the first light-emitting layer 61a and the second light-emitting layer 61b. The charge generation layer (CGL) 62 can connect the first light-emitting layer 61a and the second light-emitting layer 61b in series to achieve a tandem EL design.

[0165] On the one hand, the increased number of light-emitting layers 61 and the ability of the charge generation layer (CGL) 62 to reduce driving voltage and generate new carriers can exponentially increase the luminous efficiency of the light-emitting functional layer 6. On the other hand, at the same brightness, the display panel 10 with a tandem EL design has a lower current density than a display panel 10 with a single-layer EL design, which helps extend the service life of the display panel 10.

[0166] Illustratively, the charge generation layer (CGL) 62 may be configured to generate carriers, transport carriers, and inject carriers.

[0167] Exemplarily, the charge generation layer (CGL) 62 may include an N-type charge generation layer (n-CGL) and a P-type charge generation layer (p-CGL).

[0168] The N-type charge generation layer (n-CGL) may include, for example, an organic electron transport layer (ETL) material doped with a metal material.

[0169] The p-type charge generation layer (p-CGL) may include, for example, an organic hole transport layer (HTL) material doped with a p-type light-emitting dopant (p-dopant, PD).

[0170] In some embodiments, please continue to refer to FIG. 6 , some film layers in the light-emitting functional layer 6 may be common layers.

[0171] The common layer in the light-emitting functional layer 6 means that part of the film layer in the light-emitting functional layer 6 is formed both in the region where the multiple sub-pixels 9 (for example, the first sub-pixel 91 and the second sub-pixel 92) are located and in the gap region between the multiple sub-pixels 9 (for example, the gap region J between the first sub-pixel 91 and the second sub-pixel 92). That is, the part of the film layer in the light-emitting functional layer 6 is a whole continuous film layer. In this case, it can be considered that the multiple sub-pixels 9 (for example, the first sub-pixel 91 and the second sub-pixel 92) share the part of the film layer in the light-emitting functional layer 6, and the part of the film layer in the light-emitting functional layer 6 can be considered as the common layer in the light-emitting functional layer 6.

[0172] For example, due to process reasons, part of the film layers in the light-emitting functional layer 6 are common layers. For example, when an open mask process is used to form part of the film layers in the light-emitting functional layer 6, the material used to form part of the film layers of the light-emitting functional layer 6 will be deposited in the area where multiple sub-pixels 9 (for example, the first sub-pixel 91 and the second sub-pixel 92) are located. Specifically, the material used to form part of the film layers of the light-emitting functional layer 6 will be deposited in multiple pixel openings K (for example, the first pixel opening K1 and the second pixel opening K2), that is, part of the light-emitting functional layer 6 is located in the multiple pixel openings K (for example, the first pixel opening K1 and the second pixel opening K2), and is used to form the light-emitting portion 6a in the sub-pixel 9 (for example, the light-emitting portion 6a of the first sub-pixel 91 and the light-emitting portion 6a of the second sub-pixel 92); at the same time, part of the film layers used to form the light-emitting functional layer 6 (for example, the charge generation layer (CGL) 62 ) is also deposited in the gap region between the plurality of sub-pixels 9 (for example, the gap region J between the first sub-pixel 91 and the second sub-pixel 92). Specifically, the material for forming a portion of the film layer (for example, the charge generation layer (CGL) 62) of the light-emitting functional layer 6 is also deposited in the gap region between the plurality of pixel openings K (for example, the gap region between the first pixel opening K1 and the second pixel opening K2). That is, a portion of the film layer (for example, the charge generation layer (CGL) 62) of the light-emitting functional layer 6 is located in the gap region between the plurality of pixel openings K (for example, the first pixel opening K1 and the second pixel opening K2), so that two adjacent sub-pixels 9 (for example, the first sub-pixel 91 and the second sub-pixel 92) are connected via the light-emitting functional layer 6 formed in the gap region J. Specifically, the light-emitting portions 6a of two adjacent sub-pixels 9 (for example, the light-emitting portion 6a of the first sub-pixel 91 and the light-emitting portion 6a of the second sub-pixel 92) are connected via the light-emitting functional layer 6 formed in the gap region J.

[0173] That is to say, the common layer in the light-emitting functional layer 6 can cover the area where multiple sub-pixels 9 (for example, the first sub-pixel 91 and the second sub-pixel 92) are located, as well as the gap area between the multiple sub-pixels 9 (for example, the gap area J between the first sub-pixel 91 and the second sub-pixel 92), and the common layer is continuous in the gap area between the multiple sub-pixels 9 (for example, the gap area J between the first sub-pixel 91 and the second sub-pixel 92).

[0174] When the sub-pixel 9 is working, carriers easily flow laterally through the common layer in the light-emitting functional layer 6 (i.e., carriers flow from one sub-pixel 9 to another sub-pixel 9), resulting in crosstalk between adjacent sub-pixels 9, which is particularly serious at low grayscales.

[0175] In particular, when the common layer in the light-emitting functional layer 6 has a strong conductivity, crosstalk between adjacent sub-pixels 9 is likely to become more severe. For example, when the charge generation layer (CGL) 62 is a common layer, the charge generation layer (CGL) 62 has a strong conductivity, which can lead to more severe crosstalk between adjacent sub-pixels 9 and may cause color cast.

[0176] For example, as shown in Figure 6, when the first sub-pixel 91 is working, a signal is input to the first sub-pixel 91, and the first sub-pixel 91 is lit while the second sub-pixel 92 is also lit, resulting in a decrease in the color purity of the picture of the first sub-pixel 91 and a decrease in the low grayscale color gamut, affecting the display effect of the display panel 10.

[0177] Based on this, in some embodiments, as shown in FIG7 , which is a structural diagram of a display panel 10 according to some embodiments, the display panel 10 further includes a partition structure 32 a. The partition structure 32 a is located between the first pixel opening K1 and the second pixel opening K2. In other words, the partition structure 32 a is located between the first sub-pixel 91 and the second sub-pixel 92.

[0178] Since the charge generation layer (CGL) 62 is a common layer in the light-emitting functional layer 6 , at least the charge generation layer (CGL) 62 is disconnected at the partition structure 32 a in the light-emitting functional layer 6 .

[0179] It should be noted that the above “in the light-emitting functional layer 6, at least the charge generation layer (CGL) 62 is disconnected at the partition structure 32a” means that in the light-emitting functional layer 6, at least the charge generation layer (CGL) 62 is discontinuous or non-integrated at the partition structure 32a.

[0180] By setting a partition structure between the adjacent first sub-pixel 91 and the second sub-pixel 92, and making at least the charge generation layer (CGL) 62 in the light-emitting functional layer 6 disconnected at the partition structure 32a, crosstalk between the first sub-pixel 91 and the second sub-pixel 92 caused by the charge generation layer (CGL) 62 with stronger conductivity is avoided, which is beneficial to improving the display effect of the display panel 10.

[0181] For example, the partition structure 32a may include a negative photosensitive material.

[0182] Illustratively, in the light-emitting functional layer 6, other film layers except the charge generation layer (CGL) 62 may also be common layers in the light-emitting functional layer 6. For example, based on the light-emitting functional layer 6 including one or more of a hole injection layer (HIL), a hole transport layer (HTL), an electron blocking layer (EBL), a hole blocking layer (HBL), an electron transport layer (ETL) and an electron injection layer (EIL), one or more of the hole injection layer (HIL), the hole transport layer (HTL), the electron blocking layer (EBL), the hole blocking layer (HBL), the electron transport layer (ETL) and the electron injection layer (EIL) may also be common layers in the light-emitting functional layer 6.

[0183] When some of the film layers other than the charge generation layer (CGL) 62 in the light-emitting functional layer 6 are also common layers in the light-emitting functional layer 6, only the charge generation layer (CGL) 62 can be disconnected at the partition structure 32a, or other film layers serving as common layers can also be disconnected at the partition structure 32a.

[0184] For example, as shown in FIG7 , all common layers in the light-emitting functional layer 6 are disconnected at the partition structure 32a. That is, a portion of the light-emitting functional layer 6 located on the surface 32aa of the partition structure 32a away from the substrate 1 is discontinuous or non-integrated with another portion of the light-emitting functional layer 6.

[0185] By disconnecting all the common layers in the light-emitting functional layer 6 at the partition structure 32a, it is possible to prevent carriers from flowing laterally through the common layers in the light-emitting functional layer 6 (i.e., carriers flow from one sub-pixel 9 to another sub-pixel 9), thereby avoiding crosstalk between adjacent sub-pixels 9 (for example, the first sub-pixel 91 and the second sub-pixel 92), which is beneficial to further improve the display effect of the display panel 10.

[0186] For the convenience of explanation, some embodiments of the present disclosure are schematically described below by taking an example where all common layers in the light-emitting functional layer 6 are disconnected at the partition structure 32 a.

[0187] In some embodiments, please continue to refer to Figure 7. Along the third direction Z, the distance d2 between the surface 32aa of the partition structure 32a away from the substrate 1 and the substrate 1 is greater than the distance d1 between the surface 5aa of the pixel definition layer 5 away from the substrate 1 and the substrate 1.

[0188] That is, the surface 5 aa of the pixel definition layer 5 that is away from the substrate 1 is closer to the substrate 1 than the surface 32 aa of the partition structure 32 a that is away from the substrate 1 .

[0189] On the one hand, when forming the light-emitting functional layer 6 through the evaporation process, a mask needs to be provided on the side of the pixel definition layer 5 and the partition structure 32a away from the substrate 1. Since the pixel definition layer 5 is away from the surface 5aa of the substrate 1 and is closer to the substrate 1 than the surface 32aa of the partition structure 32a is away from the substrate 1, the surface 32aa of the partition structure 32a is away from the substrate 1 and is closer to the mask than the surface 5aa of the pixel definition layer 5 is away from the substrate 1. Therefore, the partition structure 32a is more likely to be scratched against the mask, and the debris of the partition structure 32a caused by the scratches may affect the reliability of the package. In addition, the debris of the partition structure 32a caused by the scratches may easily enter the pixel opening K, affecting the light emission of the light-emitting portion 6a in the pixel opening K, which may cause black spots to appear on the display panel 10, resulting in a decrease in the yield of the display panel 10.

[0190] On the other hand, since the pixel definition layer 5 is far away from the surface 5aa of the substrate 1, compared with the partition structure 32a being far away from the surface 32aa of the substrate 1 and being closer to the substrate 1, in the side view state, the partition structure 32 is likely to block the sub-pixel 9 and affect the visual experience of the display panel 10.

[0191] Based on this, in some embodiments, as shown in FIG8 , which is a structural diagram of a display panel 10 according to some embodiments, along the third direction Z, a distance d2 between the surface 32aa of the partition structure 32a away from the substrate 1 and the substrate 1 is less than or equal to a distance d1 between the surface 5aa of the pixel definition layer 5 away from the substrate 1 and the substrate 1.

[0192] That is, the surface 32aa of the partition structure 32a away from the substrate 1 is closer to the substrate 1 than the surface 5aa of the pixel definition layer 5 away from the substrate 1, as shown in Figure 8; or, the surface 32aa of the partition structure 32a away from the substrate 1 is flush with the surface 5aa of the pixel definition layer 5 away from the substrate 1.

[0193] By making the partition structure 32a away from the surface 32aa of the substrate 1 and not higher than the surface 5aa of the pixel definition layer 5 away from the substrate 1, when forming the light-emitting functional layer 6 through the evaporation process, scratches between the partition structure 32a and the mask can be avoided. In this way, debris of the partition structure 32a caused by scratches can be avoided, ensuring that the light-emitting portion 6a in the pixel opening K emits light normally, improving packaging reliability, and facilitating improving the yield of the display panel 10.

[0194] On the other hand, since the partition structure 32a is away from the surface 32aa of the substrate 1 and is not higher than the surface 5aa of the pixel definition layer 5 away from the substrate 1, in the side view state, the partition structure 32 can be avoided from blocking the sub-pixel 9, thereby improving the visual experience of the display panel 10.

[0195] In some embodiments, please continue to refer to FIG. 8 and, in conjunction with FIG. 9 , FIG. 9 illustrates a structural diagram of a partition structure 32a of a display panel 10 according to some embodiments. The display panel 10 further includes a first dielectric layer 31 positioned between the partition structure 32a and the substrate 1. An opening T is defined on a surface 31a of the first dielectric layer 31 facing away from the substrate 1, with at least a portion of the partition structure 32a positioned within the opening T.

[0196] Please continue to refer to Figure 9. By disposing at least a portion of the partition structure 32a in the opening T, while ensuring that the surface 32aa of the partition structure 32a away from the substrate 1 is not higher than the surface 5aa of the pixel definition layer 5 away from the substrate 1, the dimension g1 of the partition structure 32a along the third direction Z (for the sake of convenience of description, hereinafter collectively referred to as the height g1 of the partition structure 32a) can be increased, that is, the distance between the surface 32aa of the partition structure 32a away from the substrate 1 and the surface 32ad of the partition structure 32a close to the substrate 1 is increased, so that the edge of the partition structure 32a has a larger step difference, which is beneficial to improving the partition effect of the partition structure 32a on the light-emitting functional layer 6 and avoiding the light-emitting functional layer 6 from being continuous at the partition structure 32a.

[0197] For example, the first dielectric layer 3 may include a planar layer, which is mainly used to block water oxygen and alkaline ions.

[0198] For example, the first dielectric layer 3 may be obtained by coating PI (Polyimide) using a spin coating process, or by depositing silicon nitride, silicon oxide, or silicon oxynitride using a PECVD process.

[0199] Exemplarily, the opening T may penetrate the first dielectric layer 3 .

[0200] Alternatively, as shown in FIG9 , the opening T may not penetrate the first dielectric layer 31 , that is, the depth g2 of the opening T is smaller than the thickness g3 of the first dielectric layer 31 .

[0201] It should be noted that the “depth g2 of the opening T” refers to the dimension g2 of the opening T along the third direction Z. The “thickness g3 of the first dielectric layer 31 ” refers to the dimension g3 of the first dielectric layer 31 along the third direction Z.

[0202] In some embodiments, please continue to refer to FIG. 9 , a side 32ac of the partition structure 32a close to the second pixel opening K2 may be provided with an undercut structure.

[0203] Alternatively, as shown in Figure 10, which is a structural diagram of a partition structure 32a of a display panel 10 according to some embodiments, a side 32ab of the partition structure 32a close to the first pixel opening K1 may be provided with an undercut structure.

[0204] Alternatively, as shown in FIG11 , which is a structural diagram of a partition structure 32a of a display panel 10 according to some embodiments, a side 32ac of the partition structure 32a close to the second pixel opening K2 and a side 32ab of the partition structure 32a close to the first pixel opening K1 may both be provided with an undercut structure.

[0205] It should be noted that the above-mentioned “undercut structure” is formed by the side 32ac of the partition structure 32a close to the second pixel opening K1 and / or the side 32ab of the partition structure 32a close to the first pixel opening K1 being retracted a certain distance into the interior of the partition structure 32a.

[0206] The aforementioned “in the light-emitting functional layer 6 , at least the charge generation layer (CGL) 62 is disconnected at the partition structure 32 a ” may specifically mean that in the light-emitting functional layer 6 , at least the charge generation layer 62 is disconnected at the undercut structure (undercut) of the partition structure 32 a .

[0207] By setting an undercut structure, and in the light-emitting functional layer 6, at least the charge generation layer 62 is disconnected at the undercut structure, at least the crosstalk between the first sub-pixel 91 and the second sub-pixel 92 caused by the charge generation layer (CGL) 62 with stronger conductivity can be avoided, which is beneficial to improving the display effect of the display panel 10.

[0208] 9 , 10 and 11 , the undercut structure is located within the opening T, and a distance d4 is formed between the undercut structure and the sidewall of the opening T. In other words, the undercut structure and the sidewall of the opening T do not contact each other.

[0209] In some embodiments, as shown in Figures 9, 12A, 12B, and 12C, Figures 12A, 12B, and 12C are all structural diagrams of a partition structure 32a of a display panel 10 according to some embodiments. An undercut structure is provided on a side 32ac of the partition structure 32a near the second pixel opening K2, and a side 32ab of the partition structure 32a near the first pixel opening K1 at least partially aligns with the sidewall of the opening T.

[0210] For example, referring to Figures 9, 12A, 12B, and 12C, the slope of the sidewall of the opening T near the undercut structure is greater than the slope of the sidewall of the opening T away from the undercut structure. Because the undercut structure is provided on the side 32ac of the partition structure 32a near the second pixel opening K2 in the embodiment shown in Figures 9, 12A, 12B, and 12C, the slope of the sidewall of the opening T near the side 32ac of the partition structure 32a is greater than the slope of the sidewall of the opening T near the side 32ab of the partition structure 32a.

[0211] That is to say, the side wall of one side 32ab of the partition structure 32a close to the opening T has a smaller slope and is relatively flat. When the partition structure 32a is formed in the opening T, it is convenient for the side 32ab close to the first pixel opening K1 to adhere to the side wall, which is conducive to making the side wall fit with the side 32ab of the first pixel opening K1.

[0212] For example, as shown in FIG12A , along the third direction Z, a distance d2 between a surface 32aa of the partition structure 32a away from the substrate 1 and the substrate 1 may be smaller than a distance d3 between a surface 31a of the first dielectric layer 3 away from the substrate 1 and the substrate 1. In other words, the surface 31a of the first dielectric layer 31 away from the substrate 1 is farther away from the substrate 1 than the surface 32aa of the partition structure 32aa away from the substrate 1.

[0213] Because the surface 31a of the first dielectric layer 31 away from the substrate 1 is farther away from the substrate 1 than the surface 32aa of the partition structure 32aa away from the substrate 1, the side 32ab of the partition structure 32a close to the first pixel opening K1 can be completely attached to the side wall of the opening T.

[0214] Alternatively, as shown in FIG12B , along the third direction Z, the distance d2 between the surface 32aa of the partition structure 32a away from the substrate 1 and the substrate 1 may be equal to the distance d3 between the surface 31a of the first dielectric layer 3 away from the substrate 1 and the substrate 1. In other words, the surface 31a of the first dielectric layer 31 away from the substrate 1 is flush with the surface 32aa of the partition structure 32aa away from the substrate 1.

[0215] Since the surface 31a of the first dielectric layer 31 away from the substrate 1 is flush with the surface 32aa of the partition structure 32aa away from the substrate 1 , the side 32ab of the partition structure 32a close to the first pixel opening K1 can be completely aligned with the side wall of the opening T.

[0216] Alternatively, as shown in FIG12C , along the third direction Z, the distance d2 between the surface 32aa of the partition structure 32a away from the substrate 1 and the substrate 1 may be greater than the distance d3 between the surface 31a of the first dielectric layer 3 away from the substrate 1 and the substrate 1. In other words, the surface 31a of the first dielectric layer 31 away from the substrate 1 is closer to the substrate 1 than the surface 32aa of the partition structure 32aa away from the substrate 1.

[0217] Because the surface 31a of the first dielectric layer 31 away from the substrate 1 is closer to the substrate 1 than the surface 32aa of the partition structure 32aa away from the substrate 1, a side 32ab of the partition structure 32a close to the first pixel opening K1 can be partially in contact with the side wall of the opening T, while another portion extends outside the opening T. In addition, the portion of the side 32ab of the partition structure 32a close to the first pixel opening K1 that extends outside the opening T does not contact the surface 31a of the first dielectric layer 31 away from the substrate 1.

[0218] Alternatively, as shown in FIG9 , along the third direction Z, the distance d2 between the surface 32aa of the partition structure 32a away from the substrate 1 and the substrate 1 may be greater than the distance d3 between the surface 31a of the first dielectric layer 3 away from the substrate 1 and the substrate 1. In other words, the surface 31a of the first dielectric layer 31 away from the substrate 1 is closer to the substrate 1 than the surface 32aa of the partition structure 32aa away from the substrate 1.

[0219] Because the surface 31a of the first dielectric layer 31 away from the substrate 1 is closer to the substrate 1 than the surface 32aa of the partition structure 32aa away from the substrate 1, a side 32ab of the partition structure 32a close to the first pixel opening K1 can be partially aligned with the side wall of the opening T, while another portion extends outside the opening T. In addition, the portion of the side 32ab of the partition structure 32a close to the first pixel opening K1 that extends outside the opening T overlaps the surface 31a of the first dielectric layer 31 away from the substrate 1.

[0220] For example, as shown in Figure 9, the portion of the partition structure 32a overlapping the surface 31a of the first dielectric layer 31 away from the substrate 1 includes a first side surface 32ae, and a portion extending outside the opening T based on a side 32ab of the partition structure 32a close to the first pixel opening K1, overlapping the surface 31a of the first dielectric layer 31 away from the substrate 1, and the first side surface 32ae is close to the first pixel opening K1 and belongs to the side 32ab of the partition structure 32a close to the first pixel opening K1.

[0221] The first side surface 32ae and the surface 31a of the first dielectric layer 31 away from the substrate 1 form a first angle R1. This first angle R1 is oriented toward the opening T and is an acute angle. That is, the first side surface 32ae is an inclined surface, allowing for a smooth transition from the first side surface 32ae, which is away from the surface 31a of the first dielectric layer 31, to the surface 32aa of the partition structure 32a, which is away from the substrate 1.

[0222] When forming the pixel definition layer (PDL) 5, the pixel definition layer (PDL) 5 is formed on the surface 31a of the first dielectric layer 31 away from the substrate 1, the first side surface 32ae, and the surface 32aa of the partition structure 32a away from the substrate 1. Since the surface 31a of the first dielectric layer 31 away from the substrate 1 can be smoothly transitioned from the first side surface 32ae to the surface 32aa of the partition structure 32a away from the substrate 1, the pixel definition layer (PDL) 5 can be continuously formed between the surface 31a of the first dielectric layer 31 away from the substrate 1, the first side surface 32ae, and the surface 32aa of the partition structure 32a away from the substrate 1. This can prevent the pixel definition layer (PDL) 5 from being disconnected at the partition structure 32a, and can reduce the stress on the pixel definition layer (PDL) 5 in the transition region (i.e., the first side surface 32ae) between the surface 31a of the first dielectric layer 31 away from the substrate 1 and the surface 32aa of the partition structure 32a away from the substrate 1, thereby improving the stability of the display panel 10.

[0223] In other embodiments, as shown in Figures 10, 13A, 13B, and 13C, Figures 13A, 13B, and 13C are structural diagrams of a partition structure 32a of a display panel 10 according to some embodiments. An undercut structure is provided on a side 32ab of the partition structure 32a near the first pixel opening K1, and a side 32ac of the partition structure 32a near the second pixel opening K2 at least partially aligns with the sidewall of the opening T.

[0224] For example, referring to Figures 10, 13A, 13B, and 13C, the slope of the sidewall of the opening T near the undercut structure is greater than the slope of the sidewall of the opening T away from the undercut structure. Because the undercut structure is provided on the side 32ab of the partition structure 32a near the first pixel opening K1 in the embodiment shown in Figures 10, 13A, 13B, and 13C, the slope of the sidewall of the opening T near the side 32ab' of the partition structure 32a is greater than the slope of the sidewall of the opening T near the side 32ac' of the partition structure 32a.

[0225] That is to say, the side wall of one side 32ac of the partition structure 32a close to the opening T has a smaller slope and is relatively flat. When the partition structure 32a is formed in the opening T, it is convenient for the side 32ac close to the first pixel opening K1 to adhere to the side wall, which is conducive to making the side wall fit with the side 32ac of the first pixel opening K1.

[0226] For example, as shown in FIG13A , along the third direction Z, a distance d2 between a surface 32aa of the partition structure 32a away from the substrate 1 and the substrate 1 may be smaller than a distance d3 between a surface 31a of the first dielectric layer 3 away from the substrate 1 and the substrate 1. In other words, the surface 31a of the first dielectric layer 31 away from the substrate 1 is farther away from the substrate 1 than the surface 32aa of the partition structure 32aa away from the substrate 1.

[0227] Because the surface 31a of the first dielectric layer 31 away from the substrate 1 is farther away from the substrate 1 than the surface 32aa of the partition structure 32aa away from the substrate 1, the side 32ac of the partition structure 32a close to the second pixel opening K2 can be completely attached to the side wall of the opening T.

[0228] Alternatively, as shown in FIG13B , along the third direction Z, the distance d2 between the surface 32aa of the partition structure 32a away from the substrate 1 and the substrate 1 may be equal to the distance d3 between the surface 31a of the first dielectric layer 3 away from the substrate 1 and the substrate 1. In other words, the surface 31a of the first dielectric layer 31 away from the substrate 1 is flush with the surface 32aa of the partition structure 32aa away from the substrate 1.

[0229] Since the surface 31a of the first dielectric layer 31 away from the substrate 1 is flush with the surface 32aa of the partition structure 32aa away from the substrate 1 , the side 32ac of the partition structure 32a close to the second pixel opening K2 can be completely attached to the side wall of the opening T.

[0230] Alternatively, as shown in FIG13C , along the third direction Z, the distance d2 between the surface 32aa of the partition structure 32a away from the substrate 1 and the substrate 1 may be greater than the distance d3 between the surface 31a of the first dielectric layer 3 away from the substrate 1 and the substrate 1. In other words, the surface 31a of the first dielectric layer 31 away from the substrate 1 is closer to the substrate 1 than the surface 32aa of the partition structure 32aa away from the substrate 1.

[0231] Because the surface 31a of the first dielectric layer 31 away from the substrate 1 is closer to the substrate 1 than the surface 32aa of the partition structure 32aa away from the substrate 1, a side 32ac of the partition structure 32a close to the second pixel opening K2 can be partially in contact with the side wall of the opening T, while another portion extends outside the opening T. In addition, the portion of the side 32ac of the partition structure 32a close to the second pixel opening K2 that extends outside the opening T does not contact the surface 31a of the first dielectric layer 31 away from the substrate 1.

[0232] Alternatively, as shown in FIG10 , along the third direction Z, a distance d2 between a surface 32aa of the partition structure 32a away from the substrate 1 and the substrate 1 may be greater than a distance d3 between a surface 31a of the first dielectric layer 3 away from the substrate 1 and the substrate 1. In other words, a surface 31a of the first dielectric layer 31 away from the substrate 1 is closer to the substrate 1 than a surface 32aa of the partition structure 32aa away from the substrate 1.

[0233] Because the surface 31a of the first dielectric layer 31 away from the substrate 1 is closer to the substrate 1 than the surface 32aa of the partition structure 32aa away from the substrate 1, a side 32ac of the partition structure 32a close to the second pixel opening K2 can be partially aligned with the side wall of the opening T, while another portion extends outside the opening T. In addition, the portion of the side 32ac of the partition structure 32a close to the second pixel opening K2 that extends outside the opening T overlaps the surface 31a of the first dielectric layer 31 away from the substrate 1.

[0234] For example, as shown in Figure 10, the portion of the partition structure 32a overlapping the surface 31a of the first dielectric layer 31 away from the substrate 1 includes the first side surface 32ae, and the portion extending outside the opening T based on the side 32ac of the partition structure 32a close to the second pixel opening K2, overlapping the surface 31a of the first dielectric layer 31 away from the substrate 1, and the first side surface 32ae close to the second pixel opening K2 and belongs to the side 32ac of the partition structure 32a close to the second pixel opening K2.

[0235] The first side surface 32ae and the surface 31a of the first dielectric layer 31 away from the substrate 1 form a first angle R1. This first angle R1 is oriented toward the opening T and is an acute angle. That is, the first side surface 32ae is an inclined surface, allowing for a smooth transition from the first side surface 32ae, which is away from the surface 31a of the first dielectric layer 31, to the surface 32aa of the partition structure 32a, which is away from the substrate 1.

[0236] When forming the pixel definition layer (PDL) 5, the pixel definition layer (PDL) 5 is formed on the surface 31a of the first dielectric layer 31 away from the substrate 1, the first side surface 32ae, and the surface 32aa of the partition structure 32a away from the substrate 1. Since the surface 31a of the first dielectric layer 31 away from the substrate 1 can be smoothly transitioned from the first side surface 32ae to the surface 32aa of the partition structure 32a away from the substrate 1, the pixel definition layer (PDL) 5 can be continuously formed between the surface 31a of the first dielectric layer 31 away from the substrate 1, the first side surface 32ae, and the surface 32aa of the partition structure 32a away from the substrate 1. This can prevent the pixel definition layer (PDL) 5 from being disconnected at the partition structure 32a, and can reduce the stress on the pixel definition layer (PDL) 5 in the transition region (i.e., the first side surface 32ae) between the surface 31a of the first dielectric layer 31 away from the substrate 1 and the surface 32aa of the partition structure 32a away from the substrate 1, thereby improving the stability of the display panel 10.

[0237] In some embodiments, as shown in Figures 14A and 14B, which are both partial planar structural diagrams of the display panel 10 according to some embodiments, the partition structure 32a is disposed around the first pixel opening K1 or the second pixel opening K2 and has at least one notch Q.

[0238] Based on the fact that the partition structure 32a is arranged around the first pixel opening K1 and the partition structure 32a has at least one gap Q, at least the charge generation layer (CGL) 62 in the light-emitting functional layer 6 can be disconnected at the partition structure 32a surrounding the first pixel opening K1 and continuous at the gap Q, that is, the part of at least the charge generation layer (CGL) 62 of the light-emitting functional layer 6 located in the first pixel opening K1 and other parts (for example, the part of at least the charge generation layer (CGL) 62 of the light-emitting functional layer 6 located in the second pixel opening K2) are only connected at the gap Q, which can reduce the crosstalk between the first sub-pixel 91 and other sub-pixels 9 (for example, the second sub-pixel 92) caused by at least the charge generation layer (CGL) 62 in the light-emitting functional layer 6, which is beneficial to improving the display effect of the display panel 10.

[0239] Based on the fact that the partition structure 32a is arranged around the second pixel opening K2 and the partition structure 32a has at least one gap Q, at least the charge generation layer (CGL) 62 in the light-emitting functional layer 6 can be disconnected at the partition structure 32a surrounding the second pixel opening K2 and continuous at the gap Q, that is, the part of at least the charge generation layer (CGL) 62 of the light-emitting functional layer 6 located in the second pixel opening K2 and other parts (for example, the part of at least the charge generation layer (CGL) 62 of the light-emitting functional layer 6 located in the first pixel opening K1) are only connected at the gap Q, which can reduce the crosstalk between the second sub-pixel 92 and other sub-pixels 9 (for example, the first sub-pixel 91) caused by at least the charge generation layer (CGL) 62 in the light-emitting functional layer 6, which is beneficial to improving the display effect of the display panel 10.

[0240] For example, referring to FIG. 14A , the partition structure 32 a is disposed around the first pixel opening K1 or the second pixel opening K2 , and the partition structure 32 a has a gap Q.

[0241] Alternatively, please continue to refer to FIG. 14B , the partition structure 32 a is disposed around the first pixel opening K1 or the second pixel opening K2 , and the partition structure 32 a has a plurality of gaps Q.

[0242] It is understood that when the partition structure 32a has multiple gaps Q, the partition structure 32a is divided into multiple block-shaped partition portions 32a', that is, the partition structure 32a includes multiple block-shaped partition portions 32a'. The multiple partition portions 32a' are spaced around the first pixel opening K1 or the second pixel opening K2.

[0243] In some other embodiments, as shown in FIG15 , which is a partial plan view of the display panel 10 according to some embodiments, the partition structure 32 a has a closed loop shape surrounding the first pixel opening K1 or the second pixel opening K2 .

[0244] Based on the fact that the partition structure 32a has a closed loop shape surrounding the first pixel opening K1, at least the charge generation layer (CGL) 62 in the light-emitting functional layer 6 can be disconnected at the partition structure 32a surrounding the first pixel opening K1, that is, the portion of at least the charge generation layer (CGL) 62 of the light-emitting functional layer 6 located within the first pixel opening K1 and other portions (for example, the portion of at least the charge generation layer (CGL) 62 of the light-emitting functional layer 6 located within the second pixel opening K2) are not connected. This can avoid crosstalk between the first sub-pixel 91 and other sub-pixels 9 (for example, the second sub-pixel 92) caused by at least the charge generation layer (CGL) 62 in the light-emitting functional layer 6, which is beneficial to further improve the display effect of the display panel 10.

[0245] Based on the fact that the partition structure 32a has a closed loop shape surrounding the second pixel opening K2, at least the charge generation layer (CGL) 62 in the light-emitting functional layer 6 can be disconnected at the partition structure 32a surrounding the second pixel opening K2, that is, the portion of at least the charge generation layer (CGL) 62 of the light-emitting functional layer 6 located within the second pixel opening K2 and other portions (for example, the portion of at least the charge generation layer (CGL) 62 of the light-emitting functional layer 6 located within the first pixel opening K1) are not connected. This can avoid crosstalk between the second sub-pixel 92 and other sub-pixels 9 (for example, the first sub-pixel 91) caused by at least the charge generation layer (CGL) 62 in the light-emitting functional layer 6, which is beneficial to further improve the display effect of the display panel 10.

[0246] In some embodiments, referring to Figures 14A, 14B, and 15, the partition structure 32a includes a third sub-partition structure 323 located between the first sub-pixel 91 and the second sub-pixel 92. The third sub-partition structure 323 can serve as both a portion of the partition structure 32a surrounding the first pixel opening K1 and a portion of the partition structure 32a surrounding the second pixel opening K2. That is, only one partition structure 32a (i.e., the third sub-partition structure 323) is provided between the first sub-pixel 91 and the second sub-pixel 92. The third sub-partition structure 323 can serve as a common partition structure for both the partition structure 32a surrounding the first pixel opening K1 and the partition structure 32a surrounding the second pixel opening K2. This can reduce the distance between the first sub-pixel 91 and the second sub-pixel 92, making the layout of the multiple sub-pixels 9 in the display panel 10 more compact and facilitating an increase in the pixel density of the display panel 10.

[0247] In other embodiments, as shown in FIG16 , which is a partial plan view of the structure of the display panel 10 according to some embodiments, the partition structure 32a surrounding the first pixel opening K1 includes a first sub-partition structure 321, and the partition structure 32a surrounding the second pixel opening K2 includes a second sub-partition structure 322. The first sub-partition structure 321 and the second sub-partition structure 322 are located between the first sub-pixel 91 and the second sub-pixel 92, and are sequentially arranged along the arrangement direction of the first sub-pixel 91 and the second sub-pixel 92.

[0248] That is, two partition structures 32a (i.e., the first sub-partition structure 321 and the second sub-partition structure 322) are provided between the first sub-pixel 91 and the second sub-partition structure 322. When at least the charge generation layer (CGL) 62 in the light-emitting functional layer 6 is not disconnected or not completely disconnected at one of the first sub-partition structure 321 and the second sub-partition structure 322, at least the charge generation layer (CGL) 62 in the light-emitting functional layer 6 may be disconnected at the other of the first sub-partition structure 321 and the second sub-partition structure 322. For example, when at least the charge generation layer (CGL) 62 in the light-emitting functional layer 6 is not disconnected or not completely disconnected at the first sub-partition structure 321, at least the charge generation layer (CGL) 62 in the light-emitting functional layer 6 may be disconnected at the second sub-partition structure 322.

[0249] Therefore, by arranging the first sub-partition structure 321 and the second sub-partition structure 322 in sequence between the first sub-pixel 91 and the second sub-pixel 92 along the arrangement direction of the first sub-pixel 91 and the second sub-pixel 92, at least the charge generation layer (CGL) 62 in the light-emitting functional layer 6 can be completely disconnected at the partition structure 32a, thereby further avoiding the crosstalk between the first sub-pixel 91 and the second sub-pixel 92 caused by the charge generation layer (CGL) 62 with stronger conductivity, which is beneficial to improving the display effect of the display panel 10.

[0250] It should be noted that Figure 16 only takes the partition structure 32a having a closed loop shape surrounding the first pixel opening K1 or the second pixel opening K2 as an example to schematically illustrate the setting method of the partition structure 32a between the first sub-pixel 91 and the second sub-pixel 92. Based on the situation that the partition structure 32a is set around the first pixel opening K1 or the second pixel opening K2, and the partition structure 32a has at least one gap Q, corresponding settings can also be made, which will not be repeated here.

[0251] In some embodiments, the common electrode layer 7 may be continuous at the partition structure 32 a .

[0252] Alternatively, as shown in Figure 17, which is a cross-sectional view of the display panel 10 according to some embodiments, the common electrode layer 7 may also be disconnected at the partition structure 32a.

[0253] For example, please continue to refer to Figure 17, and in combination with Figures 14A and 14B, based on the partition structure 32a being arranged around the first pixel opening K1 or the second pixel opening K2, and the partition structure 32a having at least one gap Q, the common electrode layer 7 can be continuous at at least one gap Q, so as to facilitate the transmission of the common electrode (for example, cathode) signal between the first sub-pixel 91 and the second sub-pixel 92.

[0254] Alternatively, please continue to refer to Figure 17 and combine it with Figure 15. Based on the fact that the partition structure 32a has a closed loop shape surrounding the first pixel opening K1 or the second pixel opening K2, in order to ensure the continuity of the common electrode layer 7 between the first sub-pixel 91 and the second sub-pixel 92, a connection structure can be added to make the common electrode layer 7 between the first sub-pixel 91 and the second sub-pixel 92 continuous, so as to facilitate the transmission of the common electrode (for example, cathode) signal between the first sub-pixel 91 and the second sub-pixel 92.

[0255] The following is a detailed description of the method for manufacturing the display panel 10 .

[0256] In some embodiments, as shown in FIG18 , FIG18 is a flow chart of a method for manufacturing a display panel 10 according to some embodiments. The method for manufacturing the display panel 10 includes steps S1 to S3 .

[0257] S1: As shown in FIG19 , FIG19 is a structural diagram corresponding to step S1 in the method for manufacturing the display panel 10 in the embodiment shown in FIG18 . A partition structure 32 a is formed on the substrate 1 .

[0258] S2: As shown in Figure 20, Figure 20 is a structural diagram corresponding to step S2 in the method for manufacturing the display panel 10 in the embodiment shown in Figure 18. A pixel definition layer 5 is formed on the substrate 1 having the partition structure 32a formed thereon.

[0259] The pixel definition layer 5 is provided with a plurality of pixel openings K. The plurality of pixel openings K include a first pixel opening K1 and a second pixel opening K2 that are adjacent to each other. The partition structure 32 a is located between the first pixel opening K1 and the second pixel opening K2 .

[0260] The surface 32aa of the partition structure 32a away from the substrate 1 is closer to the substrate 1 than the surface 5aa of the pixel definition layer 5 away from the substrate 1; alternatively, the surface 32aa of the partition structure 32a away from the substrate 1 is flush with the surface 5aa of the pixel definition layer 5 away from the substrate 1. In other words, along the third direction Z, the distance d2 between the surface 32aa of the partition structure 32a away from the substrate 1 and the substrate 1 is less than or equal to the distance d1 between the surface 5aa of the pixel definition layer 5 away from the substrate 1 and the substrate 1.

[0261] S3: As shown in FIG21 , FIG21 is a structural diagram corresponding to step S3 in the method for manufacturing the display panel 10 according to the embodiment shown in FIG18 . A light-emitting functional layer 6 is formed on a side of the pixel definition layer 5 away from the substrate 1 .

[0262] 6 , the light-emitting functional layer 6 includes a first light-emitting layer 61a, a charge generation layer (CGL) 62, and a second light-emitting layer 61b stacked sequentially away from the substrate 1. At least the charge generation layer (CGL) 62 of the light-emitting functional layer 6 is disconnected at the partition structure 32a.

[0263] By setting a partition structure 32a between the first pixel opening K1 and the second pixel opening K2 (i.e., between the first sub-pixel 91 and the second sub-pixel 92), and making at least the charge generation layer (CGL) 62 in the light-emitting functional layer 6 disconnected at the partition structure 32a, crosstalk between the first sub-pixel 91 and the second sub-pixel 92 caused by the charge generation layer (CGL) 62 with stronger conductivity is avoided, which is beneficial to improving the display effect of the display panel 10.

[0264] Furthermore, by making the partition structure 32a away from the surface 32aa of the substrate 1 and no higher than the surface 5aa of the pixel definition layer 5 away from the substrate 1, when forming the light-emitting functional layer 6 through the evaporation process, scratches between the partition structure 32a and the mask can be avoided. In this way, debris of the partition structure 32a caused by scratches can be avoided, ensuring that the light-emitting portion 6a in the pixel opening K emits light normally, and improving the packaging reliability, which is conducive to improving the yield of the display panel 10.

[0265] On the other hand, since the partition structure 32a is away from the surface 32aa of the substrate 1 and is not higher than the surface 5aa of the pixel definition layer 5 away from the substrate 1, in the side view state, the partition structure 32 can be avoided from blocking the sub-pixel 9, thereby improving the visual experience of the display panel 10.

[0266] In some embodiments, please continue to refer to FIG. 18 . Before the above step S1 , the method for manufacturing the display panel 10 further includes step S0 .

[0267] S0: As shown in FIG22, FIG22 is a structural diagram corresponding to step S0 in the method for manufacturing the display panel 10 according to the embodiment shown in FIG18. A first dielectric layer 31 is formed on the substrate 1. An opening T is formed on a surface 31a of the first dielectric layer 31 away from the substrate 1.

[0268] For example, referring to FIG. 22 , forming the opening T on the surface 31 a of the first dielectric layer 31 away from the substrate 1 may include the following steps:

[0269] Photoresist (PR) is coated on a surface 31 a of the first dielectric layer 31 away from the substrate 1 .

[0270] The first dielectric layer 31 is exposed using a mask, and then developed to form an opening T.

[0271] In some embodiments, please continue to refer to FIG18 and FIG23, which is a structural diagram corresponding to step S1 in the method for manufacturing the display panel 10 according to the embodiment shown in FIG18. Based on the above step S0, step S1 in the method for manufacturing the display panel 10 includes step S11 and step S12.

[0272] S11 : forming a partition layer 32 on a side of the first dielectric layer 31 away from the substrate 1 .

[0273] S12 : Expose the target area M of the partition layer 32 to form a partition structure 32 a . At least a portion of the partition structure 32 a is located within the opening T.

[0274] By setting at least a portion of the partition structure 32a in the opening T, while ensuring that the surface 32aa of the partition structure 32a away from the substrate 1 is not higher than the surface 5aa of the pixel definition layer 5 away from the substrate 1, the height g1 of the partition structure 32a can be increased, that is, the distance between the surface 32aa of the partition structure 32a away from the substrate 1 and the surface 32ad of the partition structure 32a close to the substrate 1 is increased, so that the edge of the partition structure 32a has a larger step difference, which is beneficial to improving the partition effect of the partition structure 32a on the light-emitting functional layer 6 and avoiding the light-emitting functional layer 6 from being continuous at the partition structure 32a.

[0275] Exemplarily, the material of the barrier layer 32 includes a negative photosensitive material, such as a negative photoresist.

[0276] It should be noted that the portion of the negative photoresist that is exposed to light (i.e., the exposed portion) will not dissolve in the photoresist developer, while the portion that is not exposed to light (i.e., the portion outside the exposed portion) will dissolve in the photoresist developer or dissolve very slowly.

[0277] Please continue to refer to Figure 23. Based on the material of the isolation layer 32 including negative photoresist, after the isolation layer 32 is formed on the side of the first dielectric layer 31 away from the substrate 1, a mask can be used to expose the target area M of the isolation layer 32, and then a development reaction is performed to form a isolation structure 32a.

[0278] 23 , a portion of the target region M overlaps with the opening T, forming an overlapping region J1 , and a distance d5 is formed between the target region M and the sidewall of the opening T. After the target region M is exposed, at least a portion of the partition structure 32 a is located within the opening T.

[0279] Another portion m1 of the target area M is located outside the opening T and close to one of the first pixel opening K1 and the second pixel opening K2. After the target area M is exposed, a portion of the partition structure 32a is overlapped on the surface 31a of the first dielectric layer 32 away from the substrate 1.

[0280] For example, please continue to refer to Figure 23. The dimension h1 of the portion of the partition layer 32 located in the opening T along the third direction Z (for the convenience of description, hereinafter collectively referred to as the thickness h1 of the portion of the partition layer 32 located in the opening T) is greater than the dimension h2 of the portion of the partition layer 32 not located in the opening T along the third direction Z (for the convenience of description, hereinafter collectively referred to as the thickness h2 of the portion of the partition layer 32 not located in the opening T).

[0281] When the target area M of the isolation layer 32 is exposed, since the thickness h1 of the portion of the target area M located within the opening T is relatively large, the side of the portion of the target area M located within the opening T away from the mask may be insufficiently exposed and easily dissolved in the photoresist developer, forming an undercut structure.

[0282] When the target area M of the partition layer 32 is exposed, the portion of the target area M not located within the opening T can be fully exposed because the thickness h2 of the portion of the target area M not located within the opening T is relatively small. After the development process, the resulting partition structure 32a overlaps the portion of the surface 31a of the first dielectric layer 32 away from the substrate 1, and the side away from the undercut structure can be inclined.

[0283] The above description is merely a specific embodiment of the present disclosure, but the scope of protection of the present disclosure is not limited thereto. Any changes or substitutions that a person skilled in the art can conceive within the technical scope disclosed in the present disclosure should be included within the scope of protection of the present disclosure. Therefore, the scope of protection of the present disclosure should be based on the scope of protection of the claims.

Claims

1. A display panel, comprising: substrate, A pixel definition layer is located on one side of the substrate; the pixel definition layer is provided with a plurality of pixel openings, the plurality of pixel openings including a first pixel opening and a second pixel opening that are adjacently arranged; a light-emitting functional layer located on a side of the pixel definition layer away from the substrate, wherein a portion of the light-emitting functional layer is located within the first pixel opening and the second pixel opening; the light-emitting functional layer comprises a first light-emitting layer, a charge generation layer, and a second light-emitting layer stacked in sequence in a direction away from the substrate, wherein at least a portion of the charge generation layer in the light-emitting functional layer is located between the first pixel opening and the second pixel opening; a partition structure located between the first pixel opening and the second pixel opening, wherein at least the charge generation layer in the light-emitting functional layer is disconnected at the partition structure; The partition structure is away from the surface of the substrate and closer to the substrate than the surface of the pixel definition layer is away from the substrate; or the partition structure is away from the surface of the substrate and flush with the surface of the pixel definition layer is away from the substrate.

2. The display panel according to claim 1, wherein The display panel further includes a first dielectric layer, wherein the first dielectric layer is located between the partition structure and the substrate; An opening is provided on a surface of the first dielectric layer away from the substrate, and at least a portion of the partition structure is located in the opening.

3. The display panel according to claim 2, wherein: The first dielectric layer is farther away from the surface of the substrate and closer to the substrate than the partition structure is farther away from the surface of the substrate.

4. The display panel according to claim 2, wherein: The partition structure is provided with an undercut structure on a side close to the first pixel opening; and / or the partition structure is provided with an undercut structure on a side close to the second pixel opening; The undercut structure is located in the opening, and a distance exists between the undercut structure and a sidewall of the opening; In the light-emitting functional layer, at least the charge generation layer is disconnected at the undercut structure.

5. The display panel according to claim 4, wherein: The partition structure is provided with an undercut structure on a side close to one of the first pixel opening and the second pixel opening; A side of the partition structure close to the other of the first pixel opening and the second pixel opening is at least partially in contact with a sidewall of the opening. The display panel according to claim 5 , wherein: A side of the partition structure close to the other of the first pixel opening and the second pixel opening is partially overlapped on a surface of the first dielectric layer away from the substrate.

7. The display panel according to claim 6, wherein: The portion of the partition structure overlapping the surface of the first dielectric layer away from the substrate includes a first side surface close to the other of the first pixel opening and the second pixel opening, and the first side surface and the surface of the first dielectric layer away from the substrate have a first angle; the first angle is toward the opening, and the first angle is an acute angle.

8. The display panel according to claim 1, wherein: The partition structure has a closed loop shape surrounding the first pixel opening or the second pixel opening.

9. The display panel according to claim 8, wherein: The display panel further includes a common electrode layer, which is located on a side of the second light-emitting layer away from the substrate; and the common electrode layer is continuous at the partition structure.

10. The display panel according to claim 1, wherein The partition structure is disposed around the first pixel opening or the second pixel opening, and the partition structure has at least one gap.

11. The display panel according to claim 10, wherein: The display panel further includes a common electrode layer, which is located on a side of the second light-emitting layer away from the substrate; the common electrode layer is disconnected at the partition structure and continuous at the at least one notch.

12. The display panel according to claim 10, wherein: The partition structure includes a plurality of block-shaped partition parts, and the plurality of partition parts are arranged at intervals around the first pixel opening or the second pixel opening.

13. The display panel according to any one of claims 1 to 12, wherein: The partition structure includes a negative photosensitive material.

14. The display panel according to any one of claims 5 to 7, wherein: The slope of the side wall of the opening close to the undercut structure is greater than the slope of the side wall of the opening away from the undercut structure.

15. The display panel according to any one of claims 2 to 7, wherein: The depth of the opening is less than the thickness of the first dielectric layer.

16. A method for preparing a display panel, comprising: forming a partition structure on the substrate; forming a pixel definition layer on the substrate having the partition structure formed thereon; The pixel definition layer is provided with a plurality of pixel openings, the plurality of pixel openings including a first pixel opening and a second pixel opening disposed adjacent to each other, the partition structure being located between the first pixel opening and the second pixel opening; the partition structure being away from the surface of the substrate and closer to the substrate than the surface of the pixel definition layer away from the substrate; or the partition structure being away from the surface of the substrate and flush with the surface of the pixel definition layer away from the substrate; A light-emitting functional layer is formed on the side of the pixel definition layer away from the substrate; the light-emitting functional layer includes a first light-emitting layer, a charge generating layer and a second light-emitting layer stacked in sequence in a direction away from the substrate; in the light-emitting functional layer, at least the charge generating layer is disconnected at the partition structure.

17. The method for manufacturing a display panel according to claim 16, wherein: Before forming the partition structure on the substrate, the method further includes: forming a first dielectric layer on the substrate; forming an opening on a surface of the first dielectric layer away from the substrate; Wherein, at least a portion of the partition structure is located in the opening.

18. The method for manufacturing a display panel according to claim 17, wherein: The step of forming a partition structure on the substrate includes: forming a partition layer on a side of the first dielectric layer away from the substrate; performing an exposure process on a target area of ​​the partition layer to form a partition structure; Part of the target area overlaps with the opening and has a distance from the sidewall of the opening; another part of the target area is located outside the opening and close to the other of the first pixel opening and the second pixel opening.

19. The method for manufacturing a display panel according to claim 18, wherein: The material of the isolation layer includes negative photosensitive material.

20. A display device comprising: The display panel according to any one of claims 1 to 15; The cover plate is arranged on the light-emitting side of the display panel.

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