Display device, drive method, and electronic apparatus

Abstract

One purpose of the present invention is to provide a display device, a drive method, and an electronic apparatus that make it possible to reduce the size of a frame by, e.g., reducing the number of drivers for driving pixels.　This display device has a plurality of pixels individually including a first transistor for outputting a current corresponding to an input voltage and a light-emitting element for emitting light in accordance with the output current of the first transistor, an operation for correcting a threshold voltage of the first transistor being performed simultaneously for all of the pixels, and a light emission operation performed by the light-emitting element being performed simultaneously for all of the pixels.

Description

Display device, driving method, and electronic device

[0001] The present technology relates to a display device, a driving method, and an electronic device.

[0002] The following Patent Document 1 discloses a display device that performs collective light emission drive to simultaneously emit light from multiple rows of organic EL elements, and also discloses a technique for correcting the threshold voltage of a drive transistor that supplies a current to the organic EL elements according to the potential of the gate electrode.

[0003] Japanese Patent Application Laid-Open No. 2021-128194

[0004] In the display device of Patent Document 1, the threshold voltage of the drive transistor is corrected by shifting it by 1H for each row, which requires that control signals for the transistors to be operated during the correction be generated row by row, and a vertical scanner (vertical driver) is required for each type of control signal for the transistor used during the correction.

[0005] An object of the present technology is to provide a display device, a driving method, and an electronic device that can reduce the frame size by reducing the number of drivers that drive pixels, for example.

[0006] The present technology provides, for example, a display device having a plurality of pixels each including a first transistor that outputs a current according to an input voltage and a light-emitting element that emits light according to the output current of the first transistor, in which a correction operation for the threshold voltage of the first transistor is performed simultaneously for all pixels, and a light-emitting operation by the light-emitting element is performed simultaneously for all pixels.

[0007] The present technology is, for example, a method for driving a display device having a plurality of pixels each including a first transistor that outputs a current according to an input voltage and a light-emitting element that emits light according to the output current of the first transistor, wherein a correction operation for the threshold voltage of the first transistor is performed simultaneously for all pixels, and a light-emitting operation by the light-emitting element is performed simultaneously for all pixels.

[0008] The present technology relates to, for example, an electronic device having a display device of the present technology.

[0009] FIG. 1 is a diagram showing a schematic configuration example of a display device according to a first embodiment of the present technology. FIG. 2 is a diagram showing a configuration example of a pixel circuit included in the display device. FIG. 3 is a diagram for explaining an operation example (operation example 1) in a comparative example. FIG. 4 is an explanatory diagram of operation in each state. FIG. 5 is a diagram for explaining an operation example (operation example 2) in the comparative example. FIG. 6 is a diagram showing a schematic configuration example of a display device according to a comparative example. FIG. 7 is a diagram showing an operation example of a display device according to this embodiment. FIG. 8 is a diagram showing a schematic configuration example of a display device according to a second embodiment. FIG. 9 is a diagram showing a schematic configuration example of a display device according to a third embodiment. FIG. 10 is a diagram showing a flow of leakage current that affects a holding voltage. FIG. 11 is a diagram showing a configuration example of a display device according to a fourth embodiment. FIG. 12 is a diagram showing a configuration example of a pixel circuit. FIG. 13 is a diagram showing a configuration example of a pixel circuit. FIG. 14 is a diagram showing a configuration example of a pixel circuit. FIG. 15 is a diagram showing a configuration example of a pixel circuit. FIG. 16 is a diagram showing a configuration example of a pixel circuit. FIG. 17 is a perspective view showing an example of the appearance of a head-mounted display. Fig. 18 is a perspective view showing an example of the appearance of another head-mounted display. Fig. 19A is a front view showing an example of the appearance of a digital still camera. Fig. 19B is a rear view showing an example of the appearance of a digital still camera. Fig. 20 is a perspective view showing an example of the appearance of a television device. Fig. 21 is a perspective view showing an example of the appearance of a smartphone. Fig. 22A is a view showing an example of the interior of a vehicle from the rear to the front of the vehicle. Fig. 22B is a view showing an example of the interior of a vehicle from diagonally rear to diagonally front of the vehicle.

[0010] Hereinafter, embodiments of the present technology will be described with reference to the drawings. The description will be made in the following order. In this specification and the drawings, components having substantially the same functions or configurations will be assigned the same reference numerals, and redundant description will be omitted as appropriate. <1. First embodiment> 1-1. Example of schematic configuration of display device 1-2. Example of configuration of pixel circuit 1-3. Example of operation of comparative example 1 1-4. Example of operation of comparative example 2 1-5. Example of schematic configuration of display device of comparative example 1-6. Example of operation of this embodiment 1-7. Effects <2. Second embodiment> <3. Third embodiment> <4. Fourth embodiment> <5. Other example configurations of pixel circuit> <6. Modified examples> <7. Application examples>

[0011] 1. First Embodiment 1-1. Schematic Configuration Example of Display Device FIG. 1 is a diagram showing a schematic configuration example of a display device 1 according to a first embodiment of the present technology. The display device 1 is a device that displays images and the like using light-emitting elements. The light-emitting elements are, for example, LEDs (Light Emitting Diodes). LEDs include LEDs used in micro LED displays and OLEDs (Organic Light Emitting Diodes) used in organic EL (Electro-Luminescence) displays. Hereinafter, the display device 1 will be described as employing LEDs as light-emitting elements. The display device 1 is, for example, a display mounted in an electronic device. Specific examples of electronic devices to which the display device 1 can be applied will be described later.

[0012] The display device 1 has, as its component circuit blocks, a pixel section 2, a horizontal driver (H_Dr) 3, a WS driver (WS_Dr) 4, and a timing controller (TCON) 5. The WS driver 4 is a vertical driver (also called a scanning line driving circuit, vertical scanner, vertical transfer circuit, etc.). In other words, the display device 1 is composed of only one vertical driver. In the display device 1, for example, these circuit blocks are mounted on a substrate. The substrate includes, for example, a semiconductor substrate such as silicon.

[0013] The pixel section 2 has a plurality of pixels (pixel circuits) PIX arranged in a matrix of m rows and n columns (m and n are natural numbers), and forms a pixel region of the display device 1. The pixel region is an image formation region, i.e., a display region, of the display device 1. Note that FIG. 1 exemplarily shows one column and two rows of pixels PIX, and the other pixels PIX are not shown. The pixel section 2 is provided with pixels representing the three primary colors, for example, R (red), G (green), and B (blue), and represents a color image.

[0014] The pixel section 2 has signal lines SGL extending along the column direction of the pixel array and control lines WSL, DSL, and AZSL extending along the row direction of the pixel array. In the display device 1, the column direction is basically the V (vertical) direction, and the row direction is the horizontal direction. The signal lines SGL are provided for each pixel column, and the control lines WSL, DSL, and AZSL are provided for each pixel row. The signal lines SGL connect the output terminal of the corresponding column of the horizontal driver 3 to the pixel group of the corresponding column. The control lines WSL connect the output terminal of the corresponding row of the WS driver 4 to the pixel group of the corresponding row. Meanwhile, the control lines DSL connect the timing controller 5 to all pixels PIX in the pixel region. The control lines AZSL connect the timing controller 5 to all pixels PIX in the pixel region.

[0015] The horizontal driver 3 is configured, for example, by a RAMPDAC circuit that uses a ramp waveform analog signal to generate an output signal to the signal line SGL. The horizontal driver 3 is not limited to this, and may be configured, for example, by a voltage follower circuit having a voltage follower circuit in an output section to the signal line SGL. The horizontal driver 3 distributes image data input from the timing controller 5 to each signal line SGL, converts the distributed image data into pixel signals (e.g., gamma-corrected pixel signals), and outputs the converted image data to the corresponding signal lines SGL of the pixel section 2.

[0016] The WS driver 4 is configured, for example, by a shift register-type circuit having a shift register circuit in its signal input section. The WS driver 4 is not limited to this, and may be configured, for example, by an address decoder-type circuit having an address decoder in its signal input section. The WS driver 4 generates a shift signal for each pixel row from a signal input from the timing controller 5, and generates a control signal (signal WS (Write scan)) for each pixel row using the generated shift signal and outputs it to the control line WSL of the corresponding row. In other words, the WS driver 4 functions as a vertical driver that drives multiple pixels PIX row by row.

[0017] The timing controller 5 controls the operation timing of each circuit block constituting the display device 1. The timing controller 5 is connected to the horizontal driver 3 and the WS driver 4. The timing controller 5 outputs image data and a signal indicating the operation timing of the horizontal driver 3 to the horizontal driver 3. The timing controller 5 also outputs a signal indicating the operation timing of the WS driver 4 to the WS driver 4. The timing controller 5 is also connected to each of the control lines DSL and AZSL of the pixel unit 2. The timing controller 5 generates a control signal (signal DS (Drive scan)) and outputs it to the control line DSL, and generates a control signal (signal AZ (Auto Zero scan)) and outputs it to the control line AZSL.

[0018] 1-2. Example of Pixel Circuit Configuration FIG. 2 is a diagram showing an example of the configuration of a pixel PIX included in the display device 1. The pixel PIX shown in FIG. 2 includes capacitors C11 and C12, transistors MP12 to MP15, and a light-emitting element EL. Transistors MP12 to MP15 are P-type metal oxide semiconductor field effect transistors (MOSFETs). The gate of transistor MP12 is connected to a control line WSL, the source is connected to a signal line SGL, and the drain is connected to the gate of transistor MP14 and capacitor C12. One end of capacitor C11 is connected to a power supply line VCCP, and the other end is connected to capacitor C12, the drain of transistor MP13, and the source of transistor MP14. One end of capacitor C12 is connected to the other end of capacitor C11, the drain of transistor MP13, and the source of transistor MP14, and the other end is connected to the drain of transistor MP12 and the gate of transistor MP14. The gate of transistor MP13 is connected to the control line DSL, the source is connected to the power supply line VCCP, and the drain is connected to the source of transistor MP14, the other end of capacitor C11, and one end of capacitor C12. The gate of transistor MP14 is connected to the drain of transistor MP12 and the other end of capacitor C12, the source is connected to the drain of transistor MP13, the other end of capacitor C11, and one end of capacitor C12, and the drain is connected to the anode of the light-emitting element EL and the source of transistor MP15. The gate of transistor MP15 is connected to the control line AZSL, the source is connected to the drain of transistor MP14 and the anode of the light-emitting element EL, and the drain is connected to the power supply line VSS2. The anode of the light-emitting element EL is connected to the drain of transistor MP14 and the source of transistor MP15, and the cathode is connected to the power supply line Vcath.

[0019] The transistor MP12 (second transistor) functions as a write transistor (WSTr) that controls writing of a signal voltage to the signal line SGL. The transistor MP13 (third transistor) functions as a light-emitting control transistor (DSTr) that controls whether the light-emitting element EL emits light. The transistor MP14 (first transistor) functions as a drive transistor (DrvTr) that generates a drive current for the light-emitting element EL. The transistor MP15 (fourth transistor) functions as an initialization transistor (AZTr) that initializes the anode voltage of the light-emitting element EL. The back gates of the transistors MP12 to MP15 are connected to the power supply line VCCP. The capacitor C11 functions as an auxiliary capacitance (Csub) for the capacitor C12, and the capacitor C12 functions as a storage capacitance (Cs) that holds the input voltage to the transistor MP14.

[0020] With this configuration, in pixel PIX, when transistor MP12 is turned on, the voltage across capacitor C12 is set based on the pixel signal supplied from signal line SGL. Transistor MP13 is turned on and off based on the signal on control line DSL. While transistor MP13 is on, transistor MP14 passes a current corresponding to the voltage across capacitor C12 through light-emitting element EL. Light-emitting element EL emits light based on the current supplied from transistor MP14. In this way, pixel PIX emits light at a luminance corresponding to the pixel signal. Transistor MP15 is turned on and off based on the signal on control line AZSL. While transistor MP15 is on, the anode voltage of light-emitting element EL is initialized by being set to the voltage of power supply line VSS2.

[0021] The transistors MP12 to MP15 may be transistors using low temperature polysilicon (LTPS), and at least one of the transistors MP12 and MP15 may be a transistor using an oxide semiconductor.

[0022] 1-3. Operation Example 1 of Comparative Example Before describing a specific operation example of the display device 1 of this embodiment, an operation example of the pixel PIX of a comparative example will be described.

[0023] FIG. 3 is a diagram illustrating an example of operation (Operation Example 1) in a comparative example. The vertical direction (V1-V4 direction) in FIG. 3 represents the number of V (vertical) stages in the pixel array (e.g., V1 = 1st stage, V2 = 2nd stage, ...), and the horizontal direction (1H-4H direction) represents time. WS, DS, and AZ represent the levels of the signals WS, DS, and AZ. The "state" in the diagram represents the state of the pixel PIX. "Initialization" represents a state in which the input voltage to the transistor MP14 is being initialized, "Vth correction" represents a state in which the threshold voltage Vth of the transistor MP14 is being corrected, and "Writing" represents a state in which the signal voltage Vsig of the pixel signal is being written to the pixel PIX. "Emission" represents a state in which the light-emitting element EL is controlled to emit light, and "Quenching" represents a state in which the light-emitting element EL is extinguished. In this way, FIG. 3 exemplarily illustrates the emission timing for four stages V1 to V4. Specific operations in each state will be described later.

[0024] As shown in FIG. 3 , in the V1 stage, initialization, Vth correction, and writing are performed sequentially in the 1st horizontal period (H), and light is emitted in the next 1st horizontal period (H2). Note that this example illustrates an example in which one cycle is 4H, and light is extinguished in the 4th horizontal period. That is, each stage repeats the operations from the 1st horizontal period to the 4th horizontal period in sequence. In the V2 stage, initialization, Vth correction, and writing are performed sequentially in the 2nd horizontal period, and light is emitted in the next 1st horizontal period (H3). Light is then extinguished in the 1st horizontal period, which corresponds to the 4th horizontal period of one cycle. In the V3 stage, initialization, Vth correction, and writing are performed sequentially in the 3rd horizontal period, and light is emitted in the next 1st horizontal period (H4). Light is then extinguished in the 2nd horizontal period, which corresponds to the 4th horizontal period of one cycle. In the V4 stage, initialization, Vth correction, and writing are performed sequentially in the 4th horizontal period, and light is emitted in the next 1st horizontal period (H1). Light is then extinguished in the 3rd horizontal period, which corresponds to the 4th horizontal period of one cycle. In this way, in the example of operation shown in FIG. 3, the timing of each state is shifted by 1H for each step.

[0025] (Explanation of Operation in Each State) Here, the operation in each state will be explained. FIG. 4 is an explanatory diagram of the operation in each of the above-mentioned states. Specifically, FIG. 4 is an explanatory diagram of the operation (writing) in 1H of the V1 stage shown in FIG. 3. In the diagram, Vs, Vg, and Vd (=Vand) represent the voltages of the source, gate, and drain (=anode of the light-emitting element EL) of transistor MP14 (DrvTr). Since transistors MP12, MP13, and MP15 are P-channel types, when signals WS, DS, and AZ are at a low level (low potential), they are in a conductive state (active state), and when they are at a high level (high potential), they are in a non-conductive state (inactive state). In the following explanation, the conductive state will be referred to as the on state, and the non-conductive state will be referred to as the off state.

[0026] The period from time T0 (start of 1H) to T1 is the extinction period. At time T0, signals WS and DS are controlled to a high level, and signal AZ is controlled to a low level. That is, at time T0, transistors MP12 and MP13 are in an off state, and transistor MP15 is in an on state. With transistor MP13 in an off state, the current supply from the power supply line VCCP to transistor MP14 is cut off. Furthermore, with transistor MP15 in an on state, the drain current of transistor MP14 is discharged to the power supply line VSS2 via transistor MP15. As a result, no drive current flows to the light-emitting element EL, and the light-emitting element EL enters an extinction state.

[0027] The next period, from time T1 to time T3, is the initialization period. At time T1, signal WS switches from high to low, turning on transistor MP12. At this time, a signal of reference voltage Vofs is output to signal line SGL, and transistor MP12 turns on, initializing the gate voltage Vg of transistor MP14 to reference voltage Vofs. Also at time T1, signal DS also switches from high to low, turning on transistor MP13. This initializes the source voltage Vs of transistor MP14 to the power supply voltage of the power supply line VCCP. In other words, the gate-source voltage Vgs of transistor MP14 is Vgs = Vofs - the power supply voltage of the power supply line VCCP. Note that this gate-source voltage Vgs is set to a value suitable for Vth correction (described later) (e.g., a value that turns on transistor MP14). The state in which the input voltage of transistor MP14 is set to a predetermined value is the initialization state. At time T2 after the gate voltage Vg of transistor MP14 is initialized, signal WS switches from low to high, turning off transistor MP12. At time T3 after the source voltage Vs of transistor MP14 is initialized, signal DS switches from low to high, turning off transistor MP13.

[0028] The period from time T3 to T4 is the Vth correction period. At time T3, transistors MP12 and MP13 are turned off, causing the gate-source voltage Vgs of transistor MP14 to decrease and reach the threshold voltage Vth of transistor MP14. This causes the threshold voltage Vth of transistor MP14 to be held in capacitor C12. This operation of charging and holding the threshold voltage Vth of each transistor MP14 in capacitor C12 is Vth correction. Then, at time T4 after the Vth correction has been performed, signal WS again switches from high to low, turning transistor MP12 on.

[0029] The period from time T4 to time T5 is the period during which the signal voltage Vsig is written. That is, in this operation example, the Vth correction is completed by writing the signal voltage Vsig using the WS signal. From time T4 to time T5, the signal voltage Vsig is output as a pixel signal to the signal line SGL, and the transistor MP12 is turned on, so that the gate voltage Vg of the transistor MP14 becomes the signal voltage Vsig. Then, at time T5, the signal WS switches from low to high, turning off the transistor MP12.

[0030] After that, at time T6, signal AZ switches from low to high, turning transistor MP15 off. Then, at time T7, signal DS switches from high to low, turning transistor MP13 on. This causes current to be supplied to transistor MP14 from the power supply line VCCP through transistor MP13. Note that the gate voltage Vg of transistor MP14 after writing fluctuates in conjunction with fluctuations in source voltage Vs, because capacitor C12 is connected between the gate and source of transistor MP14.

[0031] The period from time T7 to the 3rd horizontal period is the light-emitting period. With transistor MP15 in the off state and transistor MP13 in the on state, the drain-source current Ids of transistor MP14 flows through the light-emitting element EL. This causes the anode voltage Vand of the light-emitting element EL to rise and reach the threshold voltage of the light-emitting element EL after the end of the 1H period, time T8, has elapsed, and the light-emitting element EL enters an emission state corresponding to the signal voltage Vsig at time T9. In other words, the anode-cathode voltage Voled of the light-emitting element EL reaches a value corresponding to the signal voltage Vsig, and the light-emitting element EL emits light with a luminance corresponding to the signal voltage Vsig. At this time, the threshold voltage Vth of transistor MP14 is offset by the voltage held in capacitor C12, so that the pixel PIX emits light with the variations in threshold voltage Vth corrected for. Then, in the extinction period at the start of the 4th hour, the signal DS switches from low level to high level, turning off the transistor MP13, and the signal AZ switches from high level to low level, turning on the transistor MP15.

[0032] In this way, up until now, initialization, Vth correction (at the same time, writing the signal voltage Vsig to the signal line SGL), writing, and light emission (and quenching) have been carried out sequentially for each 1V (vertical) stage.

[0033] The process from initialization to writing is performed within 1H, but simultaneously with the Vth correction, it is necessary to write the signal voltage Vsig to multiple columns of signal lines SGL using selector switches (SELs / w) on the driver side. The number of columns of signal lines SGL that can be written to varies depending on the 1H period, but the existence of periods for initialization and Vth correction limits the number of signal lines SGL that can be written to.

[0034] Furthermore, in Operation Example 1, the timing for switching the signal levels of the signals WS, DS, and AZ is shifted every V stage. Therefore, three vertical drivers for WS, DS, and AZ are required to operate pixel PIX in Operation Example 1. In this way, Operation Example 1 requires three vertical drivers to display an image by repeating initialization, Vth correction, writing, and light emission (extinction) at timings shifted every V stage.

[0035] 1-4. Operation Example 2 of Comparative Example FIG. 5 is a diagram for explaining an operation example (operation example 2) in the comparative example. It is also conceivable that the pixels PIX are driven by surface-to-surface emission in order to suppress display delays of each pixel PIX and improve moving image characteristics. Driving by surface-to-surface emission refers to a drive method in which the entire screen is illuminated (light emission starts) and extinguished (light emission ends) in a single batch.

[0036] In operation example 2 shown in Figure 5, in the V1 stage, initialization, Vth correction, and writing are performed sequentially in the 1st H, but no light is emitted in the next 1st H (2nd H). Note that this example illustrates an example where one cycle is 5H, and no light is emitted from the 2nd to 4th Hs, but light is emitted in the 5th H. In the next V2 stage, initialization, Vth correction, and writing are performed sequentially in the 2nd H, and light is emitted in the 5th H. In the V3 stage, initialization, Vth correction, and writing are performed sequentially in the 3rd H, and light is emitted in the 5th H. In the V4 stage, initialization, Vth correction, and writing are performed sequentially in the 4th H, and light is emitted in the 5th H.

[0037] As described above, in the operation example shown in FIG. 5 , initialization, Vth correction, and writing are performed for the second, third, and fourth stages, with the timing shifted by 1H for each stage, and all stages emit light simultaneously at the fifth stage. In other words, the timing of the light emission start control and the light emission end control are the same for all stages. In this operation example 2, initialization and writing are performed within 1H. As in operation example 1, there is a period for initialization and Vth correction, which limits the number of signal lines SGL that can be written. Furthermore, operation example 2 also requires the same driving system as operation example 1. In other words, because the signal level switching timing of signals WS, DS, and AZ differs for each V stage, three vertical drivers for WS, DS, and AZ are basically required, as in operation example 1. Below, we will explain an example configuration of a display device in a comparative example that performs the operations of operation examples 1 and 2.

[0038] 1-5. Schematic Configuration Example of a Display Device of a Comparative Example Fig. 6 is a diagram showing a schematic configuration example of a display device 10 of a comparative example. The display device 10 has, as circuit blocks of components, a pixel section 12, a horizontal driver 13, a WS driver 14A, a DS driver (DS_Dr) 14B, an AZ driver (AZ_Dr) 14C, and a timing controller 15. The WS driver 14A, the DS driver 14B, and the AZ driver 14C are vertical drivers. In other words, the display device 10 has three vertical driver systems.

[0039] The pixel section 12 has a plurality of pixels PIX arranged in a matrix, forming a pixel region of the display device 10. The pixel section 12 has signal lines SGL extending along the pixel column direction and control lines WSL, DSL, and AZSL extending along the pixel row direction. The signal lines SGL are provided for each pixel column, and the control lines WSL, DSL, and AZSL are provided for each pixel row. The signal lines SGL connect the output terminals of corresponding columns of the horizontal driver 13 to the pixel groups of the corresponding columns. The control lines WSL connect the output terminals of corresponding rows of the WS driver 14A to the pixel groups of the corresponding rows. The control lines DSL connect the output terminals of corresponding rows of the DS driver 14B to the pixel groups of the corresponding rows. The control lines AZSL connect the output terminals of corresponding rows of the AZ driver 14C to the pixel groups of the corresponding rows.

[0040] The horizontal driver 13 is configured with, for example, a RAMPDAC circuit or a voltage follower circuit. The horizontal driver 13 distributes image data input from the timing controller 15 to each signal line SGL, converts the distributed image data into pixel signals, and outputs the pixel signals to the corresponding signal lines SGL of the pixel unit 12.

[0041] Each of the WS driver 14A, DS driver 14B, and AZ driver 14C is configured, for example, with a shift register circuit or an address decoder circuit. The WS driver 14A generates a shift signal for each pixel row from a signal input from the timing controller 15, and generates a control signal (signal WS) for each pixel row using the generated shift signal and outputs it to the control line WSL of the corresponding row. The DS driver 14B generates a shift signal for each pixel row from a signal input from the timing controller 15, and generates a control signal (signal DS) for each pixel row using the generated shift signal and outputs it to the control line DSL of the corresponding row. The AZ driver 14C generates a shift signal for each pixel row from a signal input from the timing controller 15, and generates a control signal (signal AZ) for each pixel row using the generated shift signal and outputs it to the control line AZSL of the corresponding row.

[0042] The timing controller 15 controls the operation timing of each circuit block that constitutes the display device 10. The timing controller 15 is connected to the horizontal driver 13, the WS driver 14A, the DS driver 14B, and the AZ driver 14C. The timing controller 15 outputs image data and a signal indicating the operation timing of the horizontal driver 13 to the horizontal driver 13. The timing controller 15 also outputs a signal indicating the operation timing of the WS driver 14A to the WS driver 14A. The timing controller 15 outputs a signal indicating the operation timing of the DS driver 14B to the DS driver 14B. The timing controller 15 outputs a signal indicating the operation timing of the AZ driver 14C to the AZ driver 14C.

[0043] As described above, the display device 10 of the comparative example needs to have three vertical drivers to operate the pixel PIX in operation example 1 or operation example 2. Therefore, in the operation example of the pixel PIX in the present embodiment described below, initialization is performed simultaneously on the entire screen, Vth correction is performed simultaneously on the entire screen, and light emission and extinction are performed simultaneously on the entire screen, thereby eliminating the DS driver 14B and the AZ driver 14C and leaving only one vertical driver system, the WS driver 4, as shown in FIG. 1 , thereby reducing the frame size.

[0044] 1-6. Operation Example of the Present Embodiment FIG. 7 is a diagram showing an operation example of the display device 1 according to the present embodiment. Specifically, in the display device 1, the horizontal driver 3, the WS driver 4, and the timing controller 5 drive the pixel unit 2 so that each pixel PIX performs the following operation. Note that this example illustrates an example in which one cycle is 6H. In the V1 stage, initialization and Vth correction are performed sequentially in the first H. At the start time t0 of the first H before initialization, the signals WS and DS are controlled to a high level, and transistors MP12 and MP13 are in an off state. Also, at time t0, the signal AZ is at a low level, and transistor MP15 is in an on state. From this state, at time t1, the signals WS and DS switch to a low level, turning transistors MP12 and MP13 on, thereby entering the initialization state. Thereafter, at times t2 and t3, the signals WS and DS sequentially switch to a high level, turning transistors MP12 and MP13 off, thereby entering the Vth correction state. Next, at time t4, the signal AZ goes high, completing the Vth correction.

[0045] Then, writing is performed in the 2nd H. Specifically, at time t5, the signal WS switches from high to low, turning on the transistor MP12. Then, at time t6, the signal WS switches back to high, turning off the transistor MP12.

[0046] Then, light is emitted in the 6th H. Specifically, at time t7, the signal DS switches from high to low, turning on the transistor MP13. Then, at time t8 at the end of the 6th H, the signal DS switches to high, turning off the transistor MP13, and the light is extinguished. In other words, the light-emitting element EL is extinguished except for the 6th H, during which light emission is controlled.

[0047] Similarly, in the V2 stage, initialization and Vth correction are performed sequentially in the 1st H, then writing is performed in the 3rd H, and light is emitted in the 6th H. In the V3 stage, initialization and Vth correction are performed sequentially in the 1st H, then writing is performed in the 4th H, and light is emitted in the 6th H. In the V4 stage, initialization and Vth correction are performed sequentially in the 1st H, then writing is performed in the 5th H, and light is emitted in the 6th H. Note that the operation in each state is basically the same as that described in the comparative example above.

[0048] As described above, in this embodiment, initialization and Vth correction are performed for all V stages simultaneously in the first horizontal period. Specifically, the initialization start timing and initialization end timing are the same for all pixels PIX, and initialization control is performed for all pixels simultaneously. Furthermore, the Vth correction start timing and Vth correction end timing are the same for all pixels PIX, and Vth correction control is performed for all pixels simultaneously. Writing is performed by shifting 1H for each stage between the second horizontal period and the fifth horizontal period. Then, light emission is performed for all V stages simultaneously in the sixth horizontal period. Specifically, the light emission start timing and light emission end timing are the same for all pixels PIX, and light emission control is performed for all pixels simultaneously. In other words, initialization, Vth correction, and light emission / extinction are performed for all pixels simultaneously. As a result, only the WS driver 4 for WS, which shifts for each stage, is required. The remaining DS and AZ, which control initialization, Vth correction, and light emission (extinction), can use common signals for each stage, allowing driverless driving as shown in FIG. 1.

[0049] Here, we will explain the considerations when performing Vth correction for multiple V stages simultaneously, such as for all pixels simultaneously in the first embodiment. Performing Vth correction for multiple V stages simultaneously allows more of the 1H period to be used for writing the signal voltage Vsig. However, when performing Vth correction for multiple V stages simultaneously, the time from the start of Vth correction to the writing of the signal voltage Vsig to the pixel PIX (the correction end time in the comparative example) differs for each stage, resulting in brightness differences between stages. To address this issue, for example, the brightness differences can be dispersed by changing the order in which the signal voltages Vsig are written to the pixels PIX of multiple V stages that have undergone Vth correction simultaneously for each frame. Therefore, in this embodiment as well, it is preferable to write the signal voltages Vsig to the pixels PIX in an order that minimizes brightness variations.

[0050] 1-7. Effects As described above, the display device 1 according to this embodiment has multiple pixels PIX, each including a transistor MP14 that outputs a current corresponding to an input voltage and a light-emitting element EL that emits light corresponding to the output current of the transistor MP14. The threshold voltage Vth of the transistor MP14 is corrected for all pixels simultaneously, and the light-emitting element EL emits light simultaneously for all pixels. Specifically, initialization, Vth correction, and writing are performed in the first horizontal block (e.g., the first stage of a frame), and light emission is performed in the sixth horizontal block (H), allowing the remaining horizontal blocks (H) from the fifth horizontal block to be used for writing the signal voltage Vsig to the signal line SGL and the signal voltage Vsig to the pixel PIX. Furthermore, the DS and AZ drivers required in the comparative example are no longer necessary, making it possible to configure a vertical driver using only the WS driver 4. This allows for a narrower frame for the vertical driver portion.

[0051] <2. Second embodiment> In the above-described first embodiment, the control lines DSL and AZSL in the pixel section 2 extend for each pixel row along the row direction of the pixel array. However, since the control lines DSL and AZSL do not need to be provided for each pixel row, various layouts are possible.

[0052] FIG. 8 is a diagram showing a schematic configuration example of a display device 1 according to the second embodiment. As shown in the figure, the display device 1 according to this embodiment differs from the first embodiment in the layout of the control lines DSL and AZSL. Other points are the same as those of the first embodiment. That is, the display device 1 shown in FIG. 8 includes a pixel section 2, a horizontal driver 3, a WS driver 4, and a timing controller 5. The pixel section 2 includes a signal line SGL and control lines WSL, DSL, and AZSL. Note that the signal line SGL and the control line WSL are partially omitted in the figure.

[0053] In this display device 1, the control lines DSL and AZSL are each laid out in a comb-like pattern in the pixel section 2. Specifically, each of the control lines DSL and AZSL has a configuration in which a plurality of wires (only a portion of which is shown in FIG. 8 ) extending along the column direction of the pixel array branch off from a wire connected to the timing controller 5 and extending along the row direction. The wires extend for each pixel column along the column direction of the pixel array. Note that the branching direction is not limited to that shown in the figure. For example, the wires may branch in two opposite directions along the column direction. Furthermore, this comb-like layout may have the branching wires oriented along the row direction. In this way, the display device 1 of this embodiment can increase the degree of freedom in the layout of the pixel section 2. For example, the layout shown in FIG. 8 can reduce the number of wires along the row direction.

[0054] 9 is a diagram showing a schematic configuration example of a display device 1 according to a third embodiment. As in the second embodiment, the display device 1 according to this embodiment differs from the first embodiment in the layout of the control lines DSL and AZSL. Other points are the same as those in the first embodiment.

[0055] In the display device 1 shown in FIG. 9 , the control lines DSL and AZSL are each laid out in a two-dimensional grid pattern in the pixel section 2. The control lines DSL and AZSL do not need to be provided for each pixel row, so such a grid-pattern layout is also possible. The grid pattern can be determined as appropriate; for example, the control lines DSL and AZSL may surround each pixel PIX, or may surround a pixel group consisting of multiple pixels PIX in at least either the row or column direction. By arranging the control lines DSL and AZSL in a grid pattern, the degree of freedom in the layout of the pixel section 2 can be increased. Furthermore, connection to each pixel PIX can be easily and stably performed.

[0056] 4. Fourth Embodiment As described above, the reason why the luminance changes when the time from the start of Vth correction to writing differs is because the difference in time causes the potential in the pixel immediately before writing to differ. In Operational Examples 1 and 2 of the comparative example, writing is performed immediately after Vth correction in all stages, so that the correction time for each stage can be made uniform, thereby suppressing luminance variations. However, in the operation of the first embodiment described above, the time from Vth correction to writing differs for each stage, as shown in FIG. 7 . Therefore, the threshold voltage Vth charged and held in capacitor C12 between the end of Vth correction and writing is affected by leakage over time, and the correction state changes for each stage, which may result in luminance differences.

[0057] 10 is a diagram showing the flow of leakage current that affects the holding voltage of capacitor C12. In FIG. 10, dashed arrows indicate the flow of leakage current. As shown in the figure, capacitor C12 may be affected by leakage current in transistors MP12, MP13, and MP15.

[0058] 7, in the operation of the first embodiment described above, the time from writing to light emission also differs for each V stage. During Vth correction, signal AZ is brought forward relative to the light emission timing to be set to high level, and Vth correction is completed. This raises the concern that the current from capacitor C12 after Vth correction will flow to the light-emitting element EL depending on the time from writing to light emission, resulting in a deterioration in contrast. Therefore, in this embodiment, these points are improved as described below.

[0059] Fig. 11 is a diagram showing an example of the configuration of a display device 1 according to a fourth embodiment. The display device 1 of this embodiment differs from the first embodiment in the configuration of the pixel PIX. Other points are similar to those of the first embodiment. The pixel PIX shown in Fig. 11 has a transistor MP16 (adTr) provided between the transistor MP14 and the light-emitting element EL of the pixel PIX of the first embodiment (see Fig. 2).

[0060] 11 includes capacitors C11 and C12, transistors MP12 to MP16, and a light-emitting element EL. Transistors MP12 to MP16 are P-type MOSFETs. The gate of transistor MP12 is connected to a control line WSL, its source is connected to a signal line SGL, and its drain is connected to the gate of transistor MP14 and capacitor C12. One end of capacitor C11 is connected to a power supply line VCCP, and the other end is connected to capacitor C12, the drain of transistor MP13, and the source of transistor MP14. One end of capacitor C12 is connected to the other end of capacitor C11, the drain of transistor MP13, and the source of transistor MP14, and the other end is connected to the drain of transistor MP12 and the gate of transistor MP14. The gate of transistor MP13 is connected to a control line DSL, its source is connected to the power supply line VCCP, and its drain is connected to the source of transistor MP14, the other end of capacitor C11, and one end of capacitor C12. The gate of transistor MP14 is connected to the drain of transistor MP12 and the other end of capacitor C12, its source is connected to the drain of transistor MP13, the other end of capacitor C11, and one end of capacitor C12, and its drain is connected to the sources of transistors MP15 and MP16. The gate of transistor MP15 is connected to control line AZSL, its source is connected to the drain of transistor MP14 and the source of transistor MP16, and its drain is connected to power supply line VSS2. The gate of transistor MP16 is connected to control line DSL, its source is connected to the drain of transistor MP14 and the source of transistor MP15, and its drain is connected to the anode of light-emitting element EL. The anode of light-emitting element EL is connected to the drain of transistor MP16, and its cathode is connected to power supply line Vcath.

[0061] The transistor MP16 (current control transistor) functions as a transistor (adTr) that controls the flow of the drain current of the transistor MP14 to the anode of the light-emitting element EL. The back gate of the transistor MP16 is connected to the power supply line VCCP.

[0062] With this configuration, in pixel PIX, when transistor MP12 is turned on, the voltage across capacitor C12 is set based on the pixel signal supplied from signal line SGL. Transistor MP13 is turned on and off based on the signal on control line DSL. During the period when transistor MP13 is on, transistor MP14 passes a current corresponding to the voltage across capacitor C12 through light-emitting element EL. Transistor MP16 is turned on and off based on the signal on control line DSL. During the period when transistor MP16 is on, light-emitting element EL emits light based on the current supplied from transistor MP14. In this way, pixel PIX emits light at a luminance corresponding to the pixel signal. Transistor MP15 is turned on and off based on the signal on control line AZSL. During the period when transistor MP15 is on, the anode voltage of light-emitting element EL is initialized by being set to the voltage of power supply line VSS2.

[0063] The transistors MP12 to MP16 may be transistors using low temperature polysilicon (LTPS). In this embodiment, at least one of the transistors MP12 and MP15 is configured as a transistor using an oxide semiconductor.

[0064] The display device 1 shown in FIG. 11 has a substrate structure in which an oxide semiconductor is stacked on a silicon (Si) substrate serving as a base. The silicon substrate includes, for example, amorphous silicon or polycrystalline silicon. The oxide semiconductor includes, for example, indium-gallium-zinc oxide (IGZO) to form a thin-film transistor (TFT) layer. Note that the oxide semiconductor is not limited to this, and may include, for example, indium-gallium oxide, indium-tin-zinc oxide, etc. At least one of the switching transistors MP12 and MP15 is configured as an oxide semiconductor transistor including this oxide semiconductor layer. The leakage current reduction effect of the oxide semiconductor can suppress the influence of leakage current on the holding voltage of capacitor C12 after the above-described Vth correction.

[0065] Furthermore, by providing the transistor MP16, the signal DS turns on the transistor MP16 during the light-emitting period, allowing current to flow through the light-emitting element EL. The signal DS turns off the transistor MP16 during the non-light-emitting period, cutting off the current supply to the light-emitting element EL. This prevents charge leakage (indicated by the dashed arrow in FIG. 11 ) of the threshold voltage Vth of the capacitor C12 due to charge accumulation in the light-emitting element EL.

[0066] As described above, the display device 1 of this embodiment not only achieves the effects of the first embodiment described above, but also employs oxide semiconductor transistors as some of the transistors constituting the pixel PIX and adds transistor MP16 between transistor MP14 and the light-emitting element EL, thereby suppressing charge leakage that affects the holding voltage of capacitor C12. Specifically, transistor MP13 is provided between transistor MP14 and the power supply line VCCP of the current source for the light-emitting element EL, controlling the connection state between the power supply line VCCP and transistor MP14. Transistors MP16 and MP13 are controlled by a common signal WS, thereby reducing the number of control lines. Note that the control line connected to the gate of transistor MP16 may be separate from control line DSL.

[0067] 5. Other Configuration Examples of Pixel Circuits The following describes other configuration examples of the pixel PIX included in the pixel section 2 of the display device 1. Note that the following configuration examples are merely illustrative and do not exclude other configurations.

[0068] (First Configuration Example) Figure 12 shows an example of the configuration of pixel PIX. Pixel PIX has a capacitor C01, transistors MN02 and MN03, and a light-emitting element EL. Transistors MN02 and MN03 are N-type MOSFETs (Metal Oxide Semiconductor Field Effect Transistors). The gate of transistor MN02 is connected to a control line WSL, the drain is connected to a signal line SGL, and the source is connected to the gate of transistor MN03 and capacitor C01. One end of capacitor C01 is connected to the source of transistor MN02 and the gate of transistor MN03, and the other end is connected to the source of transistor MN03 and the anode of light-emitting element EL. The gate of transistor MN03 is connected to the source of transistor MN02 and one end of capacitor C01, the drain is connected to the power supply line VCCP, and the source is connected to the other end of capacitor C01 and the anode of light-emitting element EL. The anode of the light-emitting element EL is connected to the source of the transistor MN03 and the other end of the capacitor C01, and the cathode is connected to the power supply line Vcath. The voltage of the power supply line VCCP is appropriately switched between a first voltage and a second voltage lower than the first voltage.

[0069] With this configuration, in pixel PIX, when transistor MN02 is turned on, the voltage across capacitor C01 is set based on the pixel signal supplied from signal line SGL. During a period when the voltage of power supply line VCCP is at a first voltage, transistor MN03 passes a current corresponding to the voltage across capacitor C01 through light-emitting element EL. Light-emitting element EL emits light based on the current supplied from transistor MN03. In this way, pixel PIX emits light at a luminance corresponding to the pixel signal. During a period when the voltage of power supply line VCCP is at a second voltage, light-emitting element EL is turned off.

[0070] (Second Configuration Example) Figure 13 shows another configuration example of pixel PIX. This pixel PIX has a capacitor C21, transistors MN22 to MN25, and a light-emitting element EL. Transistors MN22 to MN25 are N-type MOSFETs. The gate of transistor MN22 is connected to a control line WSL, the drain is connected to a signal line SGL, and the source is connected to the gate of transistor MN24 and capacitor C21. One end of capacitor C21 is connected to the source of transistor MN22 and the gate of transistor MN24, and the other end is connected to the source of transistor MN24, the drain of transistor MN25, and the anode of light-emitting element EL. The gate of transistor MN23 is connected to a control line DSL, the drain is connected to a power supply line VCCP, and the source is connected to the drain of transistor MN24. The gate of transistor MN24 is connected to the source of transistor MN22 and one end of capacitor C21, the drain is connected to the source of transistor MN23, the source is connected to the other end of capacitor C21, the drain of transistor MN25, and the anode of light-emitting element EL. The gate of transistor MN25 is connected to control line AZSL, the drain is connected to the source of transistor MN24, the other end of capacitor C21, and the anode of light-emitting element EL, and the source is connected to power supply line VSS. The anode of light-emitting element EL is connected to the source of transistor MN24, the drain of transistor MN25, and the other end of capacitor C21, and the cathode is connected to power supply line Vcath.

[0071] With this configuration, in pixel PIX, when transistor MN22 is turned on, the voltage across capacitor C21 is set based on the pixel signal supplied from signal line SGL. Transistor MN23 is turned on and off based on the signal on control line DSL. While transistor MN23 is on, transistor MN24 passes a current corresponding to the voltage across capacitor C21 through light-emitting element EL. The light-emitting element EL emits light based on the current supplied from transistor MN24. In this way, pixel PIX emits light at a luminance corresponding to the pixel signal. Transistor MN25 is turned on and off based on the signal on control line AZSL. While transistor MN25 is on, the anode voltage of light-emitting element EL is initialized by being set to the voltage of power supply line VSS.

[0072] The transistors MN22 to MN25 may be transistors using low temperature polysilicon (LTPS), and at least one of the transistors MN22 and MN25 may be a transistor using an oxide semiconductor.

[0073] (Third Configuration Example) Figure 14 shows another configuration example of pixel PIX. This pixel PIX has a capacitor C51, transistors MP52 to MP60, and a light-emitting element EL. Transistors MP52 to MP60 are P-type MOSFETs. The gate of transistor MP52 is connected to a control line WSL, its source is connected to a signal line SGL, and its drain is connected to the drain of transistor MP53 and the source of transistor MP54. The gate of transistor MP53 is connected to a control line DSL, its source is connected to a power supply line VCCP, and its drain is connected to the drain of transistor MP52 and the source of transistor MP54. The gate of transistor MP54 is connected to the source of transistor MP55, the drain of transistor MP57, and capacitor C51, its source is connected to the drains of transistors MP52 and MP53, and its drain is connected to the sources of transistors MP58 and MP59. One end of capacitor C51 is connected to the power supply line VCCP, and the other end is connected to the gate of transistor MP54, the source of transistor MP55, and the drain of transistor MP57. Capacitor C51 may include two capacitors connected in parallel. Transistor MP55 has a gate connected to control line AZSL1, a source connected to the gate of transistor MP54, the drain of transistor MP57, and the other end of capacitor C51, and a drain connected to the source of transistor MP56. Transistor MP56 has a gate connected to control line AZSL1, a source connected to the drain of transistor MP55, and a drain connected to power supply line VSS. Transistor MP57 has a gate connected to control line WSL, a drain connected to the gate of transistor MP54, the source of transistor MP55, and the other end of capacitor C51, and a source connected to the drain of transistor MP58. The gate of the transistor MP58 is connected to the control line WSL, the drain is connected to the source of the transistor MP57, and the source is connected to the drain of the transistor MP54 and the source of the transistor MP59.The gate of transistor MP59 is connected to the control line DSL, the source is connected to the drain of transistor MP54 and the source of transistor MP58, and the drain is connected to the source of transistor MP60 and the anode of light-emitting element EL. The gate of transistor MP60 is connected to control line AZSL2, the source is connected to the drain of transistor MP59 and the anode of light-emitting element EL, and the drain is connected to the power supply line VSS. The anode of light-emitting element EL is connected to the drain of transistor MP59 and the source of transistor MP60, and the cathode is connected to the power supply line Vcath.

[0074] With this configuration, in pixel PIX, transistors MP52, MP54, MP58, and MP57 are turned on, and the voltage across capacitor C51 is set based on the pixel signal supplied from signal line SGL. Transistors MP53 and MP59 are turned on and off based on the signal on control line DSL. While transistors MP53 and MP59 are on, transistor MP54 passes a current corresponding to the voltage across capacitor C51 through light-emitting element EL. The light-emitting element EL emits light based on the current supplied from transistor MP54. In this way, pixel PIX emits light at a luminance corresponding to the pixel signal. Transistors MP55 and MP56 are turned on and off based on the signal on control line AZSL1. While transistors MP55 and MP56 are on, the gate voltage of transistor MP54 is initialized by being set to the voltage of power supply line VSS. Transistor MP60 is turned on and off based on the signal on control line AZSL2. During the period in which the transistor MP60 is in the on state, the voltage of the anode of the light-emitting element EL is initialized by being set to the voltage of the power supply line VSS.

[0075] The transistors MP52 to MP60 may be transistors using low temperature polysilicon (LTPS), and at least one of the transistors MP55 to MP58 and MP60 may be a transistor using an oxide semiconductor.

[0076] 15 shows another example of the configuration of the pixel PIX. The signal on the control line WSNL and the signal on the control line WSPL are mutually inverted signals.

[0077] The pixel PIX has capacitors C61 and C62, transistors MN63, MP64, and MN65 to MN67, and a light-emitting element EL. The transistors MN63, MN65 to MN67 are N-type MOSFETs, and the transistor MP64 is a P-type MOSFET. The gate of the transistor MN63 is connected to a control line WSNL, the drain is connected to a signal line SGL and the source of the transistor MP64, and the source is connected to the drain of the transistor MP64, the capacitors C61 and C62, and the gate of the transistor MN65. The gate of the transistor MP64 is connected to a control line WSPL, the source is connected to the signal line SGL and the drain of the transistor MN63, and the drain is connected to the source of the transistor MN63, the capacitors C61 and C62, and the gate of the transistor MN65. The capacitor C61 is configured using, for example, a metal oxide metal (MOM) capacitor, with one end connected to the source of transistor MN63, the drain of transistor MP64, capacitor C62, and the gate of transistor MN65, and the other end connected to the power supply line VSS2. The capacitor C61 may be configured using, for example, a metal oxide metal (MOS) capacitor or a metal insulator metal (MIM) capacitor. The capacitor C62 is configured using, for example, a MOS capacitor, with one end connected to the source of transistor MN63, the drain of transistor MP64, one end of capacitor C61, and the gate of transistor MN65, and the other end connected to the power supply line VSS2. The capacitor C62 may be configured using, for example, a MOM capacitor or a MIM capacitor. The other end of the capacitor C62 may be connected to the power supply line VSS3 (not shown). The gate of transistor MN65 is connected to the source of transistor MN63, the drain of transistor MP64, and one end of capacitors C61 and C62, the drain is connected to the power supply line VCCP, and the source is connected to the drains of transistors MN66 and MN67. The gate of transistor MN66 is connected to control line AZL, the drain is connected to the source of transistor MN65 and the drain of transistor MN67, and the source is connected to power supply line VSS1.The gate of transistor MN67 is connected to the control line DSL, the drain is connected to the source of transistor MN65 and the drain of transistor MN66, and the source is connected to the anode of light-emitting element EL. The anode of light-emitting element EL is connected to the source of transistor MN67, and the cathode is connected to the power supply line Vcath. Note that transistor MN67 and the control line DSL may be omitted, and the source of transistor MN65 may be connected to the drain of transistor MN66 and the anode of light-emitting element EL.

[0078] With this configuration, in pixel PIX, when at least one of transistors MN63 and MP64 is turned on, the voltage across capacitors C61 and C62 is set based on the pixel signal supplied from signal line SGL. Transistor MN67 is turned on and off based on the signal on control line DSL. While transistor MN67 is on, transistor MN65 passes a current corresponding to the voltage across capacitors C61 and C62 through light-emitting element EL. Light-emitting element EL emits light based on the current supplied from transistor MP65. In this way, pixel PIX emits light at a luminance corresponding to the pixel signal. Transistor MN66 may be turned on and off based on the signal on control line AZL. Transistor MN66 may also function as a resistor element having a resistance value corresponding to the signal on control line AZL. In this case, transistors MN65 and MN66 form a so-called source follower circuit.

[0079] The transistors MN63, MP64, MN65 to MN67 may be transistors using low temperature polysilicon (LTPS), and at least one of the transistors MN63, MP64, and MN66 may be a transistor using an oxide semiconductor.

[0080] (Fifth Configuration Example) Figure 16 shows another configuration example of pixel PIX. This pixel PIX has a capacitor C71, transistors MN72 to MN77, and a light-emitting element EL. Transistors MN72 to MN77 are N-type MOSFETs. The gate of transistor MN72 is connected to a control line WSL, the drain is connected to a signal line SGL, and the source is connected to the source of transistor MN74 and the drain of transistor MN75. One end of capacitor C71 is connected to the gate of transistor MN74 and the source of transistor MN76, and the other end is connected to the drain of transistor MN77, the source of transistor MN75, and the anode of light-emitting element EL. The gate of transistor MN73 is connected to a control line DSL1, the drain is connected to a power supply line VCCP, and the source is connected to the drain of transistor MN74 and the drain of transistor MN76. The gate of transistor MN74 is connected to the source of transistor MN76 and one end of capacitor C71, the drain is connected to the source of transistor MN73 and the drain of transistor MN76, and the source is connected to the source of transistor MN72 and the drain of transistor MN75. The gate of transistor MN75 is connected to control line DSL2, the drain is connected to the source of transistor MN72 and the source of transistor MN74, and the source is connected to the other end of capacitor C71, the drain of transistor MN77, and the anode of light-emitting element EL. The gate of transistor MN76 is connected to control line AZSL, the drain is connected to the source of transistor MN73 and the drain of transistor MN74, and the source is connected to the gate of transistor MN74 and one end of capacitor C71. The gate of transistor MN77 is connected to control line AZSL, the drain is connected to the other end of capacitor C71, the source of transistor MN75, and the anode of light-emitting element EL, and the source is connected to power supply line VSS. The anode of the light emitting element EL is connected to the source of the transistor MN75, the drain of the transistor MN77 and the other end of the capacitor C71, and the cathode is connected to the power supply line Vcath.

[0081] With this configuration, in pixel PIX, transistors MN72, MN74, and MN76 are turned on, and the voltage across capacitor C71 is set based on the pixel signal supplied from signal line SGL. Transistor MN73 is turned on and off based on the signal on control line DSL1, and transistor MN75 is turned on and off based on the signal on control line DSL2. While transistors MN73 and MN75 are on, transistor MN74 passes a current corresponding to the voltage across capacitor C71 through light-emitting element EL. Light-emitting element EL emits light based on the current supplied from transistor MN74. In this way, pixel PIX emits light at a luminance corresponding to the pixel signal. Transistor MN77 is turned on and off based on the signal on control line AZSL. While transistor MN77 is on, the anode voltage of light-emitting element EL is initialized by being set to the voltage of power supply line VSS.

[0082] The transistors MN72 to MN77 may be transistors using low temperature polysilicon (LTPS), and the transistor MN76 may be a transistor using an oxide semiconductor.

[0083] <6. Modifications> Although the embodiments of the present technology have been specifically described above, the content of the present technology is not limited to the above-described embodiments, and various modifications based on the technical concept of the present technology are possible. For example, the configurations, methods, processes, materials, shapes, directions, and numerical values ​​of the above-described embodiments can be combined, replaced, or modified without departing from the spirit of the present technology. Furthermore, one element can be divided into two or more elements, and some elements can be omitted. Furthermore, as long as the present technology is applicable, the above-described configurations may be appropriately deleted, modified, or added with other configurations, or replaced with alternative configurations. Furthermore, the present technology may be an appropriate combination of the above-described embodiments.

[0084] For example, the present technology can be applied to various displays. For example, the present technology can be applied to display panels such as SXRD (Silicon X-tal Reflective Display: registered trademark) used in projectors, and phase modulation panels using SLM (Spatial Light Modulator) for displaying holograms. In addition, the present technology can be applied to panels such as LCOS (Liquid crystal on silicon, LCoS is a trademark) and HTPS (High Temperature Poly-Silicon).

[0085] 7. Application Examples Next, application examples of the display systems described in the above embodiments and modifications will be described.

[0086] 17 shows an example of the appearance of a head-mounted display 110. The head-mounted display 110 has, for example, ear hooks 112 for wearing on the user's head on both sides of a glasses-shaped display unit 111. The techniques according to the above-described embodiments and the like can be applied to such a head-mounted display 110.

[0087] (Application Example 2) FIG. 18 shows an example of the appearance of another head-mounted display 120. The head-mounted display 120 is a see-through head-mounted display having a main body 121, an arm 122, and a lens barrel 123. This head-mounted display 120 is attached to eyeglasses 128. The main body 121 has a control board and a display unit for controlling the operation of the head-mounted display 120. The display unit emits image light of a display image. The arm 122 connects the main body 121 to the lens barrel 123 and supports the lens barrel 123. The lens barrel 123 projects the image light supplied from the main body 121 via the arm 122 toward the user's eyes via lenses 129 of the eyeglasses 128. The techniques according to the above-described embodiments and the like can be applied to such a head-mounted display 120.

[0088] The head-mounted display 120 is a so-called light guide plate type head-mounted display, but is not limited to this and may be, for example, a so-called birdbath type head-mounted display. The birdbath type head-mounted display includes, for example, a beam splitter and a partially transparent mirror. The beam splitter outputs light encoded with image information toward the mirror, and the mirror reflects the light toward the user's eyes. Both the beam splitter and the partially transparent mirror are partially transparent. This allows light from the surrounding environment to reach the user's eyes.

[0089] (Application Example 3) Figures 19A and 19B show an example of the appearance of a digital still camera 130, with Figure 19A showing a front view and Figure 19B showing a rear view. This digital still camera 130 is a single-lens reflex camera with interchangeable lenses and includes a camera body 131, a photographing lens unit 132, a grip 133, a monitor 134, and an electronic viewfinder 135. The photographing lens unit 132 is an interchangeable lens unit and is provided near the center of the front of the camera body 131. The grip 133 is provided on the left side of the front of the camera body 131, and is held by the photographer. The monitor 134 is provided to the left of the center of the back of the camera body 131. The electronic viewfinder 135 is provided above the monitor 134 on the back of the camera body 131. By looking through this electronic viewfinder 135, the photographer can visually confirm the optical image of the subject guided by the photographing lens unit 132 and determine the composition. The techniques according to the above-described embodiments and the like can be applied to the electronic viewfinder 135.

[0090] 20 shows an example of the appearance of a television device 140. The television device 140 has an image display screen unit 141 including a front panel 142 and a filter glass 143. The techniques according to the above-described embodiments and the like can be applied to this image display screen unit 141.

[0091] 21 shows an example of the appearance of a smartphone 150. The smartphone 150 has a display unit 151 that displays various information and an operation unit 152 that includes buttons and the like that accept operation inputs from a user. The techniques according to the above-described embodiments and the like can be applied to this display unit 151.

[0092] (Application Example 6) Figures 22A and 22B show an example configuration of a vehicle to which the technology of the present disclosure is applied, where Figure 22A shows an example of the interior of the vehicle as seen from the rear of vehicle 200, and Figure 22B shows an example of the interior of the vehicle as seen from the left rear of vehicle 200.

[0093] The vehicle in Figures 22A and 22B has a center display 201, a console display 202, a head-up display 203, a digital rearview mirror 204, a steering wheel display 205, and a rear entertainment display 206.

[0094] The center display 201 is disposed on the dashboard 261 in a position facing the driver's seat 262 and the passenger's seat 263. While FIG. 22A illustrates an example of a horizontally elongated center display 201 extending from the driver's seat 262 side to the passenger's seat 263 side, the screen size and location of the center display 201 are not limited to this. The center display 201 can display information detected by various sensors. As a specific example, the center display 201 can display an image captured by an image sensor, a distance image to obstacles in front of or to the side of the vehicle measured by a ToF sensor, and the body temperature of an occupant detected by an infrared sensor. The center display 201 can be used to display, for example, at least one of safety-related information, operation-related information, a life log, health-related information, authentication / identification-related information, and entertainment-related information.

[0095] The safety-related information includes information based on sensor detection results, such as detection of drowsiness, distraction, child mischief, whether a seatbelt is fastened, and whether a passenger is abandoned. The operation-related information includes gesture information related to passenger operations detected by sensors. The gestures may include operations of various vehicle equipment, such as air conditioning, navigation, audiovisual (AV) equipment, and lighting. The life log includes life logs of all passengers. For example, the life log includes a record of each passenger's behavior. By acquiring and storing the life log, it is possible to determine the condition of the passengers at the time of an accident. The health-related information includes the passenger's body temperature detected using a temperature sensor and information on the passenger's health condition estimated based on the detected body temperature. Alternatively, the passenger's health condition information may be estimated based on the passenger's face captured by an image sensor. Furthermore, the passenger's health condition information may be estimated based on the passenger's responses obtained through an automated voice conversation with the passenger. The authentication / identification-related information includes information on a keyless entry function that uses a sensor to perform facial authentication, a function that automatically adjusts the seat height and position by facial recognition, etc. The entertainment-related information includes information on AV device operations by occupants detected by the sensor, and information on content to be displayed that is appropriate for the occupants detected and recognized by the sensor.

[0096] The console display 202 can be used to display, for example, life log information. The console display 202 is disposed near a shift lever 265 on a center console 264 between a driver's seat 262 and a passenger seat 263. The console display 202 can also display information detected by various sensors. The console display 202 may also display an image of the vehicle's surroundings captured by an image sensor, or an image showing the distance to an obstacle around the vehicle.

[0097] The head-up display 203 is virtually displayed behind a windshield 266 in front of the driver's seat 262. The head-up display 203 can be used to display, for example, at least one of safety-related information, operation-related information, a life log, health-related information, authentication / identification-related information, and entertainment-related information. Since the head-up display 203 is often virtually disposed in front of the driver's seat 262, it is suitable for displaying information directly related to vehicle operation, such as the vehicle speed, the remaining fuel level, and the remaining battery level.

[0098] The digital rearview mirror 204 can not only display the rear of the vehicle, but also display the state of passengers in the rear seats, and can therefore be used to display life log information of passengers in the rear seats, for example.

[0099] The steering wheel display 205 is disposed near the center of the vehicle's steering wheel 267. The steering wheel display 205 can be used to display at least one of, for example, safety-related information, operation-related information, a life log, health-related information, authentication / identification-related information, and entertainment-related information. In particular, because the steering wheel display 205 is located near the driver's hands, it is suitable for displaying life log information such as the driver's body temperature, and for displaying information related to the operation of AV equipment, air conditioning equipment, etc.

[0100] The rear entertainment display 206 is attached to the rear side of the driver's seat 262 and the passenger seat 263 and is intended for viewing by rear seat passengers. The rear entertainment display 206 can be used to display, for example, at least one of safety-related information, operation-related information, a life log, health-related information, authentication / identification-related information, and entertainment-related information. In particular, since the rear entertainment display 206 is located in front of the rear seat passengers, information related to the rear seat passengers is displayed on the rear entertainment display 206. The rear entertainment display 206 may display, for example, information related to the operation of an AV device or an air conditioning system, or may display the results of measurement of the body temperature of the rear seat passengers using a temperature sensor.

[0101] The techniques according to the above-described embodiments can be applied to the center display 201, the console display 202, the head-up display 203, the digital rearview mirror 204, the steering wheel display 205, and the rear entertainment display 206.

[0102] The present technology may also be configured as follows. (1) A display device having a plurality of pixels each including a first transistor that outputs a current according to an input voltage and a light-emitting element that emits light according to the output current of the first transistor, wherein a correction operation for a threshold voltage of the first transistor is performed simultaneously for all pixels, and a light-emitting operation by the light-emitting element is performed simultaneously for all pixels. (2) The display device according to (1), wherein an initialization operation for initializing the input voltage to a predetermined voltage is performed simultaneously for all pixels before the correction operation. (3) The display device according to (1) or (2), including control lines that supply signals for controlling the correction operation and the light-emitting operation to all pixels, the control lines including control lines laid out in a comb-like pattern in a pixel region where the pixels are formed. (4) The display device according to (1) or (2), including control lines that supply signals for controlling the correction operation and the light-emitting operation to all pixels, the control lines including control lines laid out in a two-dimensional lattice pattern in a pixel region where the pixels are formed. (5) The display device according to any one of (1) to (4), wherein the pixel includes a capacitor that holds the input voltage and a second transistor that controls writing of the input voltage to the capacitor, the plurality of pixels are arranged in a matrix, and a driver that drives the plurality of pixels row by row is only a driver that drives the second transistor. (6) The display device according to any one of (1) to (5), wherein the pixel includes an oxide semiconductor transistor as a transistor that controls the correction operation and the light-emitting operation. (7) The display device according to any one of (1) to (6), wherein a current control transistor is provided between the first transistor and the light-emitting element, the current control transistor controlling a conduction state between the first transistor and the light-emitting element. (8) The display device according to (7), wherein a third transistor is provided between a power supply line of a current source of the light-emitting element and the first transistor, the third transistor controlling a connection state between the power supply line and the first transistor, and the current control transistor and the third transistor are controlled by a signal on a common control line.(9) The display device according to (7) or (8), wherein a fourth transistor is connected between the first transistor and the current control transistor, for initializing an anode voltage of the light-emitting element to a predetermined voltage. (10) The display device according to (7) or (8), wherein a fourth transistor is connected between the current control transistor and the light-emitting element, for initializing an anode voltage of the light-emitting element to a predetermined voltage. (11) A method for driving a display device having a plurality of pixels, each including a first transistor that outputs a current according to an input voltage, and a light-emitting element that emits light according to the output current of the first transistor, the method comprising: simultaneously performing a correction operation for the threshold voltage of the first transistor for all pixels; and simultaneously performing a light-emitting operation by the light-emitting element for all pixels. (12) An electronic device having the display device according to any of (1) to (10).

[0103] 1. Display device, 2. Pixel section, 3. Horizontal driver, 4. WS driver, 5. Timing controller, PIX. Pixel, SGL. . . signal line, WSL, DSL, AZSL. .

Claims

1. A display device having a plurality of pixels each including a first transistor that outputs a current according to an input voltage and a light-emitting element that emits light according to the output current of the first transistor, wherein the threshold voltage of the first transistor is corrected simultaneously for all pixels, and light is emitted by the light-emitting element simultaneously for all pixels.

2. The display device according to claim 1, wherein an initialization operation for initializing the input voltage to a predetermined voltage is performed simultaneously for all pixels before the correction operation.

3. The display device according to claim 1, further comprising control lines for supplying signals for controlling the correction operation and the light-emitting operation to all of the pixels, the control lines including control lines laid out in a comb-like shape in a pixel region in which the pixels are formed.

4. The display device according to claim 1, further comprising control lines for supplying signals for controlling the correction operation and the light-emitting operation to all of the pixels, the control lines including control lines laid out in a two-dimensional lattice pattern in a pixel region in which the pixels are formed.

5. The display device according to claim 1, wherein the pixel includes a capacitor that holds the input voltage and a second transistor that controls writing of the input voltage to the capacitor, the plurality of pixels are arranged in a matrix, and the driver that drives the plurality of pixels row by row is only a driver that drives the second transistor.

6. The display device according to claim 1, wherein the pixel has an oxide semiconductor transistor as a transistor for controlling the correction operation and the light-emitting operation.

7. The display device according to claim 1, further comprising a current control transistor between said first transistor and said light emitting element, said current control transistor controlling the conduction state between said first transistor and said light emitting element.

8. The display device according to claim 7, further comprising a third transistor between a power supply line of a current source of the light-emitting element and the first transistor, for controlling a connection state between the power supply line and the first transistor, and the current control transistor and the third transistor are controlled by a signal on a common control line.

9. The display device according to claim 7, wherein a fourth transistor is connected between the first transistor and the current control transistor, for initializing the anode voltage of the light-emitting element to a predetermined voltage.

10. The display device according to claim 7, wherein a fourth transistor for initializing the anode voltage of said light-emitting element to a predetermined voltage is connected between said current control transistor and said light-emitting element.

11. A method for driving a display device having a plurality of pixels each including a first transistor that outputs a current according to an input voltage and a light-emitting element that emits light according to the output current of the first transistor, wherein the method simultaneously performs a correction operation for the threshold voltage of the first transistor for all pixels and simultaneously performs a light-emitting operation by the light-emitting element for all pixels.

12. An electronic device comprising the display device according to claim 1.

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