Display device

Abstract

A display device is provided. The display device comprises: a data line and a scan line electrically connected to each pixel; a scan driver electrically connected to the scan line; an electrostatic discharge protection circuit electrically connected to the data line; and a first line electrically connected to the scan line and the electrostatic discharge protection circuit, and receiving a first voltage. The first line crosses a second line, the first line comprises a bridge electrode, the bridge electrode is disposed below an uppermost electrode included in the electrostatic discharge protection circuit, and a line portion is disposed below or on the same layer as the uppermost electrode included in the electrostatic discharge protection circuit.

Description

display device

[0001] The present invention relates to a display device, and more specifically, to a display device including an electrostatic protection circuit.

[0002] The display device includes a display panel including a plurality of pixels for displaying an image, a scan driver providing scan signals to the pixels, a data driver providing data voltages to the pixels, and a timing controller controlling the scan driver and the data driver.

[0003] The scan driver outputs scan signals in response to scan control signals provided by the timing controller. The data driver outputs data voltages in response to data control signals provided by the timing controller.

[0004] An object of the present invention is to provide a display device with reduced defects in the electrostatic protection circuit.

[0005] According to one embodiment of the present invention, a display device includes a plurality of pixels arranged in a display area, a data line electrically connected to a corresponding pixel among the plurality of pixels and overlapping the display area and a non-display area adjacent to the display area, a scan line electrically connected to a corresponding pixel among the plurality of pixels and overlapping the display area and the non-display area, a scan driver arranged in the non-display area and electrically connected to the scan line, an electrostatic protection circuit arranged in the non-display area and electrically connected to the data line, a first voltage line arranged in the non-display area, receiving a first voltage, and electrically connected to the scan line and the electrostatic protection circuit, and a second voltage line arranged in the non-display area, receiving a second voltage different from the first voltage, and electrically connected to the scan line and the electrostatic protection circuit. The first voltage line and the second voltage line intersect, and one of the first voltage line and the second voltage line may include a line portion and a bridge electrode disposed lower than the other one of the first voltage line and the second voltage line and the line portion within an area where the first voltage line and the second voltage line intersect. The bridge electrode may be disposed lower than the uppermost electrode constituting the electrostatic protection circuit.

[0006] The pixel may include a first transistor including a first semiconductor pattern and a first gate disposed on the first semiconductor pattern, a second transistor including a second semiconductor pattern disposed above the first gate and a second gate disposed on the second semiconductor pattern, and a light-emitting element electrically connected to at least one of the first transistor and the second transistor.

[0007] The pixel may further include a first connection electrode connected to one of the source region and the drain region of the first semiconductor pattern and positioned above the second gate, and a second connection electrode connected to the first connection electrode and positioned above the first connection electrode.

[0008] The above bridge electrode may be placed lower than the first connecting electrode.

[0009] The first semiconductor pattern may include silicon, and the second semiconductor pattern may include a metal oxide semiconductor.

[0010] The electrostatic protection circuit may include at least one first diode transistor diode-connected between the first voltage line and the data line, and at least one second diode transistor diode-connected between the data line and the second voltage line.

[0011] The at least one transistor may include a semiconductor pattern and a gate disposed on the semiconductor pattern.

[0012] The above bridge electrode may be arranged on the same layer as the gate.

[0013] The above electrostatic protection circuit electrically connects one of the source region and the drain region of the semiconductor pattern to the gate, and may further include a connection electrode arranged on the upper side of the gate.

[0014] The above connecting electrode may be arranged on the same layer as the other one of the first voltage line and the second voltage line.

[0015] The device may further include pads electrically connected to the first voltage line and the second voltage line. The display area may be positioned between the pads and the electrostatic protection circuit in the first direction.

[0016] According to one embodiment of the present invention, a display device includes a pixel, a data line electrically connected to the pixel, a scan line electrically connected to the pixel, a scan driver electrically connected to the scan line, an electrostatic protection circuit electrically connected to the data line, and a first line electrically connected to the scan line and the electrostatic protection circuit and receiving a first voltage. The first line intersects a second line, and the first line includes a line portion and a bridge electrode disposed lower than the line portion, the bridge electrode disposed lower than an uppermost electrode constituting the electrostatic protection circuit, and the line portion may be disposed lower than the uppermost electrode constituting the electrostatic protection circuit or may be disposed on the same layer.

[0017] The second line receives a second voltage different from the first voltage and can be electrically connected to the scan line and the electrostatic protection circuit.

[0018] The above electrostatic protection circuit may include at least one transistor diode-connected between the data line and the first line or the second line.

[0019] The at least one transistor may include a semiconductor pattern and a gate disposed on the semiconductor pattern. The bridge electrode may be disposed on the same layer as the gate.

[0020] The above electrostatic protection circuit electrically connects the semiconductor pattern to one of a source region and a drain region of the semiconductor pattern, and may further include a connection electrode disposed on the upper side of the gate.

[0021] The above connecting electrode may be the uppermost electrode.

[0022] The above connecting electrode may be arranged on the same layer as the other line among the first line and the second line.

[0023] The other of the first line and the second line and the line portion may be arranged on the same layer.

[0024] The other of the first line and the second line, the line portion, and the electrode of the uppermost layer may be arranged on the same layer.

[0025] The device may further include a pad electrically connected to the first line. The pixel may be positioned between the pad and the electrostatic protection circuit in the first direction.

[0026] According to the present invention, the voltage line that supplies voltage to the scan driver and the electrostatic discharge protection circuit is completed through the same process as the electrostatic discharge protection circuit or is formed before the electrostatic discharge protection circuit. Therefore, even if static electricity is generated during the display device manufacturing process, the static electricity can be dissipated through the scan driver, preventing damage to the electrostatic discharge protection circuit.

[0027] Figure 1 is a perspective view of a display device according to one embodiment of the present invention.

[0028] Figure 2 is a cross-sectional view of a display device according to one embodiment of the present invention.

[0029] Figure 3 is a plan view of a display device according to one embodiment of the present invention.

[0030] Figure 4 is a cross-sectional view of a display device according to one embodiment of the present invention.

[0031] FIG. 5 is an enlarged plan view of a portion of a display device according to one embodiment of the present invention.

[0032] Figure 6 is a cross-sectional view of a diode transistor according to one embodiment of the present invention.

[0033] FIG. 7a is a plan view showing an enlarged cross section of voltage lines according to one embodiment of the present invention.

[0034] Figure 7b is a cross-sectional view corresponding to I-I' of Figure 7a.

[0035] Figure 8 is a diagram showing a failure occurrence mechanism of an electrostatic protection circuit.

[0036] Figure 9 is an enlarged plan view of the intersection area of ​​voltage lines according to one embodiment of the present invention.

[0037] Figure 10 is a block diagram of an electronic device according to one embodiment of the present invention.

[0038] FIG. 11 is a schematic diagram of electronic devices according to one embodiment of the present invention.

[0039] In this specification, when it is said that a component (or region, layer, portion, etc.) is “on,” “connected to,” or “coupled to” another component, it means that it can be directly disposed / connected / coupled to the other component, or a third component may be disposed between them.

[0040] Identical drawing numbers indicate identical components. Furthermore, in the drawings, the thicknesses, proportions, and dimensions of the components are exaggerated for the purpose of effectively illustrating the technical content. "And / or" encompasses any combination of one or more of the associated components.

[0041] Although terms such as first, second, etc. may be used to describe various components, the components should not be limited by the terms. The terms are used solely to distinguish one component, part, region, layer, or portion from another component, part, region, layer, or portion. For example, a first component, first part, first region, first layer, or first portion could be referred to as a second component, second part, second region, second layer, or second portion without departing from the scope of the present invention, and similarly, a second component, second part, second region, second layer, or second portion could also be referred to as a first component, first part, first region, first layer, or first portion. Singular expressions include plural expressions unless the context clearly indicates otherwise.

[0042] Additionally, terms such as "below," "lower," "above," and "upper" are used to describe the relationships between components depicted in the drawings. These terms are relative concepts and are described based on the directions indicated in the drawings.

[0043] It should be understood that terms such as "include" or "have" are intended to specify the presence of a feature, number, step, operation, component, part or combination thereof described in the specification, but do not preclude the possibility of the presence or addition of one or more other features, numbers, steps, operations, components, parts or combinations thereof.

[0044] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by those skilled in the art to which this invention pertains. Furthermore, terms defined in commonly used dictionaries should be interpreted to have a meaning consistent with their meaning in the relevant technical context, and should not be interpreted in an overly idealistic or overly formal sense unless explicitly defined herein.

[0045] Hereinafter, embodiments of the present invention will be described with reference to the drawings.

[0046] Fig. 1 is a perspective view of a display device (DD) according to one embodiment of the present invention. As illustrated in Fig. 1, the display device (DD) can display an image through a display surface (DD-IS). The display surface (DD-IS) is parallel to a plane defined by a first direction (DR1) and a second direction (DR2). The normal direction of the display surface (DD-IS), i.e., the thickness direction of the display device (DD), is indicated by a third direction (DR3).

[0047] The front (or upper surface) and the back (or lower surface) of each member or unit described below are distinguished by a third direction (DR3). However, the first to third directions (DR1, DR2, DR3) illustrated in this embodiment are merely examples.

[0048] In one embodiment of the present invention, a display device (DD) having a flat display surface is illustrated, but the present invention is not limited thereto. The display device (DD) may include a curved display surface or a three-dimensional display surface. The three-dimensional display surface may include a plurality of display areas pointing in different directions, and may include, for example, a bended display surface. The display device (DD) according to the present embodiment may be a flexible display device (DD). The flexible display device (DD) may be a foldable display device capable of being folded.

[0049] In this embodiment, a display device (DD) applicable to a tablet terminal is exemplarily illustrated. Electronic modules, a camera module, a power module, etc. mounted on a main board can be arranged together with the display device (DD) in a bracket / case, etc. to form a tablet terminal. The display device (DD) according to the present invention can be applied to large electronic devices such as televisions and monitors, as well as small and medium-sized electronic devices such as cell phones, car navigation systems, game consoles, smart watches, etc.

[0050] As illustrated in Fig. 1, the display surface (DD-IS) includes an image area (DD-DA) where an image is displayed and a bezel area (DD-NDA) adjacent to the image area (DD-DA). The bezel area (DD-NDA) is an area where no image is displayed. Icon images are illustrated in Fig. 1 as examples of images.

[0051] As illustrated in Fig. 1, the image area (DD-DA) may be substantially rectangular. The term "substantially rectangular" includes not only a rectangular shape in the mathematical sense, but also a rectangular shape in which no vertices are defined in the vertex area (or corner area) but the boundary of a curve is defined.

[0052] The bezel area (DD-NDA) may surround the image area (DD-DA). However, this is not limited to this, and the shape of the bezel area (DD-NDA) may be modified. For example, the bezel area (DD-NDA) may be positioned on only one side of the image area (DD-DA).

[0053] FIG. 2 is a cross-sectional view of a display device (DD) according to one embodiment of the present invention.

[0054] The display device (DD) may include a display module (DM) and a window (WM) disposed on the display module (DM). The display module (DM) and the window (WM) may be joined by an adhesive layer (PSA). According to one embodiment of the present invention, the window (WM) may be formed by a coating method and may be in contact with the display module (DM), and in this case, the adhesive layer (PSA) may be omitted.

[0055] A display module (DM) may include a display panel (100), an input sensor (200), and an anti-reflection layer (300). The display panel (100) may include a base layer (110), a driving element layer (120), a light-emitting element layer (130), and an encapsulating layer (140).

[0056] A driving element layer (120) is arranged on the upper surface of the base layer (110). The base layer (110) may be a flexible substrate capable of bending, folding, rolling, etc. The base layer (110) may be a glass substrate, a metal substrate, a polymer substrate, etc. However, the embodiment of the present invention is not limited thereto, and the base layer (110) may be an inorganic layer, an organic layer, or a composite material layer. In fact, the base layer (110) has the same shape as the display panel (100).

[0057] The base layer (110) may have a multilayer structure. For example, the base layer (110) may include a first synthetic resin layer, a second synthetic resin layer, and inorganic layers disposed therebetween. Each of the first and second synthetic resin layers may include a polyimide-based resin, but is not particularly limited thereto.

[0058] The driving element layer (120) may be disposed on the base layer (110). The driving element layer (120) may include a plurality of insulating layers, a plurality of semiconductor patterns, a plurality of conductive patterns, signal lines, etc. The driving element layer (120) may include a pixel driver.

[0059] The light-emitting element layer (130) may be disposed on the driving element layer (120). The light-emitting element layer (130) may include a light-emitting element. For example, the light-emitting element may include an organic light-emitting material, an inorganic light-emitting material, an organic-inorganic light-emitting material, a quantum dot, a quantum rod, a micro LED, or a nano LED.

[0060] The encapsulating layer (140) may be disposed on the light-emitting element layer (130). The encapsulating layer (140) may protect the light-emitting element layer (130), i.e., the light-emitting element, from foreign substances such as moisture, oxygen, and dust particles. The encapsulating layer (140) may include at least one encapsulating inorganic layer. The encapsulating layer (140) may include a laminated structure of a first encapsulating inorganic layer / encapsulating organic layer / second encapsulating inorganic layer.

[0061] The input sensor (200) may be directly disposed on the display panel (100). The input sensor (200) may detect a user's input, for example, by electromagnetic induction and / or electrostatic capacitance. The display panel (100) and the input sensor (200) may be formed through a continuous process. Here, "directly disposed" may mean that no third component is disposed between the input sensor (200) and the display panel (100). For example, a separate adhesive layer may not be disposed between the input sensor (200) and the display panel (100).

[0062] The anti-reflection layer (300) reduces the reflectivity of external light incident from the upper side of the window (WM). The anti-reflection layer (300) according to one embodiment of the present invention may include a phase retarder and a polarizer. The phase retarder may be a film type or a liquid crystal coating type, and may include a λ / 2 phase retarder and / or a λ / 4 phase retarder. The polarizer may also be a film type or a liquid crystal coating type. The film type may include a stretchable synthetic resin film, and the liquid crystal coating type may include liquid crystals arranged in a predetermined array. The phase retarder and the polarizer may further include a protective film. The phase retarder and the polarizer themselves or the protective film may be defined as a base layer of the anti-reflection layer (300).

[0063] An anti-reflection layer (300) according to one embodiment of the present invention may include color filters. The color filters have a predetermined arrangement. The arrangement of the color filters of the plurality of groups distinguished by color may be determined by considering the arrangement of the pixels of the plurality of groups distinguished by the emission color. The anti-reflection layer (300) may further include a black matrix adjacent to the color filters. The anti-reflection layer (300) including the color filters may be directly disposed on the display panel (100).

[0064] A window (WM) according to one embodiment of the present invention may include a base layer and a light-shielding pattern. The base layer may include a glass substrate and / or a synthetic resin film, etc. The light-shielding pattern partially overlaps the base layer (WP-BS). The light-shielding pattern is arranged on the back surface of the base layer, and the light-shielding pattern may substantially define a bezel area (DD-NDA, see FIG. 1) of the display device (DD). An area where the light-shielding pattern is not arranged may define an image area (DD-DA, see FIG. 1) of the display device (DD).

[0065] Figure 3 is a plan view of a display panel (100) according to one embodiment of the present invention.

[0066] Referring to FIG. 3, a display panel (100) may include a plurality of pixels (PX), a scan driver (SDV), an emission driver (EDV), a plurality of signal lines, electrostatic protection circuits (ESD), and a plurality of pads (PD). A plurality of pixels (PX) are arranged in a display area (100-DA). A driving chip (DIC) mounted in a non-display area (100-NDA) may include a data driver. The display area (100-DA) is arranged between the electrostatic protection circuit (ESD) and the pads (PD) in a second direction (DR2).

[0067] The display area (100-DA) may correspond to the image area (DD-DA) of FIG. 1, and the non-display area (100-NDA) may correspond to the bezel area (DD-NDA). In this specification, the phrase "areas or portions correspond to areas or portions" means overlapping, and is not necessarily limited to two different areas or portions having the same shape and the same area. In one embodiment of the present invention, the data driver may also be integrated into the display panel (100) like the scan driver (SDV) and the emission driver (EDV).

[0068] The scan driver (SDV) can generate multiple scan signals, the driver chip (DIC) can generate multiple data voltages, and the emission driver (EDV) can generate multiple emission signals. Each pixel (PX) can receive a data voltage in response to the scan signal.

[0069] The plurality of signal lines may include a plurality of scan lines (SL1 to SLm), a plurality of data lines (DL1 to DLn), a plurality of light-emitting lines (EL1 to ELm), first and second control lines (SL-C1, SL-C2), first and second power lines (PL1, PL2), and first and second voltage lines (VGH, VGL). m and n are natural numbers greater than or equal to 2.

[0070] Scan lines (SL1 to SLm) overlap the display area (100-DA) and the non-display area (100-NDA) and extend in the first direction (DR1) to be electrically connected to pixels (PX) and a scan driver (SDV). Each of the scan lines (SL1 to SLm) is connected to corresponding pixels among the pixels (PX), for example, pixels arranged in the same pixel row.

[0071] Data lines (DL1 to DLn) overlap the display area (100-DA) and the non-display area (100-NDA) and extend in the second direction (DR2) to be electrically connected to pixels (PX) and a driver chip (DIC). Each of the data lines (DL1 to DLn) is connected to corresponding pixels among the pixels (PX), for example, pixels arranged in the same pixel row.

[0072] Although this embodiment illustrates that one driving chip (DIC) drives the data lines (DL1 to DLn) of the entire display area (100-DA), it is not limited thereto. One of the two driving chips (DIC) may drive one group of data lines, and the other of the two driving chips (DIC) may drive two groups of data lines. The light-emitting lines (EL1 to ELm) may extend in the first direction (DR1) and be electrically connected to the pixels (PX) and the light-emitting driver (EDV).

[0073] The first power line (PL1) receives a first power voltage, and the second power line (PL2) receives a second power voltage of a lower level than the first power voltage. Although not shown, the second electrode (e.g., cathode) of the light-emitting element is electrically connected to the second power line (PL2).

[0074] A first control line (SL-C1) may be connected to a scan driver (SDV) and may extend toward the bottom of the display panel (100). A second control line (SL-C2) may be connected to an emission driver (EDV) and may extend toward the bottom of the display panel (100). The pads (PD) may be arranged in a non-display area (100-NDA) adjacent to the bottom of the display panel (100) and may be closer to the bottom of the display panel (100) than the driving chip (DIC). The pads (PD) may be connected to the driving chip (DIC) and some signal lines. Some of the signal lines described above are connected to a corresponding pad (PD) among the plurality of pads (PD).

[0075] The first voltage line (VGH) receives a first voltage, and the second voltage line (VGL) receives a second voltage having a lower level than the first voltage. For example, the first voltage may be a positive (+) constant voltage, and the second voltage may be a negative (-) constant voltage. The first voltage line (VGH) and the second voltage line (VGL) are electrically connected to a scan driver (SDV) and electrically connected to electrostatic discharge protection circuits (ESD).

[0076] The scan driver (SDV) generates a scan signal using a first voltage received from a first voltage line (VGH) and a second voltage received from a second voltage line (VGL). An electrostatic discharge protection circuit (ESD) can be arranged for each of a plurality of data lines (DL1 to DLn) and is electrically connected to the corresponding data line. The electrostatic discharge protection circuit (ESD) can discharge static electricity to the first voltage line (VGH) when positive (+) static electricity occurs on the corresponding data line, and can discharge static electricity to the second voltage line (VGL) when negative (-) static electricity occurs on the corresponding data line.

[0077] FIG. 4 is a cross-sectional view of a display device (DD) according to one embodiment of the present invention.

[0078] Fig. 4 illustrates a cross-section of an area corresponding to one pixel (PX) of Fig. 3. In Fig. 4, some components of the display device (DD), such as the anti-reflection layer (300) or window (WM) of Fig. 2, are not illustrated.

[0079] A pixel driving circuit (PC) for driving a light emitting element (LD) may include a plurality of pixel driving elements. The pixel driving circuit (PC) may include a plurality of transistors (S-TFT, O-TFT) and a capacitor (Cst). In Fig. 4, a silicon transistor (S-TFT, or first transistor) and an oxide transistor (O-TFT, or second transistor) are illustrated as an example. The pixel driving circuit (PC) of Fig. 4 is only one embodiment, and the configuration of the pixel driving circuit (PC) is not necessarily limited thereto. The pixel driving circuit (PC) may include only one type of transistor among the silicon transistor (S-TFT) and the oxide transistor (O-TFT).

[0080] Referring to FIG. 4, the base layer (110) is illustrated as a single layer. The base layer (110) may include a synthetic resin such as polyimide. The base layer (110) may be formed by coating a synthetic resin layer on a working substrate (or carrier substrate). When the display module (DM) is completed through a subsequent process, the working substrate may be removed. In one embodiment of the present invention, the base layer (110) may have a multilayer structure including a first synthetic resin layer, at least one inorganic layer, and a second synthetic resin layer.

[0081] Referring to FIG. 4, a barrier layer (10br) may be disposed on the base layer (110). The barrier layer (10br) prevents or reduces the inflow of foreign substances from the outside. The barrier layer (10br) may include at least one inorganic layer. The barrier layer (10br) may include a silicon oxide layer and a silicon nitride layer. Each of these may be provided in multiples, and the silicon oxide layers and the silicon nitride layers may be alternately laminated.

[0082] The barrier layer (10br) may include a lower barrier layer (10br1) and an upper barrier layer (10br2). A first shielding electrode (BMLa) may be disposed between the lower barrier layer (10br1) and the upper barrier layer (10br2). The first shielding electrode (BMLa) may be disposed to correspond to a silicon transistor (S-TFT). The first shielding electrode (BMLa) may include a metal, for example, molybdenum. The first shielding electrode (BMLa) may receive a bias voltage.

[0083] A buffer layer (10bf) may be disposed on the barrier layer (10br). The buffer layer (10bf) may prevent or reduce the phenomenon of metal atoms or impurities diffusing from the base layer (110) to the first semiconductor pattern (SC1) on the upper side. The buffer layer (10bf) may include at least one inorganic layer. The buffer layer (10bf) may include a silicon oxide layer and a silicon nitride layer.

[0084] A first semiconductor pattern (SC1) may be arranged on the buffer layer (10bf). The first semiconductor pattern (SC1) may include a silicon semiconductor. For example, the silicon semiconductor may include amorphous silicon, polycrystalline silicon, etc. For example, the first semiconductor pattern (SC1) may include low-temperature polysilicon.

[0085] The first semiconductor pattern (SC1) may have different electrical properties depending on whether it is doped. The first semiconductor pattern (SC1) may include a first region having high conductivity and a second region having low conductivity. The first region may be doped with an N-type dopant or a P-type dopant. The second region may be an undoped region or a region doped at a lower concentration than the first region. A source region (SE1, hereinafter referred to as a first source region), a channel region (AC1, or active region, hereinafter referred to as a first channel region), and a drain region (DE1, hereinafter referred to as a first drain region) of a silicon transistor (S-TFT) may be formed from the first semiconductor pattern (SC1). The first source region (SE1) and the first drain region (DE1) may extend in opposite directions from the first channel region (AC1) in a cross-section.

[0086] A first insulating layer (10) may be disposed on the buffer layer (10bf). The first insulating layer (10) may cover the first semiconductor pattern (SC1). The first insulating layer (10) may be an inorganic layer. Not only the first insulating layer (10), but also the inorganic layer of the driving element layer (120) described below may have a single-layer or multi-layer structure and may include at least one of the materials described above, but is not limited thereto.

[0087] A gate (GT1, hereinafter referred to as a first gate) of a silicon transistor (S-TFT) is disposed on a first insulating layer (10). The first gate (GT1) may be a part of a metal pattern. The first gate (GT1) overlaps a first channel region (AC1). In a process of doping the first semiconductor pattern (SC1), the first gate (GT1) may be a mask. A first electrode (CE10) of a storage capacitor (Cst) is disposed on the first insulating layer (10). In a plane, the first electrode (CE10) may have an integral shape with the first gate (GT1).

[0088] A second insulating layer (20) is disposed on the first insulating layer (10) and can cover the first gate (GT1). In one embodiment of the present invention, an upper electrode overlapping the first gate (GT1) may be further disposed on the second insulating layer (20). A second electrode (CE20) overlapping the first electrode (CE10) may be disposed on the second insulating layer (20). The upper electrode may have an integral shape with the second electrode (CE20) on a plane.

[0089] A second shielding electrode (BMLb) is disposed on the second insulating layer (20). The second shielding electrode (BMLb) may be disposed to correspond to an oxide transistor (O-TFT). In one embodiment of the present invention, the second shielding electrode (BMLb) may be omitted. A third insulating layer (30) may be disposed on the second insulating layer (20). A second semiconductor pattern (SC2) may be disposed on the third insulating layer (30). The second semiconductor pattern (SC2) may include a channel region (AC2, hereinafter referred to as a second channel region) of the oxide transistor (O-TFT). The second semiconductor pattern (SC2) may include a metal oxide semiconductor. The second semiconductor pattern (SC2) may include a transparent conductive oxide (TCO) such as indium tin oxide (ITO), indium zinc oxide (IZO), indium gallium zinc oxide (IGZO), zinc oxide (ZnOx), or indium oxide (In2O3).

[0090] The metal oxide semiconductor may include a plurality of regions (SE2, AC2, DE2) that are distinguished depending on whether the transparent conductive oxide is reduced. The region where the transparent conductive oxide is reduced (hereinafter, referred to as the reduced region) has greater conductivity than the region where it is not (hereinafter, referred to as the non-reduced region). The reduced region substantially functions as a source / drain or signal line of the transistor. The non-reduced region substantially corresponds to the semiconductor region (or channel) of the transistor. A fourth insulating layer (40) may be disposed on the third insulating layer (30). As illustrated in FIG. 4, the fourth insulating layer (40) may cover the second semiconductor pattern (SC2).

[0091] A gate (GT2, hereinafter referred to as a second gate) of an oxide transistor (O-TFT) is disposed on a fourth insulating layer (40). The second gate (GT2) of the oxide transistor (O-TFT) may be a part of a metal pattern. The second gate (GT2) of the oxide transistor (O-TFT) overlaps the second channel region (AC2). A fifth insulating layer (50) is disposed on the fourth insulating layer (40), and the fifth insulating layer (50) may cover the second gate (GT2). Each of the first insulating layer (10) to the fifth insulating layer (50) may be an inorganic layer.

[0092] The first connection electrode (CNP1) and the second connection electrode (CNP2) may be disposed on the fifth insulating layer (50). Since the first connection electrode (CNP1) and the second connection electrode (CNP2) are formed through the same process, they may have the same material and the same laminated structure. The first connection electrode (CNP1) may be connected to either the first source region (SE1) or the first drain region (DE1) of the silicon transistor (S-TFT) through the first pixel contact hole (PCH1) penetrating the first to fifth insulating layers (10, 20, 30, 40, 50). As in the present embodiment, in a p-type silicon transistor (S-TFT), the first connection electrode (CNP1) may be connected to the first drain region (DE1). The second connection electrode (CNP2) can be connected to the source region (SE2) of the oxide transistor (O-TFT) through the second pixel contact hole (PCH2) penetrating the fourth and fifth insulating layers (40, 50). The connection relationship between the first connection electrode (CNP1) and the second connection electrode (CNP2) for the silicon transistor (S-TFT) and the oxide transistor (O-TFT) is not necessarily limited thereto.

[0093] The sixth insulating layer (60) may be disposed on the fifth insulating layer (50). The third connection electrode (CNP3) may be disposed on the sixth insulating layer (60). The third connection electrode (CNP3) may be connected to the first connection electrode (CNP1) through a third pixel contact hole (PCH3) penetrating the sixth insulating layer (60). The corresponding data line (DL) may be disposed on the sixth insulating layer (60). The seventh insulating layer (70) may be disposed on the sixth insulating layer (60) and may cover the third connection electrode (CNP3) and the data line (DL). Since the third connection electrode (CNP3) and the data line (DL) are formed through the same process, they may have the same material and the same laminated structure. Each of the sixth insulating layer (60) and the seventh insulating layer (70) may be an organic layer.

[0094] A light emitting element (LD) can be electrically connected to at least one of a plurality of transistors (S-TFT, O-TFT). In this embodiment, a light emitting element (LD) electrically connected to a silicon transistor (S-TFT) is illustrated as an example.

[0095] A light emitting element (LD) may include an anode (AE, or first electrode), a light emitting layer (EL), and a cathode (CE, or second electrode). The anode (AE) of the light emitting element (LD) may be disposed on a seventh insulating layer (70). The anode (AE) may be a (semi)transparent electrode or a reflective electrode. The anode (AE) may include a stacked structure of sequentially stacked ITO / Ag / ITO. The positions of the anode (AE) and the cathode (CE) may be interchanged.

[0096] A pixel defining layer (PDL) may be disposed on the seventh insulating layer (70). The pixel defining layer (PDL) may be an organic layer. The pixel defining layer (PDL) may have a property of absorbing light, and for example, the pixel defining layer (PDL) may have a black color. The pixel defining layer (PDL) may include a black coloring agent. The black coloring agent may include a black dye or a black pigment. The black coloring agent may include a metal such as chromium, an oxide thereof, or carbon black. The pixel defining layer (PDL) may correspond to a light-shielding pattern having light-shielding properties.

[0097] The pixel defining layer (PDL) may cover a portion of the anode (AE). For example, an opening (PDL-OP) exposing a portion of the anode (AE) may be defined in the pixel defining layer (PDL). An emission area (LA1) may be defined to correspond to the opening (PDL-OP). The emission area (LA1) may be surrounded by a non-emission area (NLA).

[0098] In one embodiment of the present invention, a hole control layer may be disposed between the anode (AE) and the light-emitting layer (EL). The hole control layer may include a hole transport layer and may further include a hole injection layer. An electron control layer may be disposed between the light-emitting layer (EL) and the cathode (CE). The electron control layer may include an electron transport layer and may further include an electron injection layer.

[0099] The encapsulation layer (140) can cover the light emitting element (LD). The encapsulation layer (140) can include a sequentially laminated encapsulation inorganic layer (141), an encapsulation organic layer (142), and an encapsulation inorganic layer (143), but the layers constituting the encapsulation layer (140) are not necessarily limited thereto. The encapsulation inorganic layers (141, 143) can include a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, or an aluminum oxide layer. Each of the encapsulation inorganic layers (141, 143) may have a multilayer structure. The encapsulation organic layer (142) can include an acrylic-based organic layer, but is not limited thereto.

[0100] In the present embodiment, the input sensor (200) may include at least one conductive layer (or at least one sensor conductive layer) and at least one insulating layer (or at least one sensor insulating layer). In the present embodiment, the input sensor (200) may include a first insulating layer (210, or first sensor insulating layer), a first conductive layer (220, or first sensor conductive layer), a second insulating layer (230, or second sensor insulating layer), a second conductive layer (240, or second sensor conductive layer), and a third insulating layer (250, or third sensor insulating layer). The line components of the first conductive layer (220) and the line components of the second conductive layer (240) are briefly illustrated in FIG. 4.

[0101] The first insulating layer (210) may be directly disposed on the display panel (100). The first insulating layer (210) may be an inorganic layer including at least one of silicon nitride, silicon oxynitride, and silicon oxide. Each of the first conductive layer (220) and the second conductive layer (240) may have a single-layer structure or a multi-layer structure laminated along the third direction (DR3). The first conductive layer (220) and the second conductive layer (240) may include line components defining a mesh-shaped electrode. The line components of the first conductive layer (220) and the line components of the second conductive layer (240) may or may not be connected through a contact hole penetrating the second insulating layer (230) depending on the position.

[0102] The first conductive layer (220) and the second conductive layer (240) of the single-layer structure may include a metal layer or a transparent conductive layer. The metal layer may include molybdenum, silver, titanium, copper, aluminum, or an alloy thereof. The transparent conductive layer may include a transparent conductive oxide such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnOx), or indium zinc tin oxide (IZTO). In addition, the transparent conductive layer may include a conductive polymer such as PEDOT, metal nanowires, graphene, etc.

[0103] The first conductive layer (220) and the second conductive layer (240) of the multilayer structure may include metal layers. The conductive layer of the multilayer structure may include at least one metal layer and at least one transparent conductive layer. The second insulating layer (230) may be disposed between the first conductive layer (220) and the second conductive layer (240). The third insulating layer (250) may cover the second conductive layer (240). In one embodiment of the present invention, the third insulating layer (250) may be omitted. The second insulating layer (230) and the third insulating layer (250) may include an inorganic layer or an organic layer.

[0104] Fig. 5 is an enlarged plan view of a portion of a display device (DD) according to one embodiment of the present invention. Fig. 6 is a cross-sectional view of a diode transistor (ET1) according to one embodiment of the present invention.

[0105] Referring to FIG. 5, the scan driver (SDV) may include multiple stage circuits. For example, it may include m stage circuits corresponding one-to-one to the m scan lines (SL1 to SLm) illustrated in FIG. 3. The multiple stage circuits may have the same circuit configuration. FIG. 5 illustrates first and second stage circuits (ST1, ST2) connected to first and second scan lines (SL1, SL2), respectively, as an example.

[0106] The first and second stage circuits (ST1, ST2) output scan signals corresponding to the first and second scan lines (SL1, SL2). The first and second scan lines (SL1, SL2) may receive a first voltage from a first voltage line (VGH), a second voltage from a second voltage line (VGL), and a clock signal from a signal line (not shown) to generate the scan signals. A plurality of stage circuits may also receive signals output from adjacent stage circuits.

[0107] An electrostatic discharge protection circuit (ESD) is connected to each of the plurality of data lines (DL). The ESD may include at least one diode-connected transistor between the first voltage line (VGH) or the second voltage line (VGL) and the data line (DL). In this embodiment, an ESD including two types of transistors is illustrated as an example.

[0108] An electrostatic discharge protection circuit (ESD) may include at least one first diode transistor (ET1) diode-connected between a first voltage line (VGH) and a data line (DL). In this embodiment, two first diode transistors (ET1) connected in series are illustrated as an example. The electrostatic discharge protection circuit (ESD) may include at least one second diode transistor (ET2) diode-connected between a data line (DL) and a second voltage line (VGL). In this embodiment, two second diode transistors (ET2) connected in series are illustrated as an example.

[0109] When static electricity is introduced into the data line (DL), positive (+) static electricity is induced into the first voltage line (VGH), and negative (-) static electricity is induced into the second voltage line (VGL), thereby preventing or reducing damage to the pixel (PX) connected to the data line (DL).

[0110] In this embodiment, p-type diode transistors (ET1, ET2) are illustrated as an example, but the electrostatic protection circuit (ESD) may include n-type diode transistors, or may include both p-type diode transistors and n-type diode transistors. The gates of the p-type diode transistors are connected to the terminal connected to the first voltage line (VGH) or the second voltage line (VGL) among the terminals of the p-type diode transistors, but the gates of the n-type diode transistors may be connected to the terminal opposite to the terminal connected to the first voltage line (VGH) or the second voltage line (VGL) among the terminals of the n-type diode transistors.

[0111] Fig. 6 illustrates a cross-section of one first diode transistor (ET1) as an example of a diode transistor. The stacked structure of the second diode transistor (ET2) may be identical to the stacked structure of the first diode transistor (ET1).

[0112] The first diode transistor (ET1) may include a semiconductor pattern (SC) disposed on a buffer layer (10bf) and a gate (GT) disposed on the semiconductor pattern (SC). The semiconductor pattern (SC) may include a source region (SE), a channel region (AC, or active region), and a drain region (DE). The source region (SE) and the drain region (DE) may extend in opposite directions from the channel region (AC) in a cross-section. The source region (SE) and the drain region (DE) of the semiconductor pattern (SC) correspond to both terminals of the first diode transistor (ET1) described above.

[0113] The semiconductor pattern (SC) may include a silicon semiconductor, may include the same material as the first semiconductor pattern (SC1) of FIG. 4, and may be formed by the same process. In one embodiment of the present invention, the semiconductor pattern (SC) may include a metal oxide semiconductor, may include the same material as the second semiconductor pattern (SC2) of FIG. 4, and may be formed by the same process.

[0114] The gate (GT) may be disposed on the same layer as the first gate (GT1) of FIG. 4, may include the same material, and may be formed by the same process. In one embodiment of the present invention, the gate (GT) may include the same material as the second shielding electrode (BMLb) of FIG. 4, and may be formed by the same process.

[0115] The first diode transistor (ET1) electrically connects one of the source region (SE) and the drain region (DE) of the semiconductor pattern (SC) to the gate (GT), and may further include a connection electrode (CNE) disposed on the upper side of the gate (GT). The connection electrode (CNE) may be disposed on the same layer as the first connection electrode (CNP1) of FIG. 4, may include the same material, and may be formed by the same process. In the present embodiment, the connection electrode (CNE) may be connected to the gate (GT) through the first contact hole (CH10) and to the source region (SE) through the second contact hole (CH20). The first contact hole (CH10) may penetrate the second to fifth insulating layers (20 to 50), and the second contact hole (CH20) may penetrate the first to fifth insulating layers (10 to 50).

[0116] The connecting electrode (CNE) corresponds to the uppermost electrode of the first diode transistor (ET1), i.e., the electrostatic discharge protection circuit (ESD). The term "uppermost electrode" means that it is formed as late as possible in the manufacturing process of the electrostatic discharge protection circuit (ESD). The gate (GT) and source region (SE) must be electrically connected by the connecting electrode (CNE) for the first diode transistor (ET1) to function normally.

[0117] A sixth insulating layer (60) and a seventh insulating layer (70) may be disposed on the connecting electrode (CNE). Although not shown, at least one or more layers of the sealing layer (140), the first insulating layer (210), the second insulating layer (230), and the third insulating layer (250) illustrated in FIG. 4 may be further disposed on the connecting electrode (CNE).

[0118] Fig. 7a is an enlarged plan view of the intersection area (CA) of voltage lines (VGH, VGL) according to one embodiment of the present invention. Fig. 7b is a cross-sectional view corresponding to line I-I' of Fig. 7a. Fig. 8 is a diagram illustrating a failure mechanism of an electrostatic discharge (ESD) protection circuit.

[0119] As described with reference to FIGS. 3 and 5, the first voltage line (VGH) and the second voltage line (VGL) extend from the pad (PD) to the area where the electrostatic protection circuit (ESD) of the non-display area (100-NDA) is arranged and are connected to the scan driver (SDV) at multiple points, so that multiple crossing areas (CA) can be formed between the first voltage line (VGH) and the second voltage line (VGL).

[0120] In order to insulate a first voltage line (VGH) and a second voltage line (VGL) within a crossover area (CA), one of the two lines includes a bridge electrode (BRE) arranged on a different layer from the other line. One of the first voltage line (VGH) and the second voltage line (VGL) is arranged on a different layer from the bridge electrode (BRE) and includes a line portion (LP) arranged on the same layer as the other line.

[0121] The line portion (LP) includes a first line portion (LP1) and a second line portion (LP2) that are arranged spaced apart from each other, and a bridge electrode (BRE) is arranged on a different layer from the line portion (LP) to electrically connect the first line portion (LP1) and the second line portion (LP2). Accordingly, the bridge electrode (BRE) and the other one of the first voltage line (VGH) and the second voltage line (VGL) intersect within the intersection area (CA).

[0122] As illustrated in FIGS. 7A and 7B, the first voltage line (VGH) may include a line portion (LP) and a bridge electrode (BRE). The bridge electrode (BRE) may be positioned lower than the line portion (LP). Additionally, the bridge electrode (BRE) may be positioned lower than the second voltage line (VGL).

[0123] In the present embodiment, the bridge electrode (BRE) may be disposed on the same layer as the first gate (GT1) of FIG. 4 and the gate (GT) of FIG. 6, may include the same material, and may be formed by the same process. The line portion (LP) may be disposed on the same layer as the first connection electrode (CNP1) of FIG. 4, may include the same material, and may be formed by the same process. The line portion (LP) and the second voltage line (VGL) may be disposed on the same layer, may include the same material, and may be formed by the same process. In the present embodiment, since the line portion (LP) of the first voltage line (VGH) and the second voltage line (VGL) are formed by the same process as the first connection electrode (CNP1) of FIG. 4, the bridge electrode (BRE) is disposed lower than the first connection electrode (CNP1).

[0124] The first line portion (LP1) may be connected to the bridge electrode (BRE) through the first contact hole (CH100), and the second line portion (LP2) may be connected to the bridge electrode (BRE) through the second contact hole (CH200). The first contact hole (CH100) and the second contact hole (CH200) may penetrate the first to fifth insulating layers (10 to 50).

[0125] As a result, in the present embodiment, the bridge electrode (BRE) is positioned lower than the line portion (LP) and the second voltage line (VGL). In other words, the bridge electrode (BRE) is formed before the line portion (LP) and the second voltage line (VGL), and the line portion (LP) and the second voltage line (VGL) are formed by the same process.

[0126] The bridge electrode (BRE) is positioned lower than the connecting electrode (CNE), which is the uppermost electrode constituting the electrostatic discharge protection circuit (ESD) described with reference to Fig. 6. The bridge electrode (BRE) is formed before the electrostatic discharge protection circuit (ESD) is completed in order to form the first voltage line (VGH) and the second voltage line (VGL) before or simultaneously with the completion of the electrostatic discharge protection circuit (ESD). Accordingly, damage to the electrostatic discharge protection circuit (ESD) caused by static electricity generated during the manufacturing process of the display device can be suppressed.

[0127] Figure 8 illustrates a mechanism by which an electrostatic discharge protection circuit (ESD) is damaged when a bridge electrode (BRE) is formed later than a line portion (LP) and a second voltage line (VGL).

[0128] Referring to FIGS. 6, 7b, and 8, when the bridge electrode (BRE) is formed above the line portion (LP) and the second voltage line (VGL), it can be assumed that the remaining configuration of the first voltage line (VGH), the second voltage line (VGL), and the electrostatic protection circuit (ESD) are completed, excluding the bridge electrode (BRE). When the bridge electrode (BRE) is formed above the line portion (LP) and the second voltage line (VGL), the bridge electrode (BRE) can be formed, for example, by the same process as the third connection electrode (CNP3) of FIG. 4.

[0129] If static electricity (ES) generated during the process of forming the third connection electrode (CNP3) flows through the first line portion (LP1), the static electricity (ES) may flow into the first diode transistor (ET1) and damage the first diode transistor (ET1). Accordingly, the first voltage line (VGH) may be short-circuited to the data line (DL), and pixels connected to the data line may experience black line defects.

[0130] However, as described with reference to FIGS. 5 to 7, when the bridge electrode (BRE) is formed before the line portion (LP) and the first voltage line (VGH) and the second voltage line (VGL) are formed before or simultaneously with the completion of the electrostatic discharge protection circuit (ESD), static electricity generated during a subsequent process can be dispersed through the scan driver (SDV) electrically connected to the first voltage line (VGH) and the second voltage line (VGL). Accordingly, damage to the electrostatic discharge protection circuit (ESD) caused by static electricity generated during the manufacturing process of the display device can be prevented or reduced.

[0131]

[0132] FIG. 9 is a plan view showing an enlarged cross section of voltage lines (VGH, VGL) according to one embodiment of the present invention.

[0133] According to the embodiment illustrated in Fig. 9, unlike the embodiments illustrated in Figs. 7a and 7b, the second voltage line (VGL) may include a line portion (LP0) and a bridge electrode (BRE0). The bridge electrode (BRE0) may be positioned lower than the line portion (LP0). In addition, the bridge electrode (BRE0) may be positioned lower than the first voltage line (VGH).

[0134] As described with reference to FIGS. 7a to 8, even if static electricity is generated during the manufacturing process of the display device, it is dispersed through the scan driver (SDV), so that a defect in which the second diode transistor (ET2) of FIG. 5 is damaged can be suppressed.

[0135]

[0136] In FIGS. 5 to 9, the first line and the second line intersecting the first voltage line (VGH) and the second voltage line (VGL) are described as examples, but the present invention can also be applied when one of the first voltage line (VGH) and the second voltage line (VGL) is the first line and the other signal line is the second line. The other signal line may receive a clock signal or a power supply voltage.

[0137] When the first line and the second line intersect, if the first line, which is one of the first voltage line (VGH) and the second voltage line (VGL), includes a bridge electrode, as described above, the bridge electrode (BRE) may be arranged lower than the uppermost electrode constituting the electrostatic protection circuit (ESD). If the first line, which is one of the first voltage line (VGH) and the second voltage line (VGL), does not include the bridge electrode (BRE), as described above, the first line may be arranged lower than the uppermost electrode constituting the electrostatic protection circuit (ESD) or may be arranged on the same layer.

[0138] A display device according to one embodiment of the present invention can be applied to various electronic devices. An electronic device according to one embodiment of the present invention includes the above-described display device, and the electronic device may further include a module or device having additional functions in addition to the display device.

[0139] Fig. 10 is a block diagram of an electronic device according to one embodiment of the present invention. Fig. 11 is a schematic diagram of electronic devices according to one embodiment of the present invention.

[0140] Referring to FIG. 10, an electronic device (10) according to one embodiment of the present invention may include a display module (11), a processor (12), a memory (13), and a power module (14).

[0141] The processor (12) may include at least one of a central processing unit (CPU), an application processor (AP), a graphic processing unit (GPU), a communication processor (CP), an image signal processor (ISP), and a controller.

[0142] The memory (15) may store data information necessary for the operation of the processor (12) or the display module (11). When the processor (12) executes an application stored in the memory (15), an image data signal and / or an input control signal is transmitted to the display module (11), and the display module (11) can process the received signal and output image information through a display screen.

[0143] The power module (14) may include a power supply module such as a power adapter or a battery device, and a power conversion module that converts power supplied by the power supply module to generate power required for the operation of the electronic device (10).

[0144] At least one of the components of the electronic device (11) described above may be included in the display device according to the embodiments described above. In addition, some of the individual modules functionally included in one module may be included in the display device, while others may be provided separately from the display device. For example, the display device may include the display module (11), and the processor (12), memory (13), and power module (14) may be provided in the form of other devices within the electronic device (11) other than the display device.

[0145] Referring to FIG. 11, various electronic devices to which a display device according to an embodiment of the present invention is applied may include not only image display electronic devices such as a smart phone (10_1a), a tablet PC (10_1b), a laptop (10_1c), a TV (10_1d), and a desk monitor (10_1e), but also wearable electronic devices including display modules such as smart glasses (10_2a), a head-mounted display (10_2b), and a smart watch (10_2c), and vehicle electronic devices (10_3) including display modules such as a CID (Center Information Display) and a room mirror display placed on an instrument panel, center fascia, or dashboard of an automobile.

[0146] Although the present invention has been described above with reference to preferred embodiments thereof, it will be understood by those skilled in the art or having ordinary knowledge in the art that various modifications and changes may be made to the present invention without departing from the spirit and technical scope of the present invention as set forth in the claims to be described below.

[0147] Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification, but should be defined by the patent claims.

[0148] During the manufacturing process of display devices, damage to circuits can occur due to static electricity. The electrostatic protection circuit according to the present invention is highly likely to be applied to display devices because it can suppress circuit damage caused by static electricity.

Claims

1. Multiple pixels arranged in the display area; A data line electrically connected to a corresponding pixel among the plurality of pixels and overlapping the display area and the non-display area adjacent to the display area; A scan line electrically connected to the corresponding pixel and overlapping the display area and the non-display area; A scan driver disposed in the non-display area and electrically connected to the scan line; An electrostatic protection circuit disposed in the above non-display area and electrically connected to the data line; A first voltage line disposed in the non-display area, receiving a first voltage, and electrically connected to the scan line and the electrostatic protection circuit; and A second voltage line is disposed in the non-display area, receives a second voltage different from the first voltage, and is electrically connected to the scan line and the electrostatic protection circuit, The first voltage line and the second voltage line intersect, One of the first voltage line and the second voltage line includes a line portion and a bridge electrode disposed lower than the other one of the first voltage line and the second voltage line and the line portion within an area where the first voltage line and the second voltage line intersect, The above bridge electrode is a display device positioned lower than the uppermost electrode constituting the above electrostatic protection circuit.

2. In paragraph 1, The corresponding pixels above are, A first transistor including a first semiconductor pattern and a first gate disposed on the first semiconductor pattern; A second transistor including a second semiconductor pattern disposed above the first gate and a second gate disposed on the second semiconductor pattern; and A display device including a light emitting element electrically connected to at least one of the first transistor and the second transistor.

3. In paragraph 2, The above pixel is, A first connection electrode connected to one of the source region and the drain region of the first semiconductor pattern and positioned above the second gate; and A display device further comprising a second connection electrode connected to the first connection electrode and positioned above the first connection electrode.

4. In paragraph 3, A display device in which the above bridge electrode is positioned lower than the above first connection electrode.

5. In paragraph 2, A display device wherein the first semiconductor pattern includes a silicon semiconductor and the second semiconductor pattern includes a metal oxide semiconductor.

6. In paragraph 1, The above electrostatic protection circuit, At least one first diode transistor diode-connected between the first voltage line and the data line; and A display device comprising at least one second diode transistor diode-connected between the data line and the second voltage line.

7. In paragraph 6, wherein said at least one first diode transistor comprises a semiconductor pattern and a gate disposed on said semiconductor pattern, A display device in which the above bridge electrode is arranged on the same layer as the above gate.

8. In paragraph 7, A display device in which the electrostatic protection circuit electrically connects one of the source region and the drain region of the semiconductor pattern to the gate, and further includes a connection electrode arranged on the upper side of the gate.

9. In paragraph 8, A display device in which the above-mentioned connecting electrode is arranged on the same layer as the other one of the first voltage line and the second voltage line.

10. In paragraph 1, Further comprising pads electrically connected to the first voltage line and the second voltage line, A display device in which the display area is arranged between the pads and the electrostatic protection circuit within the first direction.

11. Pixel; A data line electrically connected to the above pixel; A scan line electrically connected to the above pixel; A scan driver electrically connected to the above scan line; An electrostatic protection circuit electrically connected to the above data line; and A first line electrically connected to the scan line and the electrostatic protection circuit and receiving a first voltage, The above first line intersects the second line, The first line includes a line portion and a bridge electrode positioned lower than the line portion, A display device in which the bridge electrode is positioned lower than the uppermost electrode constituting the electrostatic protection circuit, and the line portion is positioned lower than the uppermost electrode constituting the electrostatic protection circuit or is positioned on the same layer.

12. In paragraph 11, A display device in which the second line receives a second voltage different from the first voltage and is electrically connected to the scan line and the electrostatic protection circuit.

13. In paragraph 12, A display device in which the electrostatic protection circuit includes at least one transistor diode-connected between the data line and the first line or the second line.

14. In paragraph 13, wherein at least one transistor comprises a semiconductor pattern and a gate disposed on the semiconductor pattern, A display device in which the above bridge electrode is arranged on the same layer as the above gate.

15. In paragraph 14, A display device in which the electrostatic protection circuit electrically connects the semiconductor pattern to one of a source region and a drain region of the semiconductor pattern, and further includes a connection electrode arranged on the upper side of the gate.

16. In paragraph 15, The uppermost electrode is a display device including the connecting electrode.

17. In paragraph 15, A display device in which the above connecting electrode is arranged on the same layer as one of the first line and the second line.

18. In paragraph 11, A display device in which one of the first line and the second line and the line portion are arranged on the same layer.

19. In paragraph 11, A display device in which one of the first line and the second line, the line portion, and the uppermost electrode are arranged on the same layer 20. In paragraph 11, Further comprising a pad electrically connected to the first line, A display device in which the pixel is arranged between the pad and the electrostatic protection circuit within the first direction.

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