Pixel driving circuit and driving method thereof, and display device

Abstract

A pixel driving circuit and a driving method thereof, and a display device. The pixel driving circuit comprises a driving sub-circuit, a node control sub-circuit, a following sub-circuit, and a light emitting control sub-circuit; the driving sub-circuit provides a driving current for a third node under the control of signals of a first node and a second node; under the control of signals of a first scanning signal line to a fourth scanning signal line, the node control sub-circuit provides a signal of a reference signal line for at least one of the second node and a fifth node, provides a signal of a data signal line for the second node, and provides a signal of a bias signal line for a fourth node; the following sub-circuit transmits a change amount of the potential of the third node to the second node under the control of a signal of a second light emitting signal line; and under the control of a signal of a first light emitting signal line and the signal of the second light emitting signal line, the light emitting control sub-circuit provides a signal of a first power line for the first node and provides a signal of the third node for the fourth node.

Description

Pixel driving circuit, driving method thereof and display device

[0001] The present application claims priority to the Chinese patent application No. 202410832603.1, filed on June 25, 2024, and entitled “Pixel driving circuit, driving method thereof and display device”, the content of which is incorporated herein by reference. TECHNICAL FIELD

[0002] The present disclosure relates to, but not limited to, display technology, in particular to a pixel driving circuit, a driving method thereof and a display device. BACKGROUND

[0003] Organic Light Emitting Diode (OLED) and Quantum-dot Light Emitting Diodes (QLED) are active light-emitting display devices, which have the advantages of self-emission, wide viewing angle, high contrast, low power consumption, extremely high response speed, thinness, flexibility, low cost, etc. With the continuous development of display technology, flexible display devices using OLED or QLED as light-emitting devices and controlled by Thin Film Transistor (TFT) have become the mainstream products in the current display field. SUMMARY

[0004] The following is a summary of the subject matter of the detailed description of the present disclosure. This summary is not intended to limit the scope of protection of the claims.

[0005] In a first aspect, the embodiments of the present disclosure provide a pixel driving circuit, comprising: a driving sub-circuit, a node control sub-circuit, a following sub-circuit and a light-emitting control sub-circuit;

[0006] The driving sub-circuit is electrically connected with a first node, a second node and a third node respectively, and is configured to provide a driving current to the third node under the control of signals of the first node and the second node;

[0007] The node control sub-circuit is electrically connected with the second node, a data signal line, a bias signal line, a first scan signal line to a fourth scan signal line, a fourth node, a fifth node and a reference signal line respectively, and is configured to provide a signal of the reference signal line to at least one of the second node and the fifth node, provide a signal of the data signal line to the second node, and provide a signal of the bias signal line to the fourth node under the control of signals of the first scan signal line to the fourth scan signal line;

[0008] The follower sub-circuit is electrically connected with the second node, the third node, the fifth node and the second light-emitting signal line respectively, and is configured to transmit a variation amount of a potential of the third node to the second node under control of a signal of the second light-emitting signal line.

[0009] The light-emitting control sub-circuit is electrically connected with the first power supply line, the first light-emitting signal line, the first node, the third node, the second light-emitting signal line and the fourth node respectively, and is configured to provide the first node with a signal of the first power supply line and provide the fourth node with a signal of the third node under control of signals of the first light-emitting signal line and the second light-emitting signal line.

[0010] In some possible implementation manners, the follower sub-circuit includes a first capacitor, a second capacitor and a seventh transistor.

[0011] The first capacitor includes a first plate and a second plate, the first plate of the first capacitor is electrically connected with the second node, and the second plate of the first capacitor is electrically connected with the third node.

[0012] The second capacitor includes a first plate and a second plate, the first plate of the second capacitor is electrically connected with the third node, and the second plate of the second capacitor is electrically connected with the fifth node.

[0013] The control electrode of the seventh transistor is electrically connected with the second light-emitting signal line, the first electrode of the seventh transistor is electrically connected with the second node, and the second electrode of the seventh transistor is electrically connected with the fifth node.

[0014] In some possible implementation manners, a difference between the capacitance values of the first capacitor and the second capacitor is less than or equal to a set threshold value.

[0015] In some possible implementation manners, the node control sub-circuit includes a first control sub-circuit to a third control sub-circuit.

[0016] The first control sub-circuit is electrically connected with the second node, the first scan signal line, the third scan signal line, the fifth node and the reference signal line respectively, and is configured to provide at least one of the second node and the fifth node with a signal of the reference signal line under control of signals of the first scan signal line and the third scan signal line.

[0017] The second control sub-circuit is electrically connected with the second scan signal line, the data signal line and the second node respectively, and is configured to provide the second node with a signal of the data signal line under control of a signal of the second scan signal line.

[0018] The third control sub-circuit is electrically connected with the fourth scan signal line, the bias signal line and the fourth node respectively, and is configured to provide the fourth node with a signal of the bias signal line under control of a signal of the fourth scan signal line.

[0019] In some possible implementation manners, the first control sub-circuit comprises a fifth transistor and an eighth transistor;

[0020] The control electrode of the fifth transistor is electrically connected with the first scan signal line, the first electrode of the fifth transistor is electrically connected with the reference signal line, and the second electrode of the fifth transistor is electrically connected with the second node.

[0021] The control electrode of the eighth transistor is electrically connected with the third scan signal line, the first electrode of the eighth transistor is electrically connected with the fifth node, and the second electrode of the eighth transistor is electrically connected with the reference signal line.

[0022] In some possible implementation manners, the second control sub-circuit comprises a sixth transistor;

[0023] The control electrode of the sixth transistor is electrically connected with the second scan signal line, the first electrode of the sixth transistor is electrically connected with the data signal line, and the second electrode of the sixth transistor is electrically connected with the second node.

[0024] In some possible implementation manners, the third control sub-circuit comprises a fourth transistor;

[0025] The control electrode of the fourth transistor is electrically connected with the fourth scan signal line, the first electrode of the fourth transistor is electrically connected with the fourth node, and the second electrode of the fourth transistor is electrically connected with the bias signal line.

[0026] In some possible implementation manners, the driving sub-circuit comprises a second transistor;

[0027] The control electrode of the second transistor is electrically connected with the second node, the first electrode of the second transistor is electrically connected with the first node, and the second electrode of the second transistor is electrically connected with the third node.

[0028] In some possible implementation manners, the light-emitting control sub-circuit comprises a first transistor and a third transistor;

[0029] The control electrode of the first transistor is electrically connected with the first light-emitting signal line, the first electrode of the first transistor is electrically connected with the first power supply line, and the second electrode of the first transistor is electrically connected with the first node.

[0030] The control electrode of the third transistor is electrically connected with the second light-emitting signal line, the first electrode of the third transistor is electrically connected with the third node, and the second electrode of the third transistor is electrically connected with the fourth node.

[0031] In some possible implementation manners, the light-emitting control sub-circuit comprises a first transistor and a third transistor, the driving sub-circuit comprises a second transistor, the node control sub-circuit comprises a fourth transistor to a sixth transistor and an eighth transistor, and the following sub-circuit comprises a first capacitor, a second capacitor and a seventh transistor;

[0032] The control electrode of the first transistor is electrically connected with the first light-emitting signal line, the first electrode of the first transistor is electrically connected with the first power supply line, and the second electrode of the first transistor is electrically connected with the first node;

[0033] The control electrode of the second transistor is electrically connected with the second node, the first electrode of the second transistor is electrically connected with the first node, and the second electrode of the second transistor is electrically connected with the third node;

[0034] The control electrode of the third transistor is electrically connected with the second light-emitting signal line, the first electrode of the third transistor is electrically connected with the third node, and the second electrode of the third transistor is electrically connected with the fourth node;

[0035] The control electrode of the fourth transistor is electrically connected with the fourth scanning signal line, the first electrode of the fourth transistor is electrically connected with the fourth node, and the second electrode of the fourth transistor is electrically connected with the bias signal line;

[0036] The control electrode of the fifth transistor is electrically connected with the first scanning signal line, the first electrode of the fifth transistor is electrically connected with the reference signal line, and the second electrode of the fifth transistor is electrically connected with the second node;

[0037] The control electrode of the sixth transistor is electrically connected with the second scanning signal line, the first electrode of the sixth transistor is electrically connected with the data signal line, and the second electrode of the sixth transistor is electrically connected with the second node;

[0038] The control electrode of the seventh transistor is electrically connected with the second light-emitting signal line, the first electrode of the seventh transistor is electrically connected with the second node, and the second electrode of the seventh transistor is electrically connected with the fifth node;

[0039] The control electrode of the eighth transistor is electrically connected with the third scanning signal line, the first electrode of the eighth transistor is electrically connected with the fifth node, and the second electrode of the eighth transistor is electrically connected with the reference signal line;

[0040] The first capacitor includes a first plate and a second plate, the first plate of the first capacitor is electrically connected with the second node, and the second plate of the first capacitor is electrically connected with the third node;

[0041] The second capacitor includes a first plate and a second plate, the first plate of the second capacitor is electrically connected with the third node, and the second plate of the second capacitor is electrically connected with the fifth node.

[0042] In some possible implementation manners, at least one of the first transistor to the eighth transistor is an N-type transistor.

[0043] In a second aspect, the embodiments of the present disclosure provide a display device, characterized in that the display device comprises the pixel driving circuit according to any one of the first aspect.

[0044] In some possible implementation manners, the display device further includes a first control unit, a second control unit, a third control unit and a fourth control unit;

[0045] The first control unit is electrically connected with the first scan signal line and is configured to provide a signal to the first scan signal line. The second control unit is electrically connected with the second scan signal line and is configured to provide a signal to the second scan signal line. The third control unit is electrically connected with the third scan signal line and is configured to provide a signal to the third scan signal line. The fourth control unit is electrically connected with the fourth scan signal line and is configured to provide a signal to the fourth scan signal line.

[0046] The content displayed by the display device includes a plurality of display frames. In at least one display frame, a time period during which the first control unit provides an effective level signal to the first scan signal line at least partially overlaps at least one of a time period during which the third control unit provides an effective level signal to the third scan signal line and a time period during which the fourth control unit provides an effective level signal to the second scan signal line, and does not overlap a time period during which the second control unit provides an effective level signal to the second scan signal line.

[0047] The time period during which the second control unit provides an effective level signal to the second scan signal line at least partially overlaps at least one of the time period during which the third control unit provides an effective level signal to the third scan signal line and the time period during which the fourth control unit provides an effective level signal to the second scan signal line.

[0048] The time period during which the third control unit provides an effective level signal to the third scan signal line at least partially overlaps the time period during which the fourth control unit provides an effective level signal to the fourth scan signal line.

[0049] In some possible implementation manners, a start time of the time period during which the first control unit provides an effective level signal to the first scan signal line is earlier than or equal to a start time of the time period during which the third control unit provides an effective level signal to the third scan signal line. A start time of the time period during which the third control unit provides an effective level signal to the third scan signal line is earlier than or equal to a start time of the time period during which the fourth control unit provides an effective level signal to the fourth scan signal line.

[0050] The first control unit provides an end time of a time period in which the first control unit provides the valid level signal to the first scan signal line, which is earlier than or equal to an end time of a time period in which the third control unit provides the valid level signal to the third scan signal line; the third control unit provides an end time of a time period in which the third control unit provides the valid level signal to the third scan signal line, which is earlier than or equal to an end time of a time period in which the fourth control unit provides the valid level signal to the fourth scan signal line; the second control unit provides a start time of a time period in which the second control unit provides the valid level signal to the second scan signal line, which is later than or equal to an end time of a time period in which the first control unit provides the valid level signal to the first scan signal line; and the second control unit provides an end time of a time period in which the second control unit provides the valid level signal to the second scan signal line, which is earlier than or equal to a start time of a time period in which the third control unit provides the valid level signal to the third scan signal line.

[0051] In some possible implementation manners, the display device further includes a fifth control unit and a sixth control unit.

[0052] The fifth control unit is electrically connected with the first light-emitting signal line and is configured to provide a signal to the first light-emitting signal line; and the sixth control unit is electrically connected with the second light-emitting signal line and is configured to provide a signal to the second light-emitting signal line.

[0053] The content displayed by the display device includes a plurality of display frames, and in at least one display frame, a time period in which the fifth control unit provides the valid level signal to the first light-emitting signal line at least partially overlaps with a time period in which the sixth control unit provides the valid level signal to the second light-emitting signal line.

[0054] In some possible implementation manners, a start time of a time period in which the fifth control unit provides the valid level signal to the first light-emitting signal line is later than or equal to an end time of a time period in which the sixth control unit provides the valid level signal to the second light-emitting signal line.

[0055] In a third aspect, an embodiment of the present disclosure provides a driving method of a pixel driving circuit, configured to drive the pixel driving circuit as described in any of the embodiments of the first aspect, and the method includes:

[0056] The driving sub-circuit provides a driving current to the third node under the control of signals of the first node and the second node;

[0057] The node control sub-circuit provides a signal of the reference signal line to at least one of the second node and the fifth node, a signal of the data signal line to the second node, and a signal of the bias signal line to the fourth node under the control of signals of the first scan signal line to the fourth scan signal line;

[0058] The following sub-circuit transmits a change amount of a potential of the third node to the second node under the control of a signal of the second light-emitting signal line.

[0059] The light emitting control sub-circuit provides the signal of the first power supply line to the first node and the signal of the third node to the fourth node under the control of the signals of the first light emitting signal line and the second light emitting signal line.

[0060] Other aspects can become apparent after consideration of the drawings and detailed description.

[0061] SUMMARY

[0062] The accompanying drawings are included to provide a further understanding of the present disclosure and are incorporated in and constitute a part of this specification, illustrate embodiments of the present disclosure and serve to explain the principles of the present disclosure, and should not be considered limiting of the present disclosure's scope.

[0063] FIG. 1 is a structural schematic diagram of a pixel driving circuit according to an example embodiment of the present disclosure;

[0064] FIG. 2 is an equivalent circuit diagram of a driving sub-circuit according to an example embodiment;

[0065] FIG. 3 is an equivalent circuit diagram of a following sub-circuit according to an example embodiment;

[0066] FIG. 4 is an equivalent circuit diagram of a node control sub-circuit according to an example embodiment;

[0067] FIG. 5 is an equivalent circuit diagram of a first control sub-circuit according to an example embodiment;

[0068] FIG. 6 is an equivalent circuit diagram of a second control sub-circuit according to an example embodiment;

[0069] FIG. 7 is an equivalent circuit diagram of a third control sub-circuit according to an example embodiment;

[0070] FIG. 8 is an equivalent circuit diagram of a light emitting control sub-circuit according to an example embodiment;

[0071] FIG. 9 is an equivalent circuit diagram of a pixel driving circuit according to an example embodiment;

[0072] FIG. 10 is a working timing diagram of the pixel driving circuit according to FIG. 9.

[0073] DETAILED DESCRIPTION

[0074] For the purpose of making the objects, technical solutions and advantages of the present disclosure clearer, the following will describe the embodiments of the present disclosure in detail with reference to the drawings. Note that the embodiments can be implemented in a variety of different forms. It should be understood by those skilled in the art that the embodiments and contents can be changed into various forms without departing from the spirit and scope of the present disclosure. Therefore, the present disclosure should not be interpreted as being limited to the contents described in the following embodiments. The embodiments in the present disclosure and the features in the embodiments can be combined with each other arbitrarily without conflict. In order to keep the following description of the embodiments of the present disclosure clear and brief, the present disclosure omits the detailed description of some known functions and known components. The drawings of the embodiments of the present disclosure only involve the structures related to the embodiments of the present disclosure, and other structures can be referred to the generally designed

[0075] The scale of the drawings in the present disclosure can be used as a reference in the actual process, but is not limited thereto. For example, the width-length ratio of the channel, the thickness and spacing of each film layer, and the width and spacing of each signal line can be adjusted according to actual needs. The number of pixels in the display substrate and the number of sub-pixels in each pixel are also not limited to the number shown in the drawings. The drawings described in the present disclosure are only schematic structural diagrams, and one embodiment of the present disclosure is not limited to the shapes or values shown in the drawings.

[0076] In the present specification, ordinal numbers such as "first", "second", "third" and the like are provided to avoid confusion of components, and are not intended to be limited in terms of quantity.

[0077] In the present specification, for the convenience of description, words indicating the orientation or positional relationship such as "middle", "upper", "lower", "front", "rear", "vertical", "horizontal", "top", "bottom", "inner", "outer" and the like are used to describe the positional relationship of the components with reference to the drawings, and are only for the convenience of description of the present specification and simplification of the description, and are not intended to indicate or imply that the device or element referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as a limitation on the present disclosure. The positional relationship of the components is appropriately changed according to the direction of describing each component. Therefore, it is not limited to the words described in the specification, and can be appropriately changed according to the situation.

[0078] In the present specification, unless explicitly specified and limited, the terms "mount", "connect", "connection" should be understood broadly. For example, it can be fixedly connected, or detachably connected, or integrally connected; it can be mechanically connected, or electrically connected; it can be directly connected, or indirectly connected through an intermediate piece, or the communication inside two elements. For those skilled in the art, the specific meaning of the above terms in the present disclosure can be understood according to the specific circumstances.

[0079] In this specification, a transistor means an element including at least three terminals of a gate electrode, a drain electrode, and a source electrode. The transistor has a channel region between the drain electrode (a drain electrode terminal, a drain region, or a drain electrode) and the source electrode (a source electrode terminal, a source region, or a source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. Note that, in this specification, the channel region means a region where current flows mainly.

[0080] In this specification, the first electrode can be a drain electrode and the second electrode can be a source electrode, or the first electrode can be a source electrode and the second electrode can be a drain electrode. In the case of using a transistor having opposite polarity or in the case of changing the direction of current in circuit operation, the functions of the "source electrode" and the "drain electrode" are sometimes interchanged. Thus, in this specification, the "source electrode" and the "drain electrode" can be interchanged with each other.

[0081] In this specification, "electrically connected" includes the case where components are connected through an element having some function of electricity. The element having some function of electricity is not particularly limited as long as electric signals can be transmitted and received between components to be connected. Examples of the element having some function of electricity include not only an electrode and a wiring but also a switching element such as a transistor, a resistor, an inductor, a capacitor, and another element having some function.

[0082] In this specification, "parallel" means a state where an angle formed between two straight lines is greater than or equal to -10° and less than or equal to 10°, and thus includes a state where the angle is greater than or equal to -5° and less than or equal to 5°. In addition, "perpendicular" means a state where an angle formed between two straight lines is greater than or equal to 80° and less than or equal to 100°, and thus includes a state where the angle is greater than or equal to 85° and less than or equal to 95°.

[0083] In this specification, "film" and "layer" can be interchanged with each other. For example, "a conductive layer" can be changed into "a conductive film". Similarly, "an insulating film" can be changed into "an insulating layer".

[0084] In this specification, "disposed in the same layer" means that two (or more) structures are patterned by the same patterning process, and the materials thereof can be the same or different. For example, the materials of precursors for forming the two (or more) structures disposed in the same layer are the same, and the materials finally formed can be the same or different.

[0085] In this specification, a triangle, a rectangle, a trapezoid, a pentagon, or a hexagon is not strictly a triangle, a rectangle, a trapezoid, a pentagon, or a hexagon, but can be an approximately triangle, a rectangle, a trapezoid, a pentagon, or a hexagon, and can have some small deformation due to a tolerance, can have a rounded corner, a rounded side, and deformation, or the like.

[0086] In the present disclosure, "about" means not strictly limited boundaries, allowing values within the range of process and measurement errors.

[0087] The display panel of the OLED or QLED includes a substrate and a plurality of sub-pixels disposed on the substrate, at least one of the sub-pixels including a pixel driving circuit. At present, when the threshold voltage of the driving transistor in the pixel driving circuit is compensated by using the source following compensation mode, the following efficiency will affect the display effect.

[0088] FIG. 1 is a structural schematic diagram of a pixel driving circuit provided by an example embodiment of the present disclosure. As shown in FIG. 1, the pixel driving circuit can include a driving sub-circuit, a node control sub-circuit, a following sub-circuit, and a light-emitting control sub-circuit.

[0089] The driving sub-circuit is electrically connected with the first node N1, the second node N2, and the third node N3 respectively, and is configured to provide a driving current to the third node N3 under the control of signals of the first node N1 and the second node N2.

[0090] The node control sub-circuit is electrically connected with the second node N2, a data signal line Data, a bias signal line Var, a first scan signal line Gate1 to a fourth scan signal line Gate4, a fourth node N4, a fifth node N5, and a reference signal line Vref respectively, and is configured to provide a signal of the reference signal line Vref to at least one of the second node N2 and the fifth node N5, provide a signal of the data signal line Data to the second node N2, and provide a signal of the bias signal line Var to the fourth node N4 under the control of signals of the first scan signal line Gate1 to the fourth scan signal line Gate4.

[0091] The following sub-circuit is electrically connected with the second node N2, the third node N3, the fifth node N5, and a second light-emitting signal line EM2 respectively, and is configured to transmit a change amount of the potential of the third node N3 to the second node N2 under the control of a signal of the second light-emitting signal line EM2.

[0092] The light-emitting control sub-circuit is electrically connected with a first power supply line VDD, a first light-emitting signal line EM1, the first node N1, the third node N3, the second light-emitting signal line EM2, and the fourth node N4 respectively, and is configured to provide a signal of the first power supply line VDD to the first node N1 and provide a signal of the third node N3 to the fourth node N4 under the control of signals of the first light-emitting signal line EM1 and the second light-emitting signal line EM2.

[0093] The driving sub-circuit is electrically connected with the first node N1, the second node N2 and the third node N3 respectively, and can provide a driving current to the third node N3 under the control of signals of the first node N1 and the second node N2. The following sub-circuit is electrically connected with the second node N2, the third node N3, the fifth node N5 and the second light-emitting signal line EM2 respectively, and can transmit a change amount of the potential of the third node N3 to the second node N2 under the control of a signal of the second light-emitting signal line EM2. By transmitting the change amount of the potential of the third node N3 to the second node N2 through the following sub-circuit, the voltage between the second node N2 and the third node N3 connected with the driving sub-circuit can be kept in a relatively stable range, the uniformity is kept, the following efficiency is improved, and the display effect is improved.

[0094] FIG. 2 is an equivalent circuit diagram of a driving sub-circuit provided by an example embodiment. As shown in FIG. 2, in an example embodiment, the driving sub-circuit can include a second transistor T2.

[0095] In an example embodiment, as shown in FIG. 2, the control electrode of the second transistor T2 is electrically connected with the second node N2, the first electrode of the second transistor T2 is electrically connected with the first node N1, and the second electrode of the second transistor T2 is electrically connected with the third node N3.

[0096] In an example embodiment, the second transistor T2 can be referred to as a driving transistor, and the driving current flowing between the first node N1 and the third node N3 is determined according to the potential difference between the gate electrode (also the second node N2) and the first electrode (also the first node N1) of the second transistor T2.

[0097] In an example embodiment, the first electrode (also the first node N1) of the second transistor T2 can be a drain electrode, and the second electrode (also the third node N3) can be a source electrode. By transmitting the change amount of the potential of the third node N3 to the second node N2 through the following sub-circuit, the efficiency of the source follower is improved, the voltage between the control electrode and the second electrode of the second transistor T2 is kept in a relatively stable range, and the uniformity is kept.

[0098] An example structure of the driving sub-circuit is shown in FIG. 2. It is easy for those skilled in the art to understand that the implementation of the driving sub-circuit is not limited to this.

[0099] FIG. 3 is an equivalent circuit diagram of a following sub-circuit provided by an example embodiment. As shown in FIG. 3, in an example embodiment, the following sub-circuit can include a first capacitor C1, a second capacitor C2 and a seventh transistor T7.

[0100] In an example embodiment, as shown in FIG. 3, the first capacitor C1 includes a first plate C11 and a second plate C12, the first plate C11 of the first capacitor is electrically connected to the second node N2, and the second plate C12 of the first capacitor is electrically connected to the third node N3; the second capacitor C2 includes a first plate C21 and a second plate C22, the first plate C21 of the second capacitor is electrically connected to the third node N3, and the second plate C22 of the second capacitor is electrically connected to the fifth node N5; the control electrode of the seventh transistor T7 is electrically connected to the second light-emitting signal line EM2, the first electrode of the seventh transistor T7 is electrically connected to the second node N2, and the second electrode of the seventh transistor T7 is electrically connected to the fifth node N5.

[0101] In the embodiments of the present disclosure, the follower sub-circuit can transmit the change amount of the potential of the third node N3 to the second node N2 by setting the seventh transistor T7 and the timing cooperation to realize the parallel connection of the first capacitor C1 and the second capacitor C2, can improve the following efficiency, keep the voltage between the control electrode and the second electrode of the second transistor T2 in a relatively stable range, and keep the uniformity. In addition, the parallel connection of the first capacitor C1 and the second capacitor C2 can improve the compensation accuracy of the threshold voltage Vth of the second transistor T2.

[0102] In an example embodiment, the difference between the capacitance values of the first capacitor C1 and the second capacitor C2 is less than or equal to a set threshold value. The capacitance values of the first capacitor C1 and the second capacitor C2 are the same or similar, which can avoid the influence of the too small driving current flowing to the third node N3 on the display effect on the basis of realizing the parallel connection of the first capacitor C1 and the second capacitor C2.

[0103] In an example embodiment, the capacitance value of at least one of the first capacitor C1 and the second capacitor C2 can be 100 femto Farad (fF) to 300 femto Farad (fF), 1 femto Farad (fF) = 10^-15 Farad (F). For example, the capacitance value of at least one of the first capacitor C1 and the second capacitor C2 can be 200 femto Farad (fF).

[0104] An example structure of the follower sub-circuit is shown in FIG. 3. It is easy for those skilled in the art to understand that the implementation of the follower sub-circuit is not limited to this.

[0105] FIG. 4 is an equivalent circuit diagram of a node control sub-circuit provided by an example embodiment. As shown in FIG. 4, in an example embodiment, the node control sub-circuit can include a first control sub-circuit to a third control sub-circuit.

[0106] The first control sub-circuit is electrically connected with the second node N2, the first scan signal line Gate1, the third scan signal line Gate3, the fifth node N5 and the reference signal line Vref respectively, and is configured to provide a signal of the reference signal line Vref to at least one of the second node N2 and the fifth node N5 under control of signals of the first scan signal line Gate1 and the third scan signal line Gate3.

[0107] The second control sub-circuit is electrically connected with the second scan signal line Gate2, the data signal line Data and the second node N2 respectively, and is configured to provide a signal of the data signal line Data to the second node N2 under control of a signal of the second scan signal line Gate2.

[0108] The third control sub-circuit is electrically connected with the fourth scan signal line Gate4, the bias signal line Var and the fourth node N4 respectively, and is configured to provide a signal of the bias signal line Var to the fourth node N4 under control of a signal of the fourth scan signal line Gate4.

[0109] An exemplary structure of the node control sub-circuit is shown in FIG. 4. It is easily understood by those skilled in the art that the implementation of the node control sub-circuit is not limited to this.

[0110] An equivalent circuit diagram of the first control sub-circuit provided by an exemplary embodiment is shown in FIG. 5. As shown in FIG. 5, in an exemplary embodiment, the first control sub-circuit can include a fifth transistor T5 and an eighth transistor T8.

[0111] In an exemplary embodiment, as shown in FIG. 5, the control electrode of the fifth transistor T5 is electrically connected with the first scan signal line Gate1, the first electrode of the fifth transistor T5 is electrically connected with the reference signal line Vref, and the second electrode of the fifth transistor T5 is electrically connected with the second node N2; the control electrode of the eighth transistor T8 is electrically connected with the third scan signal line Gate3, the first electrode of the eighth transistor T8 is electrically connected with the fifth node N5, and the second electrode of the eighth transistor T8 is electrically connected with the reference signal line Vref.

[0112] An exemplary structure of the first control sub-circuit is shown in FIG. 5. It is easily understood by those skilled in the art that the implementation of the first control sub-circuit is not limited to this.

[0113] An equivalent circuit diagram of the second control sub-circuit provided by an exemplary embodiment is shown in FIG. 6. As shown in FIG. 6, in an exemplary embodiment, the second control sub-circuit can include a sixth transistor T6.

[0114] In an example embodiment, as shown in FIG. 6, the control electrode of the sixth transistor T6 is electrically connected with the second scan signal line Gate2, the first electrode of the sixth transistor T6 is electrically connected with the data signal line Data, and the second electrode of the sixth transistor T6 is electrically connected with the second node N2.

[0115] An example structure of the second control sub-circuit is shown in FIG. 6. It is easily understood by those skilled in the art that the implementation of the second control sub-circuit is not limited to this.

[0116] FIG. 7 is an equivalent circuit diagram of a third control sub-circuit according to an example embodiment. As shown in FIG. 7, in an example embodiment, the third control sub-circuit can include a fourth transistor T4.

[0117] In an example embodiment, as shown in FIG. 7, the control electrode of the fourth transistor T4 is electrically connected with the fourth scan signal line Gate4, the first electrode of the fourth transistor T4 is electrically connected with the fourth node N4, and the second electrode of the fourth transistor T4 is electrically connected with the bias signal line Var.

[0118] An example structure of the third control sub-circuit is shown in FIG. 7. It is easily understood by those skilled in the art that the implementation of the third control sub-circuit is not limited to this.

[0119] FIG. 8 is an equivalent circuit diagram of a light emitting control sub-circuit according to an example embodiment. As shown in FIG. 8, in an example embodiment, the light emitting control sub-circuit can include a first transistor T1 and a third transistor T3.

[0120] In an example embodiment, as shown in FIG. 8, the control electrode of the first transistor T1 is electrically connected with the first light emitting signal line EM1, the first electrode of the first transistor T1 is electrically connected with the first power supply line VDD, and the second electrode of the first transistor T1 is electrically connected with the first node N1; the control electrode of the third transistor T3 is electrically connected with the second light emitting signal line EM2, the first electrode of the third transistor T3 is electrically connected with the third node N3, and the second electrode of the third transistor T3 is electrically connected with the fourth node N4.

[0121] In an example embodiment, as shown in FIG. 8, the fourth node N4 can be electrically connected with the first electrode of the light emitting device L.

[0122] In an example embodiment, the first transistor T1 can be referred to as a first light emitting transistor, and the third transistor T3 can be referred to as a second light emitting transistor. When the first light emitting signal line EM1 and the second light emitting signal line EM2 input valid level signals, the first transistor T1 and the third transistor T3 are turned on, and the light emitting device L emits light by forming a driving current path between the first power supply line VDD and the second power supply line VSS.

[0123] An exemplary structure of the light emitting control sub-circuit is shown in FIG. 8. It is easy for those skilled in the art to understand that the implementation of the light emitting control sub-circuit is not limited to this.

[0124] FIG. 9 is an equivalent circuit diagram of a pixel driving circuit according to an exemplary embodiment. As shown in FIG. 9, in an exemplary embodiment, the pixel driving circuit can include a driving sub-circuit, a node control sub-circuit, a following sub-circuit and a light emitting control sub-circuit, the light emitting control sub-circuit can include a first transistor T1 and a third transistor T3, the driving sub-circuit can include a second transistor T2, the node control sub-circuit can include a fourth transistor T4 to a sixth transistor T6 and an eighth transistor T8, and the following sub-circuit can include a first capacitor C1, a second capacitor C2 and a seventh transistor T7.

[0125] In an example embodiment, as shown in FIG. 9, the control electrode of the first transistor T1 is electrically connected with the first light-emitting signal line EM1, the first electrode of the first transistor T1 is electrically connected with the first power supply line VDD, and the second electrode of the first transistor T1 is electrically connected with the first node N1; the control electrode of the second transistor T2 is electrically connected with the second node N2, the first electrode of the second transistor T2 is electrically connected with the first node N1, and the second electrode of the second transistor T2 is electrically connected with the third node N3; the control electrode of the third transistor T3 is electrically connected with the second light-emitting signal line EM2, the first electrode of the third transistor T3 is electrically connected with the third node N3, and the second electrode of the third transistor T3 is electrically connected with the fourth node N4; the control electrode of the fourth transistor T4 is electrically connected with the fourth scan signal line Gate4, the first electrode of the fourth transistor T4 is electrically connected with the fourth node N4, and the second electrode of the fourth transistor T4 is electrically connected with the bias signal line Var; the control electrode of the fifth transistor T5 is electrically connected with the first scan signal line Gate1, the first electrode of the fifth transistor T5 is electrically connected with the reference signal line Vref, and the second electrode of the fifth transistor T5 is electrically connected with the second node N2; the control electrode of the sixth transistor T6 is electrically connected with the second scan signal line Gate2, the first electrode of the sixth transistor T6 is electrically connected with the data signal line Data, and the second electrode of the sixth transistor T6 is electrically connected with the second node N2; the control electrode of the seventh transistor T7 is electrically connected with the second light-emitting signal line EM2, the first electrode of the seventh transistor T7 is electrically connected with the second node N2, and the second electrode of the seventh transistor T7 is electrically connected with the fifth node N5; the control electrode of the eighth transistor T8 is electrically connected with the third scan signal line Gate3, the first electrode of the eighth transistor T8 is electrically connected with the fifth node N5, and the second electrode of the eighth transistor T8 is electrically connected with the reference signal line Vref; the first capacitor C1 includes a first plate C11 and a second plate C12, the first plate C11 of the first capacitor is electrically connected with the second node N2, and the second plate C12 of the first capacitor is electrically connected with the third node N3; the second capacitor C2 includes a first plate C21 and a second plate C22, the first plate C21 of the second capacitor is electrically connected with the third node N3, and the second plate C22 of the second capacitor is electrically connected with the fifth node N5.

[0126] In an example embodiment, as shown in FIG. 9, at least one of the first transistor T1 to the eighth transistor T8 is an N-type transistor.

[0127] An example structure of the pixel driving circuit is shown in FIG. 9. It is easy for those skilled in the art to understand that the implementation of the pixel driving circuit is not limited to this.

[0128] FIG. 10 is a timing diagram of the pixel driving circuit provided in FIG. 9. The working process of the pixel driving circuit exemplified by FIG. 9 is described below to illustrate the example embodiments of the present disclosure. The working process of the pixel driving circuit can include:

[0129] The first stage P1 is called the initial stage. The signals of the first scan signal line Gate1, the third scan signal line Gate3, the fourth scan signal line Gate4 and the second emitting signal line EM2 are all high-level signals, and the signals of the first emitting signal line EM1 and the second scan signal line Gate2 are both low-level signals. The signal of the first scan signal line Gate1 is a high-level signal, the fifth transistor T5 is turned on, the signal of the reference signal line Vref is provided to the second node N2, the gate electrode of the second transistor T2 (i.e. the second node N2) is initialized, for example, the internal pre-stored voltage is emptied, and the initialization is completed. The signal of the third scan signal line Gate3 is a high-level signal, the eighth transistor T8 is turned on, and the signal of the reference signal line Vref is provided to the fifth node N5. The signal of the second emitting signal line EM2 is a high-level signal, the seventh transistor T7 is turned on, and the second node N2 and the fifth node N5 are connected, and the initialization of the second node N2 is continued. The signal of the fourth scan signal line Gate4 is a high-level signal, the fourth transistor T4 is turned on, and the signal of the bias voltage signal line Var is provided to the fourth node, and the fourth node N4 is initialized. The signal of the second emitting signal line EM2 is a high-level signal, the third transistor T3 is turned on, the signal of the fourth node N4 is written to the third node N3, the third node N3 is initialized, the second transistor T2 is turned on, and the signal of the third node N1 is written to the first node N1, and the first node N1 is initialized. The first transistor T1 and the sixth transistor T6 are disconnected.

[0130] The fourth node N4 is electrically connected to the first electrode of the light emitting device L. When the fourth transistor T4 is turned on, the fourth node N4 provides the initial voltage of the bias voltage signal line Var to the first electrode of the light emitting device L, initializes (resets) the first electrode of the light emitting device L, for example, empties the internal pre-stored voltage, completes the initialization, and ensures that the light emitting device L does not emit light. In this stage, the light emitting device L does not emit light.

[0131] In an example embodiment, as shown in FIG. 10, the start time of the time period in which the first scan signal line Gate1 is an active level signal (such as a high-level signal) is earlier than or equal to the start time of the time period in which the third scan signal line Gate3 is an active level signal (such as a high-level signal). The start time of the time period in which the third scan signal line Gate3 is an active level signal is earlier than or equal to the start time of the time period in which the fourth scan signal line Gate4 is an active level signal (such as a high-level signal).

[0132] In an example embodiment, as shown in FIG. 10, the end time of the period in which the first scan signal line Gate 1 is an active level signal is earlier than or equal to the end time of the period in which the third scan signal line Gate 3 is an active level signal; the end time of the period in which the third scan signal line Gate 3 is an active level signal is earlier than or equal to the end time of the period in which the fourth scan signal line Gate 4 is an active level signal.

[0133] In an example embodiment, as shown in FIG. 10, the start time of the period in which the second scan signal line Gate 2 is an active level signal (e.g., a high level signal) is later than or equal to the end time of the period in which the first scan signal line Gate 1 is an active level signal; the end time of the period in which the second scan signal line Gate 2 is an active level signal is earlier than or equal to the start time of the period in which the third scan signal line Gate 3 is an active level signal.

[0134] The second stage P2 is a compensation stage (also referred to as a second transistor T2 threshold voltage Vth sampling stage). The signals of the first emission signal line EM 1, the first scan signal line Gate 1, the third scan signal line Gate 3, and the fourth scan signal line Gate 4 are all high level signals, and the signals of the second emission signal line EM 2 and the second scan signal line Gate 2 are all low level signals. The signal of the second emission signal line EM 2 is a low level signal, and the third transistor T3 and the seventh transistor T7 are turned off. The signal of the first emission signal line EM 1 is a high level signal, the first transistor T1 is turned on, and the signal of the first power supply line VDD charges the third node N3 through the first node N1 and the turned-on second transistor T2 until the voltage VN3 of the third node N3 = Vf-Vth, where Vf is the voltage value of the signal of the reference voltage signal line Vref. The signals of the first scan signal line Gate 1, the third scan signal line Gate 3, and the fourth scan signal line Gate 4 are high level signals, respectively, and the fifth transistor T5, the eighth transistor T8, and the fourth transistor T4 maintain the on state of the previous node, respectively. The signals of the second node N2, the fifth node N5, and the fourth node N4 remain unchanged from the previous stage. The sixth transistor T6 is turned off. In this stage, the light emitting device L does not emit light.

[0135] In an example embodiment, the signal of the first light-emitting signal line EM1 is the start time of the time period in which the signal is a valid level signal (e.g., a high level signal), which is later than or equal to the end time of the signal of the second light-emitting signal line EM2 being a valid level signal (e.g., a high level signal). The start time of the signal of the first light-emitting signal line EM1 being a high level signal marks the start of the second stage P2 sampling. After the signal of the second light-emitting signal line EM2 is a low level signal, the signal of the first light-emitting signal line EM1 starts to be a high level signal. The duration of the second stage P2 is the time of sampling the threshold voltage Vth of the second transistor T2, and the longer the duration of the second stage P2, the more accurate the compensation of the threshold voltage Vth of the second transistor T2.

[0136] The third stage P3 is referred to as a writing stage, in which the signals of the second scan signal line Gate2, the third scan signal line Gate3, and the fourth scan signal line Gate4 are high level signals, and the signals of the first light-emitting signal line EM1, the second light-emitting signal line EM2, and the first scan signal line Gate1 are low level signals. The signal of the first light-emitting signal line EM1 is a low level signal, the first transistor T1 is turned off, the signal of the first scan signal line Gate1 is a low level signal, and the fifth transistor T5 is turned off. The signal of the second scan signal line Gate2 is a high level signal, the sixth transistor T6 is turned on, and the signal of the data signal line Data is written to the second node N2. At this time, the voltage value of the signal of the second node N2 is VN2=Vdata-Vr, and the change in the voltage value of the signal of the third node N3 is (C1 / (C1+C2))*(Vdata-Vr) under the action of the first capacitor C1 and the second capacitor C2. At this time, the voltage VN3 of the third node N3 is Vr-Vth+(C1 / (C1+C2))*(Vdata-Vr), where C1 is the capacitance value of the first capacitor C1, and C2 is the capacitance value of the second capacitor C2. The signals of the third scan signal line Gate3 and the fourth scan signal line Gate4 are high level signals, respectively, and the eighth transistor T8 and the fourth transistor T4 maintain the on state of the previous node, and the signals of the fifth node N5 and the fourth node N4 remain unchanged from the previous stage. Among them, the third transistor T3 and the seventh transistor T7 are turned off. In this stage, the light-emitting device L does not emit light.

[0137] The fourth stage P4 is called a light emitting stage, and signals of the first light emitting signal line EM1, the second light emitting signal line EM2 and the second scan signal line Gate2 are all high level signals, and signals of the first scan signal line Gate1, the third scan signal line Gate3 and the fourth scan signal line Gate4 are all high level signals. Signals of the third scan signal line Gate3 and the fourth scan signal line Gate4 are low level signals respectively, and the eighth transistor T8 and the fourth transistor T4 are turned off. Signals of the first light emitting signal line EM1 and the second light emitting signal line EM2 are high level signals respectively, and the first transistor T1 and the third transistor T3 are turned on respectively, and a driving voltage output by the first power supply line VDD is provided to the first electrode of the light emitting device L through the turned-on first transistor T1, the turned-on second transistor T2 and the turned-on third transistor T3, so as to drive the light emitting device L to emit light.

[0138] In the P4 stage, the third scan signal line Gate3 becomes a low level signal first, and then the signal of the second light emitting signal line EM2 is a high level signal, and the signal of the third node N3 becomes the signal of the bias voltage signal line Var. At this time, source following occurs, that is, the second node N2 and the third node N3 have the same change amount.

[0139] In an example embodiment, the capacitance value of at least one of the first capacitor C1 and the second capacitor C2 can be 100 femtofarad (fF) to 300 femtofarad (fF). For example, the capacitance value of at least one of the first capacitor C1 and the second capacitor C2 can be 200 femtofarad (fF), and the capacitance value C3 of the parasitic capacitor C3 on the second node N2 ranges from 10 fF to 15 fF. Due to the P4 stage, the second light emitting signal line EM2 is a high level signal, the seventh transistor T7 is turned on, and the first capacitor C1 and the second capacitor C2 are in parallel, and at this time, the efficiency of the source follower is (C1+C2) / (C1+C2+C3) = 400 / (400+15) = 96.5%. By forming the first capacitor C1 and the second capacitor C2 in parallel, the efficiency of the source follower can be improved, the voltage difference Vgs between the gate electrode and the first electrode of the second transistor T2 is kept unchanged, and uniformity is ensured.

[0140] In the P4 stage, after the signal of the second light-emitting signal line EM2 is a high level signal, the signals of the first light-emitting signal line EM1 and the fourth scan signal line Gate4 are high level signals, the first transistor T1 and the fourth transistor T4 are opened respectively, at this time, the voltage of the third node N3 becomes the sum of the voltage Vs of the second power supply line VSS and the voltage Va of the bias voltage signal line Var, the change amount of the voltage of the third node N3 is Vs+Va-(Vr-Vth+(C1 / (C1+C2)*(Data-Vref)); the voltage value of the signal of the second node N2 becomes Vd+(C1+C2) / (C1+C2+C3)*(Vs+Va-(Vr-Vth+(C1 / (C1+C2))*(Vd-Vr)), Vd is the data voltage output by the data signal line Data.

[0141] Let C1+C2+C3=C, the capacitance value of the capacitor C is C0, that is:

[0142] Vgs=Vd*(1-C1 / C0)-Vr*(C2 / C0)-(Vs+Va)*C3 / C0+Vth*((C1+C2) / C0).

[0143] The greater the capacitance C is, the better the compensation effect of the threshold voltage Vth of the second transistor T2 is, therefore, the parallel mode of the capacitor can enhance the effect of compensating Vth.

[0144] In the driving process of the pixel driving circuit, the driving current flowing through the second transistor T2 (the driving transistor) is determined by the voltage difference between the gate electrode and the first electrode. Assuming that C3 is ignored, the voltage difference Vgs between the gate electrode and the first electrode of the second transistor T2 is (Vd-Vr)*(1-C1 / C0)+Vth, and thus the driving current of the second transistor T2 is:

[0145] I=K*(Vgs-Vth)^2=K((Vd-Vref)*(1-C1 / C0))^2.

[0146] Wherein, I is the driving current flowing through the second transistor T2, that is, the driving current of the light-emitting device L, K is a constant, Vgs is the voltage difference between the gate electrode and the first electrode of the second transistor T2, Vth is the threshold voltage of the second transistor T2, Vd is the data voltage output by the data signal line Data, and Vr is the reference voltage output by the reference signal line Vref.

[0147] The display device provided by the embodiment of the present disclosure comprises a pixel driving circuit.

[0148] The pixel driving circuit is the pixel driving circuit provided by any one of the foregoing embodiments, and has similar implementation principles and implementation effects, which will not be described here again.

[0149] In an example embodiment, the display device can further include a first control unit, a second control unit, a third control unit, and a fourth control unit.

[0150] The first control unit is electrically connected to the first scan signal line and configured to provide a signal to the first scan signal line. The second control unit is electrically connected to the second scan signal line and configured to provide a signal to the second scan signal line. The third control unit is electrically connected to the third scan signal line and configured to provide a signal to the third scan signal line. The fourth control unit is electrically connected to the fourth scan signal line and configured to provide a signal to the fourth scan signal line.

[0151] The content displayed by the display device includes a plurality of display frames. In at least one display frame, a time period in which the first control unit provides an active level signal to the first scan signal line at least partially overlaps at least one of a time period in which the third control unit provides an active level signal to the third scan signal line and a time period in which the fourth control unit provides an active level signal to the second scan signal line, and does not overlap a time period in which the second control unit provides an active level signal to the second scan signal line.

[0152] In an example embodiment, as shown in FIG. 10, a time period in which the second control unit provides an active level signal to the second scan signal line at least partially overlaps at least one of a time period in which the third control unit provides an active level signal to the third scan signal line and a time period in which the fourth control unit provides an active level signal to the second scan signal line.

[0153] In an example embodiment, as shown in FIG. 10, a time period in which the third control unit provides an active level signal to the third scan signal line at least partially overlaps a time period in which the fourth control unit provides an active level signal to the fourth scan signal line.

[0154] In an example embodiment, a start time of a time period in which the first control unit provides an active level signal to the first scan signal line is earlier than or equal to a start time of a time period in which the third control unit provides an active level signal to the third scan signal line. A start time of a time period in which the third control unit provides an active level signal to the third scan signal line is earlier than or equal to a start time of a time period in which the fourth control unit provides an active level signal to the fourth scan signal line.

[0155] The first control unit provides an end time of a time period in which the first control unit provides the active level signal to the first scan signal line, which is earlier than or equal to an end time of a time period in which the third control unit provides the active level signal to the third scan signal line; the third control unit provides an end time of a time period in which the third control unit provides the active level signal to the third scan signal line, which is earlier than or equal to an end time of a time period in which the fourth control unit provides the active level signal to the fourth scan signal line; the second control unit provides a start time of a time period in which the second control unit provides the active level signal to the second scan signal line, which is later than or equal to an end time of a time period in which the first control unit provides the active level signal to the first scan signal line; and the second control unit provides an end time of a time period in which the second control unit provides the active level signal to the second scan signal line, which is earlier than or equal to a start time of a time period in which the third control unit provides the active level signal to the third scan signal line.

[0156] In an example embodiment, the display device can further include a fifth control unit and a sixth control unit; the fifth control unit is electrically connected to the first light-emitting signal line and is configured to provide a signal to the first light-emitting signal line; and the sixth control unit is electrically connected to the second light-emitting signal line and is configured to provide a signal to the second light-emitting signal line.

[0157] The content displayed by the display device includes a plurality of display frames, and in at least one display frame, a time period in which the fifth control unit provides the active level signal to the first light-emitting signal line at least partially overlaps with a time period in which the sixth control unit provides the active level signal to the second light-emitting signal line.

[0158] In an example embodiment, as shown in FIG. 10, a start time of a time period in which the fifth control unit provides the active level signal to the first light-emitting signal line is later than or equal to an end time of a time period in which the sixth control unit provides the active level signal to the second light-emitting signal line.

[0159] The display device provided in the embodiments of the present disclosure further provides a driving method of a pixel driving circuit, which is configured to drive the pixel driving circuit, and the driving method of the pixel driving circuit includes:

[0160] The driving sub-circuit provides a driving current to the third node under the control of the signals at the first node and the second node;

[0161] The node control sub-circuit provides a signal of the reference signal line to at least one of the second node and the fifth node, a signal of the data signal line to the second node, and a signal of the bias signal line to the fourth node under the control of the signals of the first scan signal line to the fourth scan signal line;

[0162] The following sub-circuit transmits a change amount of the potential of the third node to the second node under the control of the signal of the second light-emitting signal line;

[0163] The light emitting control sub-circuit provides a signal of the first power supply line to the first node and a signal of the third node to the fourth node under the control of signals of the first light emitting signal line and the second light emitting signal line.

[0164] The pixel driving circuit is the pixel driving circuit provided by any one of the foregoing embodiments, and has similar implementation principles and implementation effects, which will not be described here.

[0165] The drawings in the disclosure only relate to the structures involved in the embodiments of the disclosure, and other structures can be referred to the general design.

[0166] For the sake of clarity, the thickness and size of the layer or microstructure are exaggerated in the drawings used to describe the embodiments of the disclosure. It can be understood that when an element such as a layer, film, region or substrate is referred to as being "on" or "under" another element, it can be "directly" on or under the other element, or there can be an intermediate element.

[0167] Although the embodiments disclosed in the disclosure are as described above, the content described is only the embodiment adopted for the purpose of facilitating the understanding of the disclosure, and is not intended to limit the disclosure. Any person skilled in the art of the disclosure can make any modification and change in the form and details without departing from the spirit and scope of the disclosure, but the patent protection scope of the disclosure shall be subject to the scope defined by the appended claims.

Claims

1. A pixel driving circuit, comprising: Driver sub-circuit, node control sub-circuit, follower sub-circuit, and light-emitting control sub-circuit; The driving sub-circuit is electrically connected to the first node, the second node and the third node respectively, and is configured to provide driving current to the third node under the control of the signals of the first node and the second node. The node control sub-circuit is electrically connected to the second node, the data signal line, the bias signal line, the first scan signal line to the fourth scan signal line, the fourth node, the fifth node, and the reference signal line, respectively. It is configured to provide the reference signal line to at least one of the second node and the fifth node, provide the data signal line to the second node, and provide the bias signal line to the fourth node under the control of the signals of the first scan signal line to the fourth scan signal line. The follower sub-circuit is electrically connected to the second node, the third node, the fifth node, and the second light-emitting signal line, respectively, and is configured to transmit the potential change of the third node to the second node under the control of the signal of the second light-emitting signal line. The light-emitting control sub-circuit is electrically connected to the first power line, the first light-emitting signal line, the first node, the third node, the second light-emitting signal line, and the fourth node, respectively. It is configured to provide the first power line signal to the first node and the third node signal to the fourth node under the control of the signals of the first light-emitting signal line and the second light-emitting signal line.

2. The pixel driving circuit according to claim 1, wherein, The follower sub-circuit includes: a first capacitor, a second capacitor, and a seventh transistor; The first capacitor includes a first plate and a second plate. The first plate of the first capacitor is electrically connected to the second node, and the second plate of the first capacitor is electrically connected to the third node. The second capacitor includes a first plate and a second plate. The first plate of the second capacitor is electrically connected to the third node, and the second plate of the second capacitor is electrically connected to the fifth node. The control electrode of the seventh transistor is electrically connected to the second light-emitting signal line, the first electrode of the seventh transistor is electrically connected to the second node, and the second electrode of the seventh transistor is electrically connected to the fifth node.

3. The pixel driving circuit according to claim 2, wherein, The difference between the capacitance values ​​of the first capacitor and the second capacitor is less than or equal to a set threshold.

4. The pixel driving circuit according to claim 1, wherein, The node control sub-circuit includes: a first control sub-circuit to a third control sub-circuit; The first control sub-circuit is electrically connected to the second node, the first scan signal line, the third scan signal line, the fifth node, and the reference signal line, respectively, and is configured to provide the reference signal line signal to at least one of the second node and the fifth node under the control of the signals of the first scan signal line and the third scan signal line. The second control sub-circuit is electrically connected to the second scan signal line, the data signal line, and the second node, respectively, and is configured to provide the data signal line signal to the second node under the control of the signal of the second scan signal line. The third control sub-circuit is electrically connected to the fourth scan signal line, the bias signal line, and the fourth node, respectively, and is configured to provide the bias signal line signal to the fourth node under the control of the signal from the fourth scan signal line.

5. The pixel driving circuit according to claim 4, wherein, The first control sub-circuit includes: a fifth transistor and an eighth transistor; The control electrode of the fifth transistor is electrically connected to the first scan signal line, the first electrode of the fifth transistor is electrically connected to the reference signal line, and the second electrode of the fifth transistor is electrically connected to the second node. The control electrode of the eighth transistor is electrically connected to the third scan signal line, the first electrode of the eighth transistor is electrically connected to the fifth node, and the second electrode of the eighth transistor is electrically connected to the reference signal line.

6. The pixel driving circuit according to claim 4, wherein, The second control sub-circuit includes: a sixth transistor; The control electrode of the sixth transistor is electrically connected to the second scan signal line, the first electrode of the sixth transistor is electrically connected to the data signal line, and the second electrode of the sixth transistor is electrically connected to the second node.

7. The pixel driving circuit according to claim 4, wherein, The third control sub-circuit includes: a fourth transistor; The control electrode of the fourth transistor is electrically connected to the fourth scan signal line, the first electrode of the fourth transistor is electrically connected to the fourth node, and the second electrode of the fourth transistor is electrically connected to the bias signal line.

8. The pixel driving circuit according to claim 1, wherein, The driving sub-circuit includes: a second transistor; The control electrode of the second transistor is electrically connected to the second node, the first electrode of the second transistor is electrically connected to the first node, and the second electrode of the second transistor is electrically connected to the third node.

9. The pixel driving circuit according to claim 1, wherein, The light-emitting control sub-circuit includes: a first transistor and a third transistor; The control electrode of the first transistor is electrically connected to the first light-emitting signal line, the first electrode of the first transistor is electrically connected to the first power supply line, and the second electrode of the first transistor is electrically connected to the first node. The control electrode of the third transistor is electrically connected to the second light-emitting signal line, the first electrode of the third transistor is electrically connected to the third node, and the second electrode of the third transistor is electrically connected to the fourth node.

10. The pixel driving circuit according to claim 1, wherein, The light-emitting control sub-circuit includes a first transistor and a third transistor; the driving sub-circuit includes a second transistor; the node control sub-circuit includes a fourth to a sixth transistor and an eighth transistor; and the follower sub-circuit includes a first capacitor, a second capacitor, and a seventh transistor. The control electrode of the first transistor is electrically connected to the first light-emitting signal line, the first electrode of the first transistor is electrically connected to the first power supply line, and the second electrode of the first transistor is electrically connected to the first node. The control electrode of the second transistor is electrically connected to the second node, the first electrode of the second transistor is electrically connected to the first node, and the second electrode of the second transistor is electrically connected to the third node. The control electrode of the third transistor is electrically connected to the second light-emitting signal line, the first electrode of the third transistor is electrically connected to the third node, and the second electrode of the third transistor is electrically connected to the fourth node. The control electrode of the fourth transistor is electrically connected to the fourth scan signal line, the first electrode of the fourth transistor is electrically connected to the fourth node, and the second electrode of the fourth transistor is electrically connected to the bias signal line. The control electrode of the fifth transistor is electrically connected to the first scan signal line, the first electrode of the fifth transistor is electrically connected to the reference signal line, and the second electrode of the fifth transistor is electrically connected to the second node. The control electrode of the sixth transistor is electrically connected to the second scan signal line, the first electrode of the sixth transistor is electrically connected to the data signal line, and the second electrode of the sixth transistor is electrically connected to the second node. The control electrode of the seventh transistor is electrically connected to the second light-emitting signal line, the first electrode of the seventh transistor is electrically connected to the second node, and the second electrode of the seventh transistor is electrically connected to the fifth node. The control electrode of the eighth transistor is electrically connected to the third scan signal line, the first electrode of the eighth transistor is electrically connected to the fifth node, and the second electrode of the eighth transistor is electrically connected to the reference signal line. The first capacitor includes a first plate and a second plate. The first plate of the first capacitor is electrically connected to the second node, and the second plate of the first capacitor is electrically connected to the third node. The second capacitor includes a first plate and a second plate. The first plate of the second capacitor is electrically connected to the third node, and the second plate of the second capacitor is electrically connected to the fifth node.

11. The pixel driving circuit according to claim 10, wherein, At least one of the first to eighth transistors is an N-type transistor.

12. A display device, wherein, include: The pixel driving circuit as described in any one of claims 1 to 11.

13. The display device according to claim 12, wherein, The display device further includes: a first control unit, a second control unit, a third control unit, and a fourth control unit; A first control unit, electrically connected to a first scan signal line, is configured to provide a signal to the first scan signal line; a second control unit, electrically connected to a second scan signal line, is configured to provide a signal to the second scan signal line; a third control unit, electrically connected to a third scan signal line, is configured to provide a signal to the third scan signal line; and a fourth control unit, electrically connected to a fourth scan signal line, is configured to provide a signal to the fourth scan signal line. The content displayed by the display device includes multiple display frames. In at least one display frame, the time period during which the first control unit provides an effective level signal to the first scan signal line overlaps at least partially with the time period during which the third control unit provides an effective level signal to the third scan signal line and the time period during which the fourth control unit provides an effective level signal to the second scan signal line, and does not overlap with the time period during which the second control unit provides an effective level signal to the second scan signal line. The time period during which the second control unit provides an effective level signal to the second scan signal line overlaps at least partially with the time period during which the third control unit provides an effective level signal to the third scan signal line and the time period during which the fourth control unit provides an effective level signal to the second scan signal line. The time period during which the third control unit provides an effective level signal to the third scan signal line overlaps at least partially with the time period during which the fourth control unit provides an effective level signal to the fourth scan signal line.

14. The display device according to claim 13, wherein, The start time of the period during which the first control unit provides an effective level signal to the first scan signal line is earlier than or equal to the start time of the period during which the third control unit provides an effective level signal to the third scan signal line; the start time of the period during which the third control unit provides an effective level signal to the third scan signal line is earlier than or equal to the start time of the period during which the fourth control unit provides an effective level signal to the fourth scan signal line. The end time of the period in which the first control unit provides a valid level signal to the first scan signal line is earlier than or equal to the end time of the period in which the third control unit provides a valid level signal to the third scan signal line; the end time of the period in which the third control unit provides a valid level signal to the third scan signal line is earlier than or equal to the end time of the period in which the fourth control unit provides a valid level signal to the fourth scan signal line; the start time of the period in which the second control unit provides a valid level signal to the second scan signal line is later than or equal to the end time of the period in which the first control unit provides a valid level signal to the first scan signal line; and the end time of the period in which the second control unit provides a valid level signal to the second scan signal line is earlier than or equal to the start time of the period in which the third control unit provides a valid level signal to the third scan signal line.

15. The display device according to claim 12, wherein, The display device further includes: a fifth control unit and a sixth control unit; The fifth control unit is electrically connected to the first light-emitting signal line and is configured to provide a signal to the first light-emitting signal line; the sixth control unit is electrically connected to the second light-emitting signal line and is configured to provide a signal to the second light-emitting signal line. The content displayed by the display device includes multiple display frames. In at least one display frame, the time period during which the fifth control unit provides an effective level signal to the first light-emitting signal line overlaps at least partially with the time period during which the sixth control unit provides an effective level signal to the second light-emitting signal line.

16. The display device according to claim 15, wherein, The start time of the period during which the fifth control unit provides an effective level signal to the first light-emitting signal line is later than or equal to the end time of the period during which the sixth control unit provides an effective level signal to the second light-emitting signal line.

17. A method for driving a pixel driving circuit, configured to drive the pixel driving circuit as claimed in any one of claims 1 to 16, the method comprising: The driving sub-circuit provides driving current to the third node under the control of the signals from the first and second nodes; Under the control of the signals from the first scan signal line to the fourth scan signal line, the node control sub-circuit provides a reference signal line signal to at least one of the second and fifth nodes, a data signal line signal to the second node, and a bias signal line signal to the fourth node. Under the control of the signal from the second light-emitting signal line, the follower circuit transmits the potential change of the third node to the second node; Under the control of the signals from the first and second light-emitting signal lines, the light-emitting control sub-circuit provides the first power line signal to the first node and the third node signal to the fourth node.

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