Method for communication, device, storage medium, and program product

Abstract

A method for communication, a device, a storage medium, and a program product. In the method, a decoding apparatus decodes a low density parity check (LDPC) code on the basis of a belief propagation (BP) algorithm to obtain an initial bit sequence that does not meet a check equation set. In addition, the decoding apparatus obtains a plurality of candidate bit sequences on the basis of performing a plurality of bit flipping operations on the initial bit sequence. In one bit flipping operation, at least one bit of the initial bit sequence is flipped. Furthermore, the decoding apparatus determines, from among the plurality of candidate bit sequences, a target bit sequence, which meets a predetermined condition, to serve as a decoding result of the LDPC code. The BP algorithm may include algorithms such as BP and Min-Sum. The initial bit sequence may be a bit sequence obtained after hard decision is performed on the value of a variable node obtained by means of BP decoding. In this way, certain randomness is introduced by means of bit flipping, thereby counteracting the influence of noise or interference, and improving the decoding performance.

Description

Method, device, storage medium and program product for communication

[0001] This application claims priority to the Chinese patent application No. 202411002100.8, filed on July 24, 2024, with the State Intellectual Property Office, and entitled “Method, device, storage medium and program product for communication”, the entire content of which is incorporated herein by reference. TECHNICAL FIELD

[0002] Embodiments of the present application generally relate to the field of communication, and more particularly to a method, apparatus, computer readable storage medium and computer program product for communication. BACKGROUND

[0003] A mobile or wireless communication network can be seen as a facility that enables wireless communication between two or more communication devices or provides wireless access to a data network for communication devices. In order to enable interworking between communication devices, such as network devices, terminal devices, etc., corresponding communication standards are developed, such as standards developed by the 3rd Generation Partnership Project (3GPP) or the European Telecommunications Standards Institute (ETSI). Examples of such standards include the 5th Generation (5G) standard, the future wireless communication standard, etc. In various communication scenarios, low density parity check (LDPC) codes can be used. However, some aspects of LDPC codes still need further optimization. rd th Generation, 5G) standard, the future wireless communication standard, etc. In various communication scenarios, low density parity check (LDPC) codes can be used. However, some aspects of LDPC codes still need further optimization. SUMMARY

[0004] Embodiments of the present application provide a technical solution for communication, in particular to a technical solution for LDPC decoding.

[0005] ​In a first aspect, a decoding method is provided. The execution subject of the method can be a decoding apparatus or a chip applied in the decoding apparatus. Hereinafter, the execution subject is taken as the decoding apparatus for example. Unless otherwise specified, the "decoding apparatus" in the present application can refer to the decoding apparatus itself, a component (for example, a communication module, a processor, a circuit, a chip, or a chip system, etc.) in the decoding apparatus, or a logic module or software capable of realizing all or part of the functions of the decoding apparatus. Hereinafter, the execution subject is taken as the decoding apparatus for example. In the method, a decoding apparatus decodes a low-density parity-check (LDPC) code based on a belief propagation (BP) algorithm, and obtains an initial bit sequence that does not satisfy a check equation set. In addition, the decoding apparatus obtains a plurality of candidate bit sequences by performing a plurality of bit flipping operations on the initial bit sequence. In one bit flipping operation, at least one bit of the initial bit sequence is flipped. In addition, the decoding apparatus determines a target bit sequence that satisfies a predetermined condition from the plurality of candidate bit sequences as a decoding result of the LDPC code. The belief propagation algorithm can include a BP algorithm, a Min-Sum algorithm, etc. The initial bit sequence can be a bit sequence obtained after a hard decision of a value of a variable node of the BP decoding. In this way, a certain randomness is introduced by means of bit flipping, so as to resist the influence of noise or interference and improve decoding performance.

[0006] In some implementations, in one bit flipping operation, the number of at least one bit that is flipped is greater than or equal to 1 and less than or equal to a predetermined flipping order. In this way, a plurality of bits can be flipped under the condition that the decoding delay is allowed, so as to improve decoding performance.

[0007] In some implementations, the predetermined flipping order is determined by the decoding apparatus or indicated at a physical layer. In this way, decoding flexibility can be improved.

[0008] In some implementations, the decoding apparatus obtaining the plurality of candidate bit sequences includes: the decoding apparatus performing a plurality of bit flipping operations on the initial bit sequence to obtain a plurality of flipped bit sequences as the plurality of candidate bit sequences. In this way, all possible flipped bit positions can be flipped, and the plurality of candidate bit sequences can be obtained for decoding, so as to improve decoding performance.

[0009] In some implementations, obtaining, by the decoding device, the plurality of candidate bit sequences includes: performing, by the decoding device, a bit flipping operation on the initial bit sequence to obtain a flipped bit sequence. Further, setting, by the decoding device, a magnitude of a channel probability information value corresponding to a flipped bit in the flipped bit sequence to a predetermined value in a first set of channel probability information values corresponding to the LDPC code to obtain a second set of channel probability information values. Further, performing, by the decoding device, a BP algorithm based on the second set of channel probability values to obtain a decision bit sequence as one of the plurality of candidate bit sequences. The channel probability information value can be a log-likelihood ratio value. In this way, the BP decoding is performed again after bit flipping to eliminate errors as much as possible and improve decoding performance.

[0010] In some implementations, performing, by the decoding device, the plurality of bit flipping operations includes: obtaining, by the decoding device, a first set of candidate bit sequences based on performing a first set of bit flipping operations on the initial bit sequence. In the first set of bit flipping operations, different N bits of the initial bit sequence are flipped. Further, obtaining, by the decoding device, a second set of candidate bit sequences based on performing a second set of bit flipping operations on the initial bit sequence based on determining that the target bit sequence is not included in the first set of candidate bit sequences. In the second set of bit flipping operations, different N+1 bits of the initial bit sequence are flipped. N is greater than or equal to 1 and less than a predetermined flipping order. In this way, the number of flipped bits can be increased step by step to obtain more candidate bit sequences and improve decoding performance.

[0011] In some implementations, determining, by the decoding device, the target bit sequence includes: determining, by the decoding device, one of the plurality of candidate bit sequences as the target bit sequence based on determining that one of the plurality of candidate bit sequences satisfies the set of check equations. In this way, the target bit sequence can be quickly determined under the condition that one of the plurality of candidate bit sequences satisfies the set of check equations, and the decoding is fast.

[0012] In some implementations, determining, by the decoding device, the target bit sequence includes: determining, by the decoding device, the target bit sequence among more than one of the plurality of candidate bit sequences based on determining that more than one of the plurality of candidate bit sequences satisfies the set of check equations and based on at least one of a second index or a third index associated with the first set of channel probability information values corresponding to the LDPC code. In this way, the target bit sequence can be determined by performing optimization among the more than one of the plurality of candidate bit sequences under the condition that the more than one of the plurality of candidate bit sequences satisfies the set of check equations, and decoding performance is improved.

[0013] In some implementations, the determining the target bit sequence by the decoding device includes: based on the determining that none of the plurality of candidate bit sequences satisfies the set of check equations, the decoding device determines a candidate target bit sequence among the plurality of candidate bit sequences based on at least one of (i) the first indicator associated with the set of check equations and (ii) the second indicator or the third indicator associated with the first set of channel probability information values corresponding to the LDPC code. Further, the decoding device determines the candidate target bit sequence as the target bit sequence based on the determining that the candidate target bit sequence passes the cyclic redundancy check. In this way, under the condition that none of the candidate bit sequences satisfies the set of check equations, the first indicator, the second indicator, and the third indicator are used to select and the cyclic redundancy check is used to check, so that a suboptimal candidate bit sequence is selected as the target sequence.

[0014] In some implementations, the decoding device further determines that the decoding of the LDPC code fails based on the determining that the candidate target bit sequence does not pass the cyclic redundancy check. In this way, serious error decoding is avoided, so that the decoding performance is guaranteed.

[0015] In some implementations, the determining the candidate target bit sequence by the decoding device includes: based on the first indicators of the plurality of candidate bit sequences, the decoding device determines a first set of candidate bit sequences among the plurality of candidate bit sequences. The first indicators of the candidate bit sequences in the first set of candidate bit sequences are smaller than the first indicators of the candidate bit sequences outside the first set of candidate bit sequences. Further, the decoding device determines the candidate target bit sequence based on the second indicators or the third indicators of the candidate bit sequences in the first set of candidate bit sequences. In this way, the candidate target bit sequence is determined by selecting among the candidate bit sequences, so that the decoding performance is improved.

[0016] In some implementations, the determining the candidate target bit sequence by the decoding device includes: based on the second indicators or the third indicators of the plurality of candidate bit sequences, the decoding device determines a second set of candidate bit sequences among the plurality of candidate bit sequences. The second indicators or the third indicators of the candidate bit sequences in the second set of candidate bit sequences are smaller than the second indicators or the third indicators of the candidate bit sequences outside the second set of candidate bit sequences. Further, the decoding device determines the candidate target bit sequence based on the first indicators of the candidate bit sequences in the second set of candidate bit sequences. In this way, the candidate target bit sequence is determined by selecting among the candidate bit sequences, so that the decoding performance is improved.

[0017] In some implementations, the decoding device further determines that the candidate bit sequence is not the target bit sequence based on the determining that the second indicator of the candidate bit sequence is greater than half of the minimum distance of the generator matrix of the LDPC code. In this way, the candidate bit sequence that does not meet the decoding condition is removed, so that the decoding speed is improved.

[0018] In some implementations, the first metric includes a number of check equations in the set of check equations that are not satisfied by the candidate bit sequence. Alternatively or additionally, the second metric includes a number of bits that are not equal between (i) the candidate bit sequence and (ii) a hard decision bit sequence obtained by performing hard decision on the first set of channel probability information values corresponding to the LDPC code. Alternatively or additionally, the third metric includes an Euclidean distance between (i) the first set of channel probability information values and (ii) a set of variable node values obtained by performing the BP algorithm based on the second set of channel probability information values. The second set of channel probability information values is obtained by setting a magnitude of a channel probability information value corresponding to a flipped bit of the candidate bit sequence to a predetermined value in the first set of channel probability information values. In this way, the metrics are set reasonably to select the candidate bit sequence, improving decoding performance.

[0019] In some implementations, the flipped bit range of the multiple bit flipping operations includes all bits of the initial bit sequence. Thus, the flipping is performed exhaustively, improving decoding performance.

[0020] In some implementations, the flipped bit range of the multiple bit flipping operations excludes one or more of: bits corresponding to columns with column weights greater than a predetermined threshold in a check matrix of the LDPC code, or bits corresponding to columns with maximum column weights in the check matrix. In this way, the bit flipping range is reduced, improving decoding speed.

[0021] In some implementations, the predetermined threshold includes any one of: 8, 9, or 10. In this way, the column weight threshold excluded from the flipped bit range is set reasonably, improving decoding speed and ensuring decoding performance.

[0022] In some implementations, the flipped bit range of the multiple bit flipping operations includes bits corresponding to variable nodes that do not satisfy the set of check equations in a predefined iteration round in the BP algorithm. In this way, the optimal iteration round can be found and the flipped bit range is optimized, improving decoding performance.

[0023] In some implementations, the predefined iteration round includes any one of: an iteration round with a minimum number of check equations in the set of check equations that are not satisfied, a last iteration round, or an iteration round in which a predetermined number of check equations in the set of check equations are first not satisfied. In this way, the predefined iteration round is determined reasonably, thus the flipped bit range is determined reasonably, improving decoding speed and ensuring decoding performance.

[0024] In some implementations, the predetermined number includes any one of: 1, 2, or 3. In this way, the optimal iteration round can be found quickly and the flipped bit range is optimized, improving decoding speed and decoding performance.

[0025] In a second aspect, a decoding apparatus is provided. The decoding apparatus can be a decoding device or a chip applied in the decoding device. Unless specifically stated, the decoding apparatus in the present application can refer to the decoding device itself, a component (for example, a communication module, a processor, a circuit, a chip, or a chip system) in the decoding device, or a logic module or software capable of realizing all or part of the functions of the decoding device. Hereinafter, the decoding apparatus is taken as an example of the decoding device. The decoding apparatus includes an obtaining module configured to decode a low-density parity-check (LDPC) code based on a belief propagation (BP) algorithm to obtain an initial bit sequence that does not satisfy a check equation set. The decoding apparatus further includes an executing module configured to obtain a plurality of candidate bit sequences by performing a plurality of bit flipping operations on the initial bit sequence. In one bit flipping operation, at least one bit of the candidate bit sequence is flipped. The decoding apparatus further includes a determining module configured to determine, from the plurality of candidate bit sequences, a target bit sequence that satisfies a predetermined condition as a decoding result of the LDPC code. In this way, a certain randomness is introduced by means of bit flipping, thereby resisting the influence of noise or interference and improving decoding performance.

[0026] In a third aspect, a decoding device is provided. The decoding device includes a processor and a memory storing instructions. The instructions, when executed by the processor, cause the communication device to perform the method according to the first aspect.

[0027] In a fourth aspect, a computer-readable storage medium is provided. The computer-readable storage medium stores instructions. The instructions, when executed by the communication device, cause the communication device to perform the method according to the first aspect.

[0028] In a fifth aspect, a computer program product is provided. The computer program product includes instructions. The instructions, when executed by the communication device, cause the communication device to perform the method according to the first aspect.

[0029] In a sixth aspect, a chip is provided. The chip includes a processing circuit. The processing circuit is configured to perform the method according to the first aspect. BRIEF DESCRIPTION OF DRAWINGS

[0030] FIG. 1A shows a communication system in which embodiments of the present application can be implemented.

[0031] FIG. 1B shows another communication system in which embodiments of the present application can be implemented.

[0032] FIG. 2 shows a schematic diagram of a Tanner graph related to embodiments of the present application.

[0033] FIG. 3 shows a schematic diagram of a cyclic shift related to embodiments of the present application.

[0034] FIG. 4 shows a schematic diagram of a LDPC code base matrix, which is related to the embodiments of the present application.

[0035] FIG. 5 shows a flow chart of a processing procedure of a decoding apparatus in the embodiments of the present application.

[0036] FIG. 6 shows a schematic diagram of decoding performance in the embodiments of the present application.

[0037] FIG. 7 shows a schematic diagram of another decoding performance in the embodiments of the present application.

[0038] FIG. 8 shows a block diagram of an apparatus in the embodiments of the present application.

[0039] FIG. 9 shows a schematic diagram of a structure of an apparatus which can be used to implement a decoding apparatus in the embodiments of the present application. DETAILED DESCRIPTION

[0040] In order to make the objects, technical solutions and advantages of the present application clearer, the present application will be further described in detail below with reference to the accompanying drawings. The specific operation methods, function descriptions and the like in the method embodiments can also be applied to the apparatus embodiments or system embodiments.

[0041] As described above, in various communication scenarios, low density parity check (LDPC) codes can be used, and the decoding of the LDPC codes needs to be optimized.

[0042] Embodiments of the present application provide a technical solution for decoding, in which a decoding apparatus decodes a low density parity check (LDPC) code based on a belief propagation (BP) algorithm, and obtains an initial bit sequence that does not satisfy a set of check equations. In addition, the decoding apparatus obtains a plurality of candidate bit sequences based on performing a plurality of bit flipping operations on the initial bit sequence. In one bit flipping operation, at least one bit of the initial bit sequence is flipped. In addition, the decoding apparatus determines a target bit sequence that satisfies a predetermined condition from the plurality of candidate bit sequences as a decoding result of the LDPC code. In this way, a certain randomness is introduced in the form of bit flipping, so as to resist the influence of noise or interference and improve the decoding performance.

[0043] FIG. 1A shows a communication system in which embodiments of the present application can be implemented.

[0044] In embodiment 100, the communication system includes a source 105, source encoding 110, an encoding apparatus 120 such as channel encoding, modulation 125, demodulation 130, a decoding apparatus 140 such as channel decoding, source recovery 145, and a sink 150. The encoding apparatus 120 performs channel encoding operations such as LDPC code. The decoding apparatus 140 performs channel decoding operations such as LDPC code.

[0045] FIG. 1B illustrates another communication system in which embodiments of the present application can be implemented.

[0046] In embodiment 160, the communication system includes a network device 165, such as a base station, terminal devices 170, 175. The network device 165 and the terminal devices 170, 175 communicate through uplink and downlink 180, 185, respectively. The terminal devices 170, 175 can also communicate through sidelink 190. In embodiment 160, the encoding apparatus 120 can be located in the network device 165, the terminal devices 170, 175 to perform LDPC encoding on the transmitting side of the uplink and downlink 180, 185 and the sidelink 190. The decoding apparatus 140 can be located in the network device 165, the terminal devices 170, 175 to perform LDPC decoding on the receiving side of the uplink and downlink 180, 185 and the sidelink 190.

[0047] The wireless communication system 100, 160 in embodiments of the present application can be applied to three major application scenarios of eMBB, URLLC and eMTC, etc. of the 5G mobile communication system, or to the communication system scenarios of 5G advanced, 6G, future communication network, etc.

[0048] It should be understood that the above wireless communication system can be applied to both high frequency scenarios (above 6G) such as millimeter waves and low frequency scenarios (sub 6G). The application scenarios of the wireless communication system include, but are not limited to, existing communication systems such as the fifth generation system (5G), new radio (NR) communication system, etc. or future evolved public land mobile network (PLMN) system, etc.

[0049] The terminal devices 170, 175 shown above can be user equipment (UE), terminal, access terminal, terminal unit, terminal station, mobile station (MS), remote station, remote terminal, mobile terminal, wireless communication device, terminal agent or terminal device, etc. The terminal devices 170, 175 can also be a communication chip with a communication module, or a vehicle with a communication function, or a vehicle-mounted device (such as a vehicle-mounted communication device, a vehicle-mounted communication chip), etc. The terminal device 170, 175 can have a wireless transceiver function, which can communicate (such as wireless communication) with one or more network devices of one or more communication systems and accept network services provided by the network device, and the network device includes but is not limited to the network device 165 shown.

[0050] The terminal devices 170, 175 can be a cellular phone, a cordless phone, a session initiation protocol (SIP) phone, a wireless local loop (WLL) station, a personal digital assistant (PDA) device, a handheld device having wireless communication function, a computing device, or other processing device connected to a wireless modem, an in-vehicle device, a wearable device, a terminal device in a 5G network, or a terminal device in a future evolved PLMN network, and the like.

[0051] The terminal devices 170, 175 can be a mobile phone, a pad, a computer with wireless transceiver function, a virtual reality (VR) terminal, an augmented reality (AR) terminal, a wireless terminal in industrial control, a wireless terminal in self driving, a wireless terminal in remote medical treatment, a wireless terminal in smart grid, a wireless terminal in transportation safety, a wireless terminal in smart city, a wireless terminal in smart home, and the like.

[0052] In addition, the terminal devices 170, 175 can be deployed on land, including indoors or outdoors, handheld or vehicle-mounted; the terminal devices 170, 175 can also be deployed on the water surface (such as ships, etc.); the terminal devices 170, 175 can also be deployed in the air (such as airplanes, balloons, and satellites, etc.). The network device 165 can be an access network device (or access network site). The access network device refers to a device that provides network access functions, such as a radio access network (RAN) base station and the like. For example, the network device 165 of the access network device can include a base station (BS), or include a base station and a wireless resource management device for controlling the base station, and the like. The network device 165 of the access network device can also include a relay station (relay device), an access point, and a base station in a 5G network or an NR base station, a base station in a future evolved PLMN network, and the like. The access network device (165) can be a wearable device or a vehicle-mounted device. The network device 165 of the access network device can also be a communication chip with a communication module.

[0053] For example, the network device 165 such as a cellular system access network device includes but is not limited to: a base station (gnodeB, gNB) in 5G, an evolved node B (eNB) in a long term evolution (LTE) system, a radio network controller (RNC), a radio controller under a cloud radio access network (CRAN) system, a base station controller (BSC), a home base station (for example, a home evolved nodeB, or a home node B, HNB), a baseband unit (BBU), a transmitting and receiving point (TRP), a transmitting point (TP), a mobile switching center, and can also be an evolved NB (eNB or eNodeB) in LTE, and can also be a base station device in a future 5G network or an access network device in a future evolved PLMN network, and can also be a wearable device or a vehicle-mounted device.

[0054] In some deployments, a network device 165, e.g., a cellular system access network device, can include a centralized unit (CU) and a distributed unit (DU). The network device can also include an active antenna unit (AAU). The CU implements part of the functionality of the network device, and the DU implements part of the functionality of the network device, e.g., the CU is responsible for handling non-real-time protocols and services, implements radio resource control (RRC), and functions of the packet data convergence protocol (PDCP) layer. The DU is responsible for handling physical layer protocols and real-time services, implements functions of the radio link control (RLC) layer, the media access control (MAC) layer, and the physical (PHY) layer. The AAU implements part of the physical layer processing functions, radio frequency processing, and related functions of the active antenna. Since the information of the RRC layer eventually becomes or is transformed from the information of the PHY layer, under this architecture, high layer signaling, such as RRC layer signaling, can also be considered as being transmitted by the DU or by the DU+AAU. It can be understood that the network device can be a device including one or more of a CU node, a DU node, and an AAU node. In addition, the CU can be divided into a network device in a radio access network (RAN) or a network device in a core network (CN), which is not limited in the present application. Examples of the network device include, but are not limited to, a Node B (NB), an evolved Node B (eNodeB or eNB), a next generation Node B (gNB), a transmission reception point (TRP), a remote radio unit (RRU), a radio head (RH), a remote radio head (RRH), an IAB node, a low power node such as a femto node, a pico node, a reconfigurable intelligent surface (RIS), a network controlled relay, etc. The network device 165, e.g., a base station, can contain a baseband unit (BBU) and a remote radio unit (RRU). The BBU and the RRU can be placed in different places, e.g., RRU pull-out, placed in a high traffic area, and the BBU placed in a central machine room. The BBU and the RRU can also be placed in the same machine room. The BBU and the RRU can also be different components under one rack.

[0055] In addition, the network device 165, for example, a cellular system access network device, can be connected to a core network (CN) device, which can be used to provide core network services for the access network device 165 and the terminal devices 170, 175. The core network device can correspond to different devices under different systems. For example, in 3G, the core network device can correspond to a serving GPRS support node (SGSN) and / or a gateway GPRS support node (GGSN) of a general packet radio service (GPRS). In 4G, the core network device can correspond to a mobility management entity (MME) and / or a serving gateway (S-GW). In 5G, the core network device can correspond to an access and mobility management function (AMF), a session management function (SMF), a user plane function (UPF), etc.

[0056] Embodiments 100, 160 can be used for various application scenarios such as enhanced mobile broadband (eMBB), ultra-reliable low latency communications (URLLC), and enhanced machine-type communication (eMTC).

[0057] Low-density parity-check (LDPC) code is a channel coding scheme very close to the Shannon limit, with good performance and low complexity, and has been determined by 3GPP as a 5G data channel coding scheme.

[0058] The encoding manner of the LDPC code is to use a generator matrix. The LDPC code has a quasi-cyclic (QC) structure, and by setting the shift amount of each block, bad structures such as short cycles are avoided, and the code distance is improved. The decoding algorithms of the LDPC code currently mainly include Min-Sum (MS) and Belief Propagation (BP) decoding algorithms. The theoretical performance of the BP decoding algorithm is better, but the information storage amount is large, and the m c→vThe calculation is complicated and is not conducive to hardware implementation, so Offset-MS and Normalized-MS decoding algorithms are used in actual communication systems at present. Offset-MS, Normalized-MS and other MS algorithms can be regarded as a simplified algorithm of the BP algorithm.

[0059] The QC-LDPC code actually used is represented by a base matrix BG, and the elements in BG are 0 or 1. The 1 in the base matrix BG is extended to a cyclic shift matrix, and the 0 is extended to a 0 matrix of the corresponding size. After the extension, the check matrix is obtained. The BG graph model of the QC-LDPC code is BG=(X, Y, F), wherein X corresponds to the variables of the BG graph, Y corresponds to the check equations, and F is the edge relationship thereof. After QC expansion with a lifting factor of Z c , the Tanner graph is obtained, that is, a bipartite graph G=(V, C, E), wherein V is a variable node, C is a check node, and E is the edge relationship thereof.

[0060] For example, in the embodiment 200 of FIG. 2, the variable nodes are V1(235), …, V12(290), and the check nodes are C1(205), …, C6(230). There is an edge relationship 295 between C1(230) and V1(235). The number of variable nodes, check nodes and edge relationships in the embodiment 200 are exemplary and do not constitute a limitation on the present application. The number of variable nodes corresponds to the number of columns N=|V|=Z c |X| of the check matrix, and the number of check nodes corresponds to the number of rows M=|C|=Z c |Y| of the check matrix, and the number of non-zero elements of the check matrix is |E|=Z|F|.

[0061] The BG can also be written in the form of a matrix as H BG . Based on the base matrix H BG and the lifting size Zc, the base matrix H BG can be extended to a complete check matrix for encoding or decoding. Zc can also be referred to as an extension factor, a lifting factor, an extension value, an extension coefficient, a lifting size, etc.

[0062] The lifting process is to lift the elements in the matrix H BG to a Zc×Zc square matrix, wherein 0 is lifted to a Zc×Zc 0 matrix, and 1 is lifted to a matrix that is a unit matrix right-circu larly shifted by P i,j , wherein P i,jShifting Value (SV) value corresponding to the ith row and jth column. The variable node, check node, and edge relationship of the improved complete check matrix can also be shown in FIG. 2, where the number of variable nodes, check nodes, and edge relationships are exemplary and do not limit the present application.

[0063] FIG. 3 shows a schematic diagram of cyclic shift related to embodiments of the present application. The results of cyclically shifting a 4*4 identity matrix right by 1, 2, and 3 times are shown in 305, 310, and 315, respectively.

[0064] The base graphs of the 5G LDPC code are BG1 and BG2, which have a common matrix structure, as shown in embodiment 400 in FIG. 4. In embodiment 400, part A corresponds to the information column region of the high code rate, part B corresponds to the core check region of the high code rate. Part C is a 0 matrix, and part D is the incremental redundancy part of the matrix, corresponding to the low code rate matrix, and part E is the incremental redundancy region, which is an identity matrix structure. The values of the base matrix are 0 and 1, where a value of 0 represents an empty element, and a value of 1 represents an edge in the base graph, or a corresponding check node associated with a corresponding variable node.

[0065] Related to embodiments of the present application, the belief propagation decoding algorithm or the min-sum decoding algorithm is used. Let the log-likelihood ratio (LLR) value received by the decoding device 140 be y, and the decoding is performed in an iterative manner. In the lth iteration, let the transfer information from the variable node to the check node be The information transferred from the check node to the variable node is Let Then the variable node transfers information in the following manner:

[0066] where y v is the value corresponding to the variable node v in the received LLR.

[0067] In the BP decoding process, the information transferred from the check node c to the variable node v is

[0068] In the min-sum decoding algorithm, formula (2) can be simplified, and the approximate amplitude is calculated in the following manner

[0069] After each iteration, all v node information is summarized as and the hard decision is the symbol t v .

[0070] When the number of iterations reaches the upper limit, or t vAll the check equations in the check equation set can be made to pass, then the decoding terminates, and t v As a result of decoding.

[0071] The belief propagation decoding method has good performance and complexity advantage on long code and low density LDPC code, but is low in efficiency on short code, especially on short circle and dense matrix. The belief propagation algorithm is prone to fall into a certain trap set and cannot be correctly decoded, so that error floor is generated, and it is difficult to adapt to ultra-high reliability communication.

[0072] In relation to the embodiments of the present application, the GRAND bit flipping decoding can have a check matrix H and a received LLR value, and a symbol w can be obtained by hard decision on the LLR value. The GRAND decoding can adopt the following process.

[0073] 1. Check w, if the result of H*w is all 0, the check passes, and the decoding ends.

[0074] 2. If the check fails, flip a certain position of w randomly (i.e. 0->1 or 1->0), check w1 after flipping, if the check passes, the decoding ends, otherwise flip another position of w and check, until a flipping vector that passes the check is found, or any position of w is flipped once.

[0075] 3. Flip any position of w once, in the case that the check fails, flip any two positions of w, and judge whether the check passes.

[0076] 4. After trying all the flipping combinations of two positions, enter the flipping combinations of 3, 4, 5, … positions, and flip until the correct check result is found.

[0077] Therefore, the GRAND decoding is a decoding method that finds the code word closest to the accepted symbol by continuously trying to flip 1, 2, 3, … symbols and takes it as the decoding result.

[0078] The advantage of the GRAND decoding is that it only needs a check matrix to decode, and can be used for any code, and can always find the code word closest to the accepted symbol in Hamming distance as the decoding result. For example, TBCC and TURBO code in 4G, Polar and LDPC in 5G, for ultra-high code rate or extremely short code length, the GRAND can quickly get the decoding result. However, when the code rate is slightly reduced or the code length is slightly increased, the average complexity and maximum complexity of the decoding increase by the order of combination number. Therefore, its application range is limited, and it is not suitable for current mainstream communication systems.

[0079] Embodiments of the present application aim at the non-optimal performance of BP decoding in the case of short codes. A GRAND decoding, such as a low-order GRAND decoding, is introduced on the basis of BP decoding to improve performance and reduce error floor without significantly increasing overall complexity.

[0080] FIG. 5 shows a flowchart of a processing procedure of a decoding apparatus in an embodiment of the present application. In flow 500, at 510, the decoding apparatus 140 decodes a low-density parity-check (LDPC) code based on a belief propagation (BP) algorithm to obtain an initial bit sequence that does not satisfy a set of check equations. At 520, the decoding apparatus 140 obtains a plurality of candidate bit sequences based on performing a plurality of bit flipping operations on the initial bit sequence. In one bit flipping operation, at least one bit of the initial bit sequence is flipped. At 530, the decoding apparatus determines a target bit sequence that satisfies a predetermined condition from the plurality of candidate bit sequences as a decoding result of the LDPC code. The belief propagation algorithm can include a BP algorithm, a Min-Sum algorithm, etc. The initial bit sequence can be a bit sequence obtained after hard decision of values of variable nodes obtained by BP decoding. In this way, randomness is introduced by means of bit flipping to resist the influence of noise or interference and improve decoding performance. It will be understood that flow 500 can also include other operations implemented at the decoding apparatus 140 described above with reference to FIGS. 1A to 4, which will not be described herein again.

[0081] In an embodiment of the present application, a random noise guessing decoding method based on belief propagation decoding can be used. This method can use the following steps or operations to specifically implement flow 500.

[0082] In step 1, the decoding apparatus 140 receives channel LLR values y, and obtains a decoding result t after BP decoding or Min-sum decoding. The code length of t can be N, where the first k bits are information bits. If t cannot satisfy all check equations in the set of check equations, t is taken as an initial bit sequence, i.e., the current decoding result. The decoding apparatus 140 records the number of check nodes x1 that t does not satisfy, and the number of bits x2 that the sign of t is not equal to the hard decision of the channel LLR values, and performs the following process.

[0083] In step 2, the decoding apparatus 140 flips one bit in t, and takes the flipped symbol as t', and uses the check equations to verify t'.

[0084] In step 3, the decoding apparatus 140 records the number of check nodes x'1 that do not satisfy the check equations, and the number of bits x'2 that the sign of t is not equal to the hard decision of the channel LLR values y, and performs whether to update the decoding result t to t' according to a judgment rule, updates x1 to x'1, and updates x2 to x'2.

[0085] In step 4, the decoding device 140 flips the 2nd, 3rd, 4th,... bit in t, and repeats steps 2 and 3

[0086] In an embodiment of the present application, the decoding device 140 performs multiple bit flipping operations includes that the decoding device 140 obtains a first set of candidate bit sequences based on performing a first set of bit flipping operations on the initial bit sequence. In the first set of bit flipping operations, different N bits of the initial bit sequence are flipped. The decoding device 140 obtains a second set of candidate bit sequences based on performing a second set of bit flipping operations on the initial bit sequence based on determining that the target bit sequence is not included in the first set of candidate bit sequences, wherein in the second set of bit flipping operations, different N+1 bits of the initial bit sequence are flipped. N is greater than or equal to 1 and less than a predetermined flipping order. In this way, the number of flipped bits can be increased step by step, more candidate bit sequences are obtained, and the decoding performance is improved.

[0087] In step 5, the decoding device 140 selects 2 bit flips in t, and repeats 2, 3, and loops this step until all combinations of 2 bits are selected

[0088] In step 6, the decoding device 140 selects 3, 4, 5,... O bits in t to flip, and repeats 2, 3, and loops this step until all combinations of the number of bits are selected. O is the maximum flipping order or the predetermined flipping order. In an embodiment of the present application, the sequence obtained after each flipping of the initial bit sequence t corresponds to a candidate bit sequence.

[0089] In an embodiment of the present application, in a bit flipping operation, the number of at least one bit flipped is greater than or equal to 1 and less than or equal to a predetermined flipping order O. In this way, multiple bits can be flipped under the condition that the decoding delay is allowed, and the decoding performance is improved. In an embodiment of the present application, the predetermined flipping order O is determined by the decoding device 140 or indicated at the physical layer, for example, indicated by the encoding device 120 at the physical layer. In this way, the decoding flexibility can be improved.

[0090] In an embodiment of the present application, the bit flipping operation can be performed on the initial bit sequence to obtain multiple flipped bit sequences as multiple candidate bit sequences. In this way, all possible flipped bit positions can be flipped, and multiple candidate bit sequences are obtained for decoding, and the decoding performance is improved.

[0091] In step 7, the decoding device 140 updates t, and finally retains the decoding result t as the final decoding result, i.e., the target bit sequence.

[0092] In the embodiments of the present application, the decoding method using the random flipping noise is used, the complexity and error correction performance depend on the maximum flipping order O, and the maximum flipping order is determined by the bit error ratio (BER) of the received symbol. Directly using the symbol of the channel LLR for flipping has high complexity and poor performance, and after the BP iteration, even if there is no way to obtain the correct codeword, the BER can be greatly reduced, and on this basis, the random flipping can obtain high-order performance at a lower maximum flipping order with a smaller complexity cost.

[0093] Those skilled in the art can understand that the BP decoding can also be a Min-Sum decoding, offset-Min-Sum, or scale-Min-Sum decoding method, which is not limited in the present application.

[0094] In the embodiments of the present application, the method is improved on the basis of the foregoing embodiments, for example, the BP decoding is performed again after the random flipping. In this way, the decoding device 140 obtains a plurality of candidate bit sequences, including: the decoding device 140 performs a bit flipping operation on the initial bit sequence to obtain a flipped bit sequence. In the first set of channel probability information values corresponding to the LDPC code, the decoding device 140 sets the amplitude of the channel probability information value corresponding to the flipped bit in the flipped bit sequence to a predetermined value, and obtains a second set of channel probability information values. The decoding device 140 performs the BP algorithm based on the second set of channel probability values to obtain a decision bit sequence as one of the plurality of candidate bit sequences. The first channel probability information value can be the channel LLR value received by the decoding device 140. In this way, the BP decoding is performed again after the bit flipping, and the errors are eliminated as much as possible to improve the decoding performance.

[0095] In the embodiments of the present application, the operations of the BP decoding, the flipping, and the re-BP decoding can be implemented by the following steps or operations.

[0096] In step 1, the decoding device 140 receives the channel LLR value y, and obtains the decoding result t (the code length of t is N, and the information bit is the first-k bit) after the BP (or Min-sum) decoding. If t cannot satisfy all the check equations, t is the current decoding result, the decoding device 140 records the number of check nodes x1 that t does not satisfy, and the number of bits x2 that t is not equal to the hard decision symbol of the channel LLR value, and performs the following process.

[0097] In step 2, the decoding device 140 flips one bit in t and sets the channel LLR value corresponding to the flipped bit to a predetermined value, such as an amplitude of infinity, a sign corresponding to the flipped bit, or a hardware maximum. The amplitude and sign of this bit are not changed in subsequent decoding. The decoding device 140 uses the flipped LLR values to perform BP decoding to obtain a hard decision symbol value t' and checks the symbol t' against the set of check equations.

[0098] In step 3, the decoding device 140 records the number of check nodes x'1 that do not satisfy the check equations and the number of bits x'2 in which the symbol t does not equal the hard decision of the channel LLR values, and performs an update rule to determine whether to update the decoding result t to t' and to update x1 to x'1 and x2 to x'2.

[0099] In step 4, the decoding device 140 flips the second, third, fourth,... bit in t and repeats steps 2 and 3.

[0100] In step 5, the decoding device 140 selects two bits in t to flip and repeats steps 2 and 3 until all combinations of two bits have been selected.

[0101] In step 6, the decoding device 140 selects three, four, five,... O bits in t to flip and repeats steps 2 and 3 until all combinations of O bits have been selected. O is the maximum number of flips.

[0102] In step 7, the decoding device 140 updates t and the current decoding result t is retained as the final decoding result.

[0103] In embodiments of the present application, the update rule can be implemented in the following manner.

[0104] The update rule can use a first metric, which is the number of check equations in the set of check equations that are not satisfied by the candidate bit sequence, or the number of check nodes x1 that are not satisfied by the decoding result t. The update rule can also use a second metric. The second metric includes the number of bits in which (i) the candidate bit sequence and (ii) a hard decision bit sequence obtained by performing a hard decision on the first set of channel probability information values corresponding to the LDPC code are not equal. That is, the second metric can be the number of bits x2 in which the symbol t does not equal the hard decision of the channel LLR values.

[0105] The first metric and the second metric can be used in the method of flipping after BP decoding, or in the method of flipping after BP decoding and then performing BP decoding.

[0106] The decision rule can also use the third indicator for the method of flipping after BP decoding and then performing BP decoding again. The third indicator includes the Euclidean distance between (i) the first set of channel probability information values and (ii) a set of variable node values obtained by performing the BP algorithm based on the second set of channel probability information values. The second set of channel probability information values is obtained by setting the magnitude of the channel probability information value corresponding to the flipped bit of the candidate bit sequence to a predetermined value in the first set of channel probability information values. For example, the v-node information z after flipping and post-BP decoding can be used as the third indicator for decision making, for example, the Euclidean distance between z and the received LLR y can be used as the decision rule x3.

[0107] In this way, the candidate target bit sequence can be determined by selection among the candidate bit sequences, and the decoding performance can be improved.

[0108] In the embodiments of the present application, in the process of determining the target bit sequence, the decoding apparatus 140 can determine one candidate bit sequence as the target bit sequence based on determining that one candidate bit sequence among the plurality of candidate bit sequences satisfies the set of check equations. In this way, the target bit sequence can be quickly determined under the condition that one candidate bit sequence satisfies the set of check equations, and the decoding can be quickly performed.

[0109] In the embodiments of the present application, in the process of determining the target bit sequence, the decoding apparatus 140 can determine the target bit sequence among the plurality of candidate bit sequences based on determining that more than one candidate bit sequence among the plurality of candidate bit sequences satisfies the set of check equations, based on the second indicator, the third indicator, or both the second indicator and the third indicator associated with the first set of channel probability information values corresponding to the LDPC code. In this way, the target bit sequence can be determined by selection among the plurality of candidate bit sequences under the condition that more than one candidate bit sequence satisfies the set of check equations, and the decoding performance can be improved.

[0110] Specifically, when there is a decoding result t such that all checks pass (i.e., x1=0), all other decoding results that do not pass the check are not considered, and the final decoding result is selected among all the code words that pass the check according to x2. At this time, the code word with the smallest x2 can be selected as the decoding result.

[0111] In the embodiments of the present application, the decoding device 140 determines that the candidate bit sequence is not the target bit sequence based on determining that the second index of the candidate bit sequence is greater than half of the minimum distance of the generator matrix of the LDCP code. Specifically, when the decoding device 140 knows the minimum distance d of the code word space C of the encoding matrix, all code words x2>d / 2 are rejected. In this way, the candidate bit sequences that do not meet the decoding condition can be removed, and the decoding speed is improved. The maximum likelihood code word can be selected from the candidate bit sequences that can pass the check equation as the decoding result, and the maximum number of flips in decoding can be limited to eliminate meaningless flip times.

[0112] In the embodiments of the present application, the decoding device 140 determines the target bit sequence includes: the decoding device 140 determines a candidate target bit sequence from the plurality of candidate bit sequences based on (i) the first index associated with the set of check equations, and (ii) at least one of the second index or the third index associated with the set of first channel probability information values corresponding to the LDPC code, based on determining that no candidate bit sequence in the plurality of candidate bit sequences satisfies the set of check equations. In addition, the decoding device 140 determines the candidate target bit sequence as the target bit sequence based on determining that the candidate target bit sequence passes the cyclic redundancy check. The decoding device 140 determines that the decoding of the LDCP code fails based on determining that the candidate target bit sequence does not pass the cyclic redundancy check. Specifically, when there is no decoding result t such that all checks pass, the decoding device 140 selects the final decoding result from all decoding results according to x1 and x2, and then performs a cyclic redundancy check (CRC) on the decoding result. If the CRC check passes, the decoding is successful, otherwise the decoding fails. In this way, under the condition that the candidate bit sequence does not satisfy the set of check equations, the first index, the second index, and the third index are used for selection, and the cyclic redundancy code is used for check, so that the suboptimal candidate bit sequence is selected as the target sequence. Even if all the check equations cannot be passed, the result after the flip after the BP iteration can still pass the CRC check, so that the decoding is correct; limiting the maximum number of flips in decoding can eliminate meaningless flip times.

[0113] In the embodiments of the present application, the determining, by the decoding apparatus 140, of the candidate target bit sequence comprises: determining, by the decoding apparatus 140, a first candidate bit sequence set in the plurality of candidate bit sequences based on the first indicators of the plurality of candidate bit sequences. The first indicators of the candidate bit sequences in the first candidate bit sequence set are smaller than the first indicators of the candidate bit sequences outside the first candidate bit sequence set. In addition, the decoding apparatus 140 determines the candidate target bit sequence based on the second indicators or the third indicators of the candidate bit sequences in the first candidate bit sequence set. Specifically, the decoding apparatus 140 first performs screening according to the principle of x1 being minimum, and selects the decoding result with x2 being minimum from all the decoding results with x1 being minimum. In this way, the candidate target bit sequence is determined by performing optimization among the candidate bit sequences, thereby improving the decoding performance.

[0114] In the embodiments of the present application, the determining, by the decoding apparatus 140, of the candidate target bit sequence comprises: determining, by the decoding apparatus 140, a second candidate bit sequence set in the plurality of candidate bit sequences based on the second indicators or the third indicators of the plurality of candidate bit sequences. The second indicators or the third indicators of the candidate bit sequences in the second candidate bit sequence set are smaller than the second indicators or the third indicators of the candidate bit sequences outside the second candidate bit sequence set. In addition, the decoding apparatus 140 determines the candidate target bit sequence based on the first indicators of the candidate bit sequences in the second candidate bit sequence set. Specifically, the decoding apparatus 140 first determines the decoding result with x2 being minimum, and then performs screening according to the principle of x1 being minimum. In this way, the candidate target bit sequence is determined by performing optimization among the candidate bit sequences, thereby improving the decoding performance.

[0115] In the embodiments of the present application, the decoding apparatus 140 determines that the candidate bit sequence is not the target bit sequence based on the second indicator of the candidate bit sequence being greater than half of the minimum code distance of the generating matrix of the LDCP code. Specifically, when the decoding apparatus 140 knows the minimum code distance d of the code word space C of the encoding matrix, all the code words with x2>d / 2 are rejected. In this way, the candidate bit sequences that do not meet the decoding condition are removed, thereby improving the decoding speed.

[0116] In the embodiments of the present application, for the embodiment of flipping after BP decoding and then performing BP decoding again, the decoding device 140 can use the v node information z after flipping and BP decoding as the third index for decision, for example, the Euclidean distance between z and the received LLR y can be used as the third index x3 in the decision rule. The first index x1, the second index x2 and the third index x3 are used jointly to screen the decoding result, x3 can be used in the manner of x2, for example, x2 is replaced by x3, only x1 and x3 are used to screen according to the above method, for example, without the feature of maximum distance screening according to the hard decision of the symbol of t and the channel LLR value. Alternatively, the screening is performed according to the principle of giving priority to x1, then x2 and finally x3, or the principle of giving priority to x1, then x3 and finally x2. In this way, multiple indexes are used jointly for joint decision, so as to improve the decoding performance.

[0117] In the embodiments of the present application, the flipping bit range of the aforementioned flipping method after BP decoding, or the flipping method of flipping after BP decoding and then performing BP decoding again can be determined.

[0118] In the embodiments of the present application, the flipping bit range of the multiple bit flipping operations can include all the bits of the initial bit sequence. In this case, the performance is optimal, but the complexity is correspondingly highest. For the initial bit sequence of LDPC decoding, since the probabilities of different bit errors are different, the bit flipping range can be reduced while the performance is not lost.

[0119] In the embodiments of the present application, the flipping bit range of the multiple bit flipping operations can exclude some bits. For example, in the check matrix of the LDPC code, the bits corresponding to the columns with column weights greater than a predetermined threshold. For another example, in the check matrix, the bits corresponding to the column with the maximum column weight. In this way, the bit flipping range is reduced, and the decoding speed is improved. In the embodiments of the present application, the predetermined threshold can include 8, 9 or 10. In this way, the column weight threshold excluded from the flipping bit range is reasonably set, the decoding speed is improved and the decoding performance is guaranteed. Of course, in other embodiments, the predetermined threshold can also be other appropriate values.

[0120] In the embodiments of the present application, the flipping bit range of the multiple bit flipping operation includes bits corresponding to variable nodes that do not satisfy the check equation set in the predefined iteration round of the BP algorithm. Specifically, the flipping range corresponds to a variable set that does not satisfy the check equation after the lth iteration. In this way, the flipping bit range can be reasonably determined, the decoding speed can be improved, and the decoding performance can be ensured. The bit flipping range can be reduced, so that the complexity can be reduced. Meanwhile, the performance can not be lost. For example, in the method of flipping after BP decoding and then performing BP decoding, the reason why the performance is not lost is that after the bit flipping, the BP decoding can not need to correct all errors by flipping, but only needs to give the decoder a correct direction, and then the subsequent BP decoding is used to continue error correction. Meanwhile, it is helpful to reduce the error floor. The BP decoding can fall into a trap set, and the subsequent decoding after flipping can jump out of the trap set, so that the error floor can be reduced.

[0121] In the embodiments of the present application, the predefined iteration round can include an iteration round in which the number of check equations that do not satisfy the check equation set is the smallest, or the last iteration round. Specifically, l can be an iteration round in which the number of check equations that do not satisfy the check equation set is the smallest, or the last iteration round. In this way, the optimal iteration round can be found, the flipping bit range can be optimized, and the decoding performance can be improved.

[0122] In the embodiments of the present application, the predefined iteration round can also be an iteration round in which a predetermined number of check equations in the check equation set are not satisfied for the first time. In some examples, the predetermined number can include 1, 2, or 3. Specifically, l can be an iteration round in which the number of check equations that do not satisfy the check equation set is 1, 2, or 3 for the first time. If there is no such l, l is selected as an iteration round in which the number of check equations that do not satisfy the check equation set is the smallest, or the decoding is directly determined to fail and no flipping is performed. In this way, the optimal iteration round can be quickly found, the flipping bit range can be optimized, the decoding speed can be improved, and the decoding performance can be improved. In other examples, the predetermined number can also include other suitable values.

[0123] FIG. 6 shows a diagram of decoding performance in the embodiments of the present application, which is an illustration of error floor reduction compared with 5G BG2. In the embodiment 600, the horizontal coordinate is signal to noise ratio (SNR), and the vertical coordinate is block error ratio (BLER). The information bit length of the LDPC code is 240, and the code length is 672. In the embodiment 600, the curve 605 marked with Δ is the performance of the BP (20 iterations) + GRAND algorithm with the maximum flipping order of 3. The curve 610 marked with □ is the performance of the BP (20 iterations) + GRAND + BP post-processing (5 iterations) algorithm with the maximum flipping order of 3. The curve 615 marked with o is the performance of the BP (20 iterations) + GRAND + BP post-processing (5 iterations, excluding 0-47 bit positions from flipping) algorithm with the maximum flipping order of 3. Compared with the BP + GRAND decoding algorithm, the decoding algorithm of BP + GRAND + BP can effectively reduce the error floor, and excluding part of the bits from flipping does not lose performance and reduces the amount of computation.

[0124] FIG. 7 shows a diagram of another decoding performance in the embodiments of the present application. In the embodiment 700, the horizontal coordinate is signal to noise ratio (SNR), and the vertical coordinate is block error ratio (BLER). The simulated code length is 128, the code rate is 1 / 2, the code distance is 22, and the maximum flipping order of GRAND can reach 10. The curve 705 is the performance of the 5-order GRAND decoding (GRAND 5), the curve 710 is the performance of the 20-iteration BP decoding (BP), the curve 715 is the performance of the 10-order GRAND decoding (GRAND 10), and the curve 720 is the performance of the 20-iteration BP + 5-order GRAND decoding (BP + GRAND 5). As can be seen from the comparison of the curves, the performance from bad to good is: GRAND 5, BP, GRAND 10, and BP + GRAND 5. As can be seen from the embodiment 700, performing GRAND decoding on the result of BP can greatly improve the decoding performance of GRAND. As for the calculation complexity, the complexity of BP 20 iterations is 30,000 basic operations, the flipping number of GRAND 5-order is 15,000, the flipping number of GRAND 10-order is 185,000, and the actual GRAND flipping once also includes the check complexity (about 400 basic operations). The complexity of BP + GRAND 5 is about 60 million, and the calculation amount of BP is almost negligible. The complexity of BP + GRAND 10 is 74 million.

[0125] Figure 8 is a block diagram that can be used to implement a device 800 in accordance with some embodiments of the application. The decoding apparatus 140 can be implemented in the device 800, for example can be a part of the device 800. The decoding apparatus 140 can be implemented as a single chip, or a combination of several chips, or as a hardware circuit, or partly as a hardware circuit and partly as software, firmware or other forms, which the present application does not limit. In some embodiments, the device 800 can be an element of a communication network infrastructure, such as a base station (e.g., a NodeB, an evolved Node B (eNodeB or eNB), a next generation NodeB (sometimes referred to as a gNodeB or gNB), a home subscriber server (HSS), a gateway (GW) such as a packet gateway (PGW) or a serving gateway (SGW), or various other nodes or functions within a core network (CN) or a Public Land Mobility Network (PLMN). In other embodiments, the device 800 can be a device that connects to network infrastructure over a wireless interface, such as a mobile phone, a smartphone, or other such device that can be classified as a User Equipment (UE). In some embodiments, the device 800 can be a Machine Type Communications (MTC) device (also known as a machine-to-machine (M2M) device), or another such device that can be classified as a UE although not providing direct services to a user. In some embodiments, the device 800 can be a road side unit (RSU), a vehicle UE (V-UE), a pedestrian UE (P-UE), or an infrastructure UE (I-UE). In some scenarios, the device 800 can also be referred to as a mobile device, a term intended to reflect a device that connects to a mobile network, regardless of whether the device itself is designed or capable to move. Particular devices can utilize all or only a subset of the components shown, and the level of integration can vary from device to device. Furthermore, a device 800 can contain multiple instances of a component, such as multiple processors, memories, transmitters, receivers, etc.

[0126] The device 800 generally includes a processor 802, such as a central processing unit (CPU), and can further include specialized processors such as a graphics processing unit (GPU) or other such processors, a memory 804, a network interface 806, and a bus 808 to connect the components of the device 800. Optionally, the device 800 can also include components such as mass storage device 810, a video adapter 812, and I / O interface 816 (shown in dashed lines).

[0127] The memory 804 can include any type of non-transitory system memory readable by the processor 802, such as static random access memory (SRAM), dynamic random access memory (DRAM), synchronous DRAM (SDRAM), read-only memory (ROM), or a combination thereof. In one embodiment, the memory 804 can include more than one type of memory, such as ROM for programs at boot-up, and DRAM for program and data storage for programs at execution. The bus 808 can be one or more of several types of bus architectures including a memory bus or memory controller, a peripheral bus, or a video bus.

[0128] The device 800 can also include one or more network interfaces 806, which can include at least one of a wired network interface and a wireless network interface. As shown in FIG. 8, the network interface 806 can include a wired network interface for connecting to a network 822, and can also include a wireless access network interface 820 for connecting to other devices over a wireless link. When the device 800 is a network infrastructure element, the wireless access network interface 820 can be omitted for nodes or functions that are elements of the PLMN and not at the wireless edge. When the device 800 is infrastructure at the wireless edge of the network, both wired and wireless network interfaces can be included. When the device 800 is a wirelessly connected device, such as a user equipment, the wireless access network interface 820 can be present and can be supplemented by other wireless interfaces, such as a WiFi network interface. The network interface 806 allows the device 800 to communicate with remote entities such as those connected to the network 822.

[0129] Mass storage 810 can include any type of non-transitory storage device configured to store data, programs, and other information and to make the data, programs, and other information accessible via bus 808. Mass storage 810 can include, for example, one or more of a solid state drive, a hard disk drive, a magnetic disk drive, or an optical disk drive. In some embodiments, mass storage 810 can be remote from device 800 and can be accessed through the use of a network interface such as interface 806. In the illustrated embodiment, mass storage 810 is distinct from memory 804 that includes it, and mass storage 810 can generally perform storage tasks that are compatible with higher latencies, but can generally provide less or no volatility. In some embodiments, mass storage 810 can be integrated with heterogeneous memory 804.

[0130] Optional video adapter 812 and I / O interface 816 (shown in phantom) provide interfaces to couple device 800 to external input and output devices. Examples of input and output devices include a display 814 coupled to video adapter 812 and an I / O device 818, such as a touchscreen, coupled to I / O interface 816. Other devices can be coupled to device 800, and additional or fewer interfaces can be utilized. For example, a serial interface such as a Universal Serial Bus (USB) (not shown) can be used to provide interface to external devices. Those skilled in the art will appreciate that, in embodiments in which device 800 is part of a data center, I / O interface 816 and video adapter 812 can be virtualized and provided over network interface 806.

[0131] FIG. 9 is a structural schematic diagram of an apparatus 900 according to some embodiments of the present application. In some examples, the apparatus 900 can be used to implement the decoding apparatus 140 in the embodiments of the present application. As shown in FIG. 9, the apparatus 900 includes an obtaining module 902, an executing module 904, and a determining module 906. The apparatus 900 can be applied to the communication system as shown in FIG. 1 and FIG. 2, and can implement any of the methods provided by the foregoing embodiments. Optionally, the physical form of the apparatus 900 can be a communication device, such as a network device. Alternatively, the apparatus 900 can be other apparatus capable of implementing the functions of the communication device, such as a processor or a chip inside the communication device, etc. Specifically, the apparatus 900 can be a programmable chip, such as a field-programmable gate array (FPGA), a complex programmable logic device (CPLD), an application specific integrated circuit (ASIC), or a system on a chip (SOC), etc.

[0132] In some embodiments, the obtaining module 902 can be configured to obtain an initial bit sequence that does not satisfy a set of check equations based on belief propagation (BP) algorithm decoding of a low-density parity-check (LDPC) code. The executing module 904 can be configured to obtain a plurality of candidate bit sequences based on performing a plurality of bit flipping operations on the initial bit sequence. In one bit flipping operation, at least one bit of the initial bit sequence is flipped. The determining module 906 can be configured to determine, from the plurality of candidate bit sequences, a target bit sequence that satisfies a predetermined condition as a decoding result of the LDPC code.

[0133] In some other embodiments, the apparatus 900 can include various other units or modules that can be configured to perform various operations or functions described with regard to the foregoing method embodiments. Specific details can be obtained by referring to the detailed descriptions of the foregoing method embodiments, which will not be repeated here.

[0134] It should be noted that the division of the modules in the above embodiments of the present application is illustrative, and is only a logical function division. In actual implementation, another division manner can be used. In addition, each functional unit in each embodiment of the present application can be integrated in one processing unit, or can be physically separated, or two or more units can be integrated in one unit. The integrated unit can be implemented in the form of hardware or in the form of a software functional unit.

[0135] If the integrated unit is implemented in the form of a software function unit and sold or used as an independent product, it can be stored in a computer readable storage medium. Based on such understanding, the technical solutions of the present application can be embodied in the form of a software product in essence or all or part of the technical solutions. The computer software product is stored in a storage medium, and includes a plurality of instructions for causing a computer device (which can be a personal computer, a server, or a network device, etc.) or a processor to execute all or part of the steps of the various embodiments of the method of the present application. The foregoing storage medium includes: a U disk, a mobile hard disk, a read-only memory (Read-Only Memory, ROM), a random access memory (Random Access Memory, RAM), a magnetic disk or an optical disk, and various media that can store program codes.

[0136] Based on the above embodiments, the embodiments of the present application also provide a computer program, which, when running on a computer, causes the computer to execute any of the methods provided in the above embodiments.

[0137] Based on the above embodiments, the embodiments of the present application also provide a computer readable storage medium, which stores a computer program. The computer program is executed by a computer to cause the computer to execute any of the methods provided in the above embodiments. The storage medium can be any available medium that can be accessed by a computer. By way of example, and not limitation, the computer readable medium can include RAM, ROM, electrically erasable programmable read-only memory (Electrically Erasable Programmable Read-Only Memory, EEPROM), compact disc read-only memory (Compact Disc Read-Only Memory, CD-ROM) or other optical disk storage, magnetic disk storage medium or other magnetic storage devices, or any other medium that can be used to carry or store desired program code in the form of instructions or data structures and can be accessed by a computer.

[0138] Based on the above embodiments, the embodiments of the present application also provide a chip for reading a computer program stored in a memory, implementing any of the methods provided in the above embodiments.

[0139] Based on the above embodiments, the embodiments of the present application provide a chip system, which includes a processor for supporting a computer device to implement the functions involved in the communication devices in the above embodiments. In a possible design, the chip system further includes a memory for saving the necessary programs and data of the computer device. The chip system can be composed of a chip, or can include a chip and other discrete devices.

[0140] Those skilled in the art will appreciate that embodiments of the present application can be readily used as software, hardware, or a combination of software and hardware. In a software embodiment, the present application can be implemented with computer-executable instructions, such as programs stored in memory of a computer and executed by a processor of the computer. Of course, the present application can be implemented with programs stored in memory of any computer, and executed by a processor of any computer.

[0141] The present application is described in relation to flow diagrams and / or block diagrams of methods, apparatus (systems) and computer program products according to the present application. It is understood that each block of the flow diagrams and / or block diagrams, and combinations of blocks in the flow diagrams and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flow diagrams and / or block diagrams block or blocks.

[0142] These computer program instructions can also be stored in a computer- readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instructions which implement the function specified in the flow diagrams and / or block diagrams block or blocks.

[0143] The computer program instructions can also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer-implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flow diagrams and / or block diagrams block or blocks.

[0144] Obviously, numerous modifications and variations of the present application are possible in light of the above teachings. It is therefore to be understood that within the scope of the claims and their equivalents, the present application can be practiced otherwise than as specifically described.

Claims

1. A method of decoding, comprising: decoding a low-density parity-check (LDPC) code based on a belief propagation (BP) algorithm to obtain an initial bit sequence that does not satisfy a set of check equations; obtaining a plurality of candidate bit sequences based on performing a plurality of bit flipping operations on the initial bit sequence, wherein in one bit flipping operation, at least one bit of the initial bit sequence is flipped; and determining a target bit sequence that satisfies a predetermined condition among the plurality of candidate bit sequences as a decoding result of the LDPC code. 2.The method of claim 1, wherein in one bit flipping operation, the number of the at least one bit that is flipped is greater than or equal to 1 and less than or equal to a predetermined flipping order. 3.The method of claim 2, wherein the predetermined flipping order is determined by a decoding device, or indicated at a physical layer. 4.The method of any one of claims 1-3, wherein obtaining the plurality of candidate bit sequences comprises: performing the plurality of bit flipping operations on the initial bit sequence to obtain a plurality of flipped bit sequences as the plurality of candidate bit sequences. 5.The method of any one of claims 1-3, wherein obtaining the plurality of candidate bit sequences comprises: performing one bit flipping operation on the initial bit sequence to obtain a flipped bit sequence; setting a magnitude of a channel probability information value corresponding to a flipped bit in the flipped bit sequence to a predetermined value in a first set of channel probability information values corresponding to the LDPC code to obtain a second set of channel probability information values; and performing the BP algorithm based on the second set of channel probability values to obtain a decision bit sequence as one of the plurality of candidate bit sequences. 6.The method of any one of claims 1-5, wherein performing the plurality of bit flipping operations comprises: obtaining a first set of candidate bit sequences based on performing a first set of bit flipping operations on the initial bit sequence, wherein in the first set of bit flipping operations, different N bits of the initial bit sequence are flipped; and obtaining a second set of candidate bit sequences based on determining that the target bit sequence is not included in the first set of candidate bit sequences, wherein in the second set of bit flipping operations, different N+1 bits of the initial bit sequence are flipped, wherein N is greater than or equal to 1 and less than the predetermined flipping order. 7.The method of any one of claims 1-6, wherein determining the target bit sequence comprises: determining one of the plurality of candidate bit sequences as the target bit sequence based on determining that the one of the plurality of candidate bit sequences satisfies the set of check equations. 8.The method of any one of claims 1-6, wherein determining the target bit sequence comprises: ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ based on a determination that there is more than one candidate bit sequence of the plurality of candidate bit sequences that satisfies the set of check equations, determining the target bit sequence among the more than one candidate bit sequence based on at least one of a second metric or a third metric associated with a first set of channel probability information values corresponding to the LDPC code.

9. The method of any one of claims 1-6, wherein determining the target bit sequence comprises: based on a determination that there is no candidate bit sequence of the plurality of candidate bit sequences that satisfies the set of check equations, determining a candidate target bit sequence among the plurality of candidate bit sequences based on at least one of (i) the first metric associated with the set of check equations, and (ii) the second metric or the third metric associated with the first set of channel probability information values corresponding to the LDPC code; and based on a determination that the candidate target bit sequence passes a cyclic redundancy check, determining the candidate target bit sequence as the target bit sequence.

10. The method of claim 9, further comprising: based on a determination that the candidate target bit sequence fails the cyclic redundancy check, determining that decoding of the LDCP code fails.

11. The method of claim 9 or 10, wherein determining the candidate target bit sequence comprises: based on the first metric of the plurality of candidate bit sequences, determining a first set of candidate bit sequences of the plurality of candidate bit sequences, wherein the first metric of a candidate bit sequence of the first set of candidate bit sequences is less than the first metric of a candidate bit sequence outside of the first set of candidate bit sequences; and based on the second metric or the third metric of a candidate bit sequence of the first set of candidate bit sequences, determining the candidate target bit sequence.

12. The method of claim 9 or 10, wherein determining the target bit sequence comprises: based on the second metric or the third metric of the plurality of candidate bit sequences, determining a second set of candidate bit sequences of the plurality of candidate bit sequences, wherein the second metric or the third metric of a candidate bit sequence of the second set of candidate bit sequences is less than the second metric or the third metric of a candidate bit sequence outside of the second set of candidate bit sequences; and based on the first metric of a candidate bit sequence of the second set of candidate bit sequences, determining the candidate target bit sequence.

13. The method of any one of claims 8-12, further comprising: based on a determination that the second metric of a candidate bit sequence is greater than half of a minimum code distance of a generator matrix of the LDCP code, determining that the candidate bit sequence is not the target bit sequence.

14. The method of any one of claims 8-13, wherein at least one of: the first metric comprises a number of check equations in the set of check equations that a candidate bit sequence does not satisfy, the second metric comprises a number of check equations in the set of check equations that a candidate bit sequence does not satisfy, and the third metric comprises a number of check equations in the set of check equations that a candidate bit sequence does not satisfy. the second indicator comprises a number of bits that are not equal between (i) the candidate bit sequence, and (ii) a hard decision bit sequence obtained by performing hard decision on a first set of channel probability information values corresponding to the LDPC code, the third indicator comprises an Euclidean distance between (i) the first set of channel probability information values, and (ii) a set of variable node values obtained by performing the BP algorithm based on a second set of channel probability information values, wherein the second set of channel probability information values is obtained by setting, in the first set of channel probability information values, a magnitude of a channel probability information value corresponding to a flipped bit of a candidate bit sequence to a predetermined value.

15. The method of any one of claims 1-14, wherein the flipped bit range of the multiple bit flipping operations comprises all bits of the initial bit sequence.

16. The method of any one of claims 1-14, wherein the flipped bit range of the multiple bit flipping operations excludes at least one of: bits corresponding to columns with column weight greater than a predetermined threshold in a check matrix of the LDPC code, or bits corresponding to columns with maximum column weight in the check matrix.

17. The method of claim 16, wherein the predetermined threshold comprises any one of: 8, 9, or 10.

18. The method of any one of claims 1-14, wherein the flipped bit range of the multiple bit flipping operations comprises: bits corresponding to variable nodes that do not satisfy the set of check equations in a predefined iteration round in the BP algorithm.

19. The method of claim 18, wherein the predefined iteration round comprises: an iteration round in which a number of check equations in the set of check equations that are not satisfied is smallest, a last iteration round, or an iteration round in which a predetermined number of check equations in the set of check equations are not satisfied for the first time.

20. The method of claim 19, wherein the predetermined number comprises any one of: 1, 2, or 3.

21. A decoding apparatus comprising: an obtaining module configured to obtain an initial bit sequence that does not satisfy a set of check equations based on decoding a low-density parity-check (LDPC) code using a belief propagation (BP) algorithm; an executing module configured to obtain a plurality of candidate bit sequences based on performing a multiple bit flipping operation on the initial bit sequence, wherein at least one bit of the candidate bit sequence is flipped in a bit flipping operation; and a determining module configured to determine, among the plurality of candidate bit sequences, a target bit sequence that satisfies a predetermined condition as a decoding result of the LDPC code. a processor, and a memory storing instructions that, when executed by the processor, cause the communication device to perform the method of any one of claims 1-20.

22. A decoding device comprising:

21. A decoding apparatus comprising: an obtaining module configured to obtain an initial bit sequence that does not satisfy a set of check equations based on decoding a low-density parity-check (LDPC) code using a belief propagation (BP) algorithm; an executing module configured to obtain a plurality of candidate bit sequences based on performing a multiple bit flipping operation on the initial bit sequence, wherein at least one bit of the candidate bit sequence is flipped in a bit flipping operation; and a determining module configured to determine, among the plurality of candidate bit sequences, a target bit sequence that satisfies a predetermined condition as a decoding result of the LDPC code. a processor, and a memory storing instructions that, when executed by the processor, cause the communication device to perform the method of any one of claims 1-20.

23. A computer-readable storage medium storing instructions that, when executed by a communication device, cause the communication device to perform the method of any one of claims 1-20.

24. A computer program product comprising instructions that, when executed by a communication device, cause the communication device to perform the method of any one of claims 1-20.

25. A chip comprising processing circuitry configured to perform the method of any one of claims 1-20.

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