Display panel

Abstract

A display panel. By providing auxiliary wiring (vg2), the impedance of a first level line (VGH) is reduced. Therefore, after a gating module (10a) is turned off, a signal input on the basis of the first level line (VGH) is pulled up as a data signal is driven high. Since the impedance of the first level line (VGH) is reduced, the time for the signal of the first level line (VGH) to return to normal can be speeded up, thereby reducing the risk of dark streaks caused by overcharging of a third node (Q).

Description

Display panel

[0001] This application claims priority to Chinese patent application No. 202411083414.5, filed on August 7, 2024, the entire contents of which are incorporated herein by reference. TECHNICAL FIELD

[0002] The present application relates to the technical field of display, in particular to a display panel. BACKGROUND

[0003] In an organic light-emitting display panel, the organic light-emitting display panel includes a pixel circuit, after a data writing stage, a data signal jumps high to couple a high-level power line (VGH), so that the signal of the high-level power line jumps high, and due to the coupling capacitance between the high-level power line and A node and B node of the pixel circuit, the A node and the B node are pulled high, thereby charging more charges to the Q node, and the Q node has a higher potential than the value in the normal region, resulting in the generation of dark lines. The A node is a connection node of the input of the driving thin film transistor, the B node is a connection node of the output of the driving thin film transistor, and the Q node is a connection node of the gate of the driving thin film transistor and the storage capacitor (Cst). SUMMARY

[0004] The embodiments of the present application provide a display panel, which can improve dark lines.

[0005] The embodiments of the present application provide a display panel, which includes:

[0006] A first driving circuit includes a first level line and a first thin film transistor, and an input of the first thin film transistor is connected to the first level line;

[0007] A pixel circuit includes a gating module, a driving thin film transistor, a threshold compensation module, and a storage capacitor, a control end of the gating module is connected to an output of the first thin film transistor, an input end of the gating module is connected to a data line, an output end of the gating module and an input of the driving thin film transistor are connected to a first node, an input end of the threshold compensation module and an output of the driving thin film transistor are connected to a second node, and an output end of the threshold compensation module, a gate of the driving thin film transistor, and the storage capacitor are connected to a third node.

[0008] The first level line includes a signal trace and an auxiliary trace, the signal trace is connected to the input of the first thin film transistor, and the auxiliary trace is connected to the signal trace. BRIEF DESCRIPTION OF DRAWINGS

[0009] FIG. 1 is a plan view of a display panel according to an embodiment of the present application;

[0010] FIG. 2 is an equivalent circuit diagram of a first driving circuit of the display panel according to an embodiment of the present application;

[0011] FIG. 3 is an equivalent circuit diagram of a pixel circuit of the display panel according to an embodiment of the present application;

[0012] FIG. 4 is a timing diagram of the pixel circuit of the display panel according to an embodiment of the present application;

[0013] FIG. 5 is a schematic diagram of a cross-sectional structure of the display panel according to an embodiment of the present application;

[0014] FIG. 6 is a schematic diagram of a plan view of the first driving circuit of the display panel according to an embodiment of the present application;

[0015] FIG. 7 is an enlarged schematic diagram of portion A in FIG. 6;

[0016] FIG. 8 is an equivalent circuit diagram of a fourth driving circuit of the display panel according to an embodiment of the present application;

[0017] FIG. 9 is a schematic diagram of a plan view of the fourth driving circuit of the display panel according to an embodiment of the present application;

[0018] FIG. 10 is an enlarged schematic diagram of portion B in FIG. 9;

[0019] FIG. 11 is an equivalent circuit diagram of a fifth driving circuit of the display panel according to an embodiment of the present application;

[0020] FIG. 12 is a schematic diagram of a plan view of the fifth driving circuit of the display panel according to an embodiment of the present application;

[0021] FIG. 13 is an enlarged schematic diagram of portion C in FIG. 12. Embodiments of the present application

[0022] The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only some of the embodiments of the present application, rather than all the embodiments of the present application. Based on the embodiments in the present application, any other embodiments obtained by those skilled in the art without creative work fall within the scope of protection of the present application. In addition, it should be understood that the specific embodiments described herein are only used to illustrate and explain the present application, and are not used to limit the present application. In the present application, the embodiments can be combined with each other but are not described one by one, and the positional words such as "upper" and "lower" are generally used to refer to the upper and lower of the device in the actual use or working state, and the specific is the direction of the drawing in the drawings; and "inner" and "outer" are used in relation to the outline of the device; the words "first", "second", "third" and the like are only used as labels, and do not impose a numerical requirement or establish an order.

[0023] The embodiment of the present application provides a display panel, which is described in detail below. It should be noted that the description sequence of the following embodiments is not regarded as the limitation of the preferred sequence of the embodiments.

[0024] The embodiment of the present application provides a display panel, which comprises:

[0025] The first driving circuit comprises a first level line and a first thin film transistor, wherein the input end of the first thin film transistor is connected to the first level line;

[0026] The pixel circuit comprises a gate-on module, a driving thin film transistor, a threshold compensation module and a storage capacitor, wherein the control end of the gate-on module is connected to the output end of the first thin film transistor, the input end of the gate-on module is connected to a data line, the output end of the gate-on module and the input end of the driving thin film transistor are connected to a first node, the input end of the threshold compensation module and the output end of the driving thin film transistor are connected to a second node, and the output end of the threshold compensation module, the gate of the driving thin film transistor and the storage capacitor are connected to a third node.

[0027] The first level line comprises a signal wire and an auxiliary wire, the signal wire is connected to the input end of the first thin film transistor, and the auxiliary wire is connected to the signal wire.

[0028] Optionally, in some embodiments of the present application, the display panel further comprises a second driving circuit, a third driving circuit, a fourth driving circuit and a fifth driving circuit, and the pixel circuit comprises a first control module, a second control module, a first initialization module, a second initialization module and a third initialization module.

[0029] The control end of the threshold compensation module is connected with the output end of the second drive circuit, the control end of the first initialization module is connected with the output end of the third drive circuit, the input end of the first initialization module is connected with the first voltage end, and the output end of the first initialization module is connected with the third node; the control end of the first control module is connected with the output end of the fourth drive circuit, the input end of the first control module is connected with the first potential end, and the output end of the first control module is connected with the first node; the control end of the second control module is connected with the output end of the fourth drive circuit, the input end of the second control module is connected with the second node, and the output end of the second control module is connected with the fourth node; the control end of the second initialization module is connected with the output end of the fifth drive circuit, the input end of the second initialization module is connected with the second voltage end, and the output end of the second initialization module is connected with the fourth node; the control end of the third initialization module is connected with the output end of the fifth drive circuit, the input end of the third initialization module is connected with the third voltage end, and the output end of the third initialization module is connected with the first node; the first plate of the storage capacitor is connected with the third node, the second plate of the storage capacitor is connected with the first potential end; the anode of the display element is connected with the fourth node, and the cathode of the display element is connected with the second potential end.

[0030] In the thickness direction of the display panel, the signal trace and the auxiliary trace are arranged in different layers, and the auxiliary trace is located on the side of the signal trace away from the substrate; the auxiliary trace covers at least one of the first drive circuit, the second drive circuit, the third drive circuit, the fourth drive circuit and the fifth drive circuit.

[0031] Optionally, in some embodiments of the present application, the display panel further comprises a clock signal line, and in the plan view of the display panel, the auxiliary trace is located outside the clock signal line.

[0032] Optionally, in some embodiments of the present application, the first drive circuit further comprises a second thin film transistor, the clock signal line comprises a first clock signal line, the input pole of the second thin film transistor is connected with the first clock signal line, and the output pole of the second thin film transistor is connected with the control end of the gate-on module.

[0033] The auxiliary trace comprises a first auxiliary part, and in the plan view of the display panel, the first auxiliary part covers the first thin film transistor and the second thin film transistor.

[0034] Optionally, in some embodiments of the present application, the first auxiliary part includes a first sub-line, a second sub-line and a third sub-line, the first sub-line is connected with the signal trace through a via, the second sub-line is connected with the first sub-line and the third sub-line;

[0035] In a plan view of the display panel, the clock signal line, the signal trace, the first sub-line and the third sub-line are arranged along a second direction, the second sub-line is arranged along a first direction intersecting the second direction, a plurality of the first drive circuits are arranged along the second direction, the first thin film transistor and the second thin film transistor are arranged along the second direction, the second sub-line and the third sub-line are located on a side of the first sub-line away from the clock signal line.

[0036] The first sub-line overlaps the signal trace, the second sub-line is located between two adjacent first drive circuits, and the third sub-line covers the first thin film transistor and the second thin film transistor.

[0037] Optionally, in some embodiments of the present application, in a plan view of the display panel, in the first direction, a distance from the first sub-line to the clock signal line closest to the first sub-line is a first distance, and a distance from the first sub-line to the third sub-line closest to the first sub-line is a second distance, the second distance being greater than the first distance.

[0038] Optionally, in some embodiments of the present application, in a plan view of the display panel, a total area of the third sub-line is greater than a total area of the first sub-line.

[0039] Optionally, in some embodiments of the present application, the first drive circuit further includes a third thin film transistor, a fourth thin film transistor, a fifth thin film transistor, a sixth thin film transistor, a seventh thin film transistor, an eighth thin film transistor, a first capacitor and a second capacitor, and the clock signal line includes a second clock signal line.

[0040] Optionally, in some embodiments of the present application, in a plan view of the display panel, in the first direction, the first clock signal line is located on a side of the second clock signal line away from the first sub-line, and the third sub-line and the first sub-line are spaced apart by the third thin film transistor, the fourth thin film transistor, the fifth thin film transistor, the sixth thin film transistor, the seventh thin film transistor, the eighth thin film transistor and the second capacitor.

[0041] Optionally, in some embodiments of the present application, the fourth drive circuit further comprises a ninth thin film transistor and a tenth thin film transistor, an input terminal of the ninth thin film transistor is connected to the third voltage line, an input terminal of the tenth thin film transistor is connected to the fourth voltage line, and an output terminal of the ninth thin film transistor and an output terminal of the tenth thin film transistor are connected to form an output terminal of the fourth drive circuit.

[0042] The auxiliary wire comprises a second auxiliary part, and the second auxiliary part covers the ninth thin film transistor and the tenth thin film transistor in a plan view of the display panel.

[0043] Optionally, in some embodiments of the present application, the third voltage line, the fourth voltage line and the second auxiliary part extend along a second direction in a plan view of the display panel, the ninth thin film transistor and the tenth thin film transistor are arranged along the second direction, and the third voltage line and the second auxiliary part are connected to the same voltage.

[0044] In a first direction intersecting the second direction, the ninth thin film transistor, the tenth thin film transistor and the second auxiliary part are located between the third voltage line and the fourth voltage line, and a distance from the third voltage line to the second auxiliary part is less than a distance from the second auxiliary part to the fourth voltage line.

[0045] Optionally, in some embodiments of the present application, the fourth drive circuit further comprises an eleventh thin film transistor, a twelfth thin film transistor, a thirteenth thin film transistor, a fourteenth thin film transistor, a fifteenth thin film transistor, a sixteenth thin film transistor, a seventeenth thin film transistor, an eighteenth thin film transistor, a nineteenth thin film transistor, a twentieth thin film transistor, a twenty-first thin film transistor, a third capacitor, a fourth capacitor and a fifth capacitor, and the clock signal line comprises a third clock signal line and a fourth clock signal line.

[0046] In a plan view of the display panel, the third clock signal line and the fourth clock signal line are arranged adjacent to each other in the first direction, and the third clock signal line and the second auxiliary part are separated by the eleventh thin film transistor, the twelfth thin film transistor, the thirteenth thin film transistor, the fourteenth thin film transistor, the fifteenth thin film transistor, the sixteenth thin film transistor, the seventeenth thin film transistor, the eighteenth thin film transistor, the nineteenth thin film transistor, the twentieth thin film transistor, the twenty-first thin film transistor, the third capacitor, the fourth capacitor and the fifth capacitor.

[0047] Optionally, in some embodiments of the present application, the fifth drive circuit further comprises a twenty-second thin film transistor and a twenty-third thin film transistor, an input terminal of the twenty-second thin film transistor is connected to the fifth voltage line, an input terminal of the twenty-third thin film transistor is connected to the sixth voltage line, and an output terminal of the twenty-second thin film transistor and an output terminal of the twenty-third thin film transistor are connected to form an output terminal of the fifth drive circuit.

[0048] The auxiliary wire comprises a third auxiliary portion, in a plan view of the display panel, the third auxiliary portion covers the twenty-second thin film transistor and the twenty-third thin film transistor.

[0049] Optionally, in some embodiments of the present application, in a plan view of the display panel, the fifth voltage line, the sixth voltage line and the third auxiliary portion extend along a second direction, the twenty-second thin film transistor and the twenty-third thin film transistor are arranged along the second direction, and the fifth voltage line and the second auxiliary portion are configured to be connected to the same voltage.

[0050] In a first direction intersecting the second direction, the twenty-second thin film transistor, the twenty-third thin film transistor and the third auxiliary portion are located between the fifth voltage line and the sixth voltage line, and a distance from the fifth voltage line to the third auxiliary portion is less than a distance from the third auxiliary portion to the sixth voltage line.

[0051] Optionally, in some embodiments of the present application, the fifth drive circuit further comprises a twenty-fourth thin film transistor, a twenty-fifth thin film transistor, a twenty-sixth thin film transistor, a twenty-seventh thin film transistor, a twenty-eighth thin film transistor, a twenty-ninth thin film transistor, a thirtieth thin film transistor, a thirty-first thin film transistor, a thirty-second thin film transistor, a thirty-third thin film transistor, a thirty-fourth thin film transistor, a sixth capacitor, a seventh capacitor and an eighth capacitor, and the clock signal line comprises a fifth clock signal line and a sixth clock signal line.

[0052] In a plan view of the display panel, in the first direction, the fifth clock signal line and the sixth clock signal line are arranged adjacent to each other, and the fifth clock signal line and the second auxiliary portion are separated by the twenty-fourth thin film transistor, the twenty-fifth thin film transistor, the twenty-sixth thin film transistor, the twenty-seventh thin film transistor, the twenty-eighth thin film transistor, the twenty-ninth thin film transistor, the thirtieth thin film transistor, the thirty-first thin film transistor, the thirty-second thin film transistor, the thirty-third thin film transistor, the thirty-fourth thin film transistor, the sixth capacitor, the seventh capacitor and the eighth capacitor.

[0053] Optionally, in some embodiments of the present application, the auxiliary wire further includes a first connecting portion and a second connecting portion, the auxiliary wire further includes a second auxiliary portion and a third auxiliary portion, the second auxiliary portion covers the ninth thin film transistor and the tenth thin film transistor in the fourth drive circuit, the third auxiliary portion covers the twenty-second thin film transistor and the twenty-third thin film transistor in the fifth drive circuit, the first connecting portion connects the second auxiliary portion and the third auxiliary portion, and the second connecting portion connects the third auxiliary portion and the first auxiliary portion.

[0054] Optionally, in some embodiments of the present application, the first level wire is configured to access a high-level signal, the first thin film transistor is a P-type thin film transistor, and the gate-on module is configured to access the high-level signal to turn on.

[0055] The display panel of the embodiments of the present application reduces the impedance of the first level wire by adding the auxiliary wire, so that the signal accessed by the first level wire is pulled high when the data signal jumps high after the gate-on module is turned off. Since the impedance of the first level wire is reduced, the time for the signal of the first level wire to recover to normal can be accelerated, thereby reducing the risk of dark lines caused by overcharging of the third node.

[0056] FIG. 1 is a schematic view of a display panel 100 according to an exemplary embodiment of the present application. The display panel 100 according to the exemplary embodiment of the present application can be an organic light-emitting display panel, a micro light-emitting diode display panel, a submillimeter light-emitting diode display panel, or a quantum dot light-emitting diode display panel, etc. The display panel according to the embodiments of the present application can be assembled to realize an electronic device such as a smart phone, a mobile phone, a navigation device, a game console, a television (TV), a vehicle host, a notebook computer, a laptop computer, a tablet computer, a personal media player (PMP), a personal digital assistant (PDA), etc. In addition, the electronic device can be a flexible device.

[0057] As shown in FIG. 1, the first direction F1 can be a direction parallel to one side of the display panel 100 in a plan view, and for example, can be a lateral direction of the display panel 100. The second direction F2 can be a direction parallel to the other side of the display panel 100 in a plan view, and can be a longitudinal direction of the display panel 100.

[0058] The display panel 100 according to the exemplary embodiment of the present application has a display area AA and a non-display area NA. The non-display area NA can surround the display area AA. In an embodiment, the display area AA includes pixels for displaying an image, and the non-display area NA does not include pixels.

[0059] A plurality of display elements can be arranged in the display region AA. For example, the display elements can be organic light emitting diodes, and can emit red light, green light, blue light, or white light. The (sub)pixel in the display region AA of the display panel 100 of FIG. 1 includes such an organic light emitting diode, and also includes a pixel circuit 10 configured to control the degree of light emission of the organic light emitting diode. The pixel circuit 10 is provided in the display region AA. A drive circuit configured to control the pixel circuit 10 can be arranged in the non-display region NA.

[0060] The drive circuit includes a first drive circuit 20a, a second drive circuit 20b, a third drive circuit 20c, a fourth drive circuit 20d, and a fifth drive circuit 20e, each of which is connected to the pixel circuit 10.

[0061] Optionally, in the first direction F1, the fourth drive circuit 20d, the fifth drive circuit 20e, the third drive circuit 20c, the second drive circuit 20b, and the first drive circuit 20a are arranged in the non-display region NA in this order.

[0062] A plurality of first drive circuits 20a are arranged along the second direction F2. A plurality of fourth drive circuits 20d are arranged along the second direction F2, and a plurality of fifth drive circuits 20e are arranged along the second direction F2.

[0063] It should be noted that the pixel circuit 10 and the drive circuit each include a plurality of thin film transistors, which can be replaced according to their type (p-type or n-type) and / or operating condition, such as a p-type thin film transistor, which is turned off at a high level and turned on at a low level, with the source being the output and the drain being the input; and an n-type thin film transistor, which is turned off at a low level and turned on at a high level, with the source being the input and the drain being the output.

[0064] Referring to FIG. 2, FIG. 2 shows an equivalent circuit of the first drive circuit 20a of the display panel 100 according to an example embodiment of the present application. The first drive circuit 20a includes a plurality of thin film transistors and a capacitor. The first drive circuit 20a is configured to control the turn-on and turn-off of the gate-on module 10a of the pixel circuit 10.

[0065] In an example embodiment, as shown in FIG. 2, the thin film transistors include a first thin film transistor M1 to an eighth thin film transistor M8, and the capacitor includes a first capacitor C1 and a second capacitor C2.

[0066] It should be noted that the first drive circuit 20a of the display panel 100 according to an example embodiment of the present application will be described below with reference to FIG. 2, but is not limited thereto.

[0067] The clock signal line CK includes a first clock signal line CK1 and a second clock signal line CK2.

[0068] The gate of the first thin film transistor M1 and the first end of the second capacitor C2 are connected to a fifth node P5, the input of the first thin film transistor M1 and the second end of the second capacitor C2 are connected to the first voltage level line VGH, and the output of the first thin film transistor M1 is connected to the control end of the gate-on module 10a of the pixel circuit 10. The input of the second thin film transistor M2 is connected to the first clock signal line CK1, the output of the second thin film transistor M2 is connected to the control end of the gate-on module 10a, the gate of the second thin film transistor M2 and the first end of the first capacitor C1 are connected to a sixth node P6, and the second end of the first capacitor C1 is connected to the output of the second thin film transistor M2.

[0069] The gate of the third thin film transistor M3 is connected to the output of the seventh thin film transistor M7, the input of the third thin film transistor M3 is connected to the second clock signal line CK2, and the output of the third thin film transistor M3 is connected to the fifth node P5. The gate of the fourth thin film transistor M4 is connected to the first clock signal line CK1, the input of the fourth thin film transistor M4 is connected to the output of the fifth thin film transistor M5, and the output of the fourth thin film transistor M4 is connected to the output of the seventh thin film transistor M7.

[0070] The gate of the fifth thin film transistor M5 is connected to the fifth node P5, and the input of the fifth thin film transistor M5 is connected to the first voltage level line VGH. The gate of the sixth thin film transistor M6 is connected to the second clock signal line CK2, the input of the sixth thin film transistor M6 is connected to the second voltage level line VGL, and the output of the sixth thin film transistor M6 is connected to the fifth node P5.

[0071] The gate of the seventh thin film transistor M7 is connected to the second clock signal line CK2, and the input of the seventh thin film transistor M7 is the input end of the first driving circuit 20a.

[0072] The gate of the eighth thin film transistor M8 is connected to the second voltage level line VGL, the input of the eighth thin film transistor M8 is connected to the output of the seventh thin film transistor M7, and the output of the eighth thin film transistor M8 is connected to the sixth node P6.

[0073] It should be noted that the first driving circuit 20a controls the conduction and the closing of the gate-on module 10a of the pixel circuit 10 by controlling the conduction and the closing of the first thin film transistor M1 and the second thin film transistor M2. That is, the outputs of the first thin film transistor M1 and the second thin film transistor M2 are connected and act as the output end Pscan of the first driving circuit 20a.

[0074] In FIG. 2, the first to eighth thin film transistors M1 to M8 are all p-type transistors, and correspondingly, the first voltage level line VGH is configured to access a high-level signal, and the gate-on module 10a is set to access the high-level signal to turn on. The second voltage level line VGL is configured to access a low-level signal. However, this is only exemplary, and at least one of the first to eighth thin film transistors M1 to M8 can also be an n-type transistor. And when the transistor is replaced by an n-type, the corresponding control signal also changes accordingly, such as the first thin film transistor M1 is an n-type transistor, then the first voltage level line VGH is configured to access a low-level signal.

[0075] Referring to FIG. 3, FIG. 3 shows a pixel equivalent circuit of the display panel 100 of the exemplary embodiments of the present application. The pixel circuit 10 includes a plurality of thin film transistors and a storage capacitor. The thin film transistors can include the first to eighth transistors T1 to T8. The first transistor T1 is a driving thin film transistor.

[0076] It should be noted that the pixel circuit 10 of the display panel 100 of the exemplary embodiments of the present application will be described below with reference to FIG. 3, but is not limited thereto.

[0077] The pixel circuit 10 includes a gate-on module 10a, a driving thin film transistor T1, a threshold compensation module 10b, a storage capacitor Cst, a first control module 10c, a second control module 10d, a first initialization module 10e, a second initialization module 10f, and a third initialization module 10g.

[0078] The gate-on module 10a is configured to control the writing of a data signal to the third node Q and charge the third node Q. The control end of the gate-on module 10a is connected to the output end Pscan of the first driving circuit 20a, the input end of the gate-on module 10a is connected to the data line data, and the output end of the gate-on module 10a and the input pole of the driving thin film transistor T1 are connected to the first node A.

[0079] The threshold compensation module 10b is configured to control the voltage input to the third node Q. The input end of the threshold compensation module 10b and the output pole of the driving thin film transistor T1 are connected to the second node B, and the output end of the threshold compensation module 10b, the gate of the driving thin film transistor T1, and the storage capacitor Cst are connected to the third node Q. The control end of the threshold compensation module 10b is connected to the output end Nscan1 of the second driving circuit 20b.

[0080] The first control module 10c and the second control module 10d are configured to control the display element EL to be lighted. The control terminal of the first control module 10c is connected with the output terminal EM of the fourth drive circuit 20d, the input terminal of the first control module 10c is connected with the first potential terminal VDD, and the output terminal of the first control module 10c is connected with the first node A. The control terminal of the second control module 10d is connected with the output terminal EM of the fourth drive circuit 20d, the input terminal of the second control module 10d is connected with the second node B, and the output terminal of the second control module 10d is connected with the fourth node C. The anode of the display element EL is connected with the fourth node C, and the cathode of the display element EL is connected with the second potential terminal VSS.

[0081] The first initialization module 10e is configured to initialize the third node Q. The control terminal of the first initialization module 10e is connected with the output terminal Nscan2 of the third drive circuit 20c, the input terminal of the first initialization module 10e is connected with the first voltage terminal Vi1, and the output terminal of the first initialization module 10e is connected with the third node Q. The second initialization module 10f is configured to initialize the fourth node C. The control terminal of the second initialization module 10f is connected with the output terminal Pscan2 of the fifth drive circuit 20e, the input terminal of the second initialization module 10f is connected with the second voltage terminal Vi2, and the output terminal of the second initialization module 10f is connected with the fourth node C. The third initialization module 10g is configured to initialize the first node A. The control terminal of the third initialization module 10g is connected with the output terminal Pscan2 of the fifth drive circuit 20e, the input terminal of the third initialization module 10g is connected with the third voltage terminal Vi3, and the output terminal of the third initialization module 10g is connected with the first node A. The first plate of the storage capacitor Cst is connected with the third node Q, and the second plate of the storage capacitor Cst is connected with the first potential terminal VDD.

[0082] It should be noted that the level of the first potential terminal VDD can be higher than the level of the second potential terminal VSS. The first voltage terminal Vi1 can be configured to input a first initialization voltage, the second voltage terminal Vi2 can be configured to input a second initialization voltage, and the third voltage terminal Vi3 can be configured to input a third initialization voltage.

[0083] In FIG. 3, the gating module 10a includes a second transistor T2. The threshold compensation module 10b includes a third transistor T3. The first control module 10c includes a fifth transistor T5. The second control module 10d includes a sixth transistor T6. The first initialization module 10e includes a fourth transistor T4. The second initialization module 10f includes a seventh transistor T7. The third initialization module 10g includes an eighth transistor T8.

[0084] The gate of the second transistor T2 is connected to the output terminal Pscan of the first drive circuit 20a, the input of the second transistor T2 is connected to the data line data, and the output of the second transistor T2 and the input of the drive thin film transistor T1 are connected to the first node A. The input of the third transistor T3 and the output of the drive thin film transistor T1 are connected to the second node B, and the output of the third transistor T3, the gate of the drive thin film transistor T1, and the storage capacitor Cst are connected to the third node Q. The gate of the third transistor T3 is connected to the output terminal Nscanl of the second drive circuit 20b.

[0085] The gate of the fifth transistor T5 is connected to the output terminal EM of the fourth drive circuit 20d, the input of the fifth transistor T5 is connected to the first voltage terminal VDD, and the output of the fifth transistor T5 is connected to the first node A. The gate of the sixth transistor T6 is connected to the output terminal EM of the fourth drive circuit 20d, the input of the sixth transistor T6 is connected to the second node B, and the output of the sixth transistor T6 is connected to the fourth node C.

[0086] The gate of the fourth transistor T4 is connected to the output terminal Nscan2 of the third drive circuit 20c, the input of the fourth transistor T4 is connected to the first voltage terminal Vii, and the output of the fourth transistor T4 is connected to the third node Q. The gate of the seventh transistor T7 is connected to the output terminal Pscan2 of the fifth drive circuit 20e, the input of the seventh transistor T7 is connected to the second voltage terminal Vi2, and the output of the seventh transistor T7 is connected to the fourth node C. The gate of the eighth transistor T8 is connected to the output terminal Pscan2 of the fifth drive circuit 20e, the input of the eighth transistor T8 is connected to the third voltage terminal Vi3, and the output of the eighth transistor T8 is connected to the first node A.

[0087] In addition, according to an embodiment, the pixel circuit 10 can further include a boost capacitor Cboost including a first terminal connected to the third node Q and a second terminal connected to the gate of the second transistor T2. The boost capacitor Cboost can boost the voltage of the third node Q.

[0088] As shown in FIG. 3, the third transistor T3 and the fourth transistor T4 can be n-type transistors, and the first transistor T1, the second transistor T2, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, and the eighth transistor T8 can be p-type transistors. However, this is merely exemplary, and at least one of the first transistor T1, the second transistor T2, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, and the eighth transistor T8 can also be an n-type transistor.

[0089] Referring to FIG. 4, the timing of the pixel circuit 10 includes a data writing stage R1, in which the first transistor T1 is configured to be turned on under the control of the voltage of the third node Q, the second transistor T2 is configured to be turned on under the control of a low-level signal output by the output end Pscan of the first driving circuit 20a, and the third transistor T3 is configured to be turned on under the control of a high-potential signal output by the output end Nscan1 of the second driving circuit 20b. The fourth transistor T4 is configured to be turned off under the control of a low-potential signal output by the output end Nscan2 of the third driving circuit 20c, the fifth transistor T5 and the sixth transistor T6 are configured to be turned off under the control of a high-potential signal output by the output end EM of the fourth driving circuit 20d, and the seventh transistor T7 and the eighth transistor T8 are configured to be turned off under the control of a high-potential signal output by the output end Pscan2 of the fifth driving circuit 20e.

[0090] In the data writing stage R1, the first transistor T1, the second transistor T2, and the third transistor T3 are turned on, and the remaining transistors are turned off. The voltage of the data line data is written to the third node Q through the first node A and the second node B, and the third transistor T3 performs threshold grabbing on the first transistor T1.

[0091] The time at which the data signal input by the data line data jumps occurs after the data writing stage R1, and the third transistor T3 is still in the on state after the data signal jumps high. That is, the data signal jumps high and is coupled, so that the signal (Pscan) of the first voltage line VGH jumps high at the time R2. Due to the coupling capacitance between the first voltage line VGH and the first node A and the second node B of the pixel circuit 10, the first node A and the second node B are pulled high, thereby charging more charges to the third node Q.

[0092] It can be understood that the on duration of the third transistor T3 includes a continuous first duration, a second duration, and a third duration. The first duration is before the data writing stage R1, the second duration is in the data writing stage R1, and the third duration is after the data writing stage. The signal of the first voltage line VGH is coupled and pulled high, which occurs in the third duration.

[0093] It should be noted that the recovery time of Pscan pulled high in FIG. 4 is only an example. The recovery time of the first voltage line VGH can be determined according to the area of the auxiliary wire vg2. The larger the area of the auxiliary wire vg2, the shorter the recovery time of the signal of the first voltage line VGH, and the shorter the time at which the first node A and the second node B are pulled high. That is, the faster the signal of the first voltage line VGH pulled high drops, and the faster the voltage of the first node A and the second node B pulled high drops, thereby reducing the overcharging.

[0094] Optionally, in some embodiments, the signal of the first voltage level line VGH is pulled up to a fully recovered moment by the data signal jump, and the fully recovered moment is before the turn-off moment of the third transistor T3.

[0095] Please refer to FIG. 1 to FIG. 4, the display panel 100 provided by the embodiments of the present application includes the first driving circuit 20a, the first voltage level line VGH and the pixel circuit 10.

[0096] The first voltage level line VGH includes a signal trace vg1 and an auxiliary trace vg2, the signal trace vg1 is connected to the input terminal of the first thin film transistor M1, and the auxiliary trace vg2 is connected to the signal trace vg1.

[0097] The display panel 100 provided by the embodiments of the present application reduces the impedance of the first voltage level line VGH by adding the auxiliary trace vg2, so that the signal of the first voltage level line VGH is pulled up based on the data signal jump after the data write stage, and the reduced impedance of the first voltage level line VGH can accelerate the time of the signal of the first voltage level line VGH to recover to normal, thereby reducing the risk of dark lines caused by the third node Q due to overcharging.

[0098] Please refer to FIG. 5, the display panel 100 includes a substrate 11, a circuit structure layer 12 and a display element EL. The circuit structure layer 12 is arranged on the substrate 11, and the display element EL is arranged on the side of the circuit structure layer 12 away from the substrate 11.

[0099] The circuit structure layer 12 includes the pixel circuit 10 and the first driving circuit 20a to the fifth driving circuit 20e. The display element EL is connected to the pixel circuit 10.

[0100] The circuit structure layer 12 includes a light shielding layer Ls, a buffer layer buf, a first active layer py1, a first insulating layer jy1, a first metal layer js1, a second insulating layer jy2, a second metal layer js2, a third insulating layer jy3, a second active layer py2, a fourth insulating layer jy4, a third metal layer js3, a fifth insulating layer jy5, a fourth metal layer js4, a sixth insulating layer jy6, a fifth metal layer js5, a seventh insulating layer jy7, a sixth metal layer js6 and an eighth insulating layer jy8 arranged in sequence. The display element EL includes an anode y1, a light emitting layer y2 and a cathode y3.

[0101] Optionally, in some embodiments of the present application, the signal trace vg1 is formed in the fifth metal layer js5, and the auxiliary trace vg2 is formed in the sixth metal layer js6. The pixel circuit 10 and the first driving circuit 20a to the fifth driving circuit 20e are formed between the first active layer py1 and the sixth insulating layer jy6.

[0102] It should be noted that the auxiliary wire vg2 is arranged above the first to fifth drive circuits 20a-20e, so as to avoid the auxiliary wire vg2 from being connected with the first to fifth drive circuits 20a-20e, and to make the auxiliary wire vg2 have more layout space. In addition, the auxiliary wire vg2 is arranged on the sixth metal layer js6 farthest from the substrate 11, so as to increase the distance between the auxiliary wire vg2 and other signal lines in the thickness direction, thereby reducing the risk of interfering with other signal lines.

[0103] Optionally, the first to sixth metal layers js1-js6 can be formed of a metal element selected from chromium, copper, aluminum, gold, silver, zinc, molybdenum, tantalum, titanium, tungsten, manganese, nickel, iron, cobalt, an alloy containing any of the above metal elements, or an alloy containing any combination of the above metal elements. In addition, the first to sixth metal layers js1-js6 can have a single-layer structure or a laminated structure of two or more layers.

[0104] The materials of the first and second active layers py1 and py2 can each include monocrystalline silicon, polycrystalline silicon, or an oxide semiconductor. The materials of the first and second active layers py1 and py2 are different, but are not limited thereto, and can be the same, for example.

[0105] Optionally, in some embodiments of the present application, the signal wire vg1 and the auxiliary wire vg2 are arranged in different layers in the thickness direction of the display panel 100. The auxiliary wire vg2 is located on the side of the signal wire vg1 away from the substrate. The auxiliary wire vg2 covers at least one of the first to fifth drive circuits 20a-20e.

[0106] It should be noted that the first to fifth drive circuits 20a-20e are not short-circuited with the auxiliary wire vg2. In some embodiments, the thin film transistors of the first to fifth drive circuits 20a-20e are arranged in different layers from the auxiliary wire vg2, for example, the auxiliary wire vg2 is arranged above the layers on which all the thin film transistors are located.

[0107] Secondly, it can be understood that the larger the coverage range of the auxiliary wire vg2, the lower the impedance of the first voltage level VGH, and the better the effect of improving the dark lines. Therefore, the coverage range of the auxiliary wire vg2 can be adjusted according to actual needs. For example, the auxiliary wire vg2 can be arranged on the region of any one of the first to fifth drive circuits 20a-20e; or the auxiliary wire vg2 can be arranged on the region of any two of the first to fifth drive circuits 20a-20e; or the auxiliary wire vg2 can be arranged on the region of any three or four of the first to fifth drive circuits 20a-20e; or the auxiliary wire vg2 can be arranged on the regions of the first to fifth drive circuits 20a-20e.

[0108] Optionally, in some embodiments of the present application, the display panel 100 further comprises a clock signal line CK, and the auxiliary wire vg2 is located outside the clock signal line CK in the plan view of the display panel 100.

[0109] It can be understood that the clock signal line CK is arranged in the circuit structure layer 12. The auxiliary wire vg2 is arranged outside the clock signal line CK to avoid the auxiliary wire vg2 and the clock signal line CK from overlapping to generate parasitic capacitance, which in turn increases power consumption. Therefore, in some embodiments of the present application, the auxiliary wire vg2 is arranged outside the clock signal line CK to reduce the risk of generating parasitic capacitance, thereby reducing the risk of increasing power consumption.

[0110] Please refer to FIG. 6 and FIG. 7, in some embodiments of the present application, the auxiliary wire vg2 comprises a first auxiliary part f1, and the first auxiliary part f1 covers the first thin film transistor M1 and the second thin film transistor M2 in the plan view of the display panel 100.

[0111] It can be understood that the first thin film transistor M1 and the second thin film transistor M2 are arranged adjacently, and the layout area of any one of the two in the plan view is much larger than the area of the third thin film transistor M3 to the eighth thin film transistor M8. Therefore, a larger first auxiliary part f1 can be arranged in the area where the first thin film transistor M1 and the second thin film transistor M2 are located, and the first auxiliary part f1 is arranged directly above the first thin film transistor M1 and the second thin film transistor M2, which can reduce the risk of the first auxiliary part f1 coupling other signal lines.

[0112] Secondly, when the first thin film transistor M1 is turned on, the high-level signal of the first voltage level line VGH is accessed, at this time, the first auxiliary part f1 also accesses the same high-level signal, and the second thin film transistor M2 is turned off, so that the first auxiliary part f1 hardly interferes with the first thin film transistor M1 and the second thin film transistor M2. Therefore, covering the first thin film transistor M1 and the second thin film transistor M2 with the first auxiliary part f1 can reduce the interference with the first driving circuit 20a.

[0113] Optionally, the first auxiliary part f1 extends along the second direction F2 and covers the first thin film transistor M1 and the second thin film transistor M2 of a plurality of first driving circuits 20a to increase the area of the auxiliary wire vg2, thereby reducing the impedance of the first voltage level line VGH.

[0114] Optionally, in some embodiments, the input of the second thin-film transistor M2 includes a first input bus s1 extending along the second direction F2 and a plurality of first input branches s2 extending along the first direction F1, the plurality of first input branches s2 being arranged along the second direction F2 and connected to the first input bus s1. The output of the second thin-film transistor M2 includes a first output bus h1 extending along the second direction F2 and a plurality of first output branches h2 extending along the first direction F1, the plurality of first output branches h2 being arranged along the second direction F2. The first direction F1 and the second direction F2 intersect.

[0115] The first input branches s2 and the first output branches h2 are alternately arranged along the second direction F2, and the first input bus s1 and the first output bus h1 are separated by the first input branches s2 and the first output branches h2.

[0116] The input sr2 of the first thin-film transistor M1 extends along the first direction F1, and the first output branch h2 of the second thin-film transistor M2 is multiplexed as the output of the first thin-film transistor M1.

[0117] Optionally, in some embodiments of the present application, the first auxiliary part f1 includes a first sub-line f11, a second sub-line f12, and a third sub-line f13, the first sub-line f11 is connected to the signal wire vg1 through a via k1, and the second sub-line f12 is connected to the first sub-line f11 and the third sub-line f13.

[0118] In the plan view of the display panel 100, the clock signal line CK, the signal wire vg1, the first sub-line f11, and the third sub-line f13 extend along the second direction F2, and the second sub-line f12 extends along the first direction F1 intersecting the second direction F2. The plurality of first driving circuits 20a are arranged along the second direction F2. The first thin-film transistor M1 and the second thin-film transistor M2 are arranged along the second direction F2, and the second sub-line f12 and the third sub-line f13 are located on the side of the first sub-line f11 away from the clock signal line CK.

[0119] The first sub-line f11 overlaps the signal wire vg1, the second sub-line f12 is located between two adjacent first driving circuits 20a, and the third sub-line f13 covers the first thin-film transistor M1 and the second thin-film transistor M2.

[0120] It can be understood that the first sub-wire f11 is connected with the signal wire vg1 through the plurality of vias k1, and the impedance of the first voltage level line VGH is further reduced. In addition to avoiding the vertical parasitic capacitance with the clock signal line CK, the second sub-wire f12 and the third sub-wire f13 are further away from the clock signal line CK, and the risk of the lateral parasitic capacitance with the clock signal line CK is reduced, and the power consumption is further reduced.

[0121] Optionally, the third sub-wire f13 extends along the second direction F2 and covers the first thin film transistor M1 and the second thin film transistor M2 of the plurality of first driving circuits 20a, so as to increase the area of the auxiliary wire vg2, and further reduce the impedance of the first voltage level line VGH.

[0122] Optionally, in some embodiments, one third sub-wire f13 can be used to cover the entire area of the first thin film transistor M1 and the second thin film transistor M2, so as to increase the area of the auxiliary wire vg2, and further reduce the impedance of the first voltage level line VGH; or a plurality of third sub-wires f13 can be arranged at intervals and cover the area of the first thin film transistor M1 and the second thin film transistor M2, so as to reduce the interference with the first thin film transistor M1 and the second thin film transistor M2.

[0123] Optionally, in some embodiments, all the third sub-wires f13 are arranged between the first input bus s1 and the first output bus h1, so as to further reduce the interference with other signal lines.

[0124] Optionally, in some embodiments of the present application, in the plan view of the display panel 100, in the first direction F1, the distance between the first sub-wire f11 and the nearest clock signal line CK is a first distance L1, and the distance between the first sub-wire f11 and the nearest third sub-wire f13 is a second distance L2, and the second distance L2 is greater than the first distance L1.

[0125] It can be understood that, in the area of the first driving circuit 20a, the second distance L2 is greater than the first distance L1, so that the third sub-wire f13 is away from the clock signal line CK, and the interference of the third sub-wire f13 with the clock signal line CK is reduced, that is, the risk of forming parasitic capacitance is reduced.

[0126] Optionally, in some embodiments of the present application, in the plan view of the display panel 100, the total area of the third sub-wire f13 is greater than the total area of the first sub-wire f11.

[0127] It can be understood that, based on the fact that the third sub-wire f13 is away from the clock signal line CK, the total area of the third sub-wire f13 is set to be larger, which not only reduces the risk of forming parasitic capacitance with the clock signal line CK, but also increases the area of the auxiliary wire vg2, and further reduces the impedance of the first voltage level line VGH.

[0128] Optionally, in some embodiments of the present application, in the plan view of the display panel 100, in the first direction F1, the first clock signal line CK1 is located on the side of the second clock signal line CK2 away from the first sub-line f11, and the third sub-line f13 and the first sub-line f11 are spaced apart by the third thin film transistor M3, the fourth thin film transistor M4, the fifth thin film transistor M5, the sixth thin film transistor M6, the seventh thin film transistor M7, the eighth thin film transistor, and the second capacitor C2.

[0129] It can be understood that, by arranging the third thin film transistor M3, the fourth thin film transistor M4, the fifth thin film transistor M5, the sixth thin film transistor M6, the seventh thin film transistor M7, the eighth thin film transistor, and the second capacitor C2 between the second clock signal line CK2 and the first thin film transistor M1, the distance between the first thin film transistor M1 and the second thin film transistor M2 and the second clock signal line CK2 can be increased, and based on the third sub-line f13 being arranged above the region of the first thin film transistor M1 and the second thin film transistor M2, the risk of parasitic capacitance being generated between the third sub-line f13 and the second clock signal line CK2 can be reduced.

[0130] Please refer to FIGS. 8-10. FIG. 8 shows an equivalent circuit diagram of an exemplary fourth drive circuit 20d of the present application. FIG. 9 shows a plan view of the exemplary fourth drive circuit 20d of the present application. FIG. 10 shows a plan view of a single fourth drive circuit 20d in FIG. 9.

[0131] In exemplary embodiments, as shown in FIG. 8, the thin film transistors of the fourth drive circuit 20d include the ninth thin film transistor M9 to the twenty-first thin film transistor M21, and the capacitors include the third capacitor C3, the fourth capacitor C4, and the fifth capacitor C5. The clock signal lines CK include the third clock signal line CK3 and the fourth clock signal line CK4.

[0132] It should be noted that the fourth drive circuit 20d of the display panel 100 of the exemplary embodiments of the present application will be described below with reference to FIG. 8, but is not limited thereto.

[0133] The input terminal of the ninth thin film transistor M9 is connected to the third voltage level line VGH1, the input terminal of the tenth thin film transistor M10 is connected to the fourth voltage level line VGL1, and the output terminal of the ninth thin film transistor M9 and the output terminal of the tenth thin film transistor M10 are connected to form the output terminal EM of the fourth drive circuit 20d. The gate terminal of the ninth thin film transistor M9 is connected to the seventh node P7, and the gate terminal of the tenth thin film transistor M10 is connected to the eighth node P8. The first terminal of the fifth capacitor C5 is connected to the seventh node P7, and the second terminal of the fifth capacitor C5 is connected to the third voltage level line VGH1.

[0134] The gate of the eleventh thin film transistor M11 is connected to the ninth node P9, the input of the eleventh thin film transistor M11 is connected to the third voltage line VGH1, and the output of the eleventh thin film transistor M11 is connected to the tenth node P10. The gate of the twelfth thin film transistor M12 is connected to the eighth node P8, the input of the twelfth thin film transistor M12 is connected to the third clock signal line CK3, and the output of the twelfth thin film transistor M12 is connected to the tenth node P10; the first end of the third capacitor C3 is connected to the tenth node P10, and the second end of the third capacitor C3 is connected to the eighth node P8.

[0135] The gate of the thirteenth thin film transistor M13 is connected to the fourth clock signal line CK4, the input of the thirteenth thin film transistor M13 is connected to the fourth driving circuit 20d, and the output of the thirteenth thin film transistor M13 is connected to the eleventh node P11. The gate of the fourteenth thin film transistor M14 is connected to the fourth clock signal line CK4, the input of the fourteenth thin film transistor M14 is connected to the fourth voltage line VGL1, and the output of the fourteenth thin film transistor M14 is connected to the ninth node P9.

[0136] The gate of the fifteenth thin film transistor M15 is connected to the eleventh node P11, the input of the fifteenth thin film transistor M15 is connected to the fourth clock signal line CK4, and the output of the fifteenth thin film transistor M15 is connected to the ninth node P9.

[0137] The gate of the sixteenth thin film transistor M16 is connected to the twelfth node P12, the input of the sixteenth thin film transistor M16 is connected to the third clock signal line CK3, and the output of the sixteenth thin film transistor M16 is connected to the thirteenth node P13. The first end of the fourth capacitor C4 is connected to the twelfth node P12, and the second end of the fourth capacitor C4 is connected to the thirteenth node P13.

[0138] The gate of the seventeenth thin film transistor M17 is connected to the third clock signal line CK3, the input of the seventeenth thin film transistor M17 is connected to the thirteenth node P13, and the output of the seventeenth thin film transistor M17 is connected to the seventh node P7.

[0139] The gate of the eighteenth thin film transistor M18 is connected to the eleventh node P11, the input of the eighteenth thin film transistor M18 is connected to the third voltage line VGH1, and the output of the eighteenth thin film transistor M18 is connected to the seventh node P7. The gate of the nineteenth thin film transistor M19 is connected to the fourth voltage line VGL1, the input of the nineteenth thin film transistor M19 is connected to the ninth node P9, and the output of the nineteenth thin film transistor M19 is connected to the twelfth node P12.

[0140] The gate of the twentieth thin film transistor M20 is connected to the fourth voltage line VGL1, the input of the twentieth thin film transistor M20 is connected to the eleventh node P11, and the output of the twentieth thin film transistor M20 is connected to the eighth node P8. The gate of the twenty-first thin film transistor M21 is connected to the first control signal line Control1, the input of the twenty-first thin film transistor M21 is connected to the third voltage line VGH1, and the output of the twenty-first thin film transistor M21 is connected to the eleventh node P11.

[0141] It should be noted that the fourth drive circuit 20d controls the on and off of the first control module 10c and the second control module 10d of the pixel circuit 10 by controlling the on and off of the ninth thin film transistor M9 and the tenth thin film transistor M10. That is, the outputs of the ninth thin film transistor M9 and the tenth thin film transistor M10 are connected and act as the output end EM of the fourth drive circuit 20d.

[0142] In FIG. 8, the ninth thin film transistor M9 to the twenty-first thin film transistor M21 are all p-type transistors, and correspondingly, the third voltage line VGH1 is configured to input a high-level signal, and the first control module 10c and the second control module 10d are configured to input the high-level signal to be off. The fourth voltage line VGL1 is configured to input a low-level signal. However, this is only exemplary, and at least one of the ninth thin film transistor M9 to the twenty-first thin film transistor M21 can also be an n-type transistor. When the transistors are replaced by n-type, the corresponding control signals also change accordingly.

[0143] Optionally, in some embodiments of the present application, the auxiliary wire vg2 includes a second auxiliary part f2. In the plan view of the display panel 100, the second auxiliary part f2 covers the ninth thin film transistor M9 and the tenth thin film transistor M10.

[0144] It can be understood that the ninth thin film transistor M9 and the tenth thin film transistor M10 are arranged adjacent to each other, and the layout area of any one of the two in the plan view is much larger than the area of the eleventh thin film transistor M11 to the twenty-first thin film transistor M21. Therefore, a second auxiliary part f2 with a larger area can be arranged in the area where the ninth thin film transistor M9 and the tenth thin film transistor M10 are located, and the second auxiliary part f2 is arranged directly above the ninth thin film transistor M9 and the tenth thin film transistor M10, which can reduce the risk of the second auxiliary part f2 coupling other signal lines.

[0145] Optionally, the second auxiliary part f2 extends along the second direction F2 and covers the ninth thin film transistor M9 and the tenth thin film transistor M10 of a plurality of fourth drive circuits 20d, so as to increase the area of the second auxiliary part f2, and further reduce the impedance of the first voltage line VGH.

[0146] Optionally, in some embodiments, the input terminal of the ninth thin film transistor M9 includes a plurality of third input branches s3 extending along the first direction F1, the third input branches s3 are arranged along the second direction F2 and connected to the third voltage line VGH1. The output terminal of the ninth thin film transistor M9 includes a third output bus h3 extending along the second direction F2 and a plurality of third output branches h4 extending along the first direction F1, the third output branches h4 are arranged along the second direction F2. The first direction F1 and the second direction F2 intersect. The third input branches s3 and the third output branches h4 are arranged alternately along the second direction F2, and the third input branches s3 are arranged between the third voltage line VGH1 and the third output bus h3.

[0147] The input terminal of the tenth thin film transistor M10 includes a plurality of fourth input branches s4 extending along the first direction F1, the fourth input branches s4 are arranged along the second direction F2 and connected to the fourth voltage line VGL1.

[0148] The output terminal of the tenth thin film transistor M10 includes a fourth output bus h5 extending along the second direction F2 and connected to the third output bus h3 and a plurality of fourth output branches h6 extending along the first direction F1, the fourth output branches h6 are arranged along the second direction F2. The first direction F1 and the second direction F2 intersect. The fourth input branches s4 and the fourth output branches h6 are arranged alternately along the second direction F2, and the ninth thin film transistor M9 and the tenth thin film transistor M10 are arranged between the third voltage line VGH1 and the fourth voltage line VGL1.

[0149] Optionally, in some embodiments of the present application, in the plan view of the display panel 100, the third voltage line VGH1, the fourth voltage line VGL1 and the second auxiliary part f2 extend along the second direction F2, the ninth thin film transistor M9 and the tenth thin film transistor M10 are arranged along the second direction F2, and the third voltage line VGH1 and the second auxiliary part f2 are connected to the same voltage.

[0150] In the first direction F1 intersecting the second direction F2, the ninth thin film transistor M9, the tenth thin film transistor M10 and the second auxiliary part f2 are located between the third voltage line VGH1 and the fourth voltage line VGL1, and the distance L3 from the third voltage line VGH1 to the second auxiliary part f2 is less than the distance L4 from the second auxiliary part f2 to the fourth voltage line VGL1.

[0151] It can be understood that, because the voltage accessed by the third voltage level line VGH1 and the second auxiliary part f2 is the same, the second auxiliary part f2 is closer to the third voltage level line VGH1, and the risk of interference of the second auxiliary part f2 with other signal lines can be reduced.

[0152] Optionally, in some embodiments of the present application, in the plan view of the display panel 100, in the first direction, the third clock signal line CK3 and the fourth clock signal line CK4 are arranged adjacent to each other, and the eleventh thin film transistor M11, the twelfth thin film transistor M12, the thirteenth thin film transistor M13, the fourteenth thin film transistor M14, the fifteenth thin film transistor M15, the sixteenth thin film transistor M16, the seventeenth thin film transistor M17, the eighteenth thin film transistor M18, the nineteenth thin film transistor M19, the twentieth thin film transistor M20, the twenty-first thin film transistor M21, the third capacitor C3, the fourth capacitor C4, and the fifth capacitor C5 are arranged between the third clock signal line CK3 and the second auxiliary part f2.

[0153] It can be understood that, by arranging the eleventh thin film transistor M11, the twelfth thin film transistor M12, the thirteenth thin film transistor M13, the fourteenth thin film transistor M14, the fifteenth thin film transistor M15, the sixteenth thin film transistor M16, the seventeenth thin film transistor M17, the eighteenth thin film transistor M18, the nineteenth thin film transistor M19, the twentieth thin film transistor M20, the twenty-first thin film transistor M21, the third capacitor C3, the fourth capacitor C4, and the fifth capacitor C5 between the third clock signal line CK3 and the ninth thin film transistor M9, the distance between the ninth thin film transistor M9 and the tenth thin film transistor M10 and the third clock signal line CK can be increased, and based on the second auxiliary part f2 arranged above the region of the ninth thin film transistor M9 and the tenth thin film transistor M10, the risk of parasitic capacitance between the second auxiliary part f2 and the third clock signal line CK3 can be reduced.

[0154] Please refer to FIGS. 11-13. FIG. 11 shows an equivalent circuit diagram of an exemplary fifth drive circuit 20e. FIG. 12 shows a plan view of the exemplary fifth drive circuit 20e. FIG. 13 shows a plan view of a single fifth drive circuit 20e in FIG. 12.

[0155] In an exemplary embodiment, as shown in FIG. 11, the thin film transistors of the fifth drive circuit 20e include the twenty-second thin film transistor M22 to the thirty-fourth thin film transistor M34, and the capacitors include the sixth capacitor C6, the seventh capacitor C7, and the eighth capacitor C8. The clock signal line CK includes the fifth clock signal line CK5 and the sixth clock signal line CK6.

[0156] It should be noted that the fifth drive circuit 20e of the display panel 100 of the exemplary embodiments of the present application will be described below with reference to FIG. 11, but is not limited thereto.

[0157] The input terminal of the twenty-second thin film transistor M22 is connected to the fifth voltage line VGH2, the input terminal of the twenty-third thin film transistor M23 is connected to the sixth voltage line VGL2, and the output terminal of the twenty-second thin film transistor M22 and the output terminal of the twenty-third thin film transistor M23 are connected to form the output terminal Pscan2 of the fifth drive circuit 20e. The gate terminal of the twenty-second thin film transistor M22 is connected to the fourteenth node P14, and the gate terminal of the twenty-third thin film transistor M23 is connected to the fifteenth node P15. The first terminal of the eighth capacitor C8 is connected to the fourteenth node P14, and the second terminal of the eighth capacitor C8 is connected to the fifth voltage line VGH2.

[0158] The gate terminal of the twenty-fourth thin film transistor M24 is connected to the sixteenth node P16, the input terminal of the twenty-fourth thin film transistor M24 is connected to the fifth voltage line VGH2, and the output terminal of the twenty-fourth thin film transistor M24 is connected to the seventeenth node P17.

[0159] The gate terminal of the twenty-fifth thin film transistor M25 is connected to the fifteenth node P15, the input terminal of the twenty-fifth thin film transistor M25 is connected to the fifth clock signal line CK5, and the output terminal of the twenty-fifth thin film transistor M25 is connected to the seventeenth node P17. The first terminal of the sixth capacitor C6 is connected to the seventeenth node P17, and the second terminal of the sixth capacitor C6 is connected to the fifteenth node P15.

[0160] The gate terminal of the twenty-sixth thin film transistor M26 is connected to the sixth clock signal line CK6, the input terminal of the twenty-sixth thin film transistor M26 is connected to the input terminal of the fifth drive circuit 20e, and the output terminal of the twenty-sixth thin film transistor M26 is connected to the eighteenth node P18. The gate terminal of the twenty-seventh thin film transistor M27 is connected to the sixth clock signal line CK6, the input terminal of the twenty-seventh thin film transistor M27 is connected to the sixth voltage line VGL2, and the output terminal of the twenty-seventh thin film transistor M27 is connected to the sixteenth node P16.

[0161] The gate terminal of the twenty-eighth thin film transistor M28 is connected to the eighteenth node P18, the input terminal of the twenty-eighth thin film transistor M28 is connected to the sixth clock signal line CK6, and the output terminal of the twenty-eighth thin film transistor M28 is connected to the sixteenth node P16.

[0162] The gate terminal of the twenty-ninth thin film transistor M29 is connected to the nineteenth node P19, the input terminal of the twenty-ninth thin film transistor M29 is connected to the fifth clock signal line CK5, and the output terminal of the twenty-ninth thin film transistor M29 is connected to the twentieth node P20. The first terminal of the seventh capacitor C7 is connected to the nineteenth node P19, and the second terminal of the seventh capacitor C7 is connected to the twentieth node P20.

[0163] The gate of the thirtieth thin film transistor M30 is connected to the fifth clock signal line CK5, the input of the thirtieth thin film transistor M30 is connected to the twentieth node P20, and the output of the thirtieth thin film transistor M30 is connected to the fourteenth node P14. The gate of the thirty-first thin film transistor M31 is connected to the eighteenth node P18, the input of the thirty-first thin film transistor M31 is connected to the fifth voltage level line VGH2, and the output of the thirty-first thin film transistor M31 is connected to the fourteenth node P14.

[0164] The gate of the thirty-second thin film transistor M32 is connected to the sixth voltage level line VGL2, the input of the thirty-second thin film transistor M32 is connected to the sixteenth node P16, and the output of the thirty-second thin film transistor M32 is connected to the nineteenth node P19. The gate of the thirty-third thin film transistor M33 is connected to the sixth voltage level line VGL2, the input of the thirty-third thin film transistor M33 is connected to the eighteenth node P18, and the output of the thirty-third thin film transistor M33 is connected to the fifteenth node P15.

[0165] The gate of the thirty-fourth thin film transistor M34 is connected to the second control signal line Control2, the input of the thirty-fourth thin film transistor M34 is connected to the fifth voltage level line VGH2, and the output of the thirty-fourth thin film transistor M34 is connected to the eighteenth node P18.

[0166] It should be noted that the fifth drive circuit 20e controls the turn-on and turn-off of the second initialization module 10f and the third initialization module 10g of the pixel circuit 10 by controlling the turn-on and turn-off of the twenty-second thin film transistor M22 and the twenty-third thin film transistor M23. That is, the outputs of the twenty-second thin film transistor M22 and the twenty-third thin film transistor M23 are connected and act as the output end Pscan2 of the fifth drive circuit 20e.

[0167] In FIG. 11, the twenty-second thin film transistor M22 to the thirty-fourth thin film transistor M34 are all p-type transistors, and correspondingly, the fifth voltage level line VGH2 is configured to input a high-level signal, and the second initialization module 10f and the third initialization module 10g are set to input the high-level signal to be turned off. The sixth voltage level line VGL2 is configured to input a low-level signal. However, this is only exemplary, and at least one of the twenty-second thin film transistor M22 to the thirty-fourth thin film transistor M34 can also be an n-type transistor. When the transistors are replaced by n-type, the corresponding control signals also change accordingly.

[0168] Optionally, in some embodiments of the present application, the auxiliary wiring vg2 includes a third auxiliary part f3. In the plan view of the display panel 100, the third auxiliary part f3 covers the twenty-second thin film transistor M22 and the twenty-third thin film transistor M23.

[0169] It can be understood that the twenty-second thin film transistor M22 and the twenty-third thin film transistor M23 are arranged adjacently, and the layout area of any one of the two in the plan view is much larger than the area of the twenty-fourth thin film transistor M24 to the thirty-fourth thin film transistor M34, so that a larger area of the third auxiliary part f3 can be arranged in the area where the twenty-second thin film transistor M22 and the twenty-third thin film transistor M23 are located, and the third auxiliary part f3 is arranged directly above the twenty-second thin film transistor M22 and the twenty-third thin film transistor M23, so as to reduce the risk of the third auxiliary part f3 coupling other signal lines.

[0170] Optionally, the third auxiliary part f3 extends along the second direction F2 and covers the twenty-second thin film transistor M22 and the twenty-third thin film transistor M23 of the plurality of fifth driving circuits 20e, so as to increase the area of the third auxiliary part f3, and further reduce the impedance of the first voltage line VGH.

[0171] Optionally, in some embodiments of the present application, in the plan view of the display panel 100, the fifth voltage line VGH2, the sixth voltage line VGL2 and the third auxiliary part f3 extend along the second direction F2, and the twenty-second thin film transistor M22 and the twenty-third thin film transistor M23 are arranged along the second direction F2. The fifth voltage line VGH2 and the second auxiliary part f2 are arranged to access the same voltage.

[0172] In the first direction F1 intersecting the second direction F2, the twenty-second thin film transistor M22, the twenty-third thin film transistor M23 and the third auxiliary part f3 are located between the fifth voltage line VGH2 and the sixth voltage line VGL2, and the distance L5 from the fifth voltage line VGH2 to the third auxiliary part f3 is less than the distance L6 from the third auxiliary part f3 to the sixth voltage line VGL2.

[0173] It can be understood that, because the fifth voltage line VGH2 and the third auxiliary part f3 access the same voltage, the third auxiliary part f3 is closer to the fifth voltage line VGH2, so as to reduce the risk of the third auxiliary part f3 interfering with other signal lines.

[0174] Optionally, in some embodiments of the present application, in the plan view of the display panel 100, in the first direction F1, the fifth clock signal line CK5 and the sixth clock signal line CK6 are arranged adjacent to each other, and the fifth clock signal line CK5 and the second auxiliary part f2 are spaced apart by the twenty-fourth thin film transistor M24, the twenty-fifth thin film transistor M25, the twenty-sixth thin film transistor M26, the twenty-seventh thin film transistor M27, the twenty-eighth thin film transistor M28, the twenty-ninth thin film transistor M29, the thirtieth thin film transistor M30, the thirty-first thin film transistor M31, the thirty-second thin film transistor M32, the thirty-third thin film transistor M33, the thirty-fourth thin film transistor M34, the sixth capacitor C6, the seventh capacitor C7, and the eighth capacitor C8.

[0175] It can be understood that, by arranging the twenty-fourth thin film transistor M24, the twenty-fifth thin film transistor M25, the twenty-sixth thin film transistor M26, the twenty-seventh thin film transistor M27, the twenty-eighth thin film transistor M28, the twenty-ninth thin film transistor M29, the thirtieth thin film transistor M30, the thirty-first thin film transistor M31, the thirty-second thin film transistor M32, the thirty-third thin film transistor M33, the thirty-fourth thin film transistor M34, the sixth capacitor C6, the seventh capacitor C7, and the eighth capacitor C8 between the fifth clock signal line CK5 and the twenty-second thin film transistor M22, the distance between the twenty-second thin film transistor M22 and the twenty-third thin film transistor M23 and the fifth clock signal line CK5 can be increased, and by arranging the third auxiliary part f3 above the region of the twenty-second thin film transistor M22 and the twenty-third thin film transistor M23, the risk of parasitic capacitance between the third auxiliary part f3 and the fifth clock signal line CK5 can be reduced.

[0176] Optionally, in some embodiments of the present application, the circuit structure of the fifth drive circuit 20e can be the same as that of the fourth drive circuit 20d, such as the same as that of FIG. 13 and FIG. 10, but is not limited thereto.

[0177] Optionally, in some embodiments of the present application, the auxiliary wire vg2 further includes a first connecting part f4 and a second connecting part f5, and the auxiliary wire vg2 further includes the second auxiliary part f2 and the third auxiliary part f3. In the plan view of the display panel 100, the second auxiliary part f2 covers the ninth thin film transistor M9 and the tenth thin film transistor M10 in the fourth drive circuit 20d, and the third auxiliary part f3 covers the twenty-second thin film transistor M22 and the twenty-third thin film transistor M23 in the fifth drive circuit 20e. The first connecting part f4 connects the second auxiliary part f2 and the third auxiliary part f3, and the second connecting part f5 connects the third auxiliary part f3 and the first auxiliary part f1.

[0178] That is, the auxiliary wire vg2 is arranged in the region of the first drive circuit 20a, the fourth drive circuit 20d and the fifth drive circuit 20e, and is connected into one through the first connecting part f4 and the second connecting part f5, so as to increase the area of the auxiliary wire vg2, and further greatly reduce the impedance of the first level line VGH.

[0179] Optionally, in some embodiments, the first level line VGH, the third level line VGH1 and the fifth level line VGH2 can be connected and accessed to the same signal, but are not limited thereto, for example, the three can also be independently accessed to the level signal. The second level line VGL, the fourth level line VGL1 and the sixth level line VGL2 can be connected and accessed to the same signal, but are not limited thereto, for example, the three can also be independently accessed to the level signal.

[0180] The display panel provided by the embodiment of the present application reduces the impedance of the first level line by adding the auxiliary wire, so that after the first thin film transistor is turned off, the signal accessed by the first level line is pulled high along with the jump of the data signal, and since the impedance of the first level line is reduced, the time for the signal of the first level line to recover to normal can be accelerated, thereby reducing the risk of dark lines caused by the overcharge of the Q node.

[0181] The above describes in detail the display panel provided by the embodiment of the present application, and the principle and implementation manner of the present application are described by applying specific examples; the above embodiment is only used to help understand the method of the present application and its core idea; meanwhile, for those skilled in the art, according to the idea of the present application, the specific implementation manner and application range can be changed, and the above description should not be understood as the limitation of the present application.

Claims

1. A display panel comprising: a first drive circuit comprising a first thin film transistor, an input terminal of the first thin film transistor being connected to a first level line; a pixel circuit comprising a selection module, a drive thin film transistor, a threshold compensation module and a storage capacitor, a control terminal of the selection module being connected to an output terminal of the first thin film transistor, an input terminal of the selection module being connected to a data line, an output terminal of the selection module and an input terminal of the drive thin film transistor being connected to a first node, an input terminal of the threshold compensation module and an output terminal of the drive thin film transistor being connected to a second node, an output terminal of the threshold compensation module, a gate terminal of the drive thin film transistor and the storage capacitor being connected to a third node; the first level line comprising a signal trace and an auxiliary trace, the signal trace being connected to the input terminal of the first thin film transistor, the auxiliary trace being connected to the signal trace.

2. The display panel of claim 1, wherein, the display panel further comprising a second drive circuit, a third drive circuit, a fourth drive circuit and a fifth drive circuit, the pixel circuit comprising a first control module, a second control module, a first initialization module, a second initialization module and a third initialization module; a control terminal of the threshold compensation module being connected to an output terminal of the second drive circuit, a control terminal of the first initialization module being connected to an output terminal of the third drive circuit, an input terminal of the first initialization module being connected to a first voltage terminal, an output terminal of the first initialization module being connected to the third node; a control terminal of the first control module being connected to an output terminal of the fourth drive circuit, an input terminal of the first control module being connected to a first potential terminal, an output terminal of the first control module being connected to the first node; a control terminal of the second control module being connected to an output terminal of the fourth drive circuit, an input terminal of the second control module being connected to the second node, an output terminal of the second control module being connected to a fourth node; a control terminal of the second initialization module being connected to an output terminal of the fifth drive circuit, an input terminal of the second initialization module being connected to a second voltage terminal, an output terminal of the second initialization module being connected to the fourth node; a control terminal of the third initialization module being connected to an output terminal of the fifth drive circuit, an input terminal of the third initialization module being connected to a third voltage terminal, an output terminal of the third initialization module being connected to the first node; a first plate of the storage capacitor being connected to the third node, a second plate of the storage capacitor being connected to the first potential terminal; an anode of a display element being connected to the fourth node, a cathode of the display element being connected to a second potential terminal; in a thickness direction of the display panel, the signal trace and the auxiliary trace are arranged in different layers, the auxiliary trace being located on a side of the signal trace away from a substrate; the auxiliary trace covering at least one of the first drive circuit, the second drive circuit, the third drive circuit, the fourth drive circuit and the fifth drive circuit.

3. The display panel of claim 2, wherein, The display panel further comprises a clock signal line, and in a plan view of the display panel, the auxiliary wire is located outside the clock signal line.

4. The display panel of claim 3, wherein, The first drive circuit further comprises a second thin film transistor, the clock signal line comprises a first clock signal line, an input terminal of the second thin film transistor is connected to the first clock signal line, and an output terminal of the second thin film transistor is connected to a control end of the gate module. The auxiliary wire comprises a first auxiliary part, and in a plan view of the display panel, the first auxiliary part covers the first thin film transistor and the second thin film transistor.

5. The display panel of claim 4, wherein, The first auxiliary part comprises a first sub-wire, a second sub-wire and a third sub-wire, the first sub-wire is connected to the signal wire through a via hole, the second sub-wire is connected to the first sub-wire and the third sub-wire, and the third sub-wire is connected to the second sub-wire. In a plan view of the display panel, the clock signal line, the signal wire, the first sub-wire and the third sub-wire are arranged along a second direction, the second sub-wire is arranged along a first direction intersecting the second direction, a plurality of the first drive circuits are arranged along the second direction, the first thin film transistor and the second thin film transistor are arranged along the second direction, the second sub-wire and the third sub-wire are located on a side of the first sub-wire away from the clock signal line, and the first sub-wire overlaps the signal wire. The second sub-wire is located between two adjacent first drive circuits, and the third sub-wire covers the first thin film transistor and the second thin film transistor.

6. The display panel of claim 5, wherein, In a plan view of the display panel, in the first direction, a distance from the first sub-wire to the nearest clock signal line is a first distance, and a distance from the first sub-wire to the nearest third sub-wire is a second distance, and the second distance is greater than the first distance.

7. The display panel of claim 6, wherein, In a plan view of the display panel, a total area of the third sub-wire is greater than a total area of the first sub-wire.

8. The display panel of claim 5, wherein, The first drive circuit further comprises a third thin film transistor, a fourth thin film transistor, a fifth thin film transistor, a sixth thin film transistor, a seventh thin film transistor, an eighth thin film transistor, a first capacitor and a second capacitor, and the clock signal line comprises a second clock signal line. In a plan view of the display panel, in the first direction, the first clock signal line is located on a side of the second clock signal line away from the first sub-wire, and the third sub-wire and the first sub-wire are spaced apart by the third thin film transistor, the fourth thin film transistor, the fifth thin film transistor, the sixth thin film transistor, the seventh thin film transistor, the eighth thin film transistor and the second capacitor.

9. The display panel of claim 3, wherein, The fourth drive circuit further comprises a ninth thin film transistor and a tenth thin film transistor, an input terminal of the ninth thin film transistor is connected to a third level line, an input terminal of the tenth thin film transistor is connected to a fourth level line, and an output terminal of the ninth thin film transistor and an output terminal of the tenth thin film transistor are connected to form an output end of the fourth drive circuit. The auxiliary wire comprises a second auxiliary part, in a plan view of the display panel, the second auxiliary part covers the ninth thin film transistor and the tenth thin film transistor.

10. The display panel of claim 9, wherein, In a plan view of the display panel, the third level line, the fourth level line and the second auxiliary part extend along a second direction, the ninth thin film transistor and the tenth thin film transistor are arranged along the second direction, and the third level line and the second auxiliary part are connected to the same voltage. In a first direction intersecting the second direction, the ninth thin film transistor, the tenth thin film transistor and the second auxiliary part are located between the third level line and the fourth level line, and the distance from the third level line to the second auxiliary part is less than the distance from the second auxiliary part to the fourth level line.

11. The display panel of claim 10, wherein, The fourth drive circuit further comprises an eleventh thin film transistor, a twelfth thin film transistor, a thirteenth thin film transistor, a fourteenth thin film transistor, a fifteenth thin film transistor, a sixteenth thin film transistor, a seventeenth thin film transistor, an eighteenth thin film transistor, a nineteenth thin film transistor, a twentieth thin film transistor, a twenty-first thin film transistor, a third capacitor, a fourth capacitor and a fifth capacitor, and the clock signal line comprises a third clock signal line and a fourth clock signal line. In a plan view of the display panel, in the first direction, the third clock signal line and the fourth clock signal line are arranged adjacent to each other, and the third clock signal line and the second auxiliary part are separated by the eleventh thin film transistor, the twelfth thin film transistor, the thirteenth thin film transistor, the fourteenth thin film transistor, the fifteenth thin film transistor, the sixteenth thin film transistor, the seventeenth thin film transistor, the eighteenth thin film transistor, the nineteenth thin film transistor, the twentieth thin film transistor, the twenty-first thin film transistor, the third capacitor, the fourth capacitor and the fifth capacitor.

12. The display panel of claim 3, wherein, The fifth drive circuit further comprises a twenty-second thin film transistor and a twenty-third thin film transistor, the input terminal of the twenty-second thin film transistor is connected to a fifth level line, the input terminal of the twenty-third thin film transistor is connected to a sixth level line, and the output terminal of the twenty-second thin film transistor and the output terminal of the twenty-third thin film transistor are connected to form an output terminal of the fifth drive circuit. The auxiliary wire comprises a third auxiliary part, in a plan view of the display panel, the third auxiliary part covers the twenty-second thin film transistor and the twenty-third thin film transistor.

13. The display panel of claim 12, wherein, In a plan view of the display panel, the fifth level line, the sixth level line and the third auxiliary part extend along a second direction, the twenty-second thin film transistor and the twenty-third thin film transistor are arranged along the second direction, and the fifth level line and the second auxiliary part are connected to the same voltage. In a first direction intersecting the second direction, the twenty-second thin film transistor, the twenty-third thin film transistor and the third auxiliary part are located between the fifth level line and the sixth level line, and a distance from the fifth level line to the third auxiliary part is less than a distance from the third auxiliary part to the sixth level line.

14. The display panel of claim 13, wherein, The fifth drive circuit further comprises a twenty-fourth thin film transistor, a twenty-fifth thin film transistor, a twenty-sixth thin film transistor, a twenty-seventh thin film transistor, a twenty-eighth thin film transistor, a twenty-ninth thin film transistor, a thirtieth thin film transistor, a thirty-first thin film transistor, a thirty-second thin film transistor, a thirty-third thin film transistor, a thirty-fourth thin film transistor, a sixth capacitor, a seventh capacitor and an eighth capacitor, and the clock signal line comprises a fifth clock signal line and a sixth clock signal line. In a plan view of the display panel, in the first direction, the fifth clock signal line and the sixth clock signal line are arranged adjacently, and the fifth clock signal line and the second auxiliary part are spaced apart by the twenty-fourth thin film transistor, the twenty-fifth thin film transistor, the twenty-sixth thin film transistor, the twenty-seventh thin film transistor, the twenty-eighth thin film transistor, the twenty-ninth thin film transistor, the thirtieth thin film transistor, the thirty-first thin film transistor, the thirty-second thin film transistor, the thirty-third thin film transistor, the thirty-fourth thin film transistor, the sixth capacitor, the seventh capacitor and the eighth capacitor.

15. The display panel of claim 4, wherein, The auxiliary wiring further comprises a first connecting part and a second connecting part, and further comprises a second auxiliary part and a third auxiliary part, in a plan view of the display panel, the second auxiliary part covers the ninth thin film transistor and the tenth thin film transistor in the fourth drive circuit, the third auxiliary part covers the twenty-second thin film transistor and the twenty-third thin film transistor in the fifth drive circuit, the first connecting part connects the second auxiliary part and the third auxiliary part, and the second connecting part connects the third auxiliary part and the first auxiliary part.

16. The display panel of any one of claims 1-15, wherein, The first level line is arranged to access a high-level signal, the first thin film transistor is a P-type thin film transistor, and the gating module is arranged to access the high-level signal to turn on.

17. The display panel of claim 8, wherein, The gate of the first thin film transistor and the first end of the second capacitor are connected to a fifth node, the input of the first thin film transistor and the second end of the second capacitor are connected to the first level line, the output of the first thin film transistor is connected to the control end of the gating module of the pixel circuit, the input of the second thin film transistor is connected to a first clock signal line, the output of the second thin film transistor is connected to the control end of the gating module, the gate of the second thin film transistor and the first end of the first capacitor are connected to a sixth node, and the second end of the first capacitor is connected to the output of the second thin film transistor. The gate of the third thin film transistor is connected to the output of the seventh thin film transistor, the input of the third thin film transistor is connected to a second clock signal line, and the output of the third thin film transistor is connected to the fifth node; the gate of the fourth thin film transistor is connected to the first clock signal line, the input of the fourth thin film transistor is connected to the output of the fifth thin film transistor, and the output of the fourth thin film transistor is connected to the output of the seventh thin film transistor; The gate of the fifth thin film transistor is connected to the fifth node, the input of the fifth thin film transistor is connected to a first voltage line, the gate of the sixth thin film transistor is connected to the second clock signal line, the input of the sixth thin film transistor is connected to a second voltage line, and the output of the sixth thin film transistor is connected to the fifth node; The gate of the seventh thin film transistor is connected to the second clock signal line, and the input of the seventh thin film transistor is an input end of the first drive circuit; The gate of the eighth thin film transistor is connected to the second voltage line, the input of the eighth thin film transistor is connected to the output of the seventh thin film transistor, and the output of the eighth thin film transistor is connected to a sixth node.

18. The display panel of claim 2, wherein, The gate of the second transistor is connected to the output end of the first drive circuit, the input of the second transistor is connected to the data line, the output of the second transistor and the input of the drive thin film transistor are connected to the first node, the input of the third transistor and the output of the drive thin film transistor are connected to the second node, the output of the third transistor, the gate of the drive thin film transistor, and the storage capacitor are connected to the third node, and the gate of the third transistor is connected to the output end of the second drive circuit; The gate of the fifth transistor is connected to the output end of the fourth drive circuit, the input of the fifth transistor is connected to a first potential end, the output of the fifth transistor is connected to the first node, the gate of the sixth transistor is connected to the output end of the fourth drive circuit, the input of the sixth transistor is connected to the second node, and the output of the sixth transistor is connected to a fourth node. The gate of the fifth transistor is connected to the output end of the fourth drive circuit, the input of the fifth transistor is connected to a first potential end, the output of the fifth transistor is connected to the first node, the gate of the sixth transistor is connected to the output end of the fourth drive circuit, the input of the sixth transistor is connected to the second node, and the output of the sixth transistor is connected to a fourth node. A gate of the fourth transistor is connected with an output terminal of the third drive circuit, an input pole of the fourth transistor is connected with a first voltage terminal, an output pole of the fourth transistor is connected with the third node, a gate of the seventh transistor is connected with an output terminal of the fifth drive circuit, an input pole of the seventh transistor is connected with a second voltage terminal, an output pole of the seventh transistor is connected with the fourth node, a gate of the eighth transistor is connected with an output terminal of the fifth drive circuit, an input pole of the eighth transistor is connected with the third voltage terminal, and an output pole of the eighth transistor is connected with the first node.

19. The display panel of claim 18, wherein, The signal of the first level line is pulled up to a full recovery time point by the data signal, and the full recovery time point is before a turn-off time point of the third transistor corresponding to a data writing stage.

20. The display panel of claim 2, wherein, The circuit structure layer comprises the pixel circuit and the first drive circuit to the fifth drive circuit, and a display element is connected with the pixel circuit. The circuit structure layer comprises a light shielding layer, a buffer layer, a first active layer, a first insulating layer, a first metal layer, a second insulating layer, a second metal layer, a third insulating layer, a second active layer, a fourth insulating layer, a third metal layer, a fifth insulating layer, a fourth metal layer, a sixth insulating layer, a fifth metal layer, a seventh insulating layer, a sixth metal layer and an eighth insulating layer arranged in sequence, and the display element comprises an anode, a light emitting layer and a cathode. The signal trace is formed in the fifth metal layer, the auxiliary trace is formed in the sixth metal layer, and the pixel circuit and the first drive circuit to the fifth drive circuit are formed between the first active layer and the sixth insulating layer.

Images