Display substrate and display device

Abstract

A display substrate and a display device. The display substrate comprises first data signal lines (61), second data signal lines (62), first horizontal connection lines (81), second horizontal connection lines (82), first vertical connection lines (91) and second vertical connection lines (92), wherein the first data signal lines (61) are connected to pixel drive circuits in first unit rows, and the second data signal lines (62) are connected to pixel drive circuits in second unit rows; the first horizontal connection lines (81) are connected to both the first data signal lines (61) and the first vertical connection lines (91), and the second horizontal connection lines (82) are connected to both the second data signal lines (62) and the second vertical connection lines (92); and each first vertical connection line (91) is arranged between two adjacent first data signal lines (61), and each second vertical connection line (92) is arranged between two adjacent second data signal lines (62).

Description

Display substrate and display device Technical Field

[0001] This article relates to, but is not limited to, the field of display technology, specifically to a display substrate and a display device. Background Technology

[0002] Organic light-emitting diodes (OLEDs) and quantum dot light-emitting diodes (QLEDs) are active-matrix display devices with advantages such as self-illumination, wide viewing angle, high contrast, low power consumption, extremely high response speed, thinness, flexibility, and low cost. With the continuous development of display technology, flexible displays using OLEDs or QLEDs as light-emitting devices and controlled by thin-film transistors (TFTs) have become the mainstream products in the display field.

[0003] Summary of the Invention

[0004] The following is an overview of the subject matter described in detail herein. This overview is not intended to limit the scope of the claims.

[0005] On one hand, this disclosure provides a display substrate, including a driving structure layer disposed on a substrate and a light-emitting structure layer disposed on the driving structure layer on a side away from the substrate; the driving structure layer includes a plurality of circuit units forming a plurality of unit rows and a plurality of unit columns, the plurality of unit rows including a plurality of first unit rows and a plurality of second unit rows, wherein the first unit rows are odd-numbered unit rows and the second unit rows are even-numbered unit rows, or the first unit rows are even-numbered unit rows and the second unit rows are odd-numbered unit rows; at least one circuit unit includes a pixel driving circuit, a first data signal line and a second data signal line, wherein the first data signal line is connected to the pixel driving circuit in the first unit row and the second data signal line is connected to the pixel driving circuit in the second unit row; The drive structure layer further includes at least one first horizontal connecting line and at least one second horizontal connecting line extending along a first direction, and at least one first vertical connecting line and at least one second vertical connecting line extending along a second direction, wherein the first direction and the second direction intersect; a first end of the first horizontal connecting line is connected to the first data signal line, a second end of the first horizontal connecting line is connected to the first vertical connecting line, a first end of the second horizontal connecting line is connected to the second data signal line, and a second end of the second horizontal connecting line is connected to the second vertical connecting line; in the first direction, the first vertical connecting line is disposed between two adjacent first data signal lines, and the second vertical connecting line is disposed between two adjacent second data signal lines.

[0006] In an exemplary embodiment, at least one circuit unit further includes a first initial signal line extending along the first direction, the first initial signal line being connected to the pixel driving circuit; the driving structure layer further includes at least one first initial connection line extending along the second direction, the first initial connection line being connected to the first initial signal line to form a mesh-like interconnected structure for transmitting the first initial signal; in the first direction, the first initial connection line is disposed between adjacent first data signal lines and second data signal lines.

[0007] In an exemplary embodiment, at least one circuit unit further includes a second initial signal line extending along the first direction, the second initial signal line being connected to the pixel driving circuit; the driving structure layer further includes at least one second initial connection line extending along the second direction, the second initial connection line being connected to the second initial signal line to form a mesh-like interconnected structure for transmitting the second initial signal; in the first direction, the second initial connection line is disposed between adjacent first data signal lines and second data signal lines.

[0008] In an exemplary embodiment, the second data signal line, the first data signal line, the second data signal line, the first data signal line, the first data signal line, the second data signal line, the first data signal line, and the second data signal line are periodically arranged in the first direction.

[0009] In an exemplary embodiment, at least one circuit unit includes a unit center line, which is a straight line that bisects the circuit unit in the first direction and extends along the second direction; the first data signal line and the second data signal line are symmetrically arranged with respect to the unit center line.

[0010] In an exemplary embodiment, the plurality of circuit units include a plurality of first circuit units and a plurality of second circuit units; the pixel driving circuit in the first circuit unit is connected to the first data signal line or the second data signal line located on one side of the unit center line in the first direction, and the pixel driving circuit in the second circuit unit is connected to the first data signal line or the second data signal line located on the opposite side of the unit center line in the first direction; or, the pixel driving circuit in the first circuit unit is connected to the first data signal line or the second data signal line located on the opposite side of the unit center line in the first direction, and the pixel driving circuit in the second circuit unit is connected to the first data signal line or the second data signal line located on one side of the unit center line in the first direction.

[0011] In an exemplary embodiment, in the first unit row, the first circuit unit, the second circuit unit, and the second circuit unit are periodically arranged in the first direction; in the second unit row, the second circuit unit, the second circuit unit, the first circuit unit, and the first circuit unit are periodically arranged in the first direction.

[0012] In an exemplary embodiment, in at least one unit column, the first circuit unit and the second circuit unit are alternately arranged in the second direction.

[0013] In an exemplary embodiment, the first vertical connecting line is disposed between adjacent first circuit units and second circuit units in the first direction, and the second vertical connecting line is disposed between adjacent first circuit units and second circuit units in the first direction.

[0014] In an exemplary embodiment, at least one circuit unit further includes a first initial signal line extending along the first direction, the first initial signal line being connected to the pixel driving circuit; the driving structure layer further includes at least one first initial connection line extending along the second direction, the first initial connection line being connected to the first initial signal line to form a mesh-like interconnected structure for transmitting the first initial signal, the first initial connection line being disposed between two adjacent first circuit units in the first direction, or the first initial connection line being disposed between two adjacent second circuit units in the first direction.

[0015] In an exemplary embodiment, at least one circuit unit further includes a second initial signal line extending along the first direction, the second initial signal line being connected to the pixel driving circuit; the driving structure layer further includes at least one second initial connection line extending along the second direction, the second initial connection line being connected to the second initial signal line to form a mesh-like interconnected structure for transmitting the second initial signal, the second initial connection line being disposed between two adjacent first circuit units in the first direction, or the second initial connection line being disposed between two adjacent second circuit units in the first direction.

[0016] In an exemplary embodiment, the driving structure layer further includes at least one first power trace extending along the first direction and at least one second power trace extending along the second direction; in a direction perpendicular to the display substrate, the display substrate includes a first conductive layer disposed on a substrate, a second conductive layer disposed on the side of the first conductive layer away from the substrate, a third conductive layer disposed on the side of the second conductive layer away from the substrate, and a fourth conductive layer disposed on the side of the third conductive layer away from the substrate. The first power trace and the second power trace are disposed in different conductive layers, and the second power trace is connected to the first power trace through a via, forming a mesh-like interconnected structure for transmitting power signals.

[0017] In an exemplary embodiment, in the first direction, the second power supply trace is disposed between two adjacent first data signal lines, or the second power supply trace is disposed between two adjacent second data signal lines.

[0018] In an exemplary embodiment, the first power trace is disposed in the second conductive layer and the second power trace is disposed in the third conductive layer; alternatively, the first power trace is disposed in the second conductive layer and the second power trace is disposed in the fourth conductive layer; or alternatively, the first power trace is disposed in the third conductive layer and the second power trace is disposed in the fourth conductive layer.

[0019] In an exemplary embodiment, at least one circuit unit further includes a first power electrode, which is disposed on one side of the first power trace in the second direction and connected to the first power trace; the second power trace is continuously disposed in the second direction and is connected to the first power electrode through a via.

[0020] In an exemplary embodiment, at least one circuit unit further includes a first power electrode and a second power electrode. The first power electrode is disposed on one side of the first power trace in the second direction and is connected to the first power trace. The second power electrode is disposed on the opposite side of the first power trace in the second direction and is connected to the first power trace. The second power traces are spaced apart in the second direction. The second power trace located on one side of the first power trace in the second direction is connected to the first power electrode through a via. The second power trace located on the opposite side of the first power trace in the second direction is connected to the second power electrode through a via.

[0021] In an exemplary embodiment, the light-emitting structure layer includes a plurality of light-emitting units, including a first light-emitting unit emitting red light, a second light-emitting unit emitting blue light, and a third and fourth light-emitting units emitting green light. The first light-emitting unit includes at least a first anode, the second light-emitting unit includes at least a second anode, the third light-emitting unit includes at least a third anode, and the fourth light-emitting unit includes at least a fourth anode. The orthographic projections of the first anode and the second anode onto the substrate at least partially overlap with the orthographic projections of at least two first data signal lines or at least two second data signal lines onto the substrate. The orthographic projections of the third anode and the fourth anode onto the substrate at least partially overlap with the orthographic projections of at least one first data signal line and at least one second data signal line onto the substrate.

[0022] In an exemplary embodiment, the orthographic projections of the first anode and the second anode on the substrate at least partially overlap with the orthographic projections of at least one first vertical connecting line and at least two first data signal lines on the substrate, and the two first data signal lines are symmetrically arranged with respect to the first vertical connecting line; or, the orthographic projections of the first anode and the second anode on the substrate at least partially overlap with the orthographic projections of at least one second vertical connecting line and at least two second data signal lines on the substrate, and the two second data signal lines are symmetrically arranged with respect to the second vertical connecting line.

[0023] On the other hand, this disclosure also provides a display device including the aforementioned display substrate.

[0024] After reading and understanding the accompanying diagrams and detailed descriptions, the other aspects can be understood. Attached Figure Description

[0025] The accompanying drawings are used to provide an understanding of the technical solutions of this disclosure and form part of the specification. They are used together with the embodiments of this disclosure to explain the technical solutions of this disclosure and do not constitute a limitation on the technical solutions of this disclosure.

[0026] Figure 1 is a schematic diagram of a display device;

[0027] Figure 2 is a schematic diagram of the structure of a display substrate;

[0028] Figure 3 is a schematic diagram of the planar structure of the display area in a display substrate;

[0029] Figure 4 is a schematic cross-sectional view of the display area in a display substrate;

[0030] Figure 5 is a schematic diagram of the equivalent circuit of a pixel driving circuit;

[0031] Figure 6 is a schematic diagram of the structure of a data connection line according to an exemplary embodiment of the present disclosure;

[0032] Figure 7 is a schematic diagram of the structure of a data signal line according to an exemplary embodiment of the present disclosure;

[0033] Figure 8 is a schematic diagram of the structure of a data signal line and a data connection line according to an exemplary embodiment of the present disclosure;

[0034] Figures 9A and 9B are schematic diagrams of the structure of a display substrate according to an exemplary embodiment of the present disclosure;

[0035] Figure 10 is a schematic diagram of a display substrate after a shielding layer pattern has been formed;

[0036] Figures 11A and 11B are schematic diagrams of a display substrate after a semiconductor layer pattern has been formed in this disclosure;

[0037] Figures 12A and 12B are schematic diagrams of a display substrate after the formation of the first conductive layer pattern according to the present disclosure;

[0038] Figures 13A and 13B are schematic diagrams of a display substrate after the formation of a second conductive layer pattern according to the present disclosure.

[0039] Figure 14 is a schematic diagram of a display substrate after the formation of a fourth insulating layer pattern according to the present disclosure;

[0040] Figures 15A to 15D are schematic diagrams of a display substrate after the formation of a third conductive layer pattern according to the present disclosure;

[0041] Figures 16A and 16B are schematic diagrams of a display substrate after the formation of a first planarization layer pattern according to the present disclosure;

[0042] Figures 17A to 17D are schematic diagrams of a display substrate after the formation of a fourth conductive layer pattern according to the present disclosure;

[0043] Figures 18A and 18B are schematic diagrams of a display substrate after a second planarization layer pattern has been formed in this disclosure;

[0044] Figures 19A, 19B and 19C are schematic diagrams of a display substrate after an anode conductive layer pattern has been formed in this disclosure.

[0045] Figure 20 is a schematic diagram of the structure of another display substrate according to an exemplary embodiment of the present disclosure;

[0046] Figures 21 and 22 are planar schematic diagrams of the third and fourth conductive layers in Figure 20;

[0047] Figure 23 is a schematic diagram of the structure of another display substrate according to an exemplary embodiment of the present disclosure;

[0048] Figures 24, 25 and 26 are planar schematic diagrams of the second conductive layer, the third conductive layer and the fourth conductive layer in Figure 23;

[0049] Figure 27 is a schematic diagram of the structure of another display substrate according to an exemplary embodiment of the present disclosure;

[0050] Figure 28 is a schematic diagram of the structure of another display substrate according to an exemplary embodiment of the present disclosure;

[0051] Figures 29, 30, and 31 are schematic planar views of the second, third, and fourth conductive layers in Figure 28.

[0052] Explanation of reference numerals in the attached figures: 11—First active layer; 12—Second active layer; 13—Third active layer; 14—Fourth active layer; 15—Fifth active layer; 16—Sixth active layer; 17—Seventh active layer; 21—First scan signal line; 22—Second scan signal line; 23—Emitting light control line; 31—First electrode plate; 32—Second electrode plate; 33—Plate-level connecting strip; 34—Opening; 41—First initial signal line; 42—Second initial signal line; 43—First shielding electrode; 44—Second shielding electrode; 51—First connecting electrode; 52—Second connecting electrode; 53—Third connecting electrode; 54—Fourth connecting electrode; 55—Fifth connecting electrode; 56—Sixth connecting electrode; 57—Seventh connecting electrode; 58—Eighth connecting electrode; 59—Ninth connecting electrode; 61—First data signal line; 62—Second data signal line; 63—First power line; 64—Anode connection electrode; 65—First connection block; 66—Second connection block; 71—First initial connection line; 72—Second initial connection line; 81—First horizontal connection line; 82—Second horizontal connection line; 83—First data electrode; 84—Second data electrode; 85—Dummy electrode; 91—First vertical connection line; 92—Second vertical connection line; 100—Display area; 101—Substrate; 102—Driving structure layer; 103—Light-emitting structure layer; 104—Encapsulation structure layer; 110—First power trace; 111—First power electrode; 112—Second power electrode; 113—Third power electrode; 120—Second power trace; 121—First blocking electrode; 122—Second blocking electrode; 123—Third blocking electrode; 124—First shielding connecting strip; 125—Second shielding connecting strip;126—Third shielding connecting strip; 130A—First anode; 130B—Second anode; 130C—Third anode; 130D—Fourth anode; 200—Binding area; 300—Border area. Detailed Implementation

[0053] To make the objectives, technical solutions, and advantages of this disclosure clearer, embodiments of this disclosure will be described in detail below with reference to the accompanying drawings. Note that the implementation methods can be carried out in many different forms. Those skilled in the art will readily understand that the methods and content can be varied in various forms without departing from the spirit and scope of this disclosure. Therefore, this disclosure should not be construed as limited to the content described in the following embodiments. Without conflict, the embodiments and features in the embodiments of this disclosure can be arbitrarily combined with each other.

[0054] The scale of the figures in this disclosure can be used as a reference in actual manufacturing processes, but is not limited thereto. For example, the aspect ratio of the channel, the thickness and spacing of each film layer, and the width and spacing of each signal line can be adjusted according to actual needs. The number of pixels in the display substrate and the number of sub-pixels in each pixel are not limited to the quantities shown in the figures. The figures described in this disclosure are only schematic diagrams of the structure, and one aspect of this disclosure is not limited to the shapes or values ​​shown in the figures.

[0055] The ordinal numbers “first,” “second,” and “third” used in this specification are used to avoid confusion among the constituent elements, not to limit their quantity.

[0056] In this specification, for convenience, terms such as "middle," "upper," "lower," "front," "rear," "vertical," "horizontal," "top," "bottom," "inner," and "outer" are used to indicate orientation or positional relationships in conjunction with the accompanying drawings. This is solely for the purpose of facilitating the description and simplification, and does not imply that the device or component referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, it should not be construed as a limitation of this disclosure. The positional relationships of the constituent elements may be appropriately varied depending on the orientation of each constituent element being described. Therefore, the use of terms not limited to those described in the specification may be appropriately replaced as needed.

[0057] In this specification, unless otherwise expressly specified and limited, the terms "installation," "connection," and "joining" should be interpreted broadly. For example, they may refer to a fixed connection, a detachable connection, or an integral connection; a mechanical connection or an electrical connection; a direct connection, an indirect connection via an intermediate component, or a connection within two components. Those skilled in the art will understand the specific meaning of these terms in this disclosure based on the specific circumstances.

[0058] In this specification, a transistor is a device that includes at least three terminals: a gate electrode, a drain electrode, and a source electrode. A transistor has a channel region between the drain electrode (drain electrode terminal, drain region, or drain electrode) and the source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. Note that in this specification, the channel region refers to the region through which current primarily flows.

[0059] In this specification, the first terminal of a transistor can be the drain electrode and the second terminal of a transistor can be the source electrode, or vice versa. In cases where transistors with opposite polarities are used or where the current direction changes during circuit operation, the functions of the "source electrode" and "drain electrode" are sometimes interchanged. Therefore, in this specification, the "source electrode" and "drain electrode" can be interchanged, and the "source terminal" and "drain terminal" can be interchanged.

[0060] In this specification, "electrical connection" includes the situation where components are connected together by elements that have a certain electrical function. There are no particular limitations on what constitutes an "electrical function," as long as it enables the transmission and reception of electrical signals between the connected components. Examples of "electrical functions" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other elements with various functions.

[0061] In this specification, "parallel" refers to the state where the angle formed by two straight lines is greater than or equal to -10° and less than 10°, and therefore also includes the state where the angle is greater than or equal to -5° and less than 5°. Similarly, "perpendicular" refers to the state where the angle formed by two straight lines is greater than or equal to 80° and less than 100°, and therefore also includes the state where the angle is greater than or equal to 85° and less than 95°.

[0062] In this specification, the terms "film" and "layer" may be interchanged. For example, "conductive layer" may sometimes be replaced with "conductive film." Similarly, "insulating film" may sometimes be replaced with "insulating layer."

[0063] In this specification, triangles, rectangles, trapezoids, pentagons, or hexagons are not strictly defined; they can be approximate triangles, rectangles, trapezoids, pentagons, or hexagons, and may have minor deformations due to tolerances, and may include chamfers, curved edges, and other variations. The term "approximately" in this disclosure means that the limits are not strictly defined, and the values ​​are within the allowable range of process and measurement errors.

[0064] Figure 1 is a schematic diagram of a display device. As shown in Figure 1, the display device may include a timing controller, a data driver, a scan driver, a light-emitting driver, and a pixel array. The timing controller is connected to the data driver, the scan driver, and the light-emitting driver. The data driver is connected to multiple data signal lines (D1 to Dn), the scan driver is connected to multiple scan signal lines (S1 to Sm), and the light-emitting driver is connected to multiple light-emitting signal lines (E1 to Eo). The pixel array may include multiple sub-pixels Pxij, where i and j can be natural numbers. At least one sub-pixel Pxij may include a circuit unit and a light-emitting unit. The circuit unit may include at least a pixel driving circuit, which is connected to the scan signal lines, the light-emitting signal lines, and the data signal lines. The light-emitting unit may include a light-emitting device, which is connected to the pixel driving circuit of the circuit unit. In an exemplary embodiment, the timing controller can provide grayscale values ​​and control signals of specifications suitable for the data driver to the data driver, provide clock signals, scan start signals, etc. of specifications suitable for the scan driver to the scan driver, and provide clock signals, transmit stop signals, etc. of specifications suitable for the light-emitting driver to the light-emitting driver. The data driver can use grayscale values ​​and control signals received from the timing controller to generate data voltages to be provided to data signal lines D1, D2, D3, ..., Dn. For example, the data driver can sample grayscale values ​​using a clock signal and apply data voltages corresponding to the grayscale values ​​to data signal lines D1 to Dn in pixel rows, where n can be a natural number. The scan driver can generate scan signals to be provided to scan signal lines S1, S2, S3, ..., Sm by receiving clock signals, scan start signals, etc., from the timing controller. For example, the scan driver can sequentially provide scan signals with on-level pulses to scan signal lines S1 to Sm. The scan driver can be configured as a shift register and can generate scan signals by sequentially transmitting scan start signals in the form of on-level pulses to the next stage circuit under the control of a clock signal, where m can be a natural number. The light-emitting driver can generate transmit signals to be provided to light-emitting signal lines E1, E2, E3, ..., Eo by receiving clock signals, transmit stop signals, etc., from the timing controller. For example, the light-emitting driver can sequentially provide transmit signals with cutoff level pulses to the light-emitting signal lines E1 to Eo. The light-emitting driver can be configured as a shift register and can generate transmit signals by sequentially transmitting transmit stop signals in the form of cutoff level pulses to the next stage circuit under the control of a clock signal, where o can be a natural number. In an exemplary embodiment, a pixel array can be disposed on a display substrate.

[0065] Figure 2 is a schematic diagram of a display substrate. As shown in Figure 2, the display substrate may include a display area 100, a bonding area 200 located on one side of the display area 100, and a border area 300 located on other sides of the display area 100. In an exemplary embodiment, the display area 100 may be a flat area, including multiple sub-pixels Pxij that make up a pixel array. The multiple sub-pixels Pxij are configured to display dynamic or still images, and the display area 100 may be referred to as the active area (AA). In an exemplary embodiment, the display substrate may be a flexible substrate, and therefore the display substrate may be deformable, such as being rolled, bent, folded, or rolled up.

[0066] In an exemplary embodiment, the bonding region 200 may include a lead area, a bending area, a driver chip area, and a bonding pin area arranged sequentially along a direction away from the display area. The lead area is connected to the display area 100 and includes at least data leads. The bending area is connected to the lead area and may include at least a composite insulating layer with grooves configured to bend the bonding area to the back side of the display area. The driver chip area may include an integrated circuit (IC) configured to connect to multiple data leads. The bonding pin area may include bonding pads configured to bond to an external flexible printed circuit (FPC).

[0067] In an exemplary embodiment, the bezel region 300 may include a circuit region, a power line region, a crack dam region, and a cutting region sequentially arranged along a direction away from the display region 100. The circuit region is connected to the display region 100 and may include at least a gate driving circuit connected to scan signal lines and light emission signal lines in the display region 100. The power line region is connected to the circuit region and may include at least bezel power leads extending parallel to the edge of the display region and connected to a cathode in the display region 100. The crack dam region is connected to the power line region and may include at least a plurality of cracks formed on the composite insulating layer. The cutting region is connected to the crack dam region and may include at least a cutting groove formed on the composite insulating layer, configured such that after all film layers of the display substrate have been prepared, a cutting device cuts along the cutting grooves respectively.

[0068] In an exemplary embodiment, the lead-out area in the binding area 200 and the power line area in the border area 300 may be provided with isolation dams. The isolation dams may extend along a direction parallel to the edge of the display area to form a ring structure surrounding the display area 100. The edge of the display area is the edge of the binding area or the border area of ​​the display area.

[0069] Figure 3 is a schematic diagram of the planar structure of a display area in a display substrate. As shown in Figure 3, the display area may include multiple pixel units P arranged in a matrix. At least one pixel unit P may include a first sub-pixel P1, a second sub-pixel P2, a third sub-pixel P3, and a fourth sub-pixel P4. Each sub-pixel may include a circuit unit and a light-emitting unit. The circuit unit may include at least a pixel driving circuit, which is connected to a scan signal line, a light-emitting signal line, and a data signal line, respectively. The pixel driving circuit is configured to receive the data voltage transmitted by the data signal line and output a corresponding current to the light-emitting unit under the control of the scan signal line and the light-emitting signal line. The light-emitting unit may include a light-emitting device, which is connected to the pixel driving circuit of the sub-pixel. The light-emitting device is configured to emit light of a corresponding brightness in response to the current output by the pixel driving circuit of the sub-pixel.

[0070] In an exemplary embodiment, the first sub-pixel P1 can be a red sub-pixel (R) emitting red light, the second sub-pixel P2 can be a blue sub-pixel (B) emitting blue light, the third sub-pixel P3 can be a first green sub-pixel (G1) emitting green light, and the fourth sub-pixel P4 can be a second green sub-pixel (G2) emitting green light. In an exemplary embodiment, the shape of the sub-pixels can be rectangular, rhomboid, pentagonal, or hexagonal, and the four sub-pixels can be arranged in an RGBG pattern.

[0071] In other exemplary embodiments, the pixel unit P may include three sub-pixels, which may be arranged in a horizontal or vertical manner, and this disclosure does not limit this arrangement.

[0072] Figure 4 is a cross-sectional structural diagram of a display area in a display substrate, illustrating the structure of four sub-pixels in the display area. As shown in Figure 4, in the direction perpendicular to the display substrate, the display area may include a driving structure layer 102 disposed on the substrate 101, a light-emitting structure layer 103 disposed on the side of the driving structure layer 102 away from the substrate 101, and an encapsulation structure layer 104 disposed on the side of the light-emitting structure layer 103 away from the substrate 101. In some possible implementations, the display area may include other film layers, such as a touch structure layer, etc., which are not limited herein.

[0073] In an exemplary embodiment, the substrate 101 can be a flexible substrate or a rigid substrate. The driving structure layer 102 can include multiple circuit units, each of which can include at least a pixel driving circuit composed of multiple transistors and storage capacitors. The light-emitting structure layer 103 can include multiple light-emitting units, each of which can include a light-emitting device. The light-emitting device can include at least an anode, an organic light-emitting layer, and a cathode. The anode is connected to the pixel driving circuit, the organic light-emitting layer is connected to the anode, and the cathode is connected to the organic light-emitting layer. The organic light-emitting layer emits light of a corresponding color under the driving of the anode and cathode. The encapsulation structure layer 104 can include a first encapsulation layer, a second encapsulation layer, and a third encapsulation layer stacked together. The first and third encapsulation layers can be made of inorganic materials, and the second encapsulation layer can be made of organic materials. The second encapsulation layer is disposed between the first and third encapsulation layers, forming an inorganic / organic / inorganic material stacked structure, which can ensure that external moisture cannot enter the light-emitting structure layer 103.

[0074] Figure 5 is an equivalent circuit diagram of a pixel driving circuit. In an exemplary embodiment, the pixel driving circuit can be a 3T1C, 4T1C, 5T1C, 5T2C, 6T1C, 7T1C, or 8T1C structure. As shown in Figure 5, the pixel driving circuit may include seven transistors (first transistor T1 to seventh transistor T7) and one storage capacitor C. The pixel driving circuit is connected to seven signal lines (first scan signal line S1, second scan signal line S2, light emission signal line EM, first initial signal line INIT1, second initial signal line INIT1, first power supply line VDD, and data signal line DATA).

[0075] In an exemplary embodiment, the pixel driving circuit may include a first node N1, a second node N2, a third node N3, and a fourth node N4. The first node N1 is connected to the second terminal of the first transistor T1, the first terminal of the second transistor T2, the gate electrode of the third transistor T3, and the first terminal of the storage capacitor C. The second node N2 is connected to the first terminal of the third transistor T3, the second terminal of the fourth transistor T4, and the second terminal of the fifth transistor T5. The third node N3 is connected to the second terminals of the second transistor T2, the second terminals of the third transistor T3, and the first terminal of the sixth transistor T6. The fourth node N4 is connected to the second terminal of the sixth transistor T6 and the second terminal of the seventh transistor T7.

[0076] In an exemplary embodiment, the first end of the storage capacitor C is connected to the first node N1, and the second end of the storage capacitor C is connected to the first power line VDD.

[0077] In an exemplary embodiment, the gate electrode of the first transistor T1 is connected to the second scan signal line S2, the first electrode of the first transistor T1 is connected to the first initial signal line INIT1, and the second electrode of the first transistor is connected to the first node N1.

[0078] In an exemplary embodiment, the gate electrode of the second transistor T2 is connected to the first scan signal line S1, the first electrode of the second transistor T2 is connected to the first node N1, and the second electrode of the second transistor T2 is connected to the third node N3.

[0079] In an exemplary embodiment, the gate electrode of the third transistor T3 is connected to the first node N1, the first electrode of the third transistor T3 is connected to the second node N2, and the second electrode of the third transistor T3 is connected to the third node N3.

[0080] In an exemplary embodiment, the gate electrode of the fourth transistor T4 is connected to the first scan signal line S1, the first electrode of the fourth transistor T4 is connected to the data signal line DATA, and the second electrode of the fourth transistor T4 is connected to the second node N2.

[0081] In an exemplary embodiment, the gate electrode of the fifth transistor T5 is connected to the light-emitting signal line EM, the first electrode of the fifth transistor T5 is connected to the first power supply line VDD, and the second electrode of the fifth transistor T5 is connected to the second node N2.

[0082] In an exemplary embodiment, the gate electrode of the sixth transistor T6 is connected to the light-emitting signal line EM, the first electrode of the sixth transistor T6 is connected to the third node N3, and the second electrode of the sixth transistor T6 is connected to the fourth node N4.

[0083] In an exemplary embodiment, the gate electrode of the seventh transistor T7 is connected to the first scan signal line S1, the first electrode of the seventh transistor T7 is connected to the second initial signal line INIT2, and the second electrode of the seventh transistor T7 is connected to the fourth node N4.

[0084] In an exemplary embodiment, the first electrode of the light-emitting device EL is connected to the fourth node N4, and the second electrode of the light-emitting device EL is connected to the second power line VSS. The light-emitting device EL can be an OLED, including a stacked first electrode (anode), an organic light-emitting layer, and a second electrode (cathode), or it can be a QLED, including a stacked first electrode (anode), a quantum dot light-emitting layer, and a second electrode (cathode).

[0085] In an exemplary embodiment, the first power line VDD is configured to provide a constant first power signal to the pixel driving circuit, and the second power line VSS is configured to provide a constant second power signal to the light-emitting device, wherein the first power signal is a high-level signal and the second power signal is a low-level signal. The first initial signal line INIT1 and the second initial signal line INIT2 are configured to provide constant first initial signals and second initial signals to the pixel driving circuit, respectively, which are not limited herein.

[0086] In an exemplary embodiment, the first transistor T1 to the seventh transistor T7 in the pixel driving circuit can be either P-type transistors or N-type transistors. Using the same type of transistor in the pixel driving circuit can simplify the process flow, reduce the manufacturing difficulty of the display panel, and improve the product yield. In some possible implementations, the first transistor T1 to the seventh transistor T7 may include both P-type and N-type transistors.

[0087] In an exemplary embodiment, the first transistor T1 to the seventh transistor T7 can be low-temperature polycrystalline silicon (LTPS) transistors, or oxide transistors, or a combination of both. The active layer of the LTPS transistor is made of low-temperature polycrystalline silicon (LTPS), while the active layer of the oxide transistor is made of oxide semiconductor. LTPS transistors have advantages such as high mobility and fast charging, while oxide transistors have advantages such as low leakage current. Integrating LTPS transistors and oxide transistors onto a single display substrate to form an LTPO (Low Temperature Polycrystalline + Oxide) display substrate leverages the advantages of both, enabling low-frequency driving, reducing power consumption, and improving display quality.

[0088] With the development of OLED display technology, consumers have increasingly higher requirements for the display quality and effect of display products, and narrow bezel displays have become a new trend in display product development. In one type of display substrate, because the data signals of the integrated circuits in the bonding area need to be introduced into a wider display area in a fan-out manner through data leads, the lead-out area occupies a large space, resulting in a larger bottom bezel.

[0089] To reduce the bottom bezel width, an exemplary embodiment of this disclosure provides a display substrate employing a fanout-in-pixel (FIP) structure. The display area of ​​this disclosure is provided with multiple data connection lines, which may include first connection lines and second connection lines. The first ends of the multiple first connection lines are connected to multiple data signal lines in the display area, and the second ends of the multiple first connection lines are connected to the first ends of the multiple second connection lines. The second ends of the multiple second connection lines extend to a bonding area and are then connected to an integrated circuit via multiple data leads in a lead-out area. Since the lead-out area does not require fan-shaped diagonal lines, the width of the lead-out area is reduced, thereby reducing the bottom bezel width.

[0090] Figure 6 is a schematic diagram of a data connection line according to an exemplary embodiment of the present disclosure. The data connection line adopts a FIP structure. As shown in Figure 6, in a plane parallel to the display substrate, the display substrate may include at least a display area 100, a bonding area 200 located on one side of the display area 100, and a border area 300 located on other sides of the display area 100. In a direction perpendicular to the display substrate, the display substrate may include at least a driving structure layer disposed on a substrate and a light-emitting structure layer disposed on the side of the driving structure layer away from the substrate. The driving structure layer of the display area 100 may include multiple circuit units constituting multiple unit rows and multiple unit columns, multiple data signal lines DATA, multiple horizontal connection lines FIP-H, and multiple vertical connection lines FIP-V. At least one circuit unit may include a pixel driving circuit, which is configured to output a corresponding current to the connected light-emitting device. The light-emitting structure layer of the display area 100 may include multiple light-emitting units, and at least one light-emitting unit may include a light-emitting device. The light-emitting device is connected to the pixel driving circuit of the corresponding circuit unit, and the light-emitting device is configured to emit light of a corresponding brightness in response to the current output by the connected pixel driving circuit.

[0091] In exemplary embodiments, the circuit unit referred to in this disclosure refers to a region divided according to the pixel driving circuit, and the light-emitting unit referred to in this disclosure refers to a region divided according to the light-emitting device. In exemplary embodiments, the position of the orthographic projection of the light-emitting unit on the substrate may correspond to the position of the orthographic projection of the circuit unit on the substrate, or the position of the orthographic projection of the light-emitting unit on the substrate may not correspond to the position of the orthographic projection of the circuit unit on the substrate.

[0092] In an exemplary embodiment, a plurality of circuit units arranged sequentially along the first direction X can be referred to as a unit row, and a plurality of circuit units arranged sequentially along the second direction Y can be referred to as a unit column. The plurality of unit rows and the plurality of unit columns constitute an array of circuit units arranged in an array, and the first direction X intersects the second direction Y.

[0093] In an exemplary embodiment, the first direction X and the second direction Y can be perpendicular to each other.

[0094] In an exemplary embodiment, the shape of the horizontal connecting line FIP-H can be a straight line or a broken line extending along the first direction X, and the shapes of the data signal line DATA and the vertical connecting line FIP-V can be straight lines or broken lines extending along the second direction Y. Multiple data signal lines DATA are sequentially arranged at predetermined intervals along the first direction X. At least one data signal line DATA is connected to multiple pixel driving circuits in a unit column, and the data signal line DATA is configured to provide data signals to the connected pixel driving circuits. The first end of the horizontal connecting line FIP-H is connected to the data signal line DATA, and the second end of the horizontal connecting line FIP-H is connected to the first end of the vertical connecting line FIP-V. The second end of the vertical connecting line FIP-V extends to the bonding area and connects to the data lead-in line DATA-IN, so that the data signal line DATA in the display area is connected to the data lead-in line DATA-IN in the bonding area 200 through the horizontal connecting line FIP-H and the vertical connecting line FIP-V, forming an FIP structure (also called a FIAA structure). In an exemplary embodiment, the horizontal connecting line FIP-H and the vertical connecting line FIP-V are collectively referred to as data connecting lines.

[0095] In an exemplary embodiment, the bonding area 200 may include a lead-out area, a bending area, a driver chip area, and a bonding pin area arranged sequentially along a direction away from the display area. The lead-out area is connected to the display area, and the bending area is connected to the lead-out area. The lead-out area may have multiple data leads (DATA-IN) extending along a direction away from the display area. The first end of some data leads (DATA-IN) is connected to the vertical connecting line (FIP-V) in the display area 100, and the first end of another portion of data leads (DATA-IN) is connected to the data signal line (DATA) in the display area 100. The second ends of all data leads (DATA-IN) cross the bending area along the second direction Y and are connected to the integrated circuit in the driver chip area, allowing the integrated circuit to apply data signals to the data signal line through the data leads and data connecting lines. Because the horizontal connecting line (FIP-H) and the vertical connecting line (FIP-V) are located in the display area, the length of the lead-out area in the second direction Y can be effectively reduced, significantly reducing the bottom bezel width, increasing the screen-to-body ratio, and facilitating full-screen display.

[0096] In an exemplary embodiment, the number of data connection lines in the display area can be the same as the number of data signal lines, with each data signal line connected to a corresponding data lead-out line via a data connection line. Alternatively, the number of data connection lines in the display area can be less than the number of data signal lines, with some data signal lines in the display area connected to corresponding data lead-out lines via data connection lines, and other data signal lines directly connected to data lead-out lines. This disclosure does not impose any limitations on this aspect.

[0097] In a display substrate, a data signal line is provided in a unit column, which is connected to all pixel driving circuits in the unit column. The data signal line is configured to provide data signals to all pixel driving circuits in the unit column. With the increase in resolution and refresh rate, the data writing and compensation time for a single line within a frame is shortened, leading to difficulties in data writing and insufficient compensation, resulting in a deterioration in display quality and effect.

[0098] To improve display quality and effect, the display substrate provided in the exemplary embodiments of this disclosure employs a dual-source structure. In this display substrate, each unit column of the display area is provided with two data signal lines: one data signal line is connected to the pixel driving circuit in the odd-numbered unit rows, and the other data signal line is connected to the pixel driving circuit in the even-numbered unit rows. Since the pixel driving circuits in the odd-numbered and even-numbered unit rows of each unit column are connected to different data signal lines, the data writing and compensation time of the pixel driving circuits can be increased.

[0099] Figure 7 is a schematic diagram of a data signal line structure according to an exemplary embodiment of the present disclosure. As shown in Figure 7, the display substrate may include at least a display area 100 and a bonding area 200 located on one side of the display area 100. The display area 100 of the display substrate may include a plurality of circuit units constituting a plurality of cell rows and a plurality of cell columns, and at least one circuit unit may include a pixel driving circuit. The bonding area 200 of the display substrate may include at least a switching circuit.

[0100] In an exemplary embodiment, the multiple cell rows of the display area may include multiple first cell rows and multiple second cell rows. The first cell rows may be odd-numbered, and the second cell rows may be even-numbered; alternatively, the first cell rows may be even-numbered, and the second cell rows may be odd-numbered.

[0101] In an exemplary embodiment, at least one cell column may include a first data signal line DA and a second data signal line DB. The first data signal line DA is connected to the pixel driving circuits of a plurality of first cell rows in the cell column, providing data signals to the pixel driving circuits of the plurality of first cell rows. The second data signal line DB is connected to the pixel driving circuits of a plurality of second cell rows in the cell column, providing data signals to the pixel driving circuits of the plurality of second cell rows. In an exemplary embodiment, the first data signal line DA and the second data signal line DB may be collectively referred to as data signal lines.

[0102] In an exemplary embodiment, the switching circuit of the bonding area may include multiple first switching units F1, multiple second switching units F2, a first control line, and a second control line. The control terminals of the multiple first switching units F1 are connected to the first control line, the input terminals of the multiple first switching units F1 are connected to multiple data output lines DATA-IN, and the output terminals of the multiple first switching units F1 are connected to multiple first data signal lines DA. The control terminals of the multiple second switching units F2 are connected to the second control line, the input terminals of the multiple second switching units F2 are connected to multiple data output lines DATA-IN, and the output terminals of the multiple second switching units F2 are connected to multiple second data signal lines DB.

[0103] In an exemplary embodiment, during the operation of the display substrate, when the first control line outputs a conduction signal, multiple first switch units F1 are turned on. The data signal output by the integrated circuit is provided to the pixel driving circuit in the first unit row through the data lead-in, the first switch unit F1, and the first data signal line DA. When the second control line outputs a conduction signal, multiple second switch units F2 are turned on. The data signal output by the integrated circuit is provided to the pixel driving circuit in the second unit row through the data lead-in, the second switch unit F2, and the second data signal line DB. Since the pixel driving circuits in the first and second unit rows of each unit column receive data signals respectively, the data signal holding time is increased. Therefore, the data writing time and compensation time of the pixel driving circuit can be effectively increased, ensuring the display quality and effect of high resolution and high refresh rate.

[0104] An exemplary embodiment of this disclosure provides a display substrate. In an exemplary embodiment, the display substrate may include a driving structure layer disposed on a substrate and a light-emitting structure layer disposed on a side of the driving structure layer away from the substrate; the driving structure layer includes a plurality of circuit units forming a plurality of unit rows and a plurality of unit columns, the plurality of unit rows including a plurality of first unit rows and a plurality of second unit rows, wherein the first unit rows are odd-numbered unit rows and the second unit rows are even-numbered unit rows, or the first unit rows are even-numbered unit rows and the second unit rows are odd-numbered unit rows; at least one circuit unit includes a pixel driving circuit, a first data signal line and a second data signal line, the first data signal line being connected to the pixel driving circuit in the first unit row and the second data signal line being connected to the pixel driving circuit in the second unit row; The driving structure layer further includes at least one first horizontal connecting line and at least one second horizontal connecting line extending along a first direction, and at least one first vertical connecting line and at least one second vertical connecting line extending along a second direction, wherein the first direction and the second direction intersect; a first end of the first horizontal connecting line is connected to the first data signal line, a second end of the first horizontal connecting line is connected to the first vertical connecting line, a first end of the second horizontal connecting line is connected to the second data signal line, and a second end of the second horizontal connecting line is connected to the second vertical connecting line; in the first direction, the first vertical connecting line is disposed between two adjacent first data signal lines, and the second vertical connecting line is disposed between two adjacent second data signal lines.

[0105] In an exemplary embodiment, the driving structure layer further includes at least one first power trace extending along the first direction and at least one second power trace extending along the second direction; in a direction perpendicular to the display substrate, the display substrate includes a first conductive layer disposed on a substrate, a second conductive layer disposed on the side of the first conductive layer away from the substrate, a third conductive layer disposed on the side of the second conductive layer away from the substrate, and a fourth conductive layer disposed on the side of the third conductive layer away from the substrate. The first power trace and the second power trace are disposed in different conductive layers, and the second power trace is connected to the first power trace through a via, forming a mesh-like interconnected structure for transmitting power signals.

[0106] In an exemplary embodiment, the light-emitting structure layer includes a plurality of light-emitting units, including a first light-emitting unit emitting red light, a second light-emitting unit emitting blue light, and a third and fourth light-emitting units emitting green light. The first light-emitting unit includes at least a first anode, the second light-emitting unit includes at least a second anode, the third light-emitting unit includes at least a third anode, and the fourth light-emitting unit includes at least a fourth anode. The orthographic projections of the first anode and the second anode onto the substrate at least partially overlap with the orthographic projections of at least two first data signal lines or at least two second data signal lines onto the substrate. The orthographic projections of the third anode and the fourth anode onto the substrate at least partially overlap with the orthographic projections of at least one first data signal line and at least one second data signal line onto the substrate.

[0107] In an exemplary embodiment, the orthographic projections of the first anode and the second anode on the substrate at least partially overlap with the orthographic projections of at least one second power supply trace and at least two first data signal lines on the substrate, and the two first data signal lines are symmetrically arranged with respect to the second power supply trace. Alternatively, the orthographic projections of the first anode and the second anode on the substrate at least partially overlap with the orthographic projections of at least one second power supply trace and at least two second data signal lines on the substrate, and the two second data signal lines are symmetrically arranged with respect to the second power supply trace.

[0108] Figure 8 is a schematic diagram of the structure of a data signal line and a data connection line according to an exemplary embodiment of the present disclosure. As shown in Figure 8, the driving structure layer of the display area may include multiple circuit units constituting multiple unit rows and multiple unit columns, multiple first data signal lines 61, multiple second data signal lines 62, multiple first horizontal connection lines 81, multiple second horizontal connection lines 82, multiple first vertical connection lines 91, multiple second vertical connection lines 92, multiple first power supply lines 110, and multiple second power supply lines 120. The shapes of the first horizontal connection lines 81, the second horizontal connection lines 82, and the first power supply lines 110 may be straight lines or broken lines extending along the first direction X. The shapes of the first data signal lines 61, the second data signal lines 62, the first vertical connection lines 91, the second vertical connection lines 92, and the second power supply lines 120 may be straight lines or broken lines extending along the second direction Y.

[0109] In an exemplary embodiment, the multiple unit rows may include multiple first unit rows and multiple second unit rows, which may be alternately arranged in the second direction Y. The first unit rows may be odd-numbered, and the second unit rows may be even-numbered; alternatively, the first unit rows may be even-numbered, and the second unit rows may be odd-numbered.

[0110] In an exemplary embodiment, a first data signal line 61 and a second data signal line 62 may be disposed in the same cell column. The first data signal line 61 is connected to the pixel driving circuit of a plurality of first cell rows in the cell column, and the second data signal line 62 is connected to the pixel driving circuit of a plurality of second cell rows in the cell column.

[0111] In an exemplary embodiment, in at least one cell column, the first data signal line 61 may be disposed on one side of the second data signal line 62 in the first direction X, or the second data signal line 62 may be disposed on one side of the first data signal line 61 in the first direction X. For example, in two adjacent cell columns, the first data signal line 61 may be disposed on one side of the second data signal line 62 in the first direction X. As another example, in two other adjacent cell columns, the second data signal line 62 may be disposed on one side of the first data signal line 61 in the first direction X.

[0112] In an exemplary embodiment, the second data signal line 62, the first data signal line 61, the second data signal line 62, the first data signal line 61, the first data signal line 61, the second data signal line 62, the first data signal line 61, and the second data signal line 62 can be arranged periodically in the first direction X. That is, four unit columns can be used as a repeating unit column, and multiple repeating unit columns are arranged sequentially in the first direction X. The second data signal line 62, the first data signal line 61, the second data signal line 62, the first data signal line 61, the first data signal line 61, the first data signal line 61, the first data signal line 61, the second data signal line 62, the first data signal line 61, and the second data signal line 62 in each repeating unit column are arranged sequentially in the first direction X.

[0113] In an exemplary embodiment, at least one circuit unit may include a unit center line, which may be a straight line that bisects the circuit unit in a first direction X and extends along a second direction Y, or the unit center line may be a straight line that passes through the geometric center of the circuit unit and extends along the second direction Y. The first data signal line 61 and the second data signal line 62 may be arranged in a mirror-symmetrical manner with respect to the unit center line.

[0114] In an exemplary embodiment, the plurality of circuit units may include a plurality of first circuit units Q1 and a plurality of second circuit units Q2, and both the first circuit units Q1 and the second circuit units Q2 may include pixel driving circuits. Specifically, the pixel driving circuit in the first circuit unit Q1 may be connected to a first data signal line 61 or a second data signal line 62 located on one side of the unit center line in the first direction X, and the pixel driving circuit in the second circuit unit Q2 may be connected to a first data signal line 61 or a second data signal line 62 located on the opposite side of the unit center line in the first direction X.

[0115] In some other embodiments, the pixel driving circuit in the first circuit unit Q1 may be connected to the first data signal line 61 or the second data signal line 62 located on the opposite side of the first direction X of the unit center line, and the pixel driving circuit in the second circuit unit Q2 may be connected to the first data signal line 61 or the second data signal line 62 located on the side of the first direction X of the unit center line. This disclosure does not limit the scope of the invention.

[0116] In an exemplary embodiment, in at least one unit row, the first circuit unit Q1, the second circuit unit Q2, and the second circuit unit Q2 may be arranged periodically in the first direction X, or the second circuit unit Q2, the second circuit unit Q2, the first circuit unit Q1, and the first circuit unit Q1 may be arranged periodically in the first direction X.

[0117] In an exemplary embodiment, in the first unit row, the first circuit unit Q1, the second circuit unit Q2, and the second circuit unit Q2 can be arranged periodically in the first direction X. That is, two first circuit units Q1 and two second circuit units Q2 can be used as a first repeating unit. Multiple first repeating units are arranged sequentially in the first direction X. In each first repeating unit, the first circuit unit Q1, the second circuit unit Q2, and the second circuit unit Q2 are arranged sequentially in the first direction X.

[0118] In an exemplary embodiment, in the second unit row, the second circuit unit Q2, the first circuit unit Q1, and the first circuit unit Q1 can be arranged periodically in the first direction X. That is, two second circuit units Q2 and two first circuit units Q1 can be a second repeating unit, and multiple second repeating units are arranged sequentially in the first direction X. In each second repeating unit, the second circuit unit Q2, the first circuit unit Q1, and the first circuit unit Q1 are arranged sequentially in the first direction X.

[0119] In an exemplary embodiment, in at least one unit column, the first circuit unit Q1 and the second circuit unit Q2 may be alternately arranged in the second direction Y.

[0120] In an exemplary embodiment, in the first circuit unit Q1 of the first unit row, the first data signal line 61 may be disposed on one side of the second data signal line 62 in the first direction X, and in the first circuit unit Q1 of the second unit row, the second data signal line 62 may be disposed on one side of the first data signal line 61 in the first direction X.

[0121] In an exemplary embodiment, in the second circuit unit Q2 of the first unit row, the second data signal line 62 may be disposed on one side of the first data signal line 61 in the first direction X, and in the second circuit unit Q2 of the second unit row, the first data signal line 61 may be disposed on one side of the second data signal line 62 in the first direction X.

[0122] In an exemplary embodiment, the first horizontal connecting line 81 may be disposed in one of the first and second unit rows, and the second horizontal connecting line 82 may be disposed in the other of the first and second unit rows. The first horizontal connecting line 81 and the second horizontal connecting line 82 may be alternately disposed in the second direction Y.

[0123] In an exemplary embodiment, the first vertical connecting line 91 and the second vertical connecting line 92 can be respectively arranged between adjacent unit columns. The first vertical connecting line 91 and the second vertical connecting line 92 can be alternately arranged in the first direction X, and there can be at least two unit columns between adjacent first vertical connecting lines 91 and second vertical connecting lines 92 in the first direction X.

[0124] In an exemplary embodiment, the first end of the first horizontal connecting line 81 is connected to the first data signal line 61. The second end of the first horizontal connecting line 81 extends along the first direction X or the opposite direction of the first direction X and is connected to the first end of the first vertical connecting line 91. The second end of the first vertical connecting line 91 extends along the second direction Y to the binding area and is connected to the data lead-out line. The first end of the second horizontal connecting line 82 is connected to the second data signal line 62. The second end of the second horizontal connecting line 82 extends along the first direction X or the opposite direction of the first direction X and is connected to the first end of the second vertical connecting line 92. The second end of the second vertical connecting line 92 extends along the second direction Y to the binding area and is connected to the data lead-out line.

[0125] In an exemplary embodiment, adjacent cell columns may include at least a first type of adjacent cell column, a second type of adjacent cell column, and a third type of adjacent cell column. Specifically, a first type of adjacent cell column refers to a first data signal line 61 in one cell column being adjacent to a first data signal line 61 in another cell column in the first direction X; a second type of adjacent cell column refers to a second data signal line 62 in one cell column being adjacent to a second data signal line 62 in another cell column in the first direction X; and a third type of adjacent cell column refers to a first data signal line 61 in one cell column being adjacent to a second data signal line 62 in another cell column in the first direction X.

[0126] In an exemplary embodiment, the first vertical connecting line 91 may be disposed between adjacent unit columns of the first type, that is, the first vertical connecting line 91 may be disposed between two adjacent first data signal lines 61.

[0127] In an exemplary embodiment, the second vertical connecting line 92 can be disposed between adjacent unit columns of the second type, that is, the second vertical connecting line 92 can be disposed between two adjacent second data signal lines 62.

[0128] In an exemplary embodiment, the first power supply traces 110 can be respectively disposed in the first cell row and the second cell row, and multiple first power supply traces 110 are sequentially disposed in the second direction Y. The second power supply traces 120 can be respectively disposed between adjacent cell columns, and multiple second power supply traces 120 are sequentially disposed in the first direction X. At least one second power supply trace 120 is connected to at least one first power supply trace 110 to form a mesh-like interconnected structure for transmitting power signals.

[0129] In an exemplary embodiment, the first horizontal connecting line 81, the second horizontal connecting line 82, the first vertical connecting line 91 and the second vertical connecting line 92 can be collectively referred to as data connecting lines, and the first power supply line 110 and the second power supply line 120 can be collectively referred to as power supply lines.

[0130] In an exemplary embodiment, since the first horizontal connecting line 81, the second horizontal connecting line 82, the first vertical connecting line 91, and the second vertical connecting line 92 are located in a portion of the display area, and the first power trace 110 and the second power trace 120 are located in another portion of the display area, the display area can be divided into a first area and a second area based on the location of the data connecting lines and power traces. The first area may be an area where the first horizontal connecting line 81, the second horizontal connecting line 82, the first vertical connecting line 91, and the second vertical connecting line 92 are located. The second area may be an area without the first horizontal connecting line 81, the second horizontal connecting line 82, the first vertical connecting line 91, and the second vertical connecting line 92, or it may be an area where the first power trace 110 and the second power trace 120 are located. In an exemplary embodiment, the first area may be referred to as a FIP area, and the second area may be referred to as a non-FIP area or a SIP area.

[0131] In an exemplary embodiment, the display substrate may include multiple conductive layers in a direction perpendicular to the display substrate. The first horizontal connecting line 81, the second horizontal connecting line 82, and the first power trace 110 may be disposed in the same layer and formed synchronously through the same patterning process. A first break K1 may be provided between the first horizontal connecting line 81 and the first power trace 110 disposed in the same cell row, and between the second horizontal connecting line 82 and the first power trace 110 disposed in the same cell row. The first break K1 is configured to achieve mutual insulation between the first horizontal connecting line 81 and the first power trace 110, and between the second horizontal connecting line 82 and the first power trace 110. The first vertical connecting line 91, the second vertical connecting line 92, and the second power trace 120 may be disposed in the same layer and formed synchronously through the same patterning process. A second break K2 may be provided between the first vertical connecting line 91 and the second power line 120 in the same unit column, and between the second vertical connecting line 92 and the second power line 120 in the same unit column. The second break K2 is configured to achieve mutual insulation between the first vertical connecting line 91 and the second power line 120, and mutual insulation between the second vertical connecting line 92 and the second power line 120.

[0132] In exemplary embodiments, some first unit rows or second unit rows may include at least one first lateral connection line 81 and at least one first power supply trace 110, or at least one second lateral connection line 82 and at least one first power supply trace 110. In other first unit rows or second unit rows, only the first power supply trace 110 may be included.

[0133] In exemplary embodiments, some unit columns may include at least one first vertical connecting line 91 and at least one second power supply line 120, or at least one second vertical connecting line 92 and at least one second power supply line 120. In other unit columns, only the second power supply line 120 may be included.

[0134] In an exemplary embodiment, the plurality of conductive layers may include a first conductive layer disposed on a substrate, a second conductive layer disposed on the side of the first conductive layer away from the substrate, a third conductive layer disposed on the side of the second conductive layer away from the substrate, and a fourth conductive layer disposed on the side of the third conductive layer away from the substrate. The first power trace 110 and the second power trace 120 may be disposed in different conductive layers, and the second power trace 120 may be connected to the first power trace 110 through a via.

[0135] In one exemplary embodiment, the first power trace 110 may be disposed in the second conductive layer, and the second power trace 120 may be disposed in the third conductive layer.

[0136] In another exemplary embodiment, the first power trace 110 may be disposed in the second conductive layer, and the second power trace 120 may be disposed in the fourth conductive layer.

[0137] In another exemplary embodiment, the first power trace 110 may be disposed in the third conductive layer, and the second power trace 120 may be disposed in the fourth conductive layer.

[0138] In one exemplary embodiment, the second power supply trace 120 may be continuously arranged in the second direction Y.

[0139] In another exemplary embodiment, the second power supply traces 120 may be spaced out in the second direction Y.

[0140] The following examples illustrate the display substrate of this embodiment.

[0141] Figures 9A and 9B are schematic diagrams of the structure of a display substrate according to an exemplary embodiment of the present disclosure. Figure 9A is a schematic diagram of the structure of region A in Figure 8, and Figure 9B is a schematic diagram of the structure of region B in Figure 8. Figure 9A illustrates the structure of eight circuit units in two unit rows (the Mth unit row and the M+1th unit row) and four unit columns (the Nth to the N+3th unit columns). Figure 9B illustrates the structure of eight circuit units in two unit rows (the Mth unit row and the M+1th unit row) and four unit columns (the N+20th to the N+23rd unit columns). The Mth unit row is the first unit row, and the M+1th unit row is the second unit row. In the Mth unit row, the circuit units in the Nth, N+1th, N+20th, and N+21st unit columns are first circuit units, and the circuit units in the N+2th, N+3th, N+22nd, and N+23rd unit columns are second circuit units. In the (M+1)th unit row, the circuit units in the Nth, N+1st, N+20th, and N+21st unit columns are the second circuit units, and the circuit units in the N+2nd, N+3rd, N+22nd, and N+23rd unit columns are the first circuit units.

[0142] As shown in Figures 9A and 9B, in a direction perpendicular to the display substrate, the display substrate may include at least a driving structure layer disposed on the substrate and a light-emitting structure layer disposed on the side of the driving structure layer away from the substrate. In a plane parallel to the substrate, the driving structure layer may include multiple circuit units forming multiple cell rows and multiple cell columns, and at least one circuit unit may include a pixel driving circuit. The light-emitting structure layer may include multiple light-emitting units, which may include a first light-emitting unit emitting red light, a second light-emitting unit emitting blue light, and a third and fourth light-emitting unit emitting green light. The first light-emitting unit may include at least a first anode, the second light-emitting unit may include at least a second anode, the third light-emitting unit may include at least a third anode, and the fourth light-emitting unit may include at least a fourth anode.

[0143] In an exemplary embodiment, the pixel driving circuit of at least one circuit unit can be connected to the first scan signal line 21, the second scan signal line 22, the light emission signal line 23, the first initial signal line 41, the second initial signal line 42, the first power supply line 63, and the data signal line, respectively. The data signal line may include a first data signal line 61 and a second data signal line 62 disposed in a unit column. The first data signal line 61 is connected to the pixel driving circuit in the Mth unit row (first unit row), and the second data signal line 62 is connected to the pixel driving circuit in the (M+1)th unit row (second unit row).

[0144] In an exemplary embodiment, in the Nth, N+1th, N+20th, and N+21st cell columns, the first data signal line 61 may be disposed on one side of the second data signal line 62 in the first direction X. In the N+2nd, N+3rd, N+22nd, and N+23rd cell columns, the second data signal line 62 may be disposed on one side of the first data signal line 61 in the first direction X.

[0145] In an exemplary embodiment, in at least one circuit unit, the first data signal line 61 and the second data signal line 62 may be arranged in a mirror-symmetrical manner with respect to the center line of the unit.

[0146] In an exemplary embodiment, the first scan signal line 21 and the second scan signal line 22 are configured to provide a first scan signal and a second scan signal to the pixel driving circuit, respectively; the light emission signal line 23 is configured to provide a light emission control signal to the pixel driving circuit; the first initial signal line 41 and the second initial signal line 42 are configured to provide a first initial signal and a second initial signal to the pixel driving circuit, respectively; the first power supply line 63 is configured to provide a first power supply signal to the pixel driving circuit; and the first data signal line 61 and the second data signal line 62 are configured to provide data signals to the pixel driving circuit. The multiple signal lines connected to the pixel driving circuit can be located within a circuit unit.

[0147] In an exemplary embodiment, the shapes of the first scan signal line 21, the second scan signal line 22, the light emission signal line 23, the first initial signal line 41, and the second initial signal line 42 can be straight lines or broken lines extending along the first direction X of the main body, and the shapes of the first data signal line 61, the second data signal line 62, and the first power line 63 can be straight lines or broken lines extending along the second direction Y of the main body.

[0148] In this disclosure, "A extends along direction B" means that A may include a main part and a secondary part connected to the main part. The main part is a line, line segment, or strip-shaped body. The main part extends along direction B, and the length of the main part extending along direction B is greater than the length of the secondary part extending along other directions. In the following description, "A extends along direction B" refers to "the main body of A extends along direction B".

[0149] In an exemplary embodiment, the pixel driving circuit may include at least a storage capacitor and seven transistors. The seven transistors may include a first transistor T1 as a first initialization transistor, a second transistor T2 as a compensation transistor, a third transistor T3 as a driving transistor, a fourth transistor T4 as a data writing transistor, a fifth transistor T5 as a first light-emitting control transistor, a sixth transistor T6 as a second light-emitting control transistor, and a seventh transistor T7 as a second initialization transistor. The storage capacitor may include a first electrode and a second electrode stacked together. In an exemplary embodiment, all seven transistors may be low-temperature polysilicon transistors.

[0150] In an exemplary embodiment, the gate electrode of the first transistor T1 is connected to the second scan signal line 22, the first terminal of the first transistor T1 is connected to the first initial signal line 41, and the second terminal of the first transistor T1 is connected to the first terminal of the second transistor T2 and the first plate of the storage capacitor (which is also the gate electrode of the third transistor T3). The gate electrode of the second transistor T2 is connected to the first scan signal line 21, and the second terminal of the second transistor T2 is connected to the second terminal of the third transistor T3 and the first terminal of the sixth transistor T6. The gate electrode of the fourth transistor T4 is connected to the first scan signal line 21, the first terminal of the fourth transistor T4 is connected to the first data signal line 61 or the second data signal line 62, and the second terminal of the fourth transistor T4 is connected to the first terminal of the third transistor T3 and the second terminal of the fifth transistor T5. The gate electrode of the fifth transistor T5 is connected to the light emission signal line 23, and the first terminal of the fifth transistor T5 is connected to the first power supply line 71. The gate electrode of the sixth transistor T6 is connected to the light emission signal line 23, and the second terminal of the sixth transistor T6 is connected to the second terminal of the seventh transistor T7. The gate electrode of the seventh transistor T7 is connected to the second scan signal line 22, and the first electrode of the seventh transistor T7 is connected to the second initial signal line 42.

[0151] In an exemplary embodiment, in at least one circuit unit, the first scan signal line 21 may be disposed on the side opposite to the second direction Y of the storage capacitor (third transistor T3), the second scan signal line 22 may be disposed on the side of the first scan signal line 21 away from the storage capacitor, the first initial signal line 41 may be disposed on the side of the second scan signal line 22 away from the storage capacitor, the second initial signal line 42 may be disposed on the side of the first initial signal line 41 away from the storage capacitor, and the light emission signal line 23 may be disposed on the side of the storage capacitor in the second direction Y.

[0152] In an exemplary embodiment, the pixel driving circuits of some adjacent unit columns may be substantially identical, while the pixel driving circuits of another portion of adjacent unit columns may be mirror-symmetrical with respect to the column boundary line. The column center line may be a straight line located between two adjacent unit columns and extending along the second direction Y. For example, the pixel driving circuits of the Nth unit column and the (N+1)th unit column may be substantially identical, and the pixel driving circuits of the (N+2)th unit column and the (N+3)th unit column may be substantially identical. As another example, the pixel driving circuits of the (N+1)th unit column and the (N+2)th unit column may be mirror-symmetrical with respect to the column boundary line. In an exemplary embodiment, N may be a positive integer greater than 1.

[0153] In an exemplary embodiment, the driving structure layer may further include at least one first initial connection line 71. The shape of the first initial connection line 71 may be a straight line or a broken line extending along the second direction Y, and it may be disposed between some adjacent unit columns. The first initial connection line 71 may be connected to the first initial signal line 41 to form a mesh-like interconnected structure for transmitting the first initial signal on the display substrate.

[0154] In an exemplary embodiment, the first initial connection line 71 may be disposed between adjacent cell columns of the third type, that is, the first initial connection line 71 may be disposed between adjacent first data signal lines 61 and second data signal lines 62.

[0155] In an exemplary embodiment, the driving structure layer may further include at least one second initial connection line 72. The shape of the second initial connection line 72 may be a straight line or a broken line extending along the second direction Y, and it may be disposed between some adjacent unit columns. The second initial connection line 72 may be connected to the second initial signal line 42 to form a mesh-like interconnected structure for transmitting the second initial signal on the display substrate.

[0156] In an exemplary embodiment, the second initial connection line 72 may be disposed between adjacent cell columns of the third type, that is, the second initial connection line 72 may be disposed between adjacent second data signal lines 62 and first data signal lines 61.

[0157] As shown in Figure 9A, in an exemplary embodiment, the drive structure layer may further include at least one first horizontal connecting line 81, at least one second horizontal connecting line 82, at least one first vertical connecting line 91, at least one second vertical connecting line 92, at least one first power supply trace 110, and at least one second power supply trace 120. The shapes of the first horizontal connecting line 81, the second horizontal connecting line 82, and the first power supply trace 110 may be straight lines or broken lines extending along the first direction X, and the shapes of the first vertical connecting line 91, the second vertical connecting line 92, and the second power supply trace 120 may be straight lines or broken lines extending along the second direction Y.

[0158] In an exemplary embodiment, the first horizontal connecting line 81 is configured to connect to the first data signal line 61 and the first vertical connecting line 91 respectively, and the second horizontal connecting line 82 is configured to connect to the second data signal line 62 and the second vertical connecting line 92 respectively, forming a structure in which the data connecting lines are located in the display area. The first power trace 110 and the second power trace 120 are configured to be interconnected, forming a mesh-like interconnected structure for transmitting power signals.

[0159] In an exemplary embodiment, in the second direction Y, the first lateral connecting line 81 can be disposed in the Mth unit row, the second lateral connecting line 82 can be disposed in the M+1th unit row, the first power supply line 110 can be disposed in the Mth unit row and the M+1th unit row respectively, and the first lateral connecting line 81, the second lateral connecting line 82 and the first power supply line 110 can be disposed between the second initial signal line 42 of this unit row and the light emission signal line 23 of the previous unit row.

[0160] In an exemplary embodiment, in the first direction X, the first vertical connecting line 91 can be disposed between the first data signal line 61 of the N+1th unit column and the first data signal line 61 of the N+2th unit column, the second vertical connecting line 92 can be disposed between the second data signal line 62 of the N+3th unit column and the second data signal line 62 of the N+4th unit column, and the second power supply line 120 can be disposed between the first data signal lines 61 of the N+1th and N+2th unit columns and between the second data signal lines 62 of the N+3th and N+4th unit columns, respectively.

[0161] In an exemplary embodiment, four circuit units may be spaced between two adjacent first vertical connecting lines 91 in the first direction X, and a second vertical connecting line 92 may be provided between the two first vertical connecting lines 91. Four circuit units may be spaced between two adjacent second vertical connecting lines 92 in the first direction X, and a first vertical connecting line 91 may be provided between the two second vertical connecting lines 92.

[0162] In an exemplary embodiment, there may be two circuit units between adjacent first vertical connecting lines 91 and second vertical connecting lines 92 in the first direction X, and there may be two circuit units between adjacent second power supply lines 120 in the first direction X.

[0163] In an exemplary embodiment, the Mth unit row may include at least one second lateral connection line 82 and at least one first power supply line 110, and the M+1th unit row may include at least one first lateral connection line 81 and at least one first power supply line 110. A first break is provided between the first lateral connection line 81 and the first power supply line 110, and between the second lateral connection line 82 and the first power supply line 110. The first break is configured to achieve mutual insulation between the first lateral connection line 81 and the first power supply line 110, and mutual insulation between the second lateral connection line 82 and the first power supply line 110.

[0164] In an exemplary embodiment, at least one first vertical connecting line 91 and at least one second power line 120 may be included between the N+1th and N+2th unit columns, and at least one second vertical connecting line 92 and at least one second power line 120 may be included between the N+3th and N+4th unit columns. A second break is provided between the first vertical connecting line 91 and the second power line 120, and between the second vertical connecting line 92 and the second power line 120. The second break is configured to achieve mutual insulation between the second vertical connecting line 92 and the second power line 120, and mutual insulation between the second vertical connecting line 92 and the second power line 120.

[0165] In an exemplary embodiment, the orthographic projection of the first anode 130A on the substrate at least partially overlaps with the orthographic projections of at least two first data signal lines 61 or at least two second data signal lines 62 on the substrate, and the orthographic projection of the second anode 130B on the substrate at least partially overlaps with the orthographic projections of at least two first data signal lines 61 or at least two second data signal lines 62 on the substrate.

[0166] In an exemplary embodiment, the orthographic projection of the first anode 130A on the substrate at least partially overlaps with the orthographic projections of at least one first vertical connecting line 91 and at least two first data signal lines 61 on the substrate, and the two first data signal lines 61 may be symmetrically arranged relative to the first vertical connecting line 91. Alternatively, the orthographic projection of the first anode 130A on the substrate at least partially overlaps with the orthographic projections of at least one second vertical connecting line 92 and at least two second data signal lines 62 on the substrate, and the two second data signal lines 62 may be symmetrically arranged relative to the second vertical connecting line 92.

[0167] In an exemplary embodiment, the orthographic projection of the second anode 130B onto the substrate at least partially overlaps with the orthographic projections of at least one first vertical connecting line 91 and at least two first data signal lines 61 onto the substrate, and the two first data signal lines 61 may be symmetrically arranged relative to the first vertical connecting line 91. Alternatively, the orthographic projection of the second anode 130B onto the substrate at least partially overlaps with the orthographic projections of at least one second vertical connecting line 92 and at least two second data signal lines 62 onto the substrate, and the two second data signal lines 62 may be symmetrically arranged relative to the second vertical connecting line 92.

[0168] In an exemplary embodiment, the orthographic projection of the third anode 130C on the substrate at least partially overlaps with the orthographic projections of at least one first data signal line 61 and at least one second data signal line 62 on the substrate, and the orthographic projection of the fourth anode 130D on the substrate at least partially overlaps with the orthographic projections of at least one first data signal line 61 and at least one second data signal line 62 on the substrate.

[0169] In an exemplary embodiment, the orthographic projection of the third anode 130C onto the substrate at least partially overlaps with the orthographic projections of at least one first initial connection line 71, at least one first data signal line 61, and at least one second data signal line 62 onto the substrate, and the first data signal line 61 and the second data signal line 62 may be symmetrically arranged relative to the first initial connection line 71. Alternatively, the orthographic projection of the third anode 130C onto the substrate at least partially overlaps with the orthographic projections of at least one second initial connection line 72, at least one first data signal line 61, and at least one second data signal line 62 onto the substrate, and the first data signal line 61 and the second data signal line 62 may be symmetrically arranged relative to the second initial connection line 72.

[0170] In an exemplary embodiment, the orthographic projection of the fourth anode 130D onto the substrate at least partially overlaps with the orthographic projections of at least one first initial connection line 71, at least one first data signal line 61, and at least one second data signal line 62 onto the substrate, and the first data signal line 61 and the second data signal line 62 may be symmetrically arranged relative to the first initial connection line 71. Alternatively, the orthographic projection of the fourth anode 130D onto the substrate at least partially overlaps with the orthographic projections of at least one second initial connection line 72, at least one first data signal line 61, and at least one second data signal line 62 onto the substrate, and the first data signal line 61 and the second data signal line 62 may be symmetrically arranged relative to the second initial connection line 72.

[0171] As shown in Figure 9B, in an exemplary embodiment, the second power supply traces 120 can be spaced out in the second direction Y, that is, the second power supply traces 120 in multiple cell rows in a cell column are intermittently arranged.

[0172] In an exemplary embodiment, in the second direction Y, multiple second power traces 120 can be respectively disposed between adjacent first power traces 110, and the spaced second power traces 120 are interconnected through first power electrodes and second power electrodes in the third conductive layer to form a continuous trace extending along the second direction Y.

[0173] In an exemplary embodiment, the orthographic projection of the first anode 130A on the substrate at least partially overlaps with the orthographic projections of at least one second power supply trace 120 and at least two first data signal lines 61 on the substrate, and the two first data signal lines 61 may be symmetrically arranged relative to the second power supply trace 120. Alternatively, the orthographic projection of the first anode 130A on the substrate at least partially overlaps with the orthographic projections of at least one second power supply trace 120 and at least two second data signal lines 62 on the substrate, and the two second data signal lines 62 may be symmetrically arranged relative to the second power supply trace 120.

[0174] In an exemplary embodiment, the orthographic projection of the second anode 130B on the substrate at least partially overlaps with the orthographic projections of at least one second power supply trace 120 and at least two first data signal lines 61 on the substrate, and the two first data signal lines 61 may be symmetrically arranged relative to the second power supply trace 120. Alternatively, the orthographic projection of the second anode 130B on the substrate at least partially overlaps with the orthographic projections of at least one second power supply trace 120 and at least two second data signal lines 62 on the substrate, and the two second data signal lines 62 may be symmetrically arranged relative to the second power supply trace 120.

[0175] In an exemplary embodiment, in a direction perpendicular to the display substrate, the display substrate may include a first conductive layer disposed on a substrate, a second conductive layer disposed on the side of the first conductive layer away from the substrate, a third conductive layer disposed on the side of the second conductive layer away from the substrate, and a fourth conductive layer disposed on the side of the third conductive layer away from the substrate. The first horizontal connecting line 81, the second horizontal connecting line 82, and the first power trace 110 may be disposed in the third conductive layer, while the first vertical connecting line 91, the second vertical connecting line 92, and the second power trace 120 may be disposed in the fourth conductive layer.

[0176] In an exemplary embodiment, in a cell column (such as the Nth cell column), the second vertical connecting line 92, the second data signal line 62, the first power line 63, the first data signal line 61, and the first initial connecting line 71 can be arranged sequentially in the first direction X, or the second power line 120, the second data signal line 62, the first power line 63, the first data signal line 61, and the first initial connecting line 71 can be arranged sequentially in the first direction X.

[0177] In an exemplary embodiment, in another cell column (such as the N+1 cell column), the first initial connection line 71, the second data signal line 62, the first power line 63, the first data signal line 61, and the first vertical connection line 91 can be arranged sequentially in the first direction X, or the first initial connection line 71, the second data signal line 62, the first power line 63, the first data signal line 61, and the second power line 120 can be arranged sequentially in the first direction X.

[0178] In an exemplary embodiment, in another unit column (such as the N+2th unit column), the first vertical connecting line 91, the first data signal line 61, the first power line 63, the second data signal line 62, and the second initial connecting line 72 can be arranged sequentially in the first direction X, or the second power line 120, the first data signal line 61, the first power line 63, the second data signal line 62, and the second initial connecting line 72 can be arranged sequentially in the first direction X.

[0179] In an exemplary embodiment, in another cell column (such as the N+3 cell column), the second initial connection line 72, the first data signal line 61, the first power line 63, the second data signal line 62, and the second vertical connection line 92 can be arranged sequentially in the first direction X, or the second initial connection line 72, the first data signal line 61, the first power line 63, the second data signal line 62, and the second power trace 120 can be arranged sequentially in the first direction X.

[0180] The following description uses the fabrication process of a display substrate as an example. The "patterning process" described in this disclosure includes, for metallic, inorganic, or transparent conductive materials, processes such as depositing a film, coating with photoresist, mask exposure, development, etching, and photoresist stripping; for organic materials, it includes processes such as coating with organic materials, mask exposure, and development. Deposition can be performed using any one or more of sputtering, evaporation, and chemical vapor deposition; coating can be performed using any one or more of spraying, spin coating, and inkjet printing; etching can be performed using any one or more of dry etching and wet etching. This disclosure does not limit the methods used. A "thin film" refers to a thin film made of a certain material on a substrate using deposition, coating, or other processes. If the "thin film" does not require a patterning process during the entire fabrication process, it can also be called a "layer." If the "thin film" requires a patterning process during the entire fabrication process, it is called a "thin film" before the patterning process and a "layer" after the patterning process. The "layer" after the patterning process contains at least one "pattern." The phrase "A and B are arranged in the same layer" in this disclosure means that A and B are formed simultaneously through the same patterning process, and the "thickness" of the film layer is the dimension of the film layer in the direction perpendicular to the display substrate. In the exemplary embodiments of this disclosure, "the orthographic projection of B is within the range of the orthographic projection of A" or "the orthographic projection of A includes the orthographic projection of B" means that the boundary of the orthographic projection of B falls within the boundary range of the orthographic projection of A, or the boundary of the orthographic projection of A overlaps with the boundary of the orthographic projection of B.

[0181] In an exemplary embodiment, taking eight circuit units (row M to row M+1 and column N to column N+3) as an example, the fabrication process of the display substrate in this embodiment may include the following operations. Wherein, row M is the first unit row, and row M+1 is the second unit row.

[0182] (11) Forming a masking layer pattern. In an exemplary embodiment, forming a masking layer pattern may include: depositing a masking film on a substrate, patterning the masking film using a patterning process, and forming a masking layer pattern on the substrate, as shown in FIG10, which is a schematic diagram of the masking layer pattern formed in region A of FIG8. The masking layer pattern in region B of FIG8 is substantially the same as that in region A. In an exemplary embodiment, the masking layer may be referred to as the underlying metal (LS) layer.

[0183] In an exemplary embodiment, the shielding layer pattern of each circuit unit (including the first circuit unit and the second circuit unit, hereinafter the same) in the display substrate may include at least a first shielding electrode 121, a second shielding electrode 122, a third shielding electrode 123, a first shielding connecting strip 124, a second shielding connecting strip 125, and a third shielding connecting strip 126.

[0184] In an exemplary embodiment, the first blocking electrode 121 may be rectangular in shape, with chamfered or grooved corners. The first blocking electrode 121 may be located in the middle region of the circuit unit in the first direction X and the second direction Y. In an exemplary embodiment, the first blocking electrode 121 is configured to block the channel region of the third transistor T3.

[0185] In an exemplary embodiment, the second blocking electrode 122 can be shaped like an "n" and can be disposed on the side opposite to the second direction Y of the first blocking electrode 121. One end of the second blocking electrode 122 is connected to the first blocking electrode 121, and the other end of the second blocking electrode 122 is located on the side of the first direction X of the first blocking electrode 121 or on the side opposite to the first direction X. In an exemplary embodiment, the second blocking electrode 122 is configured to block the channel region of the second transistor T2.

[0186] In an exemplary embodiment, the third blocking electrode 123 can be shaped like an "n" and can be disposed on the side opposite to the second direction Y of the second blocking electrode 122. One end of the third blocking electrode 123 is connected to the second blocking electrode 122, and the other end of the third blocking electrode 123 is located on the side of the first direction X of the first blocking electrode 121 or on the side opposite to the first direction X. In an exemplary embodiment, the third blocking electrode 123 is configured to block the channel region of the first transistor T1.

[0187] In an exemplary embodiment, the shape of the first shielding connecting strip 124 can be a straight line or a broken line extending along the first direction X of the main body. The first shielding connecting strip 124 can be disposed on one side of the first shielding electrode 121 in the first direction X or on the opposite side of the first shielding electrode 121 in the first direction X. The first end of the first shielding connecting strip 124 is connected to the first shielding electrode 121 of this circuit unit, and the second end of the first shielding connecting strip 124 is connected to the first shielding electrode 121 of the adjacent circuit unit in the first direction X.

[0188] In an exemplary embodiment, in at least one circuit unit (including at least one first circuit unit or at least one second circuit unit, hereinafter the same), the first shielding electrode 121 and the first shielding connecting strip 124 can be an integral structure that is interconnected with each other.

[0189] In an exemplary embodiment, the shape of the second shielding connecting strip 125 can be a straight line or a broken line extending along the second direction Y of the main body portion. It can be disposed on one side of the first shielding electrode 121 in the second direction Y. The first end of the second shielding connecting strip 125 is connected to the first shielding electrode 121 of this circuit unit. After the second end of the second shielding connecting strip 125 extends along the second direction Y, it is connected to the third shielding connecting strip 126 of the adjacent circuit unit in the second direction Y.

[0190] In an exemplary embodiment, the shape of the third shielding connecting strip 126 can be a straight line or a broken line extending along the second direction Y of the main body. The third shielding connecting strip 126 can be disposed on the side opposite to the second direction Y of the third shielding electrode 123. The first end of the third shielding connecting strip 126 is connected to the third shielding electrode 123 of this circuit unit. After the second end of the third shielding connecting strip 126 extends along the opposite direction of the second direction Y, it is connected to the second shielding connecting strip 125 of the adjacent circuit unit in the second direction Y.

[0191] In an exemplary embodiment, in at least one circuit unit, the third shielding connecting strip 126, the third shielding electrode 123, the second shielding electrode 122, the first shielding electrode 121, and the second shielding connecting strip 125 can be connected in sequence and form an integral structure that is interconnected with each other.

[0192] In an exemplary embodiment, in at least one unit row (including at least one first unit row or at least one second unit row, hereinafter the same), the shielding layers in multiple circuit units can be connected sequentially and are an integral structure that is interconnected.

[0193] In an exemplary embodiment, in at least one unit column, the shielding layers in multiple circuit units can be connected sequentially and form an integrated structure that is interconnected.

[0194] In an exemplary embodiment, the shielding layer may extend to the border area or the bonding area and be connected to the power lead transmitting the first power signal. Since the shielding layers in multiple cell rows and multiple cell columns are interconnected as an integral structure, it can be ensured that the shielding layers in the display substrate have the same potential, which is beneficial to improving the uniformity of the panel, avoiding display defects in the display substrate, and ensuring the display effect of the display substrate.

[0195] In an exemplary embodiment, the positions and shapes of the occlusion layers of some adjacent cell columns may be substantially the same, and the occlusion layers of some adjacent cell columns may be mirror-symmetrical with respect to the column boundary line. For example, the positions and shapes of the occlusion layers of the Nth cell column and the (N+1)th cell column may be substantially the same, and the positions and shapes of the occlusion layers of the (N+2)th cell column and the (N+3)th cell column may be substantially the same. As another example, the occlusion layers of the (N+1)th cell column and the (N+2)th cell column may be mirror-symmetrical with respect to the column boundary line.

[0196] (12) Forming a semiconductor layer pattern. In an exemplary embodiment, forming a semiconductor layer pattern may include: depositing a first insulating film and a semiconductor film sequentially on a substrate on which the aforementioned pattern is formed, patterning the semiconductor film by a patterning process to form a first insulating layer covering the shielding layer, and a semiconductor layer pattern disposed on the first insulating layer, as shown in Figures 11A and 11B. Figure 11A is a schematic diagram of the semiconductor layer pattern formed in region A of Figure 8, and Figure 11B is a planar schematic diagram of the semiconductor layer in Figure 11A. The semiconductor layer pattern in region B of Figure 8 is substantially the same as that in region A.

[0197] In an exemplary embodiment, the semiconductor layer pattern of each circuit unit in the display substrate may include at least the first active layer 11 of the first transistor T1 to the seventh active layer 17 of the seventh transistor T7, and the first active layer 11 to the seventh active layer 17 are an integral structure interconnected with each other.

[0198] In an exemplary embodiment, in the second direction Y, the first active layer 11, the second active layer 12 and the fourth active layer 14 may be located on the opposite side of the third active layer 13 in the second direction Y, and the fifth active layer 15, the sixth active layer 16 and the seventh active layer 17 may be located on the side of the third active layer 13 in the second direction Y.

[0199] In an exemplary embodiment, the fourth active layer 14 in the first circuit unit may be disposed on one side of the second active layer 12 in the first direction X, and the fourth active layer 14 in the second circuit unit may be disposed on the opposite side of the second active layer 12 in the first direction X.

[0200] In an exemplary embodiment, the third active layer 13 can be shaped like an "Ω", the first active layer 11 can be shaped like an "n", the fourth active layer 14 and the seventh active layer 17 can be shaped like an "I", and the second active layer 12, the fifth active layer 15 and the sixth active layer 16 can be shaped like an "L".

[0201] In an exemplary embodiment, each of the first active layer 11 to the seventh active layer 17 may include a first region, a second region, and a channel region located between the first region and the second region. In an exemplary embodiment, the second region 11-2 of the first active layer and the first region 12-1 of the second active layer may be interconnected, and the second region 11-2 of the first active layer may serve as the first region 12-1 of the second active layer. The first region 13-1 of the third active layer, the second region 14-2 of the fourth active layer, and the second region 15-2 of the fifth active layer may be interconnected, and the first region 13-1 of the third active layer may simultaneously serve as both the second region 14-2 of the fourth active layer and the second region 15-2 of the fifth active layer. The second region 12-2 of the second active layer, the second region 13-2 of the third active layer, and the first region 16-1 of the sixth active layer may be interconnected, and the second region 12-2 of the second active layer may simultaneously serve as both the second region 13-2 of the third active layer and the first region 16-1 of the sixth active layer. The second region 16-2 of the sixth active layer and the second region 17-2 of the seventh active layer can be interconnected, and the second region 16-2 of the sixth active layer can serve as the second region 17-2 of the seventh active layer. The first region 11-1 of the first active layer, the first region 14-1 of the fourth active layer, the first region 15-1 of the fifth active layer, and the first region 17-1 of the seventh active layer can be set independently.

[0202] In an exemplary embodiment, the first region 17-1 of the seventh active layer of this circuit unit can be disposed in the circuit unit of the next unit row, and the first region 17-1 of the seventh active layer of the circuit unit of the previous unit row can be disposed in this circuit unit.

[0203] In an exemplary embodiment, the orthographic projection of the first active layer 11 on the substrate and the orthographic projection of the third shielding electrode 123 on the substrate at least partially overlap. The third shielding electrode 123 can serve as a shielding layer for the first transistor T1, shielding the channel region of the first transistor T1 and ensuring the electrical performance of the first transistor T1.

[0204] In an exemplary embodiment, the orthographic projection of the second active layer 12 on the substrate and the orthographic projection of the second shielding electrode 122 on the substrate at least partially overlap. The second shielding electrode 122 can serve as a shielding layer for the second transistor T2, shielding the channel region of the second transistor T2 and ensuring the electrical performance of the second transistor T2.

[0205] In an exemplary embodiment, the orthographic projection of the third active layer 13 on the substrate at least partially overlaps with the orthographic projection of the first shielding electrode 121 on the substrate. The first shielding electrode 121 can serve as a shielding layer for the third transistor T3, shielding the channel region of the third transistor T3 and ensuring the electrical performance of the third transistor T3.

[0206] In an exemplary embodiment, the orthographic projection of the channel region of the third active layer 13 onto the substrate is within the range of the orthographic projection of the first shielding electrode 121 onto the substrate.

[0207] In an exemplary embodiment, the semiconductor layers of some adjacent cell columns may have substantially the same position and shape, and the semiconductor layers of some adjacent cell columns may be mirror-symmetrical with respect to the column boundary line. For example, the semiconductor layers of the Nth cell column and the (N+1)th cell column may have substantially the same position and shape, and the semiconductor layers of the (N+2)th cell column and the (N+3)th cell column may have substantially the same position and shape. As another example, the semiconductor layers of the (N+1)th cell column and the (N+2)th cell column may be mirror-symmetrical with respect to the column boundary line.

[0208] In an exemplary embodiment, the semiconductor layer may be polycrystalline silicon (p-Si), i.e., the first transistor T1 to the seventh transistor T7 are LTPS transistors. In an exemplary embodiment, patterning the semiconductor thin film using a patterning process may include: first forming an amorphous silicon (a-Si) thin film on a first insulating film; performing a hydrogen removal treatment on the amorphous silicon thin film; and then performing a crystallization treatment on the dehydrogenated amorphous silicon thin film to form a polycrystalline silicon thin film. Subsequently, the polycrystalline silicon thin film is patterned to form a semiconductor layer pattern.

[0209] (13) Forming a first conductive layer pattern. In an exemplary embodiment, forming a first conductive layer pattern may include: sequentially depositing a second insulating film and a first conductive film on a substrate on which the aforementioned pattern is formed; patterning the first conductive film using a patterning process to form a second insulating layer covering the semiconductor layer pattern; and a first conductive layer pattern disposed on the second insulating layer, as shown in Figures 12A and 12B. Figure 12A is a schematic diagram of the formation of the first conductive layer pattern in region A of Figure 8, and Figure 12B is a planar schematic diagram of the first conductive layer in Figure 12A. The first conductive layer pattern in region B of Figure 8 is substantially the same as that in region A. In an exemplary embodiment, the first conductive layer may be referred to as a first gate metal (GATE1) layer.

[0210] In an exemplary embodiment, the first conductive layer pattern of each circuit unit in the display substrate includes at least: a first scan signal line 21, a second scan signal line 22, a light emission signal line 23, and a first electrode 31 of a storage capacitor.

[0211] In an exemplary embodiment, the first electrode 31 can be rectangular in shape, with chamfered or grooved corners. The orthographic projection of the first electrode 31 onto the substrate at least partially overlaps with the orthographic projection of the third active layer of the third transistor T3 onto the substrate. In an exemplary embodiment, the first electrode 31 can simultaneously serve as an electrode of a storage capacitor and a gate electrode of the third transistor T3.

[0212] In an exemplary embodiment, the orthographic projection of the first electrode 31 onto the substrate may be within the range of the orthographic projection of the first shielding electrode 121 onto the substrate.

[0213] In an exemplary embodiment, the shape of the first scan signal line 21 can be a straight line or a broken line extending along the first direction X of the main body, and can be located on the side opposite to the second direction Y of the first electrode plate 31. The region where the first scan signal line 21 overlaps with the fourth active layer can serve as the gate electrode of the fourth transistor T4, thus enabling the first scan signal line 21 to control the conduction or disconnection of the fourth transistor T4.

[0214] In an exemplary embodiment, a first gate block 21-1 may be disposed on the first scan signal line 21. The shape of the first gate block 21-1 may be a strip extending along the second direction Y. It may be disposed on the side of the first scan signal line 21 away from the first electrode plate 31 and connected to the first scan signal line 21. The region where the first scan signal line 21 and the first gate block 21-1 overlap with the second active layer serves as the gate electrode of the second transistor T2 with a dual-gate structure, thus enabling the first scan signal line 21 to control the conduction or disconnection of the second transistor T2.

[0215] In an exemplary embodiment, the shape of the second scan signal line 22 can be a straight line or a broken line extending along the first direction X, and it can be disposed on the side of the first scan signal line 21 away from the first electrode plate 31. The region where the second scan signal line 22 overlaps with the first active layer of this circuit unit can serve as the gate electrode of the first transistor T1 of this circuit unit, thus enabling the second scan signal line 22 to control the conduction or disconnection of the first transistor T1 of this circuit unit. The region where the second scan signal line 22 overlaps with the seventh active layer of the circuit unit in the previous unit row can serve as the gate electrode of the seventh transistor T7 of the circuit unit in the previous unit row, thus enabling the second scan signal line 22 to control the conduction or disconnection of the seventh transistor T7 of the circuit unit in the previous unit row.

[0216] In an exemplary embodiment, the first transistor T1 in this unit row and the seventh transistor T7 in the previous unit row are controlled by the same second scan signal line in this unit row. In an exemplary embodiment, the second scan signal line in this unit row can be equivalent to the first scan signal line in the previous unit row. By setting the second scan signal line in this unit row to simultaneously control the first transistor T1 in this unit row and the seventh transistor T7 in the previous unit row, this disclosure can effectively reduce the number of scan signal lines, which is beneficial for reducing the size of the circuit unit and improving the display resolution.

[0217] In an exemplary embodiment, the shape of the light-emitting signal line 23 can be a straight line or a broken line extending along the first direction X of the main body. The light-emitting signal line 23 can be located on one side of the first electrode plate 31 in the second direction Y. The area where the light-emitting signal line 23 overlaps with the fifth active layer can serve as the gate electrode of the fifth transistor T5. The area where the light-emitting signal line 23 overlaps with the sixth active layer can serve as the gate electrode of the sixth transistor T6. Thus, the light-emitting signal line 23 can control the conduction or disconnection of the fifth transistor T5 and the sixth transistor T6.

[0218] In an exemplary embodiment, the positions and shapes of the first conductive layers in some adjacent cell columns may be substantially the same, and the first conductive layers in some adjacent cell columns may be mirror-symmetrical with respect to the column boundary line. For example, the positions and shapes of the first conductive layers in the Nth cell column and the N+1th cell column may be substantially the same, and the positions and shapes of the first conductive layers in the N+2th cell column and the N+3th cell column may be substantially the same. As another example, the first conductive layers in the N+1th cell column and the N+2th cell column may be mirror-symmetrical with respect to the column boundary line.

[0219] In an exemplary embodiment, after the first conductive layer pattern is formed, the first conductive layer can be used as a shield to conduct the semiconductor layer. The semiconductor layer in the region shielded by the first conductive layer forms the channel region of the first transistor T1 to the seventh transistor T7. The semiconductor layer in the region not shielded by the first conductive layer is conducted, that is, the first region and the second region of the first transistor T1 to the seventh transistor T7 are both conducted.

[0220] (14) Forming a second conductive layer pattern. In an exemplary embodiment, forming a second conductive layer pattern may include: sequentially depositing a third insulating film and a second conductive film on a substrate on which the aforementioned pattern is formed; patterning the second conductive film using a patterning process to form a third insulating layer covering the first conductive layer; and a second conductive layer pattern disposed on the third insulating layer, as shown in Figures 13A and 13B. Figure 13A is a schematic diagram of the second conductive layer pattern formed in region A of Figure 8, and Figure 13B is a planar schematic diagram of the second conductive layer in Figure 13A. The second conductive layer pattern in region B of Figure 8 is substantially the same as that in region A. In an exemplary embodiment, the second conductive layer may be referred to as a second gate metal (GATE2) layer.

[0221] In an exemplary embodiment, the second conductive layer pattern of each circuit unit in the display substrate includes at least: a second electrode 32 of a storage capacitor, a first initial signal line 41, a second initial signal line 42, a first shielding electrode 43, and a second shielding electrode 44.

[0222] In an exemplary embodiment, the outline of the second electrode plate 32 of the storage capacitor can be rectangular, and the corners of the rectangle can be chamfered or grooved. The orthographic projection of the second electrode plate 32 on the substrate at least partially overlaps with the orthographic projection of the first electrode plate 31 on the substrate. The second electrode plate 32 can serve as another electrode plate of the storage capacitor, and the first electrode plate 31 and the second electrode plate 32 constitute the storage capacitor of the pixel driving circuit.

[0223] In an exemplary embodiment, the second electrode plate 32 may be provided with a board-level connecting strip 33. The shape of the board-level connecting strip 33 may be a strip extending along the first direction X. The board-level connecting strip 33 may be disposed on one side of the second electrode plate 32 in the first direction X or on the opposite side of the first direction X. The first end of the board-level connecting strip 33 is connected to the second electrode plate 32 in this circuit unit, and the second end of the board-level connecting strip 33 is connected to the second electrode plate 32 in the adjacent circuit unit in the first direction X. Since the second electrode plate 32 in each circuit unit is connected to the subsequently formed first power line, by connecting the second electrode plates 32 of adjacent circuit units to each other, the second electrode plate 32 and the board-level connecting strip 33 can be multiplexed as power signal lines. This can ensure that multiple second electrode plates in a unit row have the same potential, which is beneficial to improving the uniformity of the panel, avoiding display defects of the display substrate, and ensuring the display effect of the display substrate.

[0224] In an exemplary embodiment, the second electrode plate 32 and the board-level connecting strip 33 in a plurality of circuit units in a unit row can be an integral structure that is interconnected.

[0225] In an exemplary embodiment, the second electrode plate 32 is provided with an opening 34. The opening 34 may be rectangular in shape and may be located in the central region of the second electrode plate 32, thereby forming an annular structure. The opening 34 exposes a third insulating layer covering the first electrode plate 31, and the orthographic projection of the first electrode plate 31 onto the substrate includes the orthographic projection of the opening 34 onto the substrate. In an exemplary embodiment, the opening 34 is configured to accommodate a subsequently formed seventh via, which is located within the opening 34 and exposes the first electrode plate 31, allowing a subsequently formed first connecting electrode to be connected to the first electrode plate 31.

[0226] In an exemplary embodiment, the shape of the first initial signal line 41 can be a line shape in which the main body extends along the first direction X, and it can be located on the side of the second scan signal line 22 away from the second electrode plate 32. Each circuit unit may have a first initial connection block 41-1 on the first initial signal line 41. The first initial connection block 41-1 can be block-shaped, can be located on the side of the first initial signal line 41 away from the second electrode plate 32, and is connected to the first initial signal line 41. The first initial connection block 41-1 is configured to be connected to the first region of the first active layer through a subsequently formed sixth connection electrode.

[0227] In an exemplary embodiment, in at least one circuit unit, the first initial signal line 41 and the first initial connection block 41-1 can be an integral structure that is interconnected.

[0228] In an exemplary embodiment, the shape of the second initial signal line 42 can be a line shape in which the main body extends along the first direction X, and it can be located on the side of the first initial signal line 41 away from the second electrode plate 32. A second initial connection block 42-1 can be provided on the second initial signal line 42 of each circuit unit. The second initial connection block 42-1 can be block-shaped, can be located on the side of the second initial signal line 42 close to the second electrode plate 32, and is connected to the second initial signal line 42. The second initial connection block 42-1 is configured to be connected to the first region of the seventh active layer through a subsequently formed seventh connection electrode.

[0229] In an exemplary embodiment, in at least one circuit unit, the second initial signal line 42 and the second initial connection block 42-1 can be an integral structure that is interconnected.

[0230] In an exemplary embodiment, the first shielding electrode 43 can be block-shaped and can be disposed on the side of the first initial signal line 41 away from the second electrode plate 32, and connected to the first initial signal line 41. The orthographic projection of the first shielding electrode 43 on the substrate at least partially overlaps with the orthographic projection of the first active layer (the node between the two gate electrodes) of the first transistor T1 on the substrate. In an exemplary embodiment, since the first shielding electrode 43 is connected to the first initial signal line 41, the first shielding electrode 43 with a constant voltage can effectively shield the influence of data voltage jumps on the first transistor T1, avoid the data voltage jumps affecting the normal operation of the pixel driving circuit, and improve the display effect.

[0231] In an exemplary embodiment, in at least one circuit unit, the first initial signal line 41, the first initial connection block 41-1, and the first shielding electrode 43 can be an integral structure that is interconnected.

[0232] In an exemplary embodiment, the second shielding electrode 44 can be a strip extending along the first direction X, and can be located between the first scan signal line 21 and the second scan signal line 22. The orthographic projection of the second shielding electrode 44 on the substrate at least partially overlaps with the orthographic projection of the second active layer (the node between the two gate electrodes) of the second transistor T2 on the substrate. In an exemplary embodiment, since the second shielding electrode 44 is connected to the second electrode plate 32 through a subsequently formed fifth connection electrode, the second shielding electrode 44 with a constant voltage can effectively shield the influence of data voltage jumps on the second transistor T2, preventing data voltage jumps from affecting the normal operation of the pixel driving circuit and improving the display effect.

[0233] In an exemplary embodiment, the positions and shapes of the second conductive layers in some adjacent unit columns may be substantially the same, and the second conductive layers in some adjacent unit columns may be mirror-symmetrical with respect to the column boundary line. For example, the positions and shapes of the second conductive layers in the Nth unit column and the N+1th unit column may be substantially the same, and the positions and shapes of the second conductive layers in the N+2th unit column and the N+3th unit column may be substantially the same. As another example, the second conductive layers in the N+1th unit column and the N+2th unit column may be mirror-symmetrical with respect to the column boundary line.

[0234] (15) Forming a fourth insulating layer pattern. In an exemplary embodiment, forming a fourth insulating layer pattern may include: depositing a fourth insulating film on a substrate on which the aforementioned pattern is formed, and patterning the fourth insulating film using a patterning process to form a fourth insulating layer covering the second conductive layer. The fourth insulating layer has a plurality of vias. As shown in FIG14, which is a schematic diagram of the fourth insulating layer pattern formed in region A of FIG8, the fourth insulating layer pattern in region B of FIG8 is substantially the same as that in region A.

[0235] In an exemplary embodiment, the plurality of vias of each circuit unit in the display substrate include at least: a first via V1, a second via V2, a third via V3, a fourth via V4, a fifth via V5, a sixth via V6, a seventh via V7, an eighth via V8, a ninth via V9, a tenth via V10, an eleventh via V11, and a twelfth via V12.

[0236] In an exemplary embodiment, the orthographic projection of the first via V1 onto the substrate is within the range of the orthographic projection of the first region of the first active layer onto the substrate. The fourth, third, and second insulating layers within the first via V1 are etched away, exposing the surface of the first region of the first active layer. The first via V1 is configured to connect the via to the first region of the first active layer via, thereby enabling the subsequently formed sixth connection electrode to be connected.

[0237] In an exemplary embodiment, the orthographic projection of the second via V2 onto the substrate is located within the range of the orthographic projection of the second region of the first active layer (which is also the first region of the second active layer) onto the substrate. The fourth insulating layer, the third insulating layer, and the second insulating layer within the second via V2 are etched away, exposing the surface of the second region of the first active layer (which is also the first region of the second active layer). The second via V2 is configured to allow a subsequently formed first connection electrode to be connected to the second region of the first active layer (which is also the first region of the second active layer) through the via.

[0238] In an exemplary embodiment, the orthographic projection of the third via V3 onto the substrate is within the range of the orthographic projection of the first region of the fourth active layer onto the substrate. The fourth insulating layer, the third insulating layer, and the second insulating layer within the third via V3 are etched away, exposing the surface of the first region of the fourth active layer. The third via V3 is configured to allow a subsequently formed second connection electrode to be connected to the first region of the fourth active layer through the via.

[0239] In an exemplary embodiment, the orthographic projection of the fourth via V4 onto the substrate is within the range of the orthographic projection of the first region of the fifth active layer onto the substrate. The fourth insulating layer, the third insulating layer, and the second insulating layer within the fourth via V4 are etched away, exposing the surface of the first region of the fifth active layer. The fourth via V4 is configured to allow a subsequently formed third connection electrode to be connected to the first region of the fifth active layer through the via.

[0240] In an exemplary embodiment, the orthographic projection of the fifth via V5 onto the substrate lies within the orthographic projection of the second region of the sixth active layer (which is also the second region of the seventh active layer) onto the substrate. The fourth, third, and second insulating layers within the fifth via V5 are etched away, exposing the surface of the second region of the sixth active layer (which is also the second region of the seventh active layer). The fifth via V5 is configured to allow a subsequently formed fourth connection electrode to be connected to the second region of the sixth active layer (which is also the second region of the seventh active layer) through the via.

[0241] In an exemplary embodiment, the orthographic projection of the sixth via V6 onto the substrate is within the range of the orthographic projection of the first region of the seventh active layer onto the substrate. The fourth, third, and second insulating layers within the sixth via V6 are etched away, exposing the surface of the first region of the seventh active layer. The sixth via V6 is configured to allow the subsequently formed seventh connection electrode to be connected to the first region of the seventh active layer through the via.

[0242] In an exemplary embodiment, the orthographic projection of the seventh via V7 onto the substrate is within the range of the orthographic projection of the opening 34 onto the substrate. The fourth and third insulating layers within the seventh via V7 are etched away, exposing the surface of the first electrode plate 31. The seventh via V7 is configured to allow the subsequently formed first connection electrode to be connected to the first electrode plate 31 through the via.

[0243] In an exemplary embodiment, the orthographic projection of the eighth via V8 onto the substrate is within the range of the orthographic projection of the second electrode plate 32 onto the substrate. The fourth insulating layer within the eighth via V8 is etched away, exposing the surface of the second electrode plate 32. The eighth via V8 is configured to allow the subsequently formed third connection electrode to be connected to the second electrode plate 32 through the via.

[0244] In an exemplary embodiment, the orthographic projection of the ninth via V9 on the substrate is within the range of the orthographic projection of the first initial connection block 41-1 on the substrate of the first initial signal line 41. The fourth insulating layer in the ninth via V9 is etched away, exposing the surface of the first initial connection block 41-1. The ninth via V9 is configured to allow the subsequently formed sixth connection electrode to be connected to the first initial connection block 41-1 through the via.

[0245] In an exemplary embodiment, the orthographic projection of the tenth via V10 on the substrate is within the range of the orthographic projection of the second initial connection block 42-1 on the substrate of the second initial signal line 42. The fourth insulating layer in the tenth via V10 is etched away, exposing the surface of the second initial connection block 42-1. The tenth via V10 is configured to allow the subsequently formed seventh connection electrode to be connected to the second initial connection block 42-1 through the via.

[0246] In an exemplary embodiment, the orthographic projection of the eleventh via V11 on the substrate is within the range of the orthographic projection of the second shielding electrode 44 on the substrate. The fourth insulating layer in the eleventh via V11 is etched away, exposing the surface of the second shielding electrode 44. The eleventh via V11 is configured to allow the subsequently formed fifth connection electrode to be connected to the second shielding electrode 44 through the via.

[0247] In an exemplary embodiment, the orthographic projection of the twelfth via V12 on the substrate is within the range of the orthographic projection of the board-level connector 33 on the substrate. The fourth insulating layer within the twelfth via V12 is etched away, exposing the surface of the board-level connector 33. The twelfth via V12 is configured to allow the subsequently formed fifth connection electrode to be connected to the board-level connector 33 through the via.

[0248] (16) Forming a third conductive layer pattern. In an exemplary embodiment, forming the third conductive layer may include: depositing a third conductive film on the substrate on which the aforementioned pattern is formed, patterning the third conductive film using a patterning process, and forming a third conductive layer disposed on the fourth insulating layer, as shown in Figures 15A, 15B, 15C, and 15D. Figure 15A is a schematic diagram of the third conductive layer pattern formed in region A of Figure 8, Figure 15B is a planar schematic diagram of the third conductive layer in Figure 15A, Figure 15C is a schematic diagram of the third conductive layer pattern formed in region B of Figure 8, and Figure 15D is a planar schematic diagram of the third conductive layer in Figure 15C. In an exemplary embodiment, the third conductive layer may be referred to as the first source / drain metal (SD1) layer.

[0249] In an exemplary embodiment, the third conductive layer of each circuit unit in the display substrate includes at least: a first connecting electrode 51, a second connecting electrode 52, a third connecting electrode 53, a fourth connecting electrode 54, a fifth connecting electrode 55, a sixth connecting electrode 56, and a seventh connecting electrode 57.

[0250] In an exemplary embodiment, the first connecting electrode 51 can be a strip extending along the second direction Y. The first end of the first connecting electrode 51 is connected to the second region of the first active layer (which is also the first region of the second active layer) through the second via V2, and the second end of the first connecting electrode 51 is connected to the first electrode plate 31 through the seventh via V7. In an exemplary embodiment, since the first electrode plate 31 also serves as the gate electrode of the third transistor T3, the first connecting electrode 51 achieves the same potential for the second electrode of the first transistor T1, the first electrode of the second transistor T2, the gate electrode of the third transistor T3, and the first electrode plate 31, forming the first node N1 of the pixel driving circuit.

[0251] In an exemplary embodiment, the second connection electrode 52 may be block-shaped (e.g., rectangular), and the second connection electrode 52 is connected to the first region of the fourth active layer through a third via V3. In an exemplary embodiment, the second connection electrode 52 is configured to connect to a subsequently formed data signal line.

[0252] In an exemplary embodiment, the second connection electrode 52 can serve as the first electrode of the fourth transistor T4. Since the fourth active layer 14 in the first circuit unit is disposed on one side of the second active layer 12 in the first direction X, the first electrode of the fourth transistor T4 in the first circuit unit is disposed on one side of the second transistor T2 in the first direction X. Since the fourth active layer 14 in the second circuit unit is disposed on the opposite side of the second active layer 12 in the first direction X, the first electrode of the fourth transistor T4 in the second circuit unit is disposed on the opposite side of the second transistor T2 in the first direction X.

[0253] In an exemplary embodiment, the third connection electrode 53 can be a strip extending along the second direction Y. The first end of the third connection electrode 53 is connected to the first region of the fifth active layer via a fourth via V4, and the second end of the third connection electrode 53 is connected to the second electrode plate 32 via an eighth via V8, thus ensuring that the first electrode of the fifth transistor T5 and the second electrode plate 32 of the storage capacitor have the same potential. In an exemplary embodiment, the third connection electrode 53 is configured to connect to a subsequently formed first power line, thereby enabling the first power line to write a first power signal to the first electrode of the fifth transistor T5 and the second electrode plate 32 of the storage capacitor.

[0254] In an exemplary embodiment, the fourth connection electrode 54 may be block-shaped (e.g., rectangular), and is connected to the second region of the sixth active layer (which is also the second region of the seventh active layer) via a fifth via V5. In an exemplary embodiment, the fourth connection electrode 545 is configured to connect to a subsequently formed anode connection electrode.

[0255] In an exemplary embodiment, the fifth connecting electrode 55 can be a strip extending along the second direction Y. The first end of the fifth connecting electrode 55 is connected to the second shielding electrode 44 through the eleventh via V11, and the second end of the fifth connecting electrode 55 is connected to the plate-level connecting strip 33 through the twelfth via V12. Since the plate-level connecting strip 33 is connected to the second electrode plate 32, the second shielding electrode 44 and the second electrode plate 32 of the storage capacitor have the same potential.

[0256] In an exemplary embodiment, the sixth connection electrode 56 can be L-shaped. The first end of the sixth connection electrode 56 is connected to the first region of the first active layer through the first via V1, and the second end of the sixth connection electrode 56 is connected to the first initial connection block 41-1 through the ninth via V9. Since the first initial connection block 41-1 is connected to the first initial signal line 41, the first initial signal line 41 writes the first initial signal into the first electrode of the first transistor T1.

[0257] In an exemplary embodiment, the seventh connection electrode 57 can be a strip extending along the second direction Y. The first end of the seventh connection electrode 57 is connected to the first region of the seventh active layer through the sixth via V6, and the second end of the seventh connection electrode 57 is connected to the second initial connection block 42-1 through the tenth via V10. Since the second initial connection block 42-1 is connected to the second initial signal line 42, the second initial signal line 42 writes the second initial signal into the first electrode of the seventh transistor T7.

[0258] In an exemplary embodiment, the third conductive layer of at least one circuit unit may further include an eighth connection electrode 58 and an eighth connection block 58-1.

[0259] In an exemplary embodiment, the eighth connecting electrode 58 may be L-shaped. The first end of the eighth connecting electrode 58 is connected to the sixth connecting electrode 56, and the second end of the eighth connecting electrode 58 extends away from the sixth connecting electrode 56 and connects to the eighth connecting block 58-1. In an exemplary embodiment, the eighth connecting block 58-1 is configured to connect to a subsequently formed first initial connecting line.

[0260] In an exemplary embodiment, in at least one circuit unit, the sixth connecting electrode 56, the eighth connecting electrode 58, and the eighth connecting block 58-1 can be an integral structure that is interconnected.

[0261] In an exemplary embodiment, the eighth connecting electrode 58 and the eighth connecting block 58-1 may be disposed in a portion of the first circuit unit in the Mth unit row, and the eighth connecting block 58-1 may be located between two adjacent first circuit units in the first direction X. For example, the eighth connecting electrode 58 and the eighth connecting block 58-1 may be disposed in the circuit unit of the Mth unit row and the N+1th unit column, and the eighth connecting block 58-1 may be located between the Nth unit column and the N+1th unit column.

[0262] In an exemplary embodiment, the eighth connecting electrode 58 and the eighth connecting block 58-1 may be disposed in a portion of the second circuit unit in the M+1th unit row, and the eighth connecting block 58-1 may be located between two adjacent second circuit units in the first direction X. For example, the eighth connecting electrode 58 and the eighth connecting block 58-1 may be disposed in the circuit unit in the M+1th unit row and the Nth unit column, and the eighth connecting block 58-1 may be located between the Nth unit column and the N+1th unit column.

[0263] In an exemplary embodiment, the eighth connecting blocks 58-1 in multiple cell rows may be located on the same straight line extending along the second direction Y. For example, the eighth connecting blocks 58-1 in multiple cell rows may be located between the Nth cell column and the N+1th cell column, and the multiple eighth connecting blocks 58-1 may be located on the same column boundary line.

[0264] In an exemplary embodiment, the third conductive layer of at least one circuit unit may further include a ninth connecting electrode 59 and a ninth connecting block 59-1.

[0265] In an exemplary embodiment, the ninth connecting electrode 59 may be a strip extending along the first direction X, and may span two adjacent circuit units in a portion of the first direction X. The first end of the ninth connecting electrode 59 is connected to the seventh connecting electrode 57 in one circuit unit, and the second end of the ninth connecting electrode 59 is connected to the seventh connecting electrode 57 in another circuit unit. A ninth connecting block 59-1 is disposed between the first and second ends of the ninth connecting electrode 59 and connected to the ninth connecting electrode 59. The ninth connecting block 59-1 is configured to connect to a subsequently formed second initial connecting line.

[0266] In an exemplary embodiment, in at least two adjacent first circuit units or at least two adjacent second circuit units, the seventh connecting electrode 57, the ninth connecting electrode 59, and the ninth connecting block 59-1 can be an integral structure that is interconnected.

[0267] In an exemplary embodiment, the ninth connecting electrode 59 and the ninth connecting block 59-1 can be disposed in the second circuit unit of the Mth unit row, and the ninth connecting block 59-1 can be located between two adjacent second circuit units in the first direction X. For example, in the Mth unit row, the ninth connecting electrode 59 and the ninth connecting block 59-1 can be disposed in the circuit units of the N+2th and N+3th unit columns, and the ninth connecting block 59-1 can be located between the N+2th and N+3th unit columns.

[0268] In an exemplary embodiment, the ninth connecting electrode 59 and the ninth connecting block 59-1 can be disposed in the first circuit unit of the M+1th unit row, and the ninth connecting block 59-1 can be located between two adjacent first circuit units in the first direction X. For example, in the M+1th unit row, the ninth connecting electrode 59 and the ninth connecting block 59-1 can be disposed in the circuit units of the N+2th and N+3th unit columns, and the ninth connecting block 59-1 can be located between the N+2th and N+3th unit columns.

[0269] In an exemplary embodiment, the ninth connecting block 59-1 in multiple cell rows may be located on the same straight line extending along the second direction Y. For example, the ninth connecting block 59-1 in multiple cell rows may be located between the N+2th cell column and the N+3rd cell column, and the multiple ninth connecting blocks 59-1 may be located on the same column boundary line.

[0270] As shown in Figures 15A and 15B, in an exemplary embodiment, the third conductive layer may further include at least one first lateral connection line 81, at least one second lateral connection line 82, at least one first data electrode 83, at least one second data electrode 84, at least one dummy electrode 85, and at least one first power supply trace 110.

[0271] In an exemplary embodiment, the first horizontal connecting line 81 and the second horizontal connecting line 82 can be a straight line or a broken line extending along the first direction X. The first horizontal connecting line 81 can be disposed in one of the first and second unit rows, and the second horizontal connecting line 82 can be disposed in the other unit row. The first horizontal connecting line 81 and the second horizontal connecting line 82 can be alternately disposed in the second direction Y. For example, the first horizontal connecting line 81 can be disposed in the Mth unit row, and the second horizontal connecting line 82 can be disposed in the M+1th unit row.

[0272] In an exemplary embodiment, the shape of the first power trace 110 can be a straight line or a broken line extending along the first direction X, and the first power trace 110 can be respectively arranged in the first cell row and the second cell row. For example, the first power trace 110 can be respectively arranged in the Mth cell row and the M+1th cell row.

[0273] In an exemplary embodiment, the first lateral connection line 81, the second lateral connection line 82, and the first power supply line 110 can be respectively disposed between the second initial signal line 42 of the current cell row and the light emission signal line 23 of the previous cell row, thus being able to be far away from the third transistor T3 and the storage capacitor.

[0274] In an exemplary embodiment, a first break K1 may be provided between the first horizontal connecting line 81 and the first power supply line 110 in the same unit row, and a first break K1 may be provided between the second horizontal connecting line 82 and the first power supply line 110 in the same unit row. The first break K1 is configured to achieve mutual insulation between the first horizontal connecting line 81 and the first power supply line 110, and mutual insulation between the second horizontal connecting line 82 and the first power supply line 110.

[0275] In an exemplary embodiment, the first data electrode 83 and the second data electrode 84 can be block-shaped (e.g., rectangular). In the first direction X, the first data electrode 83 and the second data electrode 84 can be disposed between partially adjacent circuit units. In the second direction Y, the first data electrode 83 can be disposed on both sides of the first transverse connecting line 81 in the second direction Y, and the second data electrode 84 can be disposed on both sides of the second transverse connecting line 82 in the second direction Y. The two first data electrodes 83 located on both sides of the first transverse connecting line 81 in the second direction Y can be connected to the first transverse connecting line 81 respectively via a first data connecting block 83-1, and the two second data electrodes 84 located on both sides of the second transverse connecting line 82 in the second direction Y can be connected to the second transverse connecting line 82 respectively via a second data connecting block 84-1. The first data electrode 83 is configured to connect to a subsequently formed first vertical connecting line, and the second data electrode 84 is configured to connect to a subsequently formed second vertical connecting line.

[0276] In an exemplary embodiment, the first data connection block 83-1 and the second data connection block 84-1 can be strip-shaped extending along the second direction Y. A first end of the first data connection block 83-1 is connected to a first data electrode 83, and a second end of the first data connection block 83-1 is connected to a first lateral connecting line 81. A first end of the second data connection block 84-1 is connected to a second data electrode 84, and a second end of the second data connection block 84-1 is connected to a second lateral connecting line 82.

[0277] In an exemplary embodiment, the two first data electrodes 83 located on both sides of the first transverse connecting line 81 in the second direction Y can be symmetrically arranged with respect to the first transverse connecting line 81, and the two second data electrodes 84 located on both sides of the second transverse connecting line 82 in the second direction Y can be symmetrically arranged with respect to the second transverse connecting line 82.

[0278] In an exemplary embodiment, in at least one unit row, the first lateral connecting line 81, the two first data electrodes 83, and the two first data connection blocks 83-1 can be an integral structure interconnected with each other. In at least one unit row, the second lateral connecting line 82, the two second data electrodes 84, and the two second data connection blocks 84-1 can be an integral structure interconnected with each other.

[0279] In an exemplary embodiment, the first data electrode 83 and the first data connection block 83-1 may be disposed between the N+3rd and N+4th unit columns, and the second data electrode 84 and the second data connection block 84-1 may be disposed between the N+1th and N+2th unit columns.

[0280] In an exemplary embodiment, the dummy electrode 85 can be block-shaped (e.g., rectangular). In the first direction X, the dummy electrode 85 can be disposed between partially adjacent circuit units. In the second direction Y, the dummy electrode 85 can be disposed on both sides of the first horizontal connecting line 81 or the second horizontal connecting line 82 in the second direction Y, and the dummy electrode 85 is configured to connect to the subsequently formed first vertical connecting line, second vertical connecting line, or second power supply trace.

[0281] In an exemplary embodiment, the dummy electrodes 85 located on both sides of the first transverse connecting line 81 in the second direction Y can be symmetrically arranged with respect to the first transverse connecting line 81, and the dummy electrodes 85 located on both sides of the second transverse connecting line 82 in the second direction Y can be symmetrically arranged with respect to the second transverse connecting line 82.

[0282] In an exemplary embodiment, the position, shape, and connection structure of the dummy electrode 85 can be substantially the same as those of the first data electrode 83 or the second data electrode 84. The difference is that the first data electrode 83 is connected to the first lateral connection line 81 via the first data connection block 83-1, and the second data electrode 84 is connected to the second lateral connection line 82 via the second data connection block 84-1. The dummy electrode 85, however, is isolated and is neither connected to the first lateral connection line 81 nor the second lateral connection line 82. This disclosure, through the identical design of the transition area, not only improves the uniformity of subsequent etching processes but also ensures that different positions achieve the same display effect under transmitted and reflected light, achieving shadow removal and effectively avoiding appearance defects and mura on the display substrate, thus improving display quality and display performance.

[0283] As shown in Figures 15C and 15D, in an exemplary embodiment, the third conductive layer may further include a first power electrode 111 and a second power electrode 112. In the second region, the first power trace 110, the first power electrode 111, and the second power electrode 112 may be disposed in each cell row.

[0284] In an exemplary embodiment, the first power electrode 111 and the second power electrode 112 can be block-shaped (e.g., rectangular). In the first direction X, the first power electrode 111 and the second power electrode 112 can be disposed between partially adjacent circuit units. In the second direction Y, the first power electrode 111 can be disposed on one side of the first power trace 110 in the second direction Y (the side closer to the second electrode plate 32) and connected to the first power trace 110 via a first power connector block 111-1. The second power electrode 112 can be disposed on the opposite side of the first power trace 110 in the second direction Y (the side farther from the second electrode plate 32) and connected to the first power trace 110 via a second power connector block 112-1. The first power electrode 111 is configured to connect to a subsequently formed second power trace, and the second power electrode 112 is configured to connect to a subsequently formed second power trace.

[0285] In an exemplary embodiment, the first power connector 111-1 and the second power connector 112-1 can be strip-shaped extending along the second direction Y. A first end of the first power connector 111-1 is connected to a first power electrode 111, and a second end of the first power connector 111-1 is connected to a first power trace 110. A first end of the second power connector 112-1 is connected to a second power electrode 112, and a second end of the second power connector 112-1 is connected to the first power trace 110.

[0286] In an exemplary embodiment, the first power electrode 111 and the second power electrode 112 located on both sides of the first power trace 110 in the second direction Y can be symmetrically arranged with respect to the first power trace 110.

[0287] In an exemplary embodiment, two circuit units may be spaced apart between adjacent first power supply electrodes 111 or second power supply electrodes 112 in the first direction X. For example, the first power supply electrode 111 and the second power supply electrode 112 may be disposed between the (N+19)th and (N+20)th unit columns. Alternatively, the first power supply electrode 111 and the second power supply electrode 112 may be disposed between the (N+21)th and (N+22)th unit columns. Yet another example is that the first power supply electrode 111 and the second power supply electrode 112 may be disposed between the (N+23)th and (N+24)th unit columns.

[0288] In an exemplary embodiment, in at least one unit row, the first power line 110, a plurality of first power electrodes 111, a plurality of first power connection blocks 111-1, a plurality of second power electrodes 112, and a plurality of second power connection blocks 112-1 can be an integral structure that is interconnected.

[0289] In an exemplary embodiment, the position, shape, and connection structure of the first power electrode 111 can be substantially the same as the position, shape, and connection structure of the first data electrode 83, and the position, shape, and connection structure of the second power electrode 112 can be substantially the same as the position, shape, and connection structure of the second data electrode 84. The difference is that the first data electrode 83 is connected to the first lateral connection line 81 through the first data connection block 83-1, the second data electrode 84 is connected to the second lateral connection line 82 through the second data connection block 84-1, and the first power electrode 111 is connected to the first power trace 110 through the first power connection block 111-1, and the second power electrode 112 is connected to the first power trace 110 through the second power connection block 112-1. The positions, shapes, and connection structures of the first power electrode 111 and the second power electrode 112 are substantially the same as those of the dummy electrode 85. The difference is that the first power electrode 111 is connected to the first power trace 110 via the first power connector block 111-1, and the second power electrode 112 is connected to the first power trace 110 via the second power connector block 112-1. The dummy electrode 85 is isolated. This disclosure, through the identical design of the transition area, not only improves the uniformity of subsequent etching processes but also ensures that different positions achieve the same display effect under transmitted and reflected light, achieving shadow removal and effectively avoiding appearance defects and mura on the display substrate, thus improving display quality and display performance.

[0290] In an exemplary embodiment, the positions and shapes of the third conductive layers (excluding the eighth connecting electrode 58, the eighth connecting block 58-1, the ninth connecting electrode 59, the ninth connecting block 59-1, the first data connecting block 83-1, and the second data connecting block 84-1) of some adjacent unit columns can be substantially the same, and the third conductive layers (excluding the eighth connecting electrode 58, the eighth connecting block 58-1, the ninth connecting electrode 59, and the ninth connecting block 59-1) of some adjacent unit columns can be mirror-symmetrical with respect to the column boundary line. For example, the positions and shapes of the second conductive layer of the Nth unit column and the third conductive layer of the N+1th unit column can be substantially the same, and the positions and shapes of the third conductive layers of the N+2th unit column and the N+3th unit column can be substantially the same. Furthermore, the third conductive layers of the N+1th unit column and the N+2th unit column can be mirror-symmetrical with respect to the column boundary line.

[0291] (17) Forming a first planarization layer pattern. In an exemplary embodiment, forming a first planarization layer pattern may include: coating a first planarization film on a substrate on which the aforementioned pattern is formed, and patterning the first planarization film using a patterning process to form a first planarization layer covering a third conductive layer. The first planarization layer is provided with a plurality of vias, as shown in Figures 16A and 16B. Figure 16A is a schematic diagram of the formation of the first planarization layer pattern in region A of Figure 8, and Figure 16B is a schematic diagram of the formation of the first planarization layer pattern in region B of Figure 8.

[0292] In an exemplary embodiment, the plurality of vias in each circuit unit of the display substrate include at least: a twenty-first via V21, a twenty-second via V22, and a twenty-third via V23.

[0293] In an exemplary embodiment, the orthographic projection of the 21st via V21 on the substrate is within the range of the orthographic projection of the second connecting electrode 52 on the substrate. The first planarization layer within the 21st via V21 is removed, exposing the surface of the second connecting electrode 52. The 21st via V21 is configured to allow a subsequently formed first connecting block or second connecting block to be connected to the second connecting electrode 52 through the via.

[0294] In an exemplary embodiment, the twenty-first via V21 can be referred to as a data via. Since the first electrode of the fourth transistor T4 in the first circuit unit is located on one side of the second transistor T2 in the first direction X, the data via in the first circuit unit is located on one side of the second transistor T2 in the first direction X. Since the first electrode of the fourth transistor T4 in the second circuit unit is located on the opposite side of the second transistor T2 in the first direction X, the data via in the second circuit unit is located on the opposite side of the second transistor T2 in the first direction X.

[0295] In an exemplary embodiment, the orthographic projection of the 22nd via V22 on the substrate is within the range of the orthographic projection of the third connection electrode 53 on the substrate. The first planarization layer within the 22nd via V22 is removed, exposing the surface of the third connection electrode 53. The 22nd via V22 is configured to allow a subsequently formed first power line to be connected to the third connection electrode 53 through the via.

[0296] In an exemplary embodiment, the orthographic projection of the 23rd via V23 on the substrate is within the range of the orthographic projection of the fourth connecting electrode 54 on the substrate. The first planarization layer within the 23rd via V23 is removed, exposing the surface of the fourth connecting electrode 54. The 23rd via V23 is configured to allow a subsequently formed anode connecting electrode to be connected to the fourth connecting electrode 54 through the via.

[0297] In an exemplary embodiment, a second fourteenth via V24 may also be provided on the first planarization layer of at least one circuit unit. The orthographic projection of the second fourteenth via V24 onto the substrate lies within the range of the orthographic projection of the eighth connecting block 58-1 onto the substrate. The first planarization layer within the second fourteenth via V24 is removed, exposing the surface of the eighth connecting block 58-1. The second fourteenth via V24 is configured to allow a subsequently formed first initial connection line to be connected to the eighth connecting block 58-1 through the via.

[0298] In an exemplary embodiment, adjacent 24th vias V24 in the first direction X may be spaced apart by 4 circuit units. For example, the 24th via V24 may be disposed between the Nth unit column and the N+1th unit column.

[0299] In an exemplary embodiment, a second fifth via V25 may also be provided on the first planarization layer of at least one circuit unit. The orthographic projection of the second fifth via V25 onto the substrate lies within the range of the orthographic projection of the ninth connecting block 59-1 onto the substrate. The first planarization layer within the second fifth via V25 is removed, exposing the surface of the ninth connecting block 59-1. The second fifth via V25 is configured to allow a subsequently formed second initial connection line to be connected to the ninth connecting block 59-1 through the via.

[0300] In an exemplary embodiment, adjacent 25th vias V25 in the first direction X may be spaced apart by four circuit units. For example, the 25th via V25 may be disposed between the N+2nd and N+3rd unit columns.

[0301] As shown in Figure 16A, in an exemplary embodiment, a plurality of twenty-sixth vias V26 and a plurality of twenty-seventh vias V27 may also be provided on the first planarization layer.

[0302] In an exemplary embodiment, the orthographic projection of the 26th via V26 onto the substrate is within the range of the orthographic projection of the first data electrode 83 or the second data electrode 84 onto the substrate. The first planarization layer within the 26th via V26 is removed, exposing the surface of the first data electrode 83 or the second data electrode 84. The 26th via V26 is configured to allow a subsequently formed first vertical connection line or second vertical connection line to be connected to the first data electrode 83 or the second data electrode 84 through the via.

[0303] In an exemplary embodiment, the orthographic projection of the 27th via V27 on the substrate is within the range of the orthographic projection of the dummy electrode 85 on the substrate. The first planarization layer within the 27th via V27 is removed, exposing the surface of the dummy electrode 85. The 27th via V27 is configured to allow the subsequently formed first vertical connection line, second vertical connection line, or second power supply trace to be connected to the dummy electrode 85 through the via.

[0304] As shown in Figure 16B, in an exemplary embodiment, a plurality of twenty-eighth vias V28 and a plurality of twenty-ninth vias V29 may also be provided on the first planarization layer.

[0305] In an exemplary embodiment, the orthographic projection of the 28th via V28 on the substrate is within the range of the orthographic projection of the first power electrode 111 on the substrate. The first planarization layer within the 28th via V28 is removed, exposing the surface of the first power electrode 111. The 28th via V28 is configured to allow a subsequently formed second power trace to be connected to the first power electrode 111 through the via.

[0306] In an exemplary embodiment, the orthographic projection of the 29th via V29 on the substrate is within the range of the orthographic projection of the second power electrode 112 on the substrate. The first planarization layer within the 29th via V29 is removed, exposing the surface of the second power electrode 112. The 29th via V29 is configured to allow a subsequently formed second power trace to be connected to the second power electrode 112 through the via.

[0307] In an exemplary embodiment, adjacent 28th vias V28 or 29th vias V29 in the first direction X may be spaced apart by two circuit units. For example, the 28th via V28 or 29th via V29 may be located between the N+19th and N+20th unit columns. Alternatively, the 28th via V28 or 29th via V29 may be located between the N+21st and N+22nd unit columns. Yet another example is that the 28th via V28 or 29th via V29 may be located between the N+23rd and N+24th unit columns.

[0308] (18) Forming a fourth conductive layer pattern. In an exemplary embodiment, forming the fourth conductive layer may include: depositing a fourth conductive thin film on the substrate on which the aforementioned pattern is formed, patterning the third conductive thin film using a patterning process, and forming a fourth conductive layer disposed on the first planarization layer, as shown in Figures 17A, 17B, 17C, and 17D. Figure 17A is a schematic diagram of the fourth conductive layer pattern formed in region A of Figure 8, Figure 17B is a planar schematic diagram of the fourth conductive layer in Figure 17A, Figure 17C is a schematic diagram of the fourth conductive layer pattern formed in region B of Figure 8, and Figure 17D is a planar schematic diagram of the third conductive layer in Figure 17C. In an exemplary embodiment, the fourth conductive layer may be referred to as the second source / drain metal (SD2) layer.

[0309] In an exemplary embodiment, the fourth conductive layer of each circuit unit in the display substrate includes at least: a first data signal line 61, a second data signal line 62, a first power supply line 63, an anode connection electrode 64, a first connection block 65, and a second connection block 66.

[0310] In an exemplary embodiment, the shape of the first data signal line 61 can be a straight line or a broken line extending along the second direction Y, and the shape of the first connecting block 65 can be block-shaped (such as rectangular). The first connecting block 65 can be disposed on the first data signal line 61 and connected to the first data signal line 61. The first connecting block 65 can be connected to the second connecting electrode 52 of the Mth cell row (first cell row) through the twenty-first via V21. Since the second connecting electrode 52 is connected to the first region of the fourth active layer through the via, the first data signal line 61 writes the data signal into the first electrode of the fourth transistor T4 in the Mth cell row.

[0311] In an exemplary embodiment, in at least one circuit unit, the first data signal line 61 and the first connection block 65 can be an integral structure that is interconnected.

[0312] In an exemplary embodiment, the shape of the second data signal line 62 can be a straight line or a broken line extending along the second direction Y, and the shape of the second connecting block 66 can be block-shaped (such as rectangular). The second connecting block 66 can be disposed on the second data signal line 62 and connected to the second data signal line 62. The second connecting block 66 can be connected to the second connecting electrode 52 of the M+1th cell row (the second cell row) through the twenty-first via V21. Since the second connecting electrode 52 is connected to the first region of the fourth active layer through the via, the second data signal line 62 writes the data signal to the first electrode of the fourth transistor T4 in the M+1th cell row.

[0313] In an exemplary embodiment, in at least one circuit unit, the second data signal line 62 and the second connection block 66 can be an integral structure that is interconnected.

[0314] In an exemplary embodiment, in at least one cell column, the first data signal line 61 may be disposed on one side of the second data signal line 62 in the first direction X, or the second data signal line 62 may be disposed on one side of the first data signal line 61 in the first direction X. For example, the first data signal line 61 in the Nth cell column and the N+1th cell column may be disposed on one side of the second data signal line 62 in the first direction X. As another example, the second data signal line 62 in the N+2th cell column and the N+3th cell column may be disposed on one side of the first data signal line 61 in the first direction X.

[0315] In an exemplary embodiment, since the data via in the first circuit unit is located on one side of the second transistor T2 in the first direction X (i.e., on the side of the cell center line in the first direction X), the first terminal of the fourth transistor T4 in the first circuit unit is connected to either the first data signal line 61 or the second data signal line 62 located on the side of the cell center line in the first direction X. Since the data via in the second circuit unit is located on the opposite side of the second transistor T2 in the first direction X (i.e., on the opposite side of the cell center line in the first direction X), the first terminal of the fourth transistor T4 in the second circuit unit is connected to either the first data signal line 61 or the second data signal line 62 located on the opposite side of the cell center line in the first direction X. For example, for the Nth and N+1th cell columns, the pixel driving circuit in the Mth cell row (the pixel driving circuit in the first circuit unit) is connected to the first data signal line 61 located on the side of the cell center line in the first direction X, and the pixel driving circuit in the M+1th cell row (the pixel driving circuit in the second circuit unit) is connected to the second data signal line 62 located on the opposite side of the cell center line in the first direction X. For example, for the N+2th and N+3rd unit columns, the pixel driving circuit in the Mth unit row (the pixel driving circuit in the second circuit unit) is connected to the first data signal line 61 located on the opposite side of the first direction X of the unit center line, and the pixel driving circuit in the M+1th unit row (the pixel driving circuit in the first circuit unit) is connected to the second data signal line 62 located on the side of the first direction X of the unit center line.

[0316] In an exemplary embodiment, in at least one circuit unit, the first data signal line 61 and the second data signal line 62 may be arranged in a mirror symmetrical manner with respect to the center line of the unit. The first data signal line 61 mentioned in this disclosure does not include the first connecting block 65, and the second data signal line 62 does not include the second connecting block 66.

[0317] In an exemplary embodiment, the first power line 63 can be a straight line or a broken line extending along the second direction Y, and can be disposed between the first data signal line 61 and the second data signal line 62. The first power line 63 is connected to the third connection electrode 53 through the twenty-second via V22. Since the third connection electrode 53 is connected to the first region and the second electrode plate 32 of the fifth active layer through the via, the first power line 63 writes the first power signal to the first electrode of the fifth transistor T5 and the second electrode plate 32 of the storage capacitor.

[0318] In an exemplary embodiment, the first power line 63 can be a non-uniform width zigzag line, which not only facilitates the layout of the pixel structure and reduces parasitic capacitance between it and the data signal line, but also the first power line with a constant voltage can effectively shield the mutual influence between the first data signal line 61 and the second data signal line 62, avoid the data voltage jump affecting the normal operation of the pixel driving circuit, and improve the display effect.

[0319] In an exemplary embodiment, the orthographic projection of the first power line 63 on the substrate at least partially overlaps with the orthographic projection of the first connecting electrode 51 on the substrate. Since the first connecting electrode 51 serves as the first node N1 in the pixel driving circuit, the constant voltage of the first power line 63 can effectively shield the influence of other signals in the pixel driving circuit on the first node N1, preventing other signals (such as data voltage jumps) from affecting the potential of the first node N1 of the pixel driving circuit, thus improving the display effect.

[0320] In an exemplary embodiment, the orthographic projection of the first power line 63 onto the substrate may include the orthographic projection of the first connection electrode 41 onto the substrate.

[0321] In an exemplary embodiment, the anode connection electrode 64 can be block-shaped (e.g., rectangular). The anode connection electrode 64 is connected to the fourth connection electrode 54 through the twenty-third via V23, and the anode connection electrode 64 is configured to be connected to the subsequently formed anode. Since the fourth connection electrode 54 is connected to the second region of the sixth active layer and the second region of the seventh active layer, the pixel driving circuit drives the light-emitting device to emit light.

[0322] In an exemplary embodiment, the fourth conductive layer may further include at least one first initial connection line 71. The shape of the first initial connection line 71 may be a straight line or a broken line extending along the second direction Y of the main body portion. The first initial connection line 71 is connected to the eighth connection block 58-1 through the twenty-fourth via V24. Since the eighth connection block 58-1 is connected to the sixth connection electrode 56, and the sixth connection electrode 56 is connected to the first initial signal line 41, a mesh-like interconnection structure for transmitting the first initial signal is formed on the display substrate by the first initial signal line 41 extending along the first direction X of the main body portion and the first initial connection line 71 extending along the second direction Y of the main body portion. This not only effectively reduces the resistance of the first initial signal line and reduces the voltage drop of the first initial signal, but also effectively improves the uniformity of the first initial signal, effectively improves display uniformity, and enhances display quality.

[0323] In an exemplary embodiment, the first initial connection line 71 may be disposed between the Nth cell column and the N+1th cell column.

[0324] In an exemplary embodiment, the fourth conductive layer may further include at least one second initial connection line 72. The shape of the second initial connection line 72 may be a straight line or a broken line extending along the second direction Y of the main body portion. The second initial connection line 72 is connected to the ninth connection block 59-1 through the twenty-fifth via V25. Since the ninth connection block 59-1 is connected to the ninth connection electrode 59, the ninth connection electrode 59 is connected to the seventh connection electrode 57, and the seventh connection electrode 57 is connected to the second initial signal line 42, a mesh-like interconnection structure for transmitting the second initial signal is formed on the display substrate by the second initial signal line 42 extending along the first direction X of the main body portion and the second initial connection line 72 extending along the second direction Y of the main body portion. This not only effectively reduces the resistance of the second initial signal line and reduces the voltage drop of the second initial signal, but also effectively improves the uniformity of the second initial signal, effectively improves the display uniformity, and improves the display quality.

[0325] In an exemplary embodiment, the second initial connection line 72 may be disposed between the N+2th and N+3th unit columns.

[0326] As shown in Figures 17A and 17B, in an exemplary embodiment, the fourth conductive layer may further include at least one first vertical connecting line 91, at least one second vertical connecting line 92, and at least one second power supply trace 120.

[0327] In an exemplary embodiment, the shapes of the first vertical connecting line 91, the second vertical connecting line 92, and the second power line 120 can be straight lines or broken lines extending along the second direction Y. The first vertical connecting line 91 can be disposed between the first data signal line 61 of the N+1th unit column and the first data signal line 61 of the N+2th unit column. The second vertical connecting line 92 can be disposed between the second data signal line 62 of the N+3th unit column and the second data signal line 62 of the N+4th unit column. The second power line 120 can be disposed between the N-1th unit column and the Nth unit column, between the N+1th unit column and the N+2th unit column, and between the N+3th unit column and the N+4th unit column, respectively.

[0328] In an exemplary embodiment, the first vertical connecting line 91 can be connected to the first data electrode 83 through the twenty-sixth via V26. Since the first data electrode 83 is connected to the first horizontal connecting line 81, the first horizontal connecting line 81 is configured to be connected to the first data signal line, and the first vertical connecting line 91 is configured to be connected to the data lead-out line in the bonding area. Thus, the interconnection between the first horizontal connecting line 81 extending along the first direction X of the main body and the first vertical connecting line 91 extending along the second direction Y of the main body is realized. The data lead-out line in the bonding area can be connected to the first data signal line 61 through the first horizontal connecting line 81 and the first vertical connecting line 91.

[0329] In an exemplary embodiment, since the first vertical connecting line 91 is connected to the first data signal line 61 through the first horizontal connecting line 81, both the first data signal line 61 and the first vertical connecting line 91 are data transmission lines that transmit data signals to the pixel driving circuit of the first unit row. This embodiment of the present disclosure, by placing the first vertical connecting line between two adjacent first data signal lines, enables three data transmission lines to transmit data signals simultaneously. This avoids the situation where some data transmission lines are in a writing state while others are in a floating state, eliminates the mutual influence of potentials on adjacent data transmission lines, eliminates display defects caused by data signal interference, and improves display quality and effect.

[0330] In an exemplary embodiment, the second vertical connecting line 92 can be connected to the second data electrode 84 through the second sixteenth via V26. Since the second data electrode 84 is connected to the second horizontal connecting line 82, the second horizontal connecting line 82 is configured to be connected to the second data signal line, and the second vertical connecting line 92 is configured to be connected to the data lead-out line in the bonding area. Thus, the interconnection between the second horizontal connecting line 82 extending along the first direction X of the main body and the second vertical connecting line 92 extending along the second direction Y of the main body is realized. The data lead-out line in the bonding area can be connected to the second data signal line 62 through the second horizontal connecting line 82 and the second vertical connecting line 92.

[0331] In an exemplary embodiment, since the second vertical connecting line 92 is connected to the second data signal line 62 via the second horizontal connecting line 82, both the second data signal line 62 and the second vertical connecting line 92 are data transmission lines that transmit data signals to the pixel driving circuit of the second unit row. This embodiment of the present disclosure, by placing the second vertical connecting line between two adjacent second data signal lines, enables three data transmission lines to transmit data signals simultaneously. This avoids the situation where some data transmission lines are in a writing state while others are in a floating state, eliminates the mutual influence of potentials on adjacent data transmission lines, eliminates display defects caused by data signal interference, and improves display quality and effect.

[0332] In an exemplary embodiment, the first vertical connecting line 91 and the second vertical connecting line 92 can also be connected to a portion of the dummy electrodes 85 through the twenty-seventh via V27, and the second power supply line 120 can be connected to another portion of the dummy electrodes 85 through the twenty-seventh via V27.

[0333] In an exemplary embodiment, a second break K2 may be provided between the first vertical connecting line 91 and the second power line 120 arranged in the same unit column, and a second break K2 may be provided between the second vertical connecting line 92 and the second power line 120 arranged in the same unit column. The second break K2 is configured to achieve mutual insulation between the first vertical connecting line 91 and the second power line 120, and mutual insulation between the second vertical connecting line 92 and the second power line 120.

[0334] As shown in Figures 17C and 17D, in an exemplary embodiment, in the second region, the second power traces 120 can be spaced apart in the second direction Y. In the second direction Y, multiple second power traces 120 can be respectively arranged between adjacent first power traces 110.

[0335] In an exemplary embodiment, for a first power trace 110, a second power trace 120 located on the Y-side of the first power trace 110 in the second direction can be connected to the first power electrode 111 through a 28th via V28, and a second power trace 120 located on the opposite side of the Y-side of the first power trace 110 can be connected to the second power electrode 112 through a 29th via V29. For two adjacent second power traces 120 in the Y-side, one second power trace 120 can be connected to the first power electrode 111 through a 28th via V28, and the other second power trace 120 can be connected to the second power electrode 112 through a 29th via V29. Since both the first power electrode 111 and the second power electrode 112 are connected to the first power trace 110, the interconnection between the first power trace 110 extending along the first direction X and the second power trace 120 extending along the second direction Y is realized, forming a mesh-like interconnected structure for transmitting power signals on the display substrate. This not only effectively reduces the resistance of the power signal lines and decreases the voltage drop of the power signal, but also effectively improves the uniformity of the power signal, thus improving the uniformity of the display and enhancing the display quality.

[0336] In an exemplary embodiment, adjacent second power traces 120 in the first direction X may be spaced apart by two circuit units. For example, the second power traces 120 may be located between the (N+19)th and (N+20)th unit columns. Alternatively, the second power traces 120 may be located between the (N+21)th and (N+22)th unit columns. Yet another example is that the second power traces 120 may be located between the (N+23)th and (N+24)th unit columns.

[0337] In an exemplary embodiment, the first power trace 110 can extend to the bezel area and connect to the bezel power lead, and / or the second power trace 120 can extend to the bonding area and connect to the bonding power lead. The bezel power lead or the bonding power lead can be connected to the second power line, realizing the second power line located in the pixel area (VSS in Pixel, or SIP) structure. This can significantly reduce the width of the bezel power lead, reduce the width of the left and right bezels, improve the screen ratio, and facilitate the realization of full-screen display.

[0338] In an exemplary embodiment, in the Nth unit column, the second vertical connecting line 92, the second data signal line 62, the first power line 63, the first data signal line 61, and the first initial connecting line 71 can be arranged sequentially in the first direction X, or the second power line 120, the second data signal line 62, the first power line 63, the first data signal line 61, and the first initial connecting line 71 can be arranged sequentially in the first direction X.

[0339] In an exemplary embodiment, in the N+1th unit column, the first initial connection line 71, the second data signal line 62, the first power line 63, the first data signal line 61 and the first vertical connection line 91 can be arranged sequentially in the first direction X, or the first initial connection line 71, the second data signal line 62, the first power line 63, the first data signal line 61 and the second power line 120 can be arranged sequentially in the first direction X.

[0340] In an exemplary embodiment, in the N+2 unit column, the first vertical connecting line 91, the first data signal line 61, the first power line 63, the second data signal line 62, and the second initial connecting line 72 can be arranged sequentially in the first direction X, or the second power line 120, the first data signal line 61, the first power line 63, the second data signal line 62, and the second initial connecting line 72 can be arranged sequentially in the first direction X.

[0341] In an exemplary embodiment, in the N+3 unit column, the second initial connection line 72, the first data signal line 61, the first power line 63, the second data signal line 62, and the second vertical connection line 92 can be arranged sequentially in the first direction X, or the second initial connection line 72, the first data signal line 61, the first power line 63, the second data signal line 62, and the second power trace 120 can be arranged sequentially in the first direction X.

[0342] In an exemplary embodiment, the positions and shapes of the first data signal line 61, second data signal line 62, first power line 63, and anode connection electrode 64 in some adjacent cell columns may be substantially the same, and these positions and shapes may be mirror-symmetrical with respect to the column boundary line. For example, the positions and shapes of the first data signal line 61, second data signal line 62, first power line 63, and anode connection electrode 64 in the Nth cell column and the (N+1)th cell column may be substantially the same, and the positions and shapes of the first data signal line 61, second data signal line 62, first power line 63, and anode connection electrode 64 in the (N+2)th cell column and the (N+3)th cell column may also be substantially the same. Furthermore, the positions and shapes of the first data signal line 61, second data signal line 62, first power line 63, and anode connection electrode 64 in the (N+1)th cell column and the (N+2)th cell column may be mirror-symmetrical with respect to the column boundary line.

[0343] (19) Forming a second planarization layer pattern. In an exemplary embodiment, forming a second planarization layer pattern may include: coating a second planarization film on a substrate on which the aforementioned pattern is formed, and patterning the second planarization film using a patterning process to form a second planarization layer covering a fourth conductive layer. The second planarization layer has a plurality of vias, as shown in Figures 18A and 18B. Figure 18A is a schematic diagram of the formation of the second planarization layer pattern in region A of Figure 8, and Figure 18B is a schematic diagram of the formation of the second planarization layer pattern in region B of Figure 8.

[0344] In an exemplary embodiment, each circuit unit includes at least an anode via V30. The orthographic projection of the anode via V30 onto the substrate lies within the orthographic projection of the anode connection electrode 64 onto the substrate. A second planarization layer within the anode via V30 is removed, exposing the surface of the anode connection electrode 64, which is configured to allow a subsequently formed anode to be connected to the anode connection electrode 64 through the via.

[0345] At this point, the driving structure layer is fabricated on the substrate. In a plane parallel to the display substrate, the driving structure layer may include multiple circuit units. Each circuit unit may include a pixel driving circuit, and a first scan signal line, a second scan signal line, a light emission signal line, a first initial signal line, a second initial signal line, and a first power supply line connected to the pixel driving circuit. Furthermore, the pixel driving circuit in the first unit row is connected to the first data signal line, and the pixel driving circuit in the second unit row is connected to the second data signal line. In a plane perpendicular to the display substrate, the driving structure layer may include at least the following layers sequentially disposed on the substrate: a shielding layer, a first insulating layer, a semiconductor layer, a second insulating layer, a first conductive layer, a third insulating layer, a second conductive layer, a fourth insulating layer, a third conductive layer, a first planarization layer, a fourth conductive layer, and a second planarization layer. The shielding layer may include at least a shielding electrode, the semiconductor layer may include at least an active layer of a first transistor to a seventh transistor, the first conductive layer may include at least a first scan signal line, a second scan signal line, a light emission signal line, and a first electrode of a storage capacitor, the second conductive layer may include at least a first initial signal line, a second initial signal line, and a second electrode of a storage capacitor, the third conductive layer may include at least a first lateral connection line, a second lateral connection line, a first power supply trace, and multiple connection electrodes, and the fourth conductive layer may include at least a first data signal line, a second data signal line, a first power supply line, a first initial connection line, a second initial connection line, a first vertical connection line, a second vertical connection line, and a second power supply trace.

[0346] In an exemplary embodiment, the substrate can be a flexible substrate or a rigid substrate. The rigid substrate can be, but is not limited to, one or more of glass and quartz. The flexible substrate can be, but is not limited to, polyethylene terephthalate, polyethylene terephthalate, polyetheretherketone, polystyrene, polycarbonate, polyarylate, polyarylate, polyimide, polyvinyl chloride, polyethylene, and textile fibers. In an exemplary embodiment, the flexible substrate can include a first flexible material layer, a first inorganic material layer, a semiconductor layer, a second flexible material layer, and a second inorganic material layer stacked together. The materials of the first and second flexible material layers can be polyimide (PI), polyethylene terephthalate (PET), or surface-treated polymer films, etc. The materials of the first and second inorganic material layers can be silicon nitride (SiNx) or silicon oxide (SiOx), etc., to improve the substrate's resistance to water and oxygen. The first and second inorganic material layers are also called barrier layers. The material of the semiconductor layer can be amorphous silicon (a-Si).

[0347] In an exemplary embodiment, the shielding layer, the first conductive layer, the second conductive layer, the third conductive layer, and the fourth conductive layer can be made of metallic materials, such as any one or more of silver (Ag), copper (Cu), aluminum (Al), and molybdenum (Mo), or alloys of the above metals, such as aluminum-neodymium alloy (AlNd) or molybdenum-niobium alloy (MoNb). They can be single-layer structures or multi-layer composite structures, such as Mo / Cu / Mo. The first insulating layer, the second insulating layer, the third insulating layer, and the fourth insulating layer can be made of any one or more of silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxynitride (SiON). They can be single-layer, multi-layer, or composite layers. The first planarization layer and the second planarization layer can be made of organic materials, such as resin.

[0348] In an exemplary embodiment, after the driving structure layer is prepared, a light-emitting structure layer is prepared on the driving structure layer. The preparation process of the light-emitting structure layer may include the following operations.

[0349] (20) Forming an anode conductive layer pattern. In an exemplary embodiment, forming an anode conductive layer pattern may include: depositing an anode conductive film on a substrate on which the aforementioned pattern is formed, patterning the anode conductive film using a patterning process to form an anode conductive layer disposed on a second planarization layer. The anode conductive layer includes at least a plurality of anode patterns, as shown in Figures 19A, 19B and 19C. Figure 19A is a schematic diagram of the anode conductive layer pattern formed in region A of Figure 8, Figure 19B is a schematic diagram of the anode conductive layer pattern formed in region B of Figure 8, and Figure 19C is a planar schematic diagram of the anode conductive layer in Figures 19A and 19B.

[0350] In an exemplary embodiment, the plurality of anode patterns may include a first anode 130A of a red light-emitting device, a second anode 130B of a blue light-emitting device, a third anode 130C of a first green light-emitting device, and a fourth anode 130D of a second green light-emitting device. The first anode 130A may be located in a red light-emitting unit that emits red light, the second anode 130B may be located in a blue light-emitting unit that emits blue light, the third anode 130C may be located in a first green light-emitting unit that emits green light, and the fourth anode 130D may be located in a second green light-emitting unit that emits green light.

[0351] In an exemplary embodiment, the first anode 130A and the second anode 130B can be alternately arranged along the first direction X, and the third anode 130C and the fourth anode 130D can be alternately arranged along the first direction X. The third anode 130C and the fourth anode 130D can be located on one side of the first anode 130A and the second anode 130B in the second direction Y. Alternatively, the first anode 130A and the second anode 130B can be alternately arranged along the second direction Y, and the third anode 130C and the fourth anode 130D can be alternately arranged along the second direction Y. The third anode 130C and the fourth anode 130D can be located on one side of the first anode 130A and the second anode 130B in the first direction X.

[0352] In an exemplary embodiment, the first anode 130A, the second anode 130B, the third anode 130C, and the fourth anode 130D can be connected to the anode connection electrode 64 of the corresponding circuit unit through the thirtieth via V30, respectively.

[0353] In an exemplary embodiment, at least one of the first anode 130A, the second anode 130B, the third anode 130C, and the fourth anode 130D may include an anode body portion and an anode connecting portion that are connected to each other. The anode body portion may be rhomboid in shape, and the corners of the rhomboid may be provided with rounded chamfers. The anode connecting portion may be block-shaped, and the anode connecting portion is connected to the anode connecting electrode 64 through the thirtieth through-hole V30.

[0354] In an exemplary embodiment, at least one of the first anode 130A, the second anode 130B, the third anode 130C, and the fourth anode 130D may include an anode centerline, which may be a straight line passing through the geometric center of the anode body and extending along the second direction Y.

[0355] As shown in Figures 19A and 19C, the orthographic projections of the anode body of the first anode 130A and the anode body of the second anode 130B on the substrate at least partially overlap with the orthographic projections of a vertical connecting line, two data signal lines, and two first power lines on the substrate. The orthographic projections of the anode body of the third anode 130C and the anode body of the fourth anode 130D on the substrate at least partially overlap with the orthographic projections of an initial connecting line, two data signal lines, and two first power lines on the substrate.

[0356] In an exemplary embodiment, the vertical connecting line and the two data signal lines overlapping with the first anode 130A and the second anode 130B can be a first vertical connecting line 91 and two first data signal lines 61. The orthographic projection of the first vertical connecting line 91 on the substrate at least partially overlaps with the orthographic projection of the column dividing line on the substrate. The two first data signal lines 61 can be substantially mirror-symmetrical with respect to the first vertical connecting line 91. The two first power lines can be substantially mirror-symmetrical with respect to the first vertical connecting line 91.

[0357] In an exemplary embodiment, the orthographic projection of the first vertical connecting line 91 on the substrate at least partially overlaps with the orthographic projection of the anode center line on the substrate, the two first data signal lines 61 can be substantially mirror-symmetrical with respect to the anode center line, and the two first power lines can be substantially mirror-symmetrical with respect to the anode center line.

[0358] In an exemplary embodiment, the vertical connecting line and the two data signal lines overlapping with the first anode 130A and the second anode 130B can be a second vertical connecting line 92 and two second data signal lines 62. The orthographic projection of the second vertical connecting line 92 on the substrate at least partially overlaps with the orthographic projection of the column dividing line on the substrate. The two second data signal lines 62 can be substantially mirror-symmetrical with respect to the second vertical connecting line 92. The two first power lines can be substantially mirror-symmetrical with respect to the second vertical connecting line 92.

[0359] In an exemplary embodiment, the orthographic projection of the second vertical connecting line 92 on the substrate at least partially overlaps with the orthographic projection of the anode center line on the substrate, the two second data signal lines 62 can be substantially mirror-symmetrical with respect to the anode center line, and the two first power lines can be substantially mirror-symmetrical with respect to the anode center line.

[0360] In an exemplary embodiment, an initial connection line overlapping with the third anode 130C and the fourth anode 130D may be a first initial connection line 71 or a second initial connection line 72. The two data signal lines may be a first data signal line 61 and a second data signal line 62. The orthographic projection of the first initial connection line 71 or the second initial connection line 72 on the substrate at least partially overlaps with the orthographic projection of the column boundary line on the substrate. The first data signal line 61 and the second data signal line 62 may be substantially mirror-symmetrical with respect to the first initial connection line 71 or the second initial connection line 72. The shapes of the two first power lines may be substantially the same.

[0361] In an exemplary embodiment, the orthographic projection of the first initial connection line 71 or the second initial connection line 72 on the substrate at least partially overlaps with the orthographic projection of the anode center line on the substrate, and the two second data signal lines 62 can be substantially mirror-symmetrical with respect to the anode center line. The first data signal line 61 and the second data signal line 62 can be substantially mirror-symmetrical with respect to the anode center line.

[0362] As shown in Figures 19B and 19C, the orthographic projections of the anode body of the first anode 130A and the anode body of the second anode 130B on the substrate at least partially overlap with the orthographic projections of a second power supply line, two data signal lines, and two first power supply lines on the substrate. The orthographic projections of the anode body of the third anode 130C and the anode body of the fourth anode 130D on the substrate at least partially overlap with the orthographic projections of an initial connection line, two data signal lines, and two first power supply lines on the substrate.

[0363] In an exemplary embodiment, the two data signal lines overlapping with the first anode 130A and the second anode 130B can be two first data signal lines 61 or two second data signal lines 62. The orthographic projection of the second power supply line 120 on the substrate at least partially overlaps with the orthographic projection of the column boundary line on the substrate. The two first data signal lines 61 can be substantially mirror-symmetrical with respect to the second power supply line 120, the two second data signal lines 62 can be substantially mirror-symmetrical with respect to the second power supply line 120, and the two first power supply lines can be substantially mirror-symmetrical with respect to the second vertical connecting line 92.

[0364] In an exemplary embodiment, the orthographic projection of the second power line 120 on the substrate at least partially overlaps with the orthographic projection of the anode centerline on the substrate, the two first data signal lines 61 or the two second data signal lines 62 can be substantially mirror-symmetrical with respect to the anode centerline, and the two first power lines can be substantially mirror-symmetrical with respect to the anode centerline.

[0365] In an exemplary embodiment, an initial connection line overlapping with the third anode 130C and the fourth anode 130D may be a first initial connection line 71 or a second initial connection line 72. The two data signal lines may be a first data signal line 61 and a second data signal line 62. The orthographic projection of the first initial connection line 71 or the second initial connection line 72 on the substrate at least partially overlaps with the orthographic projection of the column boundary line on the substrate. The first data signal line 61 and the second data signal line 62 may be substantially mirror-symmetrical with respect to the first initial connection line 71 or the second initial connection line 72. The shapes of the two first power lines may be substantially the same.

[0366] In an exemplary embodiment, the orthographic projection of the first initial connection line 71 or the second initial connection line 72 on the substrate at least partially overlaps with the orthographic projection of the anode center line on the substrate, and the first data signal line 61 and the second data signal line 62 can be substantially mirror-symmetrical with respect to the anode center line.

[0367] In an exemplary embodiment, comparing the orthographic projections of the first anode 130A on the substrate in Figure 19A (first region) and Figure 19B (second region), it can be seen that the first anode 130A overlaps with the five vertical signal lines in the first region, and the first anode 130A overlaps with the five vertical signal lines in the second region. Therefore, the vertical metal lines below the first anode 130A in the first region and the second region are basically the same, which can ensure that the flatness of the first anode 130A in the first region and the flatness of the first anode 130A in the second region are basically the same, and can ensure that the luminous performance of the red light-emitting device in the two regions is basically the same.

[0368] In an exemplary embodiment, comparing the orthographic projections of the second anode 130B on the substrate in Figure 19A (first region) and Figure 19B (second region), it can be seen that the second anode 130B overlaps with the five vertical signal lines in the first region and in the second region. Therefore, the vertical metal lines below the second anode 130B in the first and second regions are basically the same, which can ensure that the flatness of the second anode 130B in the first region is basically the same as that in the second region, and can ensure that the luminous performance of the blue light-emitting device in the two regions is basically the same.

[0369] In an exemplary embodiment, comparing the orthographic projections of the third anode 130C on the substrate in Figure 19A (first region) and Figure 19B (second region), it can be seen that the third anode 130C overlaps with the five vertical signal lines in the first region and in the second region. Therefore, the vertical metal lines below the third anode 130C in the first and second regions are basically the same, which can ensure that the flatness of the third anode 130C in the first region is basically the same as that in the second region. This can ensure that the luminous performance of the first green light-emitting device in the two regions is basically the same, and can avoid defects such as screen-off watermarks (Mura) caused by the height difference of the third anode in the two regions.

[0370] In an exemplary embodiment, comparing the orthographic projections of the fourth anode 130D on the substrate in Figure 19A (first region) and Figure 19B (second region), it can be seen that the fourth anode 130D overlaps with the five vertical signal lines in the first region and in the second region. Therefore, the vertical metal lines below the fourth anode 130D in the first and second regions are basically the same, which can ensure that the flatness of the fourth anode 130D in the first region is basically the same as that in the second region. This can ensure that the luminous performance of the second green light-emitting device in the two regions is basically the same, and can avoid defects such as screen-off watermarks caused by the height difference of the third anode in the two regions.

[0371] In an exemplary embodiment, the anode conductive layer adopts a single-layer structure, such as indium tin oxide (ITO) or indium zinc oxide (IZO), or it can adopt a multi-layer composite structure, such as ITO / Ag / ITO.

[0372] In an exemplary embodiment, the subsequent fabrication process may include: first forming a pixel definition layer pattern, then forming an organic light-emitting layer using vapor deposition or inkjet printing, then forming a cathode on the organic light-emitting layer, and then forming an encapsulation structure layer. The encapsulation structure layer may include a first encapsulation layer, a second encapsulation layer, and a third encapsulation layer stacked together. The first and third encapsulation layers may be made of inorganic materials, and the second encapsulation layer may be made of organic materials. The second encapsulation layer is disposed between the first and third encapsulation layers to ensure that external moisture cannot enter the light-emitting structure layer.

[0373] The display substrate provided in the exemplary embodiments of this disclosure, by providing two data signal lines in each unit column, one data signal line being connected to the pixel driving circuit in the odd-numbered unit row and the other data signal line being connected to the pixel driving circuit in the even-numbered unit row, can effectively increase the data writing time and compensation time of the pixel driving circuit, and can ensure the display quality and display effect of high resolution and high refresh rate.

[0374] This disclosed display substrate achieves an FIP structure by setting data connection lines within the display area and connecting the data lead-out lines in the bonding area to the data signal lines via the data connection lines. This eliminates the need for fan-shaped diagonal lines in the lead-out line area, effectively reducing the length of the lead-out line area, significantly reducing the bottom bezel width, increasing the screen ratio, and facilitating the realization of full-screen display.

[0375] The display substrate disclosed herein, by arranging the first data signal lines and the second data signal lines, places the first vertical connecting line between two adjacent first data signal lines and the second vertical connecting line between two adjacent second data signal lines, effectively eliminating display defects caused by data signal interference and improving display quality and effect.

[0376] This disclosed display substrate achieves a SiP (System-in-Pack) structure by setting a first power line and a second power line within the display area, and the first power line and the second power line form a grid-connected structure. This not only effectively reduces the resistance of the second power line and the voltage drop of the second power signal, achieving low power consumption, but also effectively improves the uniformity of the second power signal in the display substrate, thus improving display uniformity, display quality, and display performance. Furthermore, it can significantly reduce the width of the bezel power leads, greatly reducing the bezel width, increasing the screen-to-body ratio, and facilitating the realization of full-screen displays.

[0377] This disclosure shows that by setting a second power supply trace spaced apart in a second region, the substrate can effectively reduce static electricity during the fabrication process and effectively improve the fabrication quality.

[0378] The display substrate disclosed herein, by setting a first initial connection line and a second initial connection line, wherein the first initial connection line and the first initial signal line form a mesh-like interconnected structure, and the second initial connection line and the second initial signal line form a mesh-like interconnected structure, can not only effectively reduce the resistance of the initial signal line and reduce the voltage drop of the initial signal, but also effectively improve the uniformity of the initial signal in the display substrate, effectively improve the display uniformity, and improve the display quality.

[0379] The display substrate disclosed herein ensures that the flatness of the anodes in the two regions is basically the same by setting the vertical metal lines below the anodes in the first and second regions to be basically the same. This not only ensures that the light-emitting performance of the light-emitting devices in the two regions is basically the same, avoiding large viewing angle color deviation, but also avoids defects such as screen-off watermarks caused by the height difference between the anodes in the two regions, thus improving the quality of the display substrate.

[0380] The preparation process disclosed herein is well compatible with existing preparation processes, is simple to implement, easy to carry out, has high production efficiency, low production cost, and high yield.

[0381] Figure 20 is a schematic diagram of another display substrate structure according to an exemplary embodiment of the present disclosure, and is a schematic diagram of the structure of the third conductive layer and the fourth conductive layer in region B of Figure 8. As shown in Figure 20, the main structure of the display substrate in this embodiment is basically the same as the main structure of the display substrate shown in Figures 9A and 9B. The difference is that the second power supply traces 120 in this embodiment are continuously arranged in the second direction Y, that is, the second power supply traces 120 in multiple unit rows in a unit column are a single integrated structure connected in sequence.

[0382] In an exemplary embodiment, the second power line 120 can be continuously arranged in the second direction Y, and connected to the first power line 110 through the first power electrode 111 in the third conductive layer, forming a mesh-like interconnected structure for transmitting power signals on the display substrate.

[0383] In the exemplary embodiment, the fabrication process of the display substrate and the formed film layers are basically the same as those shown in Figures 9A and 9B. The difference is that: only the first power electrode 111 and the first power connection block 111-1 are provided in the third conductive layer of the second region, and no second power electrode and the second power connection block are provided; only the twenty-eighth via is provided in the first planarization layer of the second region, and no twenty-ninth via is provided; the second power trace 120 of the fourth conductive layer in the second region can be continuously arranged in the second direction Y, and connected to multiple first power electrodes 111 through the twenty-eighth via. Since the first power electrode 111 is connected to the first power trace 110, the interconnection between the first power trace 110 extending along the first direction X and the second power trace 120 extending along the second direction Y is realized, forming a mesh-like interconnected structure for transmitting power signals on the display substrate, as shown in Figures 21 and 22. Figure 21 is a planar schematic diagram of the third conductive layer in Figure 20, and Figure 22 is a planar schematic diagram of the fourth conductive layer in Figure 20.

[0384] The display substrate provided in this embodiment not only has the same technical effects as the embodiments shown in Figures 9A and 9B, including increasing the data writing time and compensation time of the pixel driving circuit, eliminating interference of the data signal, and realizing the FIP structure and SIP structure, but also has a simple structure by setting a continuously arranged second power supply line in the second region, which can effectively improve the fabrication quality.

[0385] Figure 23 is a schematic diagram of the structure of another display substrate according to an exemplary embodiment of the present disclosure, and is a schematic diagram of the structure of the second to fourth conductive layers in region B of Figure 8. As shown in Figure 23, the main structure of the display substrate in this embodiment is basically the same as the main structure of the display substrate shown in Figures 9A and 9B. The difference is that the first lateral connecting line, the second lateral connecting line and the first power supply line in this embodiment are disposed in the second conductive layer.

[0386] In the exemplary embodiment, the fabrication process of the display substrate and the various film layers formed are basically the same as those shown in Figures 9A and 9B. The difference is that: the second conductive layer is further provided with a first lateral connecting line, a second lateral connecting line, and a first power line 110; the third conductive layer in the second region is provided with a first power electrode 111, a second power electrode 112, and a third power electrode 113 forming an interconnected integral structure. The third power electrode 113 is disposed between the first power electrode 111 and the second power electrode 112, and the third power electrode 113 is connected to the first power line 110 through a via; the second power lines 120 of the fourth conductive layer in the second region can be spaced apart in the second direction Y. Multiple second power lines 120 can be respectively disposed between adjacent first power lines 110. For two adjacent second power lines 120 in the second direction Y, one second power line 120 can be connected to the first power electrode 111 through a via, and the other second power line 120 can be connected to the second power electrode 112 through a via. Since the first power electrode 111 and the second power electrode 112 are connected to the first power trace 110 through the third power electrode 113, the interconnection between the first power trace 110 extending along the first direction X and the second power trace 120 extending along the second direction Y is realized, forming a mesh-like interconnected structure for transmitting power signals on the display substrate, as shown in Figures 24 to 26. Figure 24 is a planar schematic diagram of the second conductive layer in Figure 23, Figure 25 is a planar schematic diagram of the third conductive layer in Figure 23, and Figure 26 is a planar schematic diagram of the fourth conductive layer in Figure 23.

[0387] The display substrate provided in this embodiment not only has the same technical effects as the embodiments shown in Figures 9A and 9B, including increasing the data writing time and compensation time of the pixel driving circuit, eliminating interference of data signals, and realizing FIP structure and SIP structure, but also optimizes the arrangement of horizontal signal lines by setting the first horizontal connecting line, the second horizontal connecting line and the first power supply line in the second conductive layer, which helps to reduce and eliminate interference of data signals and improve display quality and display effect.

[0388] Figure 27 is a schematic diagram of the structure of another display substrate according to an exemplary embodiment of the present disclosure, and is a schematic diagram of the structure of the second conductive layer to the fourth conductive layer in region B of Figure 8. As shown in Figure 27, the main structure of the display substrate in this embodiment is basically the same as the main structure of the display substrate shown in Figure 23. The difference is that the second power supply line 120 in this embodiment can be continuously arranged in the second direction Y, that is, the second power supply lines 120 in multiple unit rows in a unit column are a single integrated structure connected in sequence.

[0389] In this exemplary embodiment, the fabrication process of the display substrate and the various film layers formed are basically the same as those in the embodiment shown in FIG. 23. The difference is that only the first power electrode 111 and the third power electrode 113, which form an interconnected integral structure, are provided in the third conductive layer of the second region, and no second power electrode is provided. The third power electrode 113 is connected to the first power trace 110 through a via. The second power trace 120 of the fourth conductive layer in the second region can be continuously arranged in the second direction Y and connected to multiple first power electrodes 111 through vias. Since the first power electrode 111 is connected to the first power trace 110 through the third power electrode 113, the interconnection between the first power trace 110 extending along the first direction X and the second power trace 120 extending along the second direction Y is realized, forming a mesh-like interconnected structure for transmitting power signals on the display substrate.

[0390] The display substrate provided in this embodiment not only has the same technical effects as the embodiment shown in FIG23, but also has a simple structure and can effectively improve the manufacturing quality by setting a continuous second power supply line in the second region.

[0391] Figure 28 is a schematic diagram of the structure of another display substrate according to an exemplary embodiment of the present disclosure, and is a schematic diagram of the structure of the second to fourth conductive layers in region B of Figure 8. As shown in Figure 28, the main structure of the display substrate in this embodiment is basically the same as the main structure of the display substrate shown in Figures 9A and 9B. The difference is that in this embodiment, the first horizontal connecting line, the second horizontal connecting line, and the first power supply line are disposed in the second conductive layer, and the first vertical connecting line, the second vertical connecting line, and the second power supply line are disposed in the third conductive layer.

[0392] In an exemplary embodiment, the fabrication process of the display substrate may include the following operations.

[0393] (21) to (23) sequentially form a shielding layer, a semiconductor layer and a first conductive layer pattern. The formation process and the formed shielding layer, semiconductor layer and first conductive layer pattern are basically the same as those shown in the embodiments of FIG9A and FIG9B.

[0394] (24) Forming a second conductive layer pattern. The formation process and the formed second conductive layer pattern are basically the same as those shown in the embodiments of FIG9A and FIG9B. The difference is that the second conductive layer is also provided with a first lateral connecting line, a second lateral connecting line and a first power supply line 110, as shown in FIG29, which is a planar schematic diagram of the second conductive layer in FIG28.

[0395] In an exemplary embodiment, the shape of the first power supply line 110 can be a line shape in which the main body extends along the first direction X, and it can be set in the first unit row and the second unit row, and can be located between the second initial signal line 42 of the unit row and the light emission signal line 23 of the previous unit row.

[0396] (25) to (26) sequentially form the fourth insulating layer and the third conductive layer pattern. The formation process and the formed fourth insulating layer and the third conductive layer pattern are basically the same as those shown in the embodiments of Figures 9A and 9B. The difference is that the third conductive layer is also provided with a first vertical connecting line, a second vertical connecting line and a second power supply line 120, as shown in Figure 30, which is a planar schematic diagram of the third conductive layer in Figure 28.

[0397] In an exemplary embodiment, the third conductive layer of each circuit unit in the display substrate may include at least the first connecting electrode 51 to the seventh connecting electrode 57. The structure of the connecting electrodes is substantially the same as that shown in the embodiments of FIG. 9A and FIG. 9B, except that the shape of the sixth connecting electrode 56 may be a strip shape extending along the second direction Y.

[0398] In an exemplary embodiment, the third conductive layer of at least one circuit unit may further include an eighth connection electrode 58. The shape of the eighth connection electrode 58 may be a strip extending along the first direction X, with a first end of the eighth connection electrode 58 connected to a sixth connection electrode 56 and a second end of the eighth connection electrode 58 connected to a first initial connection line 71.

[0399] In an exemplary embodiment, the third conductive layer may further include at least one first initial connection line 71. The shape of the first initial connection line 71 may be a straight line or a broken line extending along the second direction Y of the main body portion. Since the first initial connection line 71 is connected to the sixth connection electrode 56 through the eighth connection electrode 58, and the sixth connection electrode 56 is connected to the first initial signal line 41, a mesh-like interconnection structure for transmitting the first initial signal is formed on the display substrate by the first initial signal line 41 extending along the first direction X of the main body portion and the first initial connection line 71 extending along the second direction Y of the main body portion.

[0400] In an exemplary embodiment, in at least one circuit unit, the sixth connecting electrode 56, the eighth connecting electrode 58, and the first initial connecting line 71 can be an integral structure that is interconnected.

[0401] In an exemplary embodiment, the third conductive layer of at least one circuit unit may further include a ninth connection electrode 59. The ninth connection electrode 59 may be a strip shape extending along a first direction X, and may span two adjacent circuit units in a portion of the first direction X. A first end of the ninth connection electrode 59 is connected to a seventh connection electrode 57 in one circuit unit, a second end of the ninth connection electrode 59 is connected to a seventh connection electrode 57 in another circuit unit, and the portion between the first and second ends of the ninth connection electrode 59 is connected to a second initial connection line 72.

[0402] In an exemplary embodiment, the third conductive layer may further include at least one second initial connection line 72. The shape of the second initial connection line 72 may be a straight line or a broken line extending along the second direction Y of the main body portion. Since the second initial connection line 72 is connected to the seventh connection electrode 57 through the ninth connection electrode 59, and the seventh connection electrode 57 is connected to the second initial signal line 42, a mesh-like interconnection structure for transmitting the second initial signal is formed on the display substrate by the second initial signal line 42 extending along the first direction X of the main body portion and the second initial connection line 72 extending along the second direction Y of the main body portion.

[0403] In an exemplary embodiment, in at least one circuit unit, the seventh connecting electrode 57, the ninth connecting electrode 59, and the second initial connecting line 72 can be an integral structure that is interconnected.

[0404] In an exemplary embodiment, the third conductive layer may further include at least one first vertical connecting line, at least one second vertical connecting line, and at least one second power trace 120. The shape of the second power trace 120 may be a straight line or a broken line extending along the second direction Y, and it may be disposed between some adjacent cell columns. The second power trace 120 may be connected to the first power trace 110 through vias, thereby realizing the interconnection between the first power trace 110 extending along the first direction X and the second power trace 120 extending along the second direction Y, forming a mesh-like interconnected structure for transmitting power signals on the display substrate.

[0405] (27) to (28) sequentially form a first planarization layer and a fourth conductive layer. The formation process and the patterns of the first planarization layer and the fourth conductive layer are basically the same as those shown in the embodiments of FIG9A and FIG9B. The difference is that the fourth conductive layer includes at least the first data signal line 61, the second data signal line 62, the first power supply line 63 and the anode connection electrode 64 in each circuit unit, but does not have the first initial connection line, the second initial connection line, the first vertical connection line, the second vertical connection line and the second power supply line, as shown in FIG31, which is a planar schematic diagram of the fourth conductive layer in FIG28.

[0406] In the exemplary embodiment, the structure of the first data signal line 61, the second data signal line 62, the first power supply line 63 and the anode connection electrode 64 is basically the same as that of the embodiments shown in FIG9A and FIG9B, and will not be described again here.

[0407] The display substrate provided in this embodiment not only has the same technical effects as the embodiments shown in Figures 9A and 9B, including increasing the data writing time and compensation time of the pixel driving circuit, eliminating interference of data signals, and realizing FIP and SIP structures, but also optimizes the arrangement of horizontal and vertical signal lines by setting the first horizontal connecting line, the second horizontal connecting line, and the first power line in the second conductive layer, and setting the first initial connecting line, the second initial connecting line, the first vertical connecting line, the second vertical connecting line, and the second power line in the third conductive layer. This helps to reduce and eliminate interference of data signals and improves display quality and display effect.

[0408] The structures and their preparation processes shown in the foregoing embodiments of this disclosure are merely illustrative examples. In the exemplary embodiments, the corresponding structures and patterning processes can be changed or added or reduced according to actual needs, and this disclosure does not limit them.

[0409] In exemplary embodiments, the display substrate of this disclosure can be applied to display devices with pixel driving circuits, such as OLED, quantum dot display (QLED), light-emitting diode display (Micro LED or Mini LED) or quantum dot light-emitting diode display (QDLED), etc., and this disclosure does not limit it.

[0410] This disclosure also provides a display device, which includes the aforementioned display substrate. The display device can be any product or component with display function, such as a mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, or navigator, and the embodiments of the present invention are not limited thereto.

[0411] While the embodiments disclosed herein are as described above, it should be noted that these embodiments are merely exemplary and not restrictive. Therefore, this disclosure is not limited to the specific content shown and described herein. Various modifications, substitutions, or omissions can be made to the form and details of the embodiments without departing from the scope of this disclosure.

Claims

1. A display substrate, comprising a driving structure layer disposed on a substrate and a light-emitting structure layer disposed on a side of the driving structure layer away from the substrate; the driving structure layer comprising a plurality of circuit units forming a plurality of unit rows and a plurality of unit columns, the plurality of unit rows comprising a plurality of first unit rows and a plurality of second unit rows, wherein the first unit rows are odd-numbered unit rows and the second unit rows are even-numbered unit rows, or, the first unit rows are even-numbered unit rows and the second unit rows are odd-numbered unit rows; at least one circuit unit comprising a pixel driving circuit, a first data signal line and a second data signal line, the first data signal line being connected to the pixel driving circuit in the first unit row, and the second data signal line being connected to the pixel driving circuit in the second unit row; the driving... The structural layer further includes at least one first horizontal connecting line and at least one second horizontal connecting line extending along a first direction, and at least one first vertical connecting line and at least one second vertical connecting line extending along a second direction, wherein the first direction and the second direction intersect; a first end of the first horizontal connecting line is connected to the first data signal line, a second end of the first horizontal connecting line is connected to the first vertical connecting line, a first end of the second horizontal connecting line is connected to the second data signal line, and a second end of the second horizontal connecting line is connected to the second vertical connecting line; in the first direction, the first vertical connecting line is disposed between two adjacent first data signal lines, and the second vertical connecting line is disposed between two adjacent second data signal lines.

2. The display substrate according to claim 1, wherein, At least one circuit unit further includes a first initial signal line extending along the first direction, the first initial signal line being connected to the pixel driving circuit; the driving structure layer further includes at least one first initial connection line extending along the second direction, the first initial connection line being connected to the first initial signal line to form a mesh-like interconnected structure for transmitting the first initial signal; in the first direction, the first initial connection line is disposed between adjacent first data signal lines and second data signal lines.

3. The display substrate according to claim 1, wherein, At least one circuit unit further includes a second initial signal line extending along the first direction, the second initial signal line being connected to the pixel driving circuit; the driving structure layer further includes at least one second initial connection line extending along the second direction, the second initial connection line being connected to the second initial signal line to form a mesh-like interconnected structure for transmitting the second initial signal; in the first direction, the second initial connection line is disposed between adjacent first data signal lines and second data signal lines.

4. The display substrate according to claim 1, wherein, The second data signal line, the first data signal line, the second data signal line, the first data signal line, the first data signal line, the second data signal line, the first data signal line, and the second data signal line are arranged periodically in the first direction.

5. The display substrate according to claim 1, wherein, At least one circuit unit includes a unit center line, which is a straight line that bisects the circuit unit in the first direction and extends along the second direction; the first data signal line and the second data signal line are symmetrically arranged with respect to the unit center line.

6. The display substrate according to claim 5, wherein, The multiple circuit units include multiple first circuit units and multiple second circuit units; the pixel driving circuit in the first circuit unit is connected to the first data signal line or the second data signal line located on the side of the unit center line in the first direction, and the pixel driving circuit in the second circuit unit is connected to the first data signal line or the second data signal line located on the side of the unit center line in the opposite direction; or, the pixel driving circuit in the first circuit unit is connected to the first data signal line or the second data signal line located on the side of the unit center line in the opposite direction, and the pixel driving circuit in the second circuit unit is connected to the first data signal line or the second data signal line located on the side of the unit center line in the first direction.

7. The display substrate according to claim 6, wherein, In the first unit row, the first circuit unit, the second circuit unit, and the second circuit unit are periodically arranged in the first direction; in the second unit row, the second circuit unit, the second circuit unit, the first circuit unit, and the first circuit unit are periodically arranged in the first direction.

8. The display substrate according to claim 6, wherein, In at least one unit column, the first circuit unit and the second circuit unit are alternately arranged in the second direction.

9. The display substrate according to claim 6, wherein, The first vertical connecting line is disposed between adjacent first circuit units and second circuit units in the first direction, and the second vertical connecting line is disposed between adjacent first circuit units and second circuit units in the first direction.

10. The display substrate according to claim 6, wherein, At least one circuit unit further includes a first initial signal line extending along the first direction, the first initial signal line being connected to the pixel driving circuit; the driving structure layer further includes at least one first initial connection line extending along the second direction, the first initial connection line being connected to the first initial signal line to form a mesh-like interconnected structure for transmitting the first initial signal, the first initial connection line being disposed between two adjacent first circuit units in the first direction, or the first initial connection line being disposed between two adjacent second circuit units in the first direction.

11. The display substrate according to claim 6, wherein, At least one circuit unit further includes a second initial signal line extending along the first direction, the second initial signal line being connected to the pixel driving circuit; the driving structure layer further includes at least one second initial connection line extending along the second direction, the second initial connection line being connected to the second initial signal line to form a mesh-like interconnected structure for transmitting the second initial signal, the second initial connection line being disposed between two adjacent first circuit units in the first direction, or the second initial connection line being disposed between two adjacent second circuit units in the first direction.

12. The display substrate according to any one of claims 1 to 11, wherein, The driving structure layer further includes at least one first power trace extending along the first direction and at least one second power trace extending along the second direction; in a direction perpendicular to the display substrate, the display substrate includes a first conductive layer disposed on a substrate, a second conductive layer disposed on the side of the first conductive layer away from the substrate, a third conductive layer disposed on the side of the second conductive layer away from the substrate, and a fourth conductive layer disposed on the side of the third conductive layer away from the substrate. The first power trace and the second power trace are disposed in different conductive layers, and the second power trace is connected to the first power trace through a via, forming a mesh-like interconnected structure for transmitting power signals.

13. The display substrate according to claim 12, wherein, In the first direction, the second power supply trace is disposed between two adjacent first data signal lines, or the second power supply trace is disposed between two adjacent second data signal lines.

14. The display substrate according to claim 12, wherein, The first power trace is disposed in the second conductive layer, and the second power trace is disposed in the third conductive layer; or, the first power trace is disposed in the second conductive layer, and the second power trace is disposed in the fourth conductive layer; or, the first power trace is disposed in the third conductive layer, and the second power trace is disposed in the fourth conductive layer.

15. The display substrate according to claim 12, wherein, At least one circuit unit further includes a first power electrode, which is disposed on one side of the first power trace in the second direction and connected to the first power trace; the second power trace is continuously disposed in the second direction and is connected to the first power electrode through a via.

16. The display substrate according to claim 12, wherein, At least one circuit unit further includes a first power electrode and a second power electrode. The first power electrode is disposed on one side of the first power trace in the second direction and is connected to the first power trace. The second power electrode is disposed on the opposite side of the first power trace in the second direction and is connected to the first power trace. The second power traces are spaced apart in the second direction. The second power trace located on one side of the first power trace in the second direction is connected to the first power electrode through a via. The second power trace located on the opposite side of the first power trace in the second direction is connected to the second power electrode through a via.

17. The display substrate according to any one of claims 1 to 11, wherein, The light-emitting structure layer includes multiple light-emitting units, including a first light-emitting unit emitting red light, a second light-emitting unit emitting blue light, and a third and fourth light-emitting units emitting green light. The first light-emitting unit includes at least a first anode, the second light-emitting unit includes at least a second anode, the third light-emitting unit includes at least a third anode, and the fourth light-emitting unit includes at least a fourth anode. The orthographic projections of the first anode and the second anode onto the substrate at least partially overlap with the orthographic projections of at least two first data signal lines or at least two second data signal lines onto the substrate. The orthographic projections of the third anode and the fourth anode onto the substrate at least partially overlap with the orthographic projections of at least one first data signal line and at least one second data signal line onto the substrate.

18. The display substrate according to claim 17, wherein, The orthographic projections of the first anode and the second anode on the substrate at least partially overlap with the orthographic projections of at least one first vertical connecting line and at least two first data signal lines on the substrate, and the two first data signal lines are symmetrically arranged with respect to the first vertical connecting line. Alternatively, the orthographic projections of the first anode and the second anode on the substrate at least partially overlap with the orthographic projections of at least one second vertical connecting line and at least two second data signal lines on the substrate, and the two second data signal lines are symmetrically arranged with respect to the second vertical connecting line.

19. A display device comprising a display substrate as described in any one of claims 1 to 18.

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