Transistor, storage array and electronic device

Abstract

The embodiments of the present application relate to the field of electronic devices. Provided are a transistor, a storage array and an electronic device, which can improve the storage security and the storage performance. The transistor comprises a substrate and a gate structure. A trench, a source region and a drain region are disposed on the substrate. The gate structure is disposed in the trench. The gate structure comprises a dielectric layer, a first filling region, a second filling region, and a third filling region. The dielectric layer covers the inner surface of the trench. A filling material of the first filling region is disposed in contact with the bottom of the trench, and the second filling region is located above the first filling region. The third filling region is located in the second filling region. The third filling region is not in contact with the dielectric layer. A work function of the filling material in the first filling region is greater than a work function of a filling material in the second filling region. A work function of a filling material in the third filling region is greater than the work function of the filling material in the second filling region.

Description

A transistor, a memory array, and an electronic device Technical Field

[0001] This application relates to the field of electronic devices, and more particularly to a transistor, a memory array, and an electronic device. Background Technology

[0002] As the size of transistors (TRs) in the basic memory cells of dynamic random access memory (DRAM) decreases, the electric field at the gate edge of the transistor increases, leading to a more severe phenomenon of gate-induced drain leakage (GIDL). GIDL can cause data errors and affect memory security.

[0003] To mitigate the problems caused by gate-drain leakage (GIDL), the industry has introduced a dual work-function buried word line (WF BWL) structure in transistors. This structure consists of a low work-function layer with a lower work-function layer and a high work-function layer with a higher work-function layer. By increasing the thickness of the low work-function layer and decreasing the thickness of the high work-function layer, the difficulty of tunneling current formation in the gate-drain overlap region is increased, thereby improving GIDL leakage.

[0004] However, increasing the thickness of the low work function layer significantly increases the resistivity of the transistor, leading to an increase in write recovery time (tWR), which in turn affects memory performance. Summary of the Invention

[0005] This application provides a transistor, a memory array, and an electronic device that can improve GIDL leakage current and timing issues caused by increased resistivity and tWR due to the use of low work function materials in the gate structure, thereby improving memory security and performance.

[0006] In a first aspect, a transistor is provided, comprising: a substrate and a gate structure. A trench, a source region, and a drain region are disposed on the substrate. The gate structure is disposed within the trench. The gate structure includes a dielectric layer, a first filled region, a second filled region, and a third filled region. The dielectric layer covers the inner surface of the trench. A filling material of the first filled region is disposed in contact with the bottom of the trench, and the second filled region is located above the first filled region. The third filled region is located within the second filled region. The third filled region is not in contact with the dielectric layer. The work function of the filling material in the first filled region is greater than the work function of the filling material in the second filled region. The work function of the filling material in the third filled region is greater than the work function of the filling material in the second filled region.

[0007] Based on this scheme, a channel for charge flow can be formed from the source region along the outer edge of the trench to the drain region. Since the second filling region is close to the channel and the filling material in the second filling region has a low work function, the electric field strength in the region near the channel is low. This increases the difficulty of tunneling current formation in the gate-drain overlap region, thereby improving GIDL leakage and enhancing storage security. Furthermore, since the filling material in the third filling region has a high work function, its resistivity is low, resulting in a lower overall transistor resistivity. This mitigates the increased resistivity caused by using a low work function material in the gate structure, thus improving timing issues caused by increased tWR and enhancing storage performance.

[0008] In some possible implementations, the source and drain regions are located above the first fill region, on either side of the trench. Based on this approach, the distance between the high work function material in the first fill region and the drain region can be increased, thereby reducing the electric field strength between the first fill region and the drain region, increasing the difficulty of tunneling current formation in the gate-drain overlap region, and thus improving GIDL leakage current and enhancing storage security.

[0009] In some possible implementations, the filling material of the first filling region includes titanium nitride and / or tungsten. The filling material of the third filling region includes titanium nitride and / or tungsten. Based on this scheme, the filling materials of both the first and third filling regions have high work functions, which helps to reduce the overall resistivity of the transistor and ensure the transistor's storage performance.

[0010] In some possible implementations, the filling material of the second filling region includes polysilicon. Based on this approach, the filling material of the second filling region has a lower work function, which helps to reduce the electric field in the gate edge region, thereby increasing the difficulty of tunneling current formation in the gate-drain overlap region and improving GIDL leakage current.

[0011] In some possible implementations, the second filling region surrounds the third filling region in a U-shape. Based on this scheme, the third filling region is easy to etch, the process is less difficult, and the implementation cost is lower.

[0012] In some possible implementations, the surface of the third fill region that does not contact the second fill region is recessed. Based on this approach, the fill material in the third fill region can be reduced, thereby reducing the overall resistivity of the transistor, improving timing issues caused by increased tWR, and enhancing memory performance.

[0013] In some possible implementations, the second filling region surrounds the third filling region. Based on this approach, the low work function of the second filling region completely envelops the high work function material of the third filling region, which helps to further reduce the electric field in the gate edge region and improve GIDL leakage current.

[0014] In some possible implementations, the thickness of the second fill region is between 0.5 nm and 15 nm. Based on this approach, a low electric field can be ensured in the gate edge region, thereby increasing the difficulty of tunneling current formation in the gate-drain overlap region and improving GIDL leakage current.

[0015] In some possible implementations, the volume ratio of the third filling region to the second filling region is between one-ninth and nine-tenths. This approach helps reduce the overall resistivity of the transistor, thereby mitigating the increased resistivity caused by the use of low work function materials in the gate structure, and consequently improving timing issues resulting from increased tWR.

[0016] In some possible implementations, the third fill region is U-shaped. Based on this scheme, the fill material in the third fill region can be reduced, thereby reducing the overall resistivity of the transistor, improving timing issues caused by increased tWR, and enhancing memory performance.

[0017] In a second aspect, a memory cell is provided, comprising a capacitor and a transistor according to any one of the first aspects. One end of the capacitor is connected to a first electrode of the transistor. The first electrode is either the source or the drain. The other end of the capacitor is grounded.

[0018] Thirdly, a memory array is provided, including word lines, bit lines, source lines, and multiple memory cells. Each memory cell includes a capacitor and a transistor according to any one of the claims in the first aspect. The multiple memory cells are arranged in an array. The word lines are connected to the gate structure of the transistors. The bit lines are connected to a first terminal of the transistors. The source lines are connected to a second terminal of the transistors via capacitors. The first terminal and the second terminal are the source and drain of the transistors, respectively.

[0019] Fourthly, a memory is provided, including a controller and a memory array as described in the third aspect. The controller is connected to the memory array. The controller is used to access the memory array.

[0020] Fifthly, an electronic device is provided, including a circuit board processor and a memory as described in the fourth aspect. The memory is integrated on the circuit board.

[0021] A sixth aspect provides a transistor manufacturing method, comprising: forming a trench, a source region, and a drain region on a substrate; forming a gate structure within the trench; wherein the gate structure includes a dielectric layer, a first filled region, a second filled region, and a third filled region; the dielectric layer covering the inner surface of the trench; a filling material of the first filled region being disposed in contact with the bottom of the trench; the second filled region being disposed above the first filled region; and the third filled region being disposed within the second filled region; the third filled region not being in contact with the dielectric layer; the work function of the filling material in the first filled region being greater than the work function of the filling material in the second filled region; and the work function of the filling material in the third filled region being greater than the work function of the filling material in the second filled region.

[0022] It should be understood that the second to sixth aspects of this application are consistent with or correspond to the technical solutions of the first aspect of this application, and the beneficial effects achieved by each aspect and the corresponding feasible implementation are similar, and will not be repeated here. Attached Figure Description

[0023] Figure 1 is a schematic diagram of a storage unit structure;

[0024] Figure 2 is a schematic diagram of the structure of an electronic device provided in an embodiment of this application;

[0025] Figure 3 is a cross-sectional schematic diagram of a transistor provided in an embodiment of this application;

[0026] Figure 4 is a cross-sectional schematic diagram of another transistor provided in an embodiment of this application;

[0027] Figure 5 is a cross-sectional schematic diagram of another transistor provided in an embodiment of this application;

[0028] Figure 6 is a cross-sectional schematic diagram of another transistor provided in an embodiment of this application;

[0029] Figure 7 is a cross-sectional schematic diagram of a dual-function embedded word line structure transistor;

[0030] Figure 8 is a simulation diagram of the electric field strength of a transistor provided in an embodiment of this application;

[0031] Figure 9 is a schematic diagram of a storage array provided in an embodiment of this application;

[0032] Figure 10 is a schematic diagram of the structure of a memory provided in an embodiment of this application;

[0033] Figure 11 is a schematic diagram of the structure of another electronic device provided in an embodiment of this application. Detailed Implementation

[0034] The transistors, memory arrays, and electronic devices of the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. The present invention can be implemented in various forms and should not be construed as being limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art.

[0035] It should be noted that the accompanying drawings are all in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of the present invention. It should be understood that in the following description, when a layer, region, pattern, or structure is referred to as "on" a substrate, layer, region, and / or pattern, it can be located directly on another layer or substrate, and / or intercalation layers may also be present. Similarly, when a layer is referred to as "under" another layer, it can be located directly under another layer, and / or one or more intercalation layers may also be present. Furthermore, references to "on" and "under" layers can be made based on the accompanying drawings.

[0036] Additionally, it should be noted that in this specification, "connection / coupling" means not only that one component is directly coupled to another component, but also that one component is indirectly coupled to another component via an intermediate component. Furthermore, unless otherwise specified, the singular form may include the plural form, and vice versa.

[0037] To facilitate understanding, the application scenarios of the embodiments of this application will be described below.

[0038] DRAM is a common type of memory widely used in electronic devices such as mobile phones, computers, smartwatches, and automotive terminals. From a principle perspective, DRAM can be understood as a capacitor-based storage technology that uses the accumulation and release of charge to write and read data.

[0039] For example, DRAM can be composed of multiple memory cells. The structure of a memory cell can be as shown in Figure 1, including a transistor 101 and a capacitor 102. The transistor 101 includes a gate, a source, and a drain. The source or drain is grounded through the capacitor 102 (Figure 1 shows the drain being grounded through the capacitor 102 as an example).

[0040] In the embodiments of this application, the transistor can be a metal oxide semiconductor (MOS) transistor, such as an NMOS transistor, a PMOS transistor, or a CMOS transistor. Alternatively, the transistor can also be a junction field-effect transistor (JFET), but this application does not limit the specific type of transistor used.

[0041] In the memory cell, transistor 101 can function as an electronic switch. For example, the gate of transistor 101 can control the switching between the source and drain of the transistor. Capacitor 102 can store charge, and the memory 102 can record information based on the presence or absence of charge. For example, when charge is present in capacitor 102 of the memory cell, the bit information stored in that memory cell can be recorded as "1". When no charge is present in capacitor 102 of the memory cell, the bit information stored in that memory cell can be recorded as "0".

[0042] When reading the bit information stored in the memory cell, the source and drain of transistor 101 can be turned on. If transistor 101 is detected to be discharging after being turned on, it can be confirmed that the bit information stored in the memory cell is "1". If transistor 101 is not detected to be discharging after being turned on, it can be confirmed that the bit information stored in the memory cell is "0".

[0043] When writing bit information into a memory cell, the source and drain of transistor 101 can be turned on, and a high voltage can be applied to the source of transistor 101. In this way, current will flow through transistor 101 to charge capacitor 102, causing capacitor 102 to store charge, thereby writing the bit information "1".

[0044] When writing bit information into the memory cell, the source of transistor 101 can also be grounded. In this way, the charge in capacitor 102 will be released, thereby writing the bit information "0".

[0045] As transistor sizes shrink, the GIDL phenomenon may occur. GIDL refers to the phenomenon where, when a voltage is applied to the drain of a transistor, the PN junction in the drain region becomes reverse-biased. Excess electron-hole pairs generated by electrothermal energy are driven by the electric field before they can recombine, resulting in leakage current. It should be understood that leakage current in transistors within a memory cell may alter the stored bit information, thereby affecting the accuracy and security of the memory cell.

[0046] Dual-function embedded wordline structures can effectively reduce GIDL leakage. The work function, also known as the overflow work, refers to the minimum energy required to move an electron from the interior of an object to its surface. In other words, the higher the work function of a material, the greater the energy required to move an electron from the interior to the surface, the stronger the confinement of the electronic device within the material, and the more difficult it is for electrons to escape from the surface. Dual-function structures refer to using a high-work-function layer and a low-work-function layer to construct the gate of a transistor. An embedded wordline structure means that the wordline is formed within the substrate and intersects with the active region within the substrate, so that part of the wordline can be used as the gate of the transistor in the memory cell. The source and drain regions of the transistor are formed in the substrate on both sides of the gate.

[0047] In the embodiments of this application, a high work function material can refer to a material whose work function is higher than that of silicon's mid-gap work function. A low work function material can refer to a material whose work function is lower than that of silicon's mid-gap work function. Here, the mid-gap work function of silicon can be considered to be 4.5 eV.

[0048] Exemplarily, in the embodiments of this application, the high work function material can be a metal, such as tantalum, titanium, molybdenum, tungsten, platinum, aluminum, hafnium, ruthenium, etc. The high work function material can also be a metal silicide, such as titanium silicide, cobalt silicide, nickel silicide, tantalum silicide, etc. The high work function material can also be a metal nitride, such as titanium nitride, tantalum nitride, etc. The low work function material can be polycrystalline silicon, or polycrystalline silicon doped with dopants such as phosphorus, arsenic, boron, indium, etc. This application does not specifically limit the application in this regard.

[0049] By further increasing the thickness of the low-power-function layer and decreasing the thickness of the high-power-function layer in the double-power-function embedded word line structure, the barrier of the gate-drain overlap region of the transistor can be increased. This makes it more difficult for tunneling current to form in the gate-drain overlap region, thus improving GIDL leakage current.

[0050] However, the resistivity of the material used in the low work function layer is greater than that of the material used in the high work function layer. Increasing the thickness of the low work function layer will increase the resistivity of the transistor, leading to an increase in tWR. tWR describes the number of clock cycles that must be waited for to complete a valid write operation and precharge in an active memory bank. This number of clock cycles ensures that data in the buffer can be written to the memory cell before precharge occurs. Therefore, it should be understood that an increase in tWR will affect memory performance.

[0051] To address the aforementioned issues, embodiments of this application provide a transistor, a memory array, a memory, and an electronic device that can ensure low GIDL leakage current while reducing the impact on the resistivity of the transistor, thereby improving storage security without significantly affecting storage performance.

[0052] It should be noted that the transistors, memory arrays, and memory provided in this application embodiment can be applied to various electronic devices, such as the memory of various electronic devices. These electronic devices may include personal computers, mobile phones, laptops, servers, wearable devices (such as smartwatches), in-vehicle devices, base stations, handheld devices, tablets, mobile internet devices (MIDs), virtual reality (VR) terminals, augmented reality (AR) terminals, and wireless terminals in industrial control, etc.

[0053] For example, please refer to FIG2, which is a schematic diagram of the structure of an electronic device provided in an embodiment of this application. As shown in FIG2, the electronic device may include a circuit board 201 and a memory 202. The memory 202 may include transistors and a memory array provided in the embodiments of this application. The memory 202 is integrated into the circuit board 201.

[0054] Circuit board 201 can refer to a printed circuit board (PCB). Circuit board 201 can also integrate devices such as a central processing unit (CPU) and power management chips (not shown in Figure 2), which are not limited here.

[0055] Memory 202 may refer to a single memory or include multiple memories, used to store program instructions. In one embodiment, memory 202 stores computer-readable instructions, and processor 201 executes each computer-readable instruction to perform corresponding operations.

[0056] The transistors, memory arrays, and electronic devices provided in the embodiments of this application are described below.

[0057] Please refer to Figure 3, which is a cross-sectional schematic diagram of a transistor provided in an embodiment of this application. As shown in Figure 3, the transistor includes a substrate 301 and a gate structure 302. A trench 311, a source region 321, and a drain region 331 are disposed on the substrate 301. The gate structure 302 is disposed within the trench 311. The bottom of the trench 311 can refer to the bottom of the trench 311 or the area near the bottom of the trench 311. The gate structure 302 includes a dielectric layer 312, a first filling region 322, a second filling region 332, and a third filling region 342. The dielectric layer 312 covers the inner surface of the trench 311. The filling material of the first filling region 322 is disposed in contact with the bottom of the trench 311, and the second filling region 332 is located above the first filling region 322. The third filling region 342 is located within the second filling region 332. The third filling region 342 is not in contact with the dielectric layer 312. The work function of the filling material in the first filling region 322 is greater than the work function of the filling material in the second filling region 332. The work function of the filling material in the third filling region 342 is greater than the work function of the filling material in the second filling region 332.

[0058] It should be noted that, in this embodiment of the application, the size and extent of the source and drain regions in the transistor are not limited, provided that a source and drain region are present. For example, in Figure 3, the source region 321 and drain region 331 can be located above the first filling region 322, on both sides of the trench 311. This increases the distance between the high work function material of the first filling region and the drain region, which helps to reduce the electric field strength between the first filling region and the drain region, thereby increasing the difficulty of tunneling current formation in the gate-drain overlap region, improving GIDL leakage current, and enhancing storage security. It should be understood that the above is merely an illustrative description and does not imply that this application is limited thereto.

[0059] The source region 321 and drain region 331 can be formed by doping the substrate with conductive impurities (such as phosphorus or boron). In other words, the relationship between the substrate 301, trench 311, source region 321, and drain region 331 in the transistor shown in Figure 3 can also be described as follows: a trench 311 is formed in the substrate 301. The source region 321 and drain region 331 are formed on the substrate on both sides of the trench 311 by doping with conductive impurities. The material of the substrate 301 can include semiconductor materials, such as one or more of silicon, germanium, silicon-germanium, and silicon carbide; it can also include silicon-on-insulator (SOI) or germanium-on-insulator (GOI); or it can include other materials, such as one or more of group III and V compounds such as gallium arsenide. The substrate 301 can also be doped with other substances as needed to change the electrical parameters; this embodiment of the application does not limit this.

[0060] The gate structure 302 can also be referred to as the gate, gate region, or gate electrode. The source region 321 can also be referred to as the source, source structure, or source electrode. The drain region 331 can also be referred to as the drain, drain structure, or drain electrode. This application does not limit these specific terms in its embodiments.

[0061] The cross-sectional structure of trench 311 can be U-shaped or concave, as shown in Figure 3, and is not limited thereto. In this embodiment, trench 311 can be formed by etching substrate 301 once or multiple times. Exemplarily, a pad oxide layer and a hard mask layer can be deposited on the surface of substrate 301 first. Then, a layer of photoresist is spin-coated on the upper surface of the hard mask layer. Then, an exposure and development process is performed using a mask to open the photoresist in the trench 311 region. Then, using the photoresist with an opening pattern as a mask, etching downwards etches openings into the hard mask layer and pad oxide layer in the trench 311 region. Then, using the hard mask layer and pad oxide layer with the opening pattern as a mask, the substrate 301 is etched further to form trench 311 in substrate 301. The material of the pad oxide layer is, for example, silicon oxide, and the material of the hard mask layer is, for example, silicon nitride. The method for forming the hard mask layer and pad oxide layer is, for example, chemical vapor deposition (CVD). It should be understood that this is merely an illustrative example and does not imply that this application is limited thereto. For example, regarding trench 311, the methods for forming the hard mask layer and the pad oxide layer can also be implemented with reference to the disclosed technology, and are not limited here.

[0062] A gate structure 302 is formed within a trench 311. The gate structure 302 includes a dielectric layer 312, a first filling region 322, a second filling region 332, and a third filling region 342. In other words, the dielectric layer 312, the first filling region 322, the second filling region 332, and the third filling region 342 are formed within the trench 311. In this embodiment, "within the trench 311" refers to the internal region of the cavity enclosed by the inner surface of the trench 311, which will not be described further hereafter.

[0063] The dielectric layer 312 may conformally cover the inner surface of the trench 311. Here, conformal coverage means that the dielectric layer 312 is adhered to the inner surface of the trench 311. The dielectric layer 312 may have a thickness of... to The silicon dioxide layer. The dielectric layer 312 may be formed by, but is not limited to, any of the following methods: formed by a wet or dry thermal oxidation process, wherein the formation environment includes oxides, water vapor, nitric oxide, or combinations thereof; formed by an in-situ steam generation (ISSG) process, wherein the formation environment includes oxygen, water vapor, nitric oxide, or combinations thereof; or formed by a chemical vapor deposition technique using tetraethyl orthosilicate (TEOS) and oxygen as precursors.

[0064] The first filling area 322 and the second filling area 332 can be located in different regions of the trench 311. The second filling area 332 is located above the first filling area 322. The first filling area 322 can be located near the bottom region of the trench 311. The second filling area 332 can be located near the opening region of the trench 311. For example, as shown in FIG3, the first filling area 322 can be located in the bottom region of the trench 311, and the second filling area 332 can be located in the opening region of the trench 311.

[0065] The third filling region 342 is located within the second filling region 332, and the third filling region 342 is not in contact with the dielectric layer 312. In some possible implementations, the second filling region 332 may surround the third filling region 342. For example, the second filling region 332 may surround the third filling region 342 in a U-shape as shown in FIG3. As another example, the second filling region 332 may also surround the third filling region 342 in a U-shape as shown in FIG4.

[0066] In some possible implementations, the thickness of the second fill region 332 can be between 0.5 nm and 15 nm. In other possible implementations, the volume ratio of the third fill region 342 to the second fill region 332 can be between 1 / 9 and 9. In still other possible implementations, the thickness of the second fill region 332 is between 0.5 nm and 15 nm, and the volume ratio of the third fill region 342 to the second fill region 332 is between 1 / 9 and 9.

[0067] The work function of the filling material in the first filling region 322 is greater than that of the filling material in the second filling region 332. The work function of the filling material in the third filling region 342 is greater than that of the filling material in the second filling region 332. In other words, the filling materials in the first filling region 322 and the third filling region 342 can both be high work function materials. The filling material in the second filling region 332 can be a low work function material.

[0068] Furthermore, in this embodiment, the third filling area can have various shapes. For example, as shown in FIG5, the second filling area 532 can surround the third filling area 542 in a U-shape. The surface of the third filling area 542 that does not contact the second filling area 332 is recessed. As another example, as shown in FIG6, the third filling area 642 can also be U-shaped. It should be understood that the above are merely exemplary descriptions of the shape of the third filling area; the third filling area can also be other shapes, such as an inverted U-shape, etc., and are not specifically limited here.

[0069] Based on the above description, it should be understood that in the transistor provided in this application embodiment, the second filling region is close to the channel, and the filling material of the second filling region has a low work function. Therefore, the electric field in the region of the second filling region close to the channel is low, which helps to increase the difficulty of tunneling current formation in the gate-drain overlap region, thereby improving GIDL leakage current. Furthermore, the filling material in the third filling region has a high work function, resulting in low resistivity and a low overall resistivity of the transistor. This can mitigate the problem of increased resistivity caused by using a low work function material in the gate structure, thereby improving timing problems caused by increased tWR.

[0070] In addition, the transistor structure provided in this application has the advantage of being relatively easy to implement.

[0071] In some possible implementations, the transistors provided in the embodiments of this application can be manufactured by the following steps. First, a trench, a source region, and a drain region can be formed on a substrate. For example, a trench can be formed on the substrate first, and then a source region and a drain region can be formed on the substrate and on both sides of the trench, respectively. Then, a gate structure can be formed in the trench. The gate structure includes a dielectric layer, a first filled region, a second filled region, and a third filled region. The dielectric layer covers the inner surface of the trench. The filling material of the first filled region is disposed in contact with the bottom of the trench, and the second filled region is located above the first filled region. The third filled region is located within the second filled region. The third filled region is not in contact with the dielectric layer. The work function of the filling material in the first filled region is greater than the work function of the filling material in the second filled region. The work function of the filling material in the third filled region is greater than the work function of the filling material in the second filled region.

[0072] It should be noted that the method for forming trenches on the substrate and forming source and drain regions on both sides of the trenches can refer to the description in the foregoing embodiments, and will not be repeated here.

[0073] In some other possible implementations, the transistors in the embodiments of this application can be obtained by further etching of transistors based on duplex function buried word line structures (or POR structures).

[0074] Please refer to Figure 7, which is a cross-sectional schematic diagram of a dual-function buried word-line structure transistor. As shown in Figure 7, the transistor includes a substrate 701 and a gate 702. A trench is formed in the substrate 701. A source region 721 and a drain region 731 are formed in the substrate on both sides of the trench, respectively. The gate 702 includes a dielectric layer 712, a high work function layer 722, and a low work function layer 732. The dielectric layer 712 conformally covers the inner wall of the trench. The high work function layer 722 is located near the bottom of the trench, and the low work function layer 732 is located near the opening of the trench.

[0075] For example, based on the transistor shown in Figure 7, a third filling region can be etched in the low work function layer 732 and filled with a high work function material. In this way, the transistor shown in Figure 3 can be obtained.

[0076] Furthermore, after obtaining the transistor shown in Figure 3, the filling material on the surface of the third filling region that is not in contact with the dielectric layer can be etched to form a depression. This yields the transistor shown in Figure 5. It should be understood that in the transistor shown in Figure 5, the filling material in the third filling region is less than that in the transistor shown in Figure 3. Therefore, the resistivity of the transistor shown in Figure 5 is lower than that of the transistor shown in Figure 3, and the tWR of the transistor shown in Figure 5 is lower than that of the transistor shown in Figure 3. In other words, the transistor design shown in Figure 5 is beneficial for further improving the transistor's storage performance.

[0077] For example, after obtaining the transistor shown in Figure 3, the third filling region can be etched to form a trench, and the trench can be filled with a low work function material. In this way, the transistor shown in Figure 6 can be obtained.

[0078] The structure of the transistor provided in the embodiments of this application has been described above. The following simulation comparison experiment, comparing the transistor with the buried word line structure transistor and the transistor provided in the embodiments of this application, verifies the effectiveness of the transistor provided in reducing GIDL leakage current.

[0079] Please refer to Figure 8, which is a simulation diagram of the electric field strength of a transistor according to an embodiment of this application. The two transistors are identical in size, and the word line voltage connected to them is -0.5V, while the bit line voltage is 1.5V. The work function of the high work function material can be 4.6eV, and the work function of the low work function material can be 4.0eV. Furthermore, the grayscale in Figure 8 represents the electric field strength. The larger the grayscale, the stronger the electric field.

[0080] As shown in Figure 8, the grayscale of the gate edge region in the transistor provided in this embodiment is less than that in the gate edge region of the duplex function buried word line structure transistor. This means the electric field strength in the gate edge region of the transistor provided in this embodiment is less than that in the gate edge region of the duplex function buried word line structure transistor. Therefore, in the transistor provided in this embodiment, it is more difficult for tunneling current to form in the gate-drain overlap region, resulting in a lower GIDL leakage effect.

[0081] The transistors provided in this application embodiment can be applied in memory cells. In other words, this application embodiment also provides a memory cell that includes the transistors described in any of the foregoing embodiments. For example, by replacing transistor 101 in the memory cell shown in FIG1 with the transistors provided in this application embodiment, the memory cell provided in this application embodiment can be obtained. The source and drain terminals can be interchanged, which will not be elaborated here.

[0082] Please refer to Figure 9. This application embodiment also provides a memory array. Figure 9 is a schematic diagram of the memory array. As shown in Figure 9, the memory array includes multiple word lines 901, multiple bit lines 902, multiple source lines 903, and multiple memory cells 904. The gate structure of the transistor in each memory cell 904 is connected to the word line 901. The first terminal of the transistor in each memory cell 903 is connected to the bit line 902, and the second terminal of the transistor in each memory cell 903 is connected to the source line 903. The first terminal can be the source of the transistor in the memory cell 903, and the second terminal can be the drain of the transistor in the memory cell 903. Alternatively, the first terminal can be the drain of the transistor in the memory cell 903, and the second terminal can be the source of the transistor in the memory cell 903.

[0083] Please refer to Figure 10. This application embodiment also provides a memory 1000, and Figure 10 is a schematic diagram of the structure of the memory 1000. As shown in Figure 10, the memory 300 may include one or more circuit structures selected from the following: a memory array 1001, a decoder 1002, a driver 1003, a timing controller 1004, a buffer 1005, or an input / output driver 1006. In one embodiment, the memory array 1001 includes a plurality of arrayed memory cells 1011, wherein each memory cell 1011 can be used to store 1 bit or more bits of data. In some possible implementations, the structure of the memory array 1001 may be as shown in Figure 9. In other possible implementations, the memory array 1001 may also include a word line (WL), a bit line (BL), a source line (SL), and a precharge line CL. Each memory cell 1011 is electrically connected to the corresponding word line WL, bit line BL, source line SL, and precharge line CL. Different memory cells 1011 can be electrically connected via WL, BL, SL, or CL. One or more of WL, BL, SL, and CL are used to select the memory cell 1011 to be read or written in the memory array by receiving the control level output from the control circuit, thereby changing the polarization direction of the capacitor in the memory cell 1011 to realize data read / write operations. For convenience, the above WL, BL, SL, and CL are collectively referred to as signal lines in this embodiment. Decoder 1002 is used to decode the address of memory cell 1011. Decoder 1002 is used to decode the received address to determine the memory cell 1011 to be accessed. Driver 1003 is used to control the level of the signal lines according to the decoding result generated by decoder 1002, thereby realizing access to the specified memory cell 1011. Buffer 1005 is used to buffer the read data, for example, by using FIFO (first-in first-out). The timing controller 1003 controls the timing of the buffer 1005 and controls the driver 1003 to drive the signal lines in the memory array 1001. The input / output driver 1006 drives transmission signals, such as the received data signal and the data signal to be sent, enabling the data signal to be transmitted over long distances. The memory array 1001, decoder 1002, driver 1003, timing controller 1004, buffer 1005, and input / output driver 1006 can be integrated into a single chip or integrated into multiple chips.

[0084] Please refer to Figure 11. This application embodiment also provides an electronic device. As shown in Figure 11, the electronic device 1100 can be a terminal device, such as a mobile phone, tablet computer, smart bracelet, or a personal computer (PC), server, workstation, etc. The electronic device 1100 includes a bus 1101 and a system-on-chip (SoC) 1102 connected to the bus 1101. The SoC 1102 can be used to process data, such as processing application data, processing image data, and caching temporary data. In one embodiment, the SoC 1102 may include an application processor (AP) 1112 for processing applications, a graphics processing unit (GPU) 1122 for processing image data, and a first RAM 1132 for caching high-speed data. The first RAM 1132 may be static random access memory (SRAM) or embedded flash memory (eflash), etc. The AP1112, GPU1122, and first RAM1132 described above can be integrated into a single die or disposed in multiple dies. The electronic device 1100 may also include a second RAM1103 connected to the SOC1102 via bus 1101. This second RAM1103 may be Dynamic Random Access Memory (DRAM). The second RAM1103 can be used to store volatile data, such as temporary data generated by the SOC1102. The storage capacity of the second RAM1103 is typically larger than that of the first RAM1132, but its read speed is typically slower. The second RAM1103 and the first RAM1132 can have the structure shown in Figure 10, which will not be elaborated upon here. Furthermore, the electronic device 1100 may also include a communication chip 1104 and a power management chip 1105 connected to the SOC1102 via bus 1101. The communication chip 1104 can be used for protocol stack processing, or for amplifying, filtering, or performing other processing on analog radio frequency signals, or simultaneously performing the above functions. The power management chip 1105 can be used to power other chips. In one embodiment, the SOC 1102 and the second RAM 1103 can be packaged in a single package structure, such as a 2.5D or 3D package, to achieve a faster inter-chip data transfer rate. It should be understood that the memory array, memory, and electronic device provided in the embodiments of this application all include the transistors in any of the foregoing embodiments, and therefore have similar beneficial effects, which will not be elaborated upon here.

[0085] The terms “first,” “second,” “third,” “fourth,” etc. (if present) in the specification, claims, and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a particular order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms “comprising” and “having,” and any variations thereof, are intended to cover non-exclusive inclusion.

[0086] Those skilled in the art should realize that the above one or more examples are only used to illustrate the technical solutions of this application, and not to limit them; although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the foregoing embodiments, or make equivalent substitutions for some of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application.

Claims

1. A transistor, characterized by, include: Substrate, gate structure; The substrate has trenches, a source region, and a drain region. The gate structure is disposed within the trench; The gate structure includes a dielectric layer, a first filling region, a second filling region, and a third filling region; The dielectric layer covers the inner surface of the trench; the filling material of the first filling area is disposed in contact with the bottom of the trench, and the second filling area is located above the first filling area; the third filling area is located within the second filling area; the third filling area is not in contact with the dielectric layer; The work function of the filling material in the first filling region is greater than the work function of the filling material in the second filling region; the work function of the filling material in the third filling region is greater than the work function of the filling material in the second filling region.

2. The transistor of claim 1, wherein The source and drain regions are located above the first filling region and on both sides of the trench.

3. The transistor according to claim 1 or 2, characterized in that, The filling material of the first filling region includes titanium nitride and / or tungsten; the filling material of the third filling region includes titanium nitride and / or tungsten.

4. The transistor according to any one of claims 1 to 3, wherein The filling material of the second filling region includes polycrystalline silicon.

5. The transistor according to any one of claims 1 to 4, wherein The second filling area surrounds the third filling area in a U-shape.

6. The transistor of claim 4, wherein The surface of the third filling area that does not contact the second filling area is concave.

7. The transistor according to any one of claims 1 to 4, wherein The second filling area surrounds the third filling area.

8. The transistor according to any one of claims 1 to 7, wherein The thickness of the second filling region is between 0.5 nanometers and 15 nanometers.

9. The transistor according to any one of claims 1 to 8, wherein The volume ratio of the third filling area to the second filling area is between one-ninth and nine-ninth.

10. The transistor according to any one of claims 1 to 9, wherein The third filling area is in the shape of a concave "U".

11. A memory array comprising: It includes word lines, bit lines, source lines, and multiple memory cells; each memory cell includes a capacitor and a transistor as described in any one of claims 1-10; the multiple memory cells are arranged in an array. The word line is connected to the gate structure of the transistor; the bit line is connected to the first terminal of the transistor; the source line is connected to the second terminal of the transistor through the capacitor. The first terminal and the second terminal are the source and drain of the transistor, respectively.

12. A memory, comprising: Includes the controller and the storage array as described in claim 11; The controller is connected to the storage array; the controller is used to access the storage array.

13. An electronic device, comprising: It includes a circuit board and the memory of claim 12; the memory is integrated on the circuit board.

14. A method of fabricating a transistor, characterized by: include: Trenches, source regions, and drain regions are formed on the substrate; A gate structure is formed within the trench; The gate structure includes a dielectric layer, a first filling region, a second filling region, and a third filling region. The dielectric layer covers the inner surface of the trench; the filling material of the first filling area is disposed in contact with the bottom of the trench, and the second filling area is located above the first filling area; the third filling area is located within the second filling area; the third filling area is not in contact with the dielectric layer; The work function of the filling material in the first filling region is greater than the work function of the filling material in the second filling region; the work function of the filling material in the third filling region is greater than the work function of the filling material in the second filling region.

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