Display substrate and manufacturing method therefor, and display device

Abstract

A display substrate and a manufacturing method therefor, and a display device. The display substrate comprises a driving circuit layer (102) disposed on a base (101); the driving circuit layer (102) at least comprises a plurality of circuit units; at least one circuit unit comprises a pixel driving circuit, and the pixel driving circuit comprises a driving transistor, a second switch transistor, and a capacitor; the driving transistor comprises a first active layer (13); the second switch transistor comprises a third active layer (19); the capacitor comprises a second electrode plate (15-1); the third active layer (19) is provided on the side of the first active layer (13) away from the base (101); the second electrode plate (15-1) is arranged between the first active layer (13) and the third active layer (19); the second electrode plate (15-1) is connected to a second end of the first active layer (13) by means of a first via hole (V1); the second electrode plate (15-1) forms a recessed region in the first via hole (V1); a dielectric layer (20) is provided on the side of the second electrode plate (15-1) away from the base (101); at least part of the dielectric layer (20) is provided in the recessed region; and the orthographic projection of the third active layer (19) on the base (101) overlaps the orthographic projection of the recessed region on the base (101).

Description

A display substrate, its fabrication method, and a display device.

[0001] This application claims priority to Chinese Patent Application No. 202411376822.X, filed on September 29, 2024, entitled "A display substrate and its preparation method, and a display device", the contents of which shall be construed as incorporated herein by reference. Technical Field

[0002] This article relates to, but is not limited to, the field of display technology, specifically to a display substrate and its preparation method, and a display device. Background Technology

[0003] Organic light-emitting diodes (OLEDs) and quantum dot light-emitting diodes (QLEDs) are active-matrix display devices with advantages such as self-illumination, wide viewing angle, high contrast, low power consumption, extremely high response speed, thinness, flexibility, and low cost. With the continuous development of display technology, flexible displays using OLEDs or QLEDs as light-emitting devices and controlled by thin-film transistors (TFTs) have become the mainstream products in the display field. Summary of the Invention

[0004] The following is an overview of the subject matter described in detail herein. This overview is not intended to limit the scope of the claims.

[0005] On one hand, this disclosure provides a display substrate, including a driving circuit layer disposed on a substrate. The driving circuit layer includes at least a plurality of circuit units, at least one of which includes a pixel driving circuit. The pixel driving circuit includes a driving transistor, a second switching transistor, and a capacitor. The driving transistor includes a first active layer, the second switching transistor includes a third active layer, and the capacitor includes a second electrode plate. The third active layer is disposed on the side of the first active layer away from the substrate. The second electrode plate is disposed between the first active layer and the third active layer. The second electrode plate is connected to a second end of the first active layer through a first via. The second electrode plate forms a recessed region in the first via. A dielectric layer is disposed on the side of the second electrode plate away from the substrate. At least a portion of the dielectric layer is disposed in the recessed region. The orthographic projection of the third active layer on the substrate overlaps with the orthographic projection of the recessed region on the substrate.

[0006] In an exemplary embodiment, the surface of the dielectric layer on the side away from the substrate forms a plane with the surface of the second electrode plate on the side away from the substrate.

[0007] In an exemplary embodiment, the orthographic projection of the third active layer onto the substrate includes the orthographic projection of the recessed region onto the substrate.

[0008] In an exemplary embodiment, the orthographic projection of the third active layer on the substrate overlaps with the orthographic projection of the first active layer on the substrate.

[0009] In an exemplary embodiment, the first via is polygonal in shape, and the length of at least one side of the first via is less than or equal to 1 micrometer; or, the first via is circular in shape, and the diameter of the first via is less than or equal to 1 micrometer; or, the first via is elliptical in shape, and the length of the minor axis of the first via is less than or equal to 1 micrometer.

[0010] In an exemplary embodiment, the driving transistor further includes a second gate disposed between the first active layer and the second electrode plate. The orthographic projection of the second gate on the substrate overlaps with the orthographic projection of the first active layer on the substrate. The capacitor includes a first electrode plate, with the second gate serving as the first electrode plate. The orthographic projection of the second gate on the substrate overlaps with the orthographic projection of the second electrode plate on the substrate.

[0011] In an exemplary embodiment, the driving transistor further includes a first gate located on the side of the first active layer near the substrate, wherein the orthographic projection of the first gate on the substrate overlaps with the orthographic projection of the first active layer on the substrate.

[0012] In an exemplary embodiment, the pixel driving circuit further includes a first power line, the first power signal line being disposed on the side of the third active layer away from the substrate, and the first power signal line being connected to a first end of the first active layer through a fifth via.

[0013] In an exemplary embodiment, the second switching transistor further includes a third gate located between the third active layer and the second electrode plate, wherein the orthographic projection of the third gate on the substrate overlaps with the orthographic projection of the third active layer on the substrate.

[0014] In an exemplary embodiment, a light-emitting structure layer is further included on the side of the driving circuit layer away from the substrate. The light-emitting structure layer includes a light-emitting device, which includes a first electrode, a light-emitting functional layer, and a second electrode arranged sequentially along the direction away from the substrate. The pixel driving circuit also includes a second connection electrode, which is located between the third active layer and the first electrode. At least a portion of the second connection electrode is in contact with the surface of the second end of the third active layer away from the substrate. The second connection electrode is connected to the second electrode plate through a sixth via and is connected to the first electrode.

[0015] In an exemplary embodiment, the pixel driving circuit further includes a sensing signal line located on the side of the third active layer away from the substrate, and at least a portion of the sensing signal line is in contact with the surface of the first end of the third active layer away from the substrate.

[0016] In an exemplary embodiment, the pixel driving circuit further includes a first switching transistor, the first switching transistor including a second active layer, the second active layer being located between the second electrode and the third active layer, a first transition electrode being disposed on the surface of the second active layer near the substrate, the first transition electrode being in contact with the second active layer, a second gate being disposed on the side of the first transition electrode near the substrate, the first transition electrode being connected to the second gate through a third via; the second gate serving as the gate electrode of the driving transistor.

[0017] In an exemplary embodiment, the orthographic projection of the second active layer onto the substrate includes the orthographic projection of the first transfer electrode onto the substrate.

[0018] In an exemplary embodiment, the orthographic projection of the first adapter electrode on the substrate includes the orthographic projection of the third via on the substrate.

[0019] In an exemplary embodiment, the pixel driving circuit further includes a first switching transistor, the first switching transistor including a second active layer, the second active layer being located between the second electrode and the third active layer, a second transition electrode being disposed on the surface of the second active layer near the substrate, the second transition electrode being in contact with the second active layer, a data signal line being disposed on the side of the second transition electrode near the substrate, and the second transition electrode being connected to the data signal line through a fourth via.

[0020] In an exemplary embodiment, the orthographic projection of the second active layer on the substrate includes the orthographic projection of the second transfer electrode on the substrate.

[0021] In an exemplary embodiment, the orthographic projection of the second adapter electrode on the substrate includes the orthographic projection of the fourth via on the substrate.

[0022] In an exemplary embodiment, the pixel driving circuit further includes a first connection electrode, which is located on the same film layer as the second electrode plate. The first connection electrode is located between the data signal line and the second adapter electrode. The second adapter electrode is connected to the first connection electrode through the fourth via, and the first connection electrode is connected to the data signal line through the second via.

[0023] On the other hand, this disclosure also provides a method for preparing a display substrate, comprising:

[0024] A driving circuit layer is formed on a substrate. The driving circuit layer includes at least a plurality of circuit units, at least one of which includes a pixel driving circuit. The pixel driving circuit includes a second switching transistor, a driving transistor, and a capacitor. The driving transistor includes a first active layer, the second switching transistor includes a third active layer, and the capacitor includes a second electrode plate. The third active layer is disposed on the side of the first active layer away from the substrate. The second electrode plate is disposed between the first active layer and the third active layer. The second electrode plate is connected to a second end of the first active layer through a first via. A recessed region is formed in the first via on the second electrode plate. A dielectric layer is disposed on the side of the second electrode plate away from the substrate. At least a portion of the dielectric layer is disposed in the recessed region. The orthographic projection of the third active layer on the substrate overlaps with the orthographic projection of the recessed region on the substrate.

[0025] On the other hand, this disclosure also provides a display device including the aforementioned display substrate.

[0026] Other features and advantages of this application will be set forth in the following description, and will be apparent in part from the description, or may be learned by practicing the application. Other advantages of this application can be realized and obtained by means of the solutions described in the description and the accompanying drawings. Attached Figure Description

[0027] The accompanying drawings are used to provide an understanding of the technical solutions of this application and constitute a part of the specification. They are used together with the embodiments of this application to explain the technical solutions of this application and do not constitute a limitation on the technical solutions of this application.

[0028] Figure 1 is a schematic diagram of a display device;

[0029] Figure 2 is a schematic diagram of a planar structure of a display substrate;

[0030] Figure 3 is a schematic cross-sectional view of a display substrate;

[0031] Figure 4 is an equivalent circuit diagram of a pixel driving circuit of a display substrate according to an exemplary embodiment of the present disclosure;

[0032] Figure 5a is a schematic diagram showing the formation of the first via in the fabrication process of the first via in a display substrate according to an exemplary embodiment of the present disclosure;

[0033] Figure 5b is a schematic diagram showing the formation of an inorganic dielectric layer during the fabrication process of a first via in a display substrate according to an exemplary embodiment of the present disclosure.

[0034] Figure 5c is a schematic diagram of the first via formed during the fabrication process of a first via in a display substrate according to an exemplary embodiment of the present disclosure.

[0035] Figure 6 is a schematic diagram of the formation of the first conductive layer pattern during the fabrication process of a display substrate according to an embodiment of the present disclosure;

[0036] Figures 7a and 7b are schematic diagrams showing the formation of a second conductive layer pattern during the fabrication process of a display substrate according to an embodiment of the present disclosure;

[0037] Figures 8a and 8b are schematic diagrams showing the formation of a first semiconductor layer pattern during the fabrication process of a display substrate according to an embodiment of the present disclosure;

[0038] Figures 9a and 9b are schematic diagrams showing the formation of a third conductive layer pattern during the fabrication process of a display substrate according to an embodiment of the present disclosure;

[0039] Figure 10 is a schematic diagram showing the formation of a fifth insulating layer pattern during the fabrication process of a display substrate according to an embodiment of the present disclosure;

[0040] Figures 11a and 11b are schematic diagrams showing the formation of a fourth conductive layer pattern during the fabrication process of a display substrate according to an embodiment of the present disclosure.

[0041] Figures 12a and 12b are schematic diagrams showing the formation of a dielectric layer during the fabrication process of a display substrate according to an embodiment of the present disclosure;

[0042] Figure 13 is a schematic diagram of the formation of the sixth insulating layer pattern during the fabrication process of a display substrate according to an embodiment of the present disclosure;

[0043] Figures 14a and 14b are schematic diagrams showing the formation of the fifth conductive layer pattern during the fabrication process of a display substrate according to an embodiment of the present disclosure;

[0044] Figures 15a, 15b and 15c are schematic diagrams showing the formation of a second semiconductor layer pattern during the fabrication process of a display substrate according to an embodiment of the present disclosure;

[0045] Figures 16a and 16b are schematic diagrams showing the formation of the sixth conductive layer pattern during the fabrication process of a display substrate according to an embodiment of the present disclosure.

[0046] Figures 17a, 17b and 17c are schematic diagrams showing the formation of a third semiconductor layer pattern during the fabrication process of a display substrate according to an embodiment of the present disclosure;

[0047] Figure 18 is a schematic diagram showing the formation of the eighth insulating layer pattern during the fabrication process of a display substrate according to an embodiment of the present disclosure;

[0048] Figures 19a and 19b are schematic diagrams showing the formation of the seventh conductive layer pattern during the fabrication process of a display substrate according to an embodiment of the present disclosure;

[0049] Figure 20 is a schematic diagram showing the formation of the ninth insulating layer pattern during the fabrication process of a display substrate according to an embodiment of the present disclosure;

[0050] Figures 21a and 21b are schematic diagrams showing the formation of the eighth conductive layer pattern during the fabrication process of a display substrate according to an embodiment of the present disclosure. Detailed Implementation

[0051] This application describes several embodiments, but these descriptions are exemplary and not restrictive, and it will be apparent to those skilled in the art that many more embodiments and implementations are possible within the scope of the embodiments described herein. Although many possible combinations of features are shown in the drawings and discussed in the detailed description, many other combinations of the disclosed features are also possible. Unless specifically limited, any feature or element of any embodiment may be used in combination with, or may replace, any feature or element of any other embodiment.

[0052] This application includes and contemplates combinations of features and elements known to those skilled in the art. The embodiments, features, and elements disclosed in this application can also be combined with any conventional features or elements to form unique inventive solutions. Any feature or element of any embodiment can also be combined with features or elements from other inventive solutions to form another unique inventive solution. Therefore, it should be understood that any feature shown and / or discussed in this application can be implemented individually or in any suitable combination. Therefore, the embodiments are not limited except by the limitations imposed by the appended claims and their equivalents. Furthermore, various modifications and changes can be made within the scope of the appended claims.

[0053] Furthermore, in describing representative embodiments, the specification may have presented methods and / or processes as a specific sequence of steps. However, the method or process should not be limited to the specific order of steps described herein, to the extent that it does not depend on such a specific order. As will be understood by those skilled in the art, other sequences of steps are also possible. Therefore, the specific order of steps set forth in the specification should not be construed as a limitation of the claims. Moreover, the claims concerning the method and / or process should not be limited to the steps performed in the written order, and those skilled in the art will readily understand that these orders can be varied and still remain within the spirit and scope of the embodiments of this application.

[0054] The inventors of this publication have discovered that in the relevant display backplane design, the active layers of the low-temperature polycrystalline silicon thin-film transistors and the oxide thin-film transistors do not overlap with the underlying deep vias. This prevents the semiconductor layers from climbing over the vias and causing morphological differences that lead to non-uniform characteristics. In the relevant display backplane, the active layers do not overlap with the deep vias, resulting in inefficient space utilization, reduced channel length, and smaller storage capacitance. This leads to adverse effects such as short-channel effects and parasitic capacitance, ultimately causing display abnormalities.

[0055] Figure 1 is a schematic diagram of a display device. As shown in Figure 1, the display device may include a timing controller, a data driver, a scan driver, a light-emitting driver, and a pixel array. The timing controller is connected to the data driver, the scan driver, and the light-emitting driver. The data driver is connected to multiple data signal lines (D1 to Dn), the scan driver is connected to multiple scan signal lines (S1 to Sm), and the light-emitting driver is connected to multiple light-emitting signal lines (E1 to Eo). The pixel array may include multiple sub-pixels Pxij, where i and j can be natural numbers. At least one sub-pixel Pxij may include a circuit unit and a light-emitting unit. The circuit unit may include at least a pixel driving circuit, which is connected to the scan signal lines, the light-emitting signal lines, and the data signal lines. The light-emitting unit may include a light-emitting device, which is connected to the pixel driving circuit of the circuit unit. In an exemplary embodiment, the timing controller can provide grayscale values ​​and control signals of specifications suitable for the data driver to the data driver, provide clock signals, scan start signals, etc. of specifications suitable for the scan driver to the scan driver, and provide clock signals, transmit stop signals, etc. of specifications suitable for the light-emitting driver to the light-emitting driver. The data driver can use grayscale values ​​and control signals received from the timing controller to generate data voltages to be provided to data signal lines D1, D2, D3, ..., Dn. For example, the data driver can sample grayscale values ​​using a clock signal and apply data voltages corresponding to the grayscale values ​​to data signal lines D1 to Dn in pixel rows, where n can be a natural number. The scan driver can generate scan signals to be provided to scan signal lines S1, S2, S3, ..., Sm by receiving clock signals, scan start signals, etc., from the timing controller. For example, the scan driver can sequentially provide scan signals with on-level pulses to scan signal lines S1 to Sm. For example, the scan driver can be configured as a shift register and can generate scan signals by sequentially transmitting scan start signals in the form of on-level pulses to the next stage circuit under the control of a clock signal, where m can be a natural number. The light-emitting driver can generate transmit signals to be provided to light-emitting signal lines E1, E2, E3, ..., Eo by receiving clock signals, transmit stop signals, etc., from the timing controller. For example, the light-emitting driver can sequentially provide transmit signals with cutoff level pulses to the light-emitting signal lines E1 to Eo. For example, the light-emitting driver can be configured as a shift register and can generate transmit signals by sequentially transmitting transmit stop signals in the form of cutoff level pulses to the next stage circuit under the control of a clock signal, where o can be a natural number. In an exemplary embodiment, a pixel array can be disposed on a display substrate.

[0056] Figure 2 is a schematic diagram of a planar structure of a display substrate. In an exemplary embodiment, the display substrate may include a display area and a border area surrounding the display area. As shown in Figure 2, the display area of ​​the display substrate may include a plurality of pixel units P arranged in a matrix. At least one pixel unit P may include a first sub-pixel P1 emitting a first color light, a second sub-pixel P2 emitting a second color light, and a third sub-pixel P3 emitting a third color light. Each sub-pixel may include a circuit unit and a light-emitting unit. The circuit unit may include at least a pixel driving circuit, which is connected to a scan signal line, a data signal line, and a light-emitting signal line, respectively. The pixel driving circuit is configured to receive the data voltage transmitted by the data signal line and output a corresponding current to the light-emitting device under the control of the scan signal line and the light-emitting signal line. The light-emitting unit may include at least a light-emitting device, which is connected to the pixel driving circuit of the sub-pixel and is configured to emit light of a corresponding brightness in response to the current output by the pixel driving circuit of the sub-pixel.

[0057] In an exemplary embodiment, the first sub-pixel P1 can be a red sub-pixel (R) that emits red light, the second sub-pixel P2 can be a blue sub-pixel (B) that emits blue light, and the third sub-pixel P3 can be a green sub-pixel (G) that emits green light. In an exemplary embodiment, the shape of the sub-pixels can be rectangular, rhomboid, pentagonal, or hexagonal, and the three sub-pixels can be arranged in a horizontal, vertical, or triangular manner, etc., which is not limited herein.

[0058] In an exemplary embodiment, a pixel unit may include four sub-pixels, which may be arranged in a horizontal, vertical, or square manner, etc., and this disclosure does not limit the arrangement.

[0059] Figure 3 is a cross-sectional schematic diagram of a display substrate, illustrating the structure of three sub-pixels in the display substrate. As shown in Figure 3, on a plane perpendicular to the display substrate, the display area of ​​the display substrate may include a driving circuit layer 102 disposed on a substrate 101, a light-emitting structure layer 103 disposed on the side of the driving circuit layer 102 away from the substrate 101, and an encapsulation structure layer 104 disposed on the side of the light-emitting structure layer 103 away from the substrate 101. In some possible implementations, the display substrate may include other film layers, such as a touch structure layer, etc., which are not limited herein.

[0060] In an exemplary embodiment, the substrate 101 can be a flexible substrate or a rigid substrate. The driving circuit layer 102 can include multiple circuit units, each of which can include at least a pixel driving circuit, and the pixel driving circuit can include multiple transistors and storage capacitors. The light-emitting structure layer 103 can include multiple light-emitting units, each of which can include at least a light-emitting device. The light-emitting device can include an anode, an organic light-emitting layer, and a cathode. The anode is connected to the pixel driving circuit, the organic light-emitting layer is connected to the anode, and the cathode is connected to the organic light-emitting layer. The organic light-emitting layer emits light of a corresponding color under the driving of the anode and cathode. The encapsulation structure layer 104 can include a first encapsulation layer, a second encapsulation layer, and a third encapsulation layer stacked together. The first and third encapsulation layers can be made of inorganic materials, and the second encapsulation layer can be made of organic materials. The second encapsulation layer is disposed between the first and third encapsulation layers, forming an inorganic / organic / inorganic material stacked structure, which can ensure that external moisture cannot enter the light-emitting structure layer 103.

[0061] In an exemplary embodiment, the organic light-emitting layer may include a light-emitting layer (EML) and any one or more of the following: a hole injection layer (HIL), a hole transport layer (HTL), an electron blocking layer (EBL), a hole blocking layer (HBL), an electron transport layer (ETL), and an electron injection layer (EIL).

[0062] The display substrate of this disclosure will be illustrated by some exemplary embodiments below.

[0063] Figure 4 is an equivalent circuit diagram of a pixel driving circuit for a display substrate according to an exemplary embodiment of the present disclosure. In an exemplary embodiment, the pixel driving circuit may be a 3T1C, 4T1C, 5T1C, 5T2C, 6T1C, 7T1C, 8T1C, or 9T2C structure. As shown in Figure 4, the pixel driving circuit of the exemplary embodiment of the present disclosure may be a 3T1C structure, which may include three transistors (first transistor T1 to third transistor T3) and one storage capacitor C. The pixel driving circuit is connected to the sensing signal line SL, the data signal line DATA, the first power supply line VDD, the second power supply line VSS, and the scan signal line SCAN, respectively.

[0064] In an exemplary embodiment, the pixel driving circuit may include a first node N1, a second node N2, a fourth node N4, and a fifth node N5. The first node N1 is connected to the second terminal of the second transistor, the gate of the first transistor T1, and the first terminal of the storage capacitor C. The second node N2 is connected to the second terminal of the third transistor, the second terminal of the storage capacitor C, the second terminal of the first transistor T1, and the first terminal of the light-emitting device EL. The fourth node N4 is connected to the data signal line DATA and the first terminal of the second transistor. The fifth node N5 is connected to the sensing signal line SL and the first terminal of the third transistor.

[0065] In an exemplary embodiment, the first end (first plate) of the storage capacitor C is connected to the first node N1, and the second end (second plate) of the storage capacitor C is connected to the second node N2.

[0066] In an exemplary embodiment, the first transistor T1 is a driving transistor; the second transistor T2 is a first switching transistor used for writing data signals; and the third transistor T3 is a second switching transistor used for extracting threshold voltage or current.

[0067] In an exemplary embodiment, the gate electrode of the first transistor T1 is connected to the first node N1, and through the first node N1, it is connected to the second terminal of the second transistor and the first terminal of the storage capacitor C. The first terminal of the first transistor T1 is connected to the first power line VDD, and the second terminal of the first transistor T1 is connected to the second node N2. Through the second node N2, it is connected to the second terminal of the third transistor, the second terminal of the storage capacitor C, and the first terminal of the light-emitting device EL. The second terminal of the light-emitting device EL is connected to the second power line VSS. The first transistor T1 is used to generate a corresponding current at its second terminal under the control of the data signal received at its gate electrode, thereby controlling the light-emitting device EL to emit light. The gate electrode of the second transistor T2 is connected to the scan signal line SCAN, and the first terminal of the second transistor T2 is connected to the data signal line DATA through the fourth node N4. The second terminal of the second transistor T2 is connected to the first node N1, and through the first node N1, it is connected to the first terminal of the capacitor C and the gate of the first transistor T1. The second transistor T2 is used to receive the data signal transmitted by the data signal line DATA under the control of the scan signal line SCAN. The gate electrode of the third transistor T3 is connected to the scan signal line SCAN. The first terminal of the third transistor T3 is connected to the sensing signal line SL through the fifth node N5. The second terminal of the third transistor T3 is connected to the second node N2. It is connected to the second terminal of the capacitor C, the second terminal of the first transistor T1, and the first terminal of the light-emitting device EL through the second node N2. The third transistor T3 is used to extract the threshold voltage Vth and mobility of the third transistor T3 in response to the compensation timing, so as to compensate for the threshold voltage Vth.

[0068] In an exemplary embodiment, the light-emitting device EL can be an OLED, including a stacked first electrode (anode), a light-emitting functional layer, and a second electrode (cathode); the light-emitting device EL can be a QLED, including a stacked first electrode (anode), a quantum dot light-emitting layer, and a second electrode (cathode); or, the light-emitting device EL can be an LED.

[0069] In an exemplary embodiment, the first electrode of the light-emitting device EL is connected to the second node N2, and the second electrode of the light-emitting device EL is connected to the second power line VSS. The signal of the second power line VSS is a continuously provided low-level signal, and the signal of the first power line VDD is a continuously provided high-level signal.

[0070] In an exemplary embodiment, the second transistor T2 and the third transistor T3 can be oxide thin-film transistors, and the first transistor T1 can be a low-temperature polycrystalline silicon (LTPS) thin-film transistor. The active layer of the LTPS thin-film transistor is made of low-temperature polycrystalline silicon (LTPS), while the active layer of the oxide thin-film transistor is made of oxide semiconductor. LTPS thin-film transistors have advantages such as high mobility and fast charging, while oxide thin-film transistors have advantages such as low leakage current. Integrating LTPS and oxide thin-film transistors onto a single display substrate, i.e., an LTPS+Oxide (LTPO) display substrate, leverages the advantages of both, enabling low-frequency driving, reducing power consumption, and improving display quality.

[0071] This disclosure provides a display substrate including a driving circuit layer disposed on a substrate. The driving circuit layer includes at least a plurality of circuit units, at least one of which includes a pixel driving circuit. The pixel driving circuit includes a driving transistor, a second switching transistor, and a capacitor. The driving transistor includes a first active layer, the second switching transistor includes a third active layer, and the capacitor includes a second electrode plate. The third active layer is disposed on the side of the first active layer away from the substrate. The second electrode plate is disposed between the first active layer and the third active layer. The second electrode plate is connected to a second end of the first active layer through a first via. A recessed region is formed in the first via on the second electrode plate. A dielectric layer is disposed on the side of the second electrode plate away from the substrate. At least a portion of the dielectric layer is disposed in the recessed region. The orthographic projection of the third active layer on the substrate overlaps with the orthographic projection of the recessed region on the substrate.

[0072] In an exemplary embodiment, the surface of the dielectric layer on the side away from the substrate forms a plane with the surface of the second electrode plate on the side away from the substrate.

[0073] In an exemplary embodiment, the orthographic projection of the third active layer onto the substrate includes the orthographic projection of the recessed region onto the substrate.

[0074] In an exemplary embodiment, the orthographic projection of the third active layer on the substrate overlaps with the orthographic projection of the first active layer on the substrate.

[0075] In an exemplary embodiment, the first via is polygonal in shape, and the length of at least one side of the first via is less than or equal to 1 micrometer; or, the first via is circular in shape, and the diameter of the first via is less than or equal to 1 micrometer; or, the first via is elliptical in shape, and the length of the minor axis of the first via is less than or equal to 1 micrometer.

[0076] In an exemplary embodiment, the driving transistor further includes a second gate disposed between the first active layer and the second electrode plate. The orthographic projection of the second gate on the substrate overlaps with the orthographic projection of the first active layer on the substrate. The capacitor includes a first electrode plate, with the second gate serving as the first electrode plate. The orthographic projection of the second gate on the substrate overlaps with the orthographic projection of the second electrode plate on the substrate.

[0077] In an exemplary embodiment, the driving transistor further includes a first gate located on the side of the first active layer near the substrate, wherein the orthographic projection of the first gate on the substrate overlaps with the orthographic projection of the first active layer on the substrate.

[0078] In an exemplary embodiment, the pixel driving circuit further includes a first power line, the first power signal line being disposed on the side of the third active layer away from the substrate, and the first power signal line being connected to a first end of the first active layer through a fifth via.

[0079] In an exemplary embodiment, the second switching transistor further includes a third gate located between the third active layer and the second electrode plate, wherein the orthographic projection of the third gate on the substrate overlaps with the orthographic projection of the third active layer on the substrate.

[0080] In an exemplary embodiment, a light-emitting structure layer is further included on the side of the driving circuit layer away from the substrate. The light-emitting structure layer includes a light-emitting device, which includes a first electrode, a light-emitting functional layer, and a second electrode arranged sequentially along the direction away from the substrate. The pixel driving circuit also includes a second connection electrode, which is located between the third active layer and the first electrode. At least a portion of the second connection electrode is in contact with the surface of the second end of the third active layer away from the substrate. The second connection electrode is connected to the second electrode plate through a sixth via and is connected to the first electrode.

[0081] In an exemplary embodiment, the pixel driving circuit further includes a sensing signal line located on the side of the third active layer away from the substrate, and at least a portion of the sensing signal line is in contact with the surface of the first end of the third active layer away from the substrate.

[0082] In an exemplary embodiment, the pixel driving circuit further includes a first switching transistor, the first switching transistor including a second active layer, the second active layer being located between the second electrode and the third active layer, a first transition electrode being disposed on the surface of the second active layer near the substrate, the first transition electrode being in contact with the second active layer, a second gate being disposed on the side of the first transition electrode near the substrate, the first transition electrode being connected to the second gate through a third via; the second gate serving as the gate electrode of the driving transistor.

[0083] In an exemplary embodiment, the orthographic projection of the second active layer onto the substrate includes the orthographic projection of the first transfer electrode onto the substrate.

[0084] In an exemplary embodiment, the orthographic projection of the first adapter electrode on the substrate includes the orthographic projection of the third via on the substrate.

[0085] In an exemplary embodiment, the pixel driving circuit further includes a first switching transistor, the first switching transistor including a second active layer, the second active layer being located between the second electrode and the third active layer, a second transition electrode being disposed on the surface of the second active layer near the substrate, the second transition electrode being in contact with the second active layer, a data signal line being disposed on the side of the second transition electrode near the substrate, and the second transition electrode being connected to the data signal line through a fourth via.

[0086] In an exemplary embodiment, the orthographic projection of the second active layer on the substrate includes the orthographic projection of the second transfer electrode on the substrate.

[0087] In an exemplary embodiment, the orthographic projection of the second adapter electrode on the substrate includes the orthographic projection of the fourth via on the substrate.

[0088] In an exemplary embodiment, the pixel driving circuit further includes a first connection electrode, which is located on the same film layer as the second electrode plate. The first connection electrode is located between the data signal line and the second adapter electrode. The second adapter electrode is connected to the first connection electrode through the fourth via, and the first connection electrode is connected to the data signal line through the second via.

[0089] The following description uses the fabrication process of a display substrate as an example. The "patterning process" described in this disclosure includes, for metallic, inorganic, or transparent conductive materials, processes such as photoresist coating, mask exposure, development, etching, and photoresist stripping; for organic materials, it includes processes such as organic material coating, mask exposure, and development. Deposition can be performed using any one or more of sputtering, evaporation, and chemical vapor deposition; coating can be performed using any one or more of spraying, spin coating, and inkjet printing; etching can be performed using any one or more of dry etching and wet etching. This disclosure does not limit the methods used. A "thin film" refers to a thin film made of a certain material on a substrate using deposition, coating, or other processes. If the "thin film" does not require a patterning process during the entire fabrication process, it can also be called a "layer." If the "thin film" requires a patterning process during the entire fabrication process, it is called a "thin film" before the patterning process and a "layer" after the patterning process. The "layer" after the patterning process contains at least one "pattern." The phrase "A and B are arranged in the same layer" in this disclosure means that A and B are formed simultaneously through the same patterning process, and the "thickness" of the film layer is the dimension of the film layer in the direction perpendicular to the display substrate. In the exemplary embodiments of this disclosure, "the orthographic projection of B is within the range of the orthographic projection of A" or "the orthographic projection of A includes the orthographic projection of B" means that the boundary of the orthographic projection of B falls within the boundary range of the orthographic projection of A, or the boundary of the orthographic projection of A overlaps with the boundary of the orthographic projection of B.

[0090] In an exemplary embodiment, the circuit unit referred to in this disclosure refers to a region divided according to the pixel driving circuit, and the light-emitting unit referred to in this disclosure refers to a region divided according to the light-emitting device.

[0091] In an exemplary embodiment, the position of the light-emitting unit projected onto the substrate may correspond to the position of the circuit unit projected onto the substrate, or the position of the light-emitting unit projected onto the substrate may not correspond to the position of the circuit unit projected onto the substrate.

[0092] In an exemplary embodiment, a plurality of circuit units arranged sequentially along the first direction D1 can be referred to as a unit row, and a plurality of circuit units arranged sequentially along the second direction D2 can be referred to as a unit column. The plurality of unit rows and the plurality of unit columns constitute an array of circuit units arranged in an array. The first direction D1 intersects the second direction D2. For example, the first direction D1 is perpendicular to the second direction D2.

[0093] In an exemplary embodiment, taking three circuit units in the m-th row and three circuit units in the (m+1)-th row as an example, the substrate fabrication process in this embodiment may include the following operations.

[0094] (101) Forming a first conductive layer pattern. In an exemplary embodiment, forming a first conductive layer pattern may include: sequentially depositing a first insulating film and a first conductive film on a substrate, patterning the first conductive film using a patterning process to form a first insulating layer covering the substrate, and forming a first conductive layer pattern disposed on the first insulating layer, as shown in FIG6.

[0095] In an exemplary embodiment, the first conductive layer pattern may include data signal lines 11, which may be strip-shaped and extend along the second direction D2. The data signal lines 11 of the circuit cells adjacent to each other in the second direction D2 in the m-th cell row and the (m+1)-th cell row may be connected as a single unit.

[0096] In an exemplary embodiment, the data signal line 11 has first connecting portions 11-1 on opposite sides in the first direction D1. The first connecting portions 11-1 can be rectangular blocks and extend out from opposite sides of the data signal line 11 in the first direction D1. The first connecting portions 11-1 of the data signal line 11 of the circuit unit in the m-th unit row are located at one end of the data signal line 11 in the opposite direction of the second direction D2, and the first connecting portions 11-1 of the data signal line 11 of the circuit unit in the (m+1)-th unit row are located at one end of the data signal line 11 in the second direction D2. The first connecting portions 11-1 of the circuit units adjacent in the second direction D2 in the m-th unit row and the (m+1)-th unit row are connected as one unit.

[0097] In an exemplary embodiment, the data signal line 11 can be a single-layer structure, such as copper or molybdenum; or, the data signal line 11 can be a multi-layer structure, such as a titanium / aluminum / titanium stacked structure.

[0098] In an exemplary embodiment, the first insulating layer may be a silicon nitride compound or a silicon oxide compound.

[0099] (102) Forming a second conductive layer pattern. In an exemplary embodiment, forming a second conductive layer pattern may include: sequentially depositing a second insulating film and a second conductive film on a substrate on which the aforementioned pattern is formed; patterning the second conductive film using a patterning process to form a second insulating layer covering the first conductive layer pattern; and forming a second conductive layer pattern disposed on the second insulating layer, as shown in Figures 7a and 7b.

[0100] In an exemplary embodiment, the second conductive layer pattern may include a first gate 12, which includes a first portion 12-1 extending along a first direction D1 and a second portion 12-2 extending along a second direction D2. In the m-th unit row, the first portion 12-1 of a circuit unit is located on one side of the circuit unit in the second direction D2. The first portions 12-1 of adjacent circuit units in the m-th unit row are connected to form a strip structure extending along the first direction D1. The second portion 12-2 of the circuit unit in the m-th unit row is connected to the first portion 12-1 on the opposite side of the second direction D2. In the (m+1)-th unit row, the first portion 12-1 of a circuit unit is located on the opposite side of the circuit unit in the second direction D2. The first portions 12-1 of adjacent circuit units in the (m+1)-th unit row are connected to form a strip structure extending along the first direction D1. The second portion 12-2 of the circuit unit in the (m+1)-th unit row is connected to the first portion 12-1 on the opposite side of the second direction D2.

[0101] In an exemplary embodiment, the first gate 12 may be a single-layer structure, such as copper or molybdenum; or, the first gate 12 may be a multi-layer structure, such as a titanium / aluminum / titanium stacked structure.

[0102] In an exemplary embodiment, the second insulating layer may be a silicon nitride compound.

[0103] (103) Forming a first semiconductor layer pattern. In an exemplary embodiment, forming a first semiconductor layer pattern may include: depositing a third insulating film and a first semiconductor film sequentially on a substrate on which the aforementioned pattern is formed; patterning the first semiconductor film using a patterning process to form a third insulating layer covering the second conductive layer pattern; and forming a first semiconductor layer pattern disposed on the third insulating layer using the first semiconductor film, as shown in Figures 8a and 8b.

[0104] In an exemplary embodiment, the first semiconductor layer pattern may include a first active layer 13. The first active layer 13 includes a first main body portion 13-1 extending along the second direction D2, and a second connecting portion 13-2 and a third connecting portion 13-3 disposed at opposite ends of the first main body portion 13-1 in the second direction D2. The first main body portion 13-1 may be strip-shaped, and the second connecting portion 13-2 and the third connecting portion 13-3 may be rectangular blocks. The orthographic projection of the first main body portion 13-1 on the substrate overlaps with the orthographic projection of the first gate 12 on the substrate, while the orthographic projections of the second connecting portion 13-2 and the third connecting portion 13-3 on the substrate do not overlap with the orthographic projection of the first gate 12 on the substrate. The third connecting portion 13-3 serves as the first end of the first transistor T1 and is connected to the first power signal line. The second connecting portion 13-2 serves as the second end of the first transistor T1 and is connected to the first electrode of the light-emitting device, the first plate (second gate 14) of the capacitor C, and the second end of the third transistor T3.

[0105] In an exemplary embodiment, the first active layer 13 may be low-temperature polycrystalline silicon.

[0106] In an exemplary embodiment, the third insulating layer may be a silicon nitride compound or a silicon oxide compound.

[0107] (104) Forming a third conductive layer pattern. In an exemplary embodiment, forming a third conductive layer pattern may include: depositing a fourth insulating film and a third conductive layer sequentially on a substrate on which the aforementioned pattern is formed; patterning the third conductive layer by a patterning process; forming a fourth insulating film that covers the pattern of the first semiconductor layer; and forming a third conductive layer pattern disposed on the fourth insulating layer, as shown in Figures 9a and 9b.

[0108] In an exemplary embodiment, the third conductive layer pattern may include a second gate 14, which may be rectangular in shape. The orthographic projection of the second gate 14 onto the substrate overlaps with the orthographic projection of the first main body portion 13-1 of the first active layer 13 onto the substrate. However, the orthographic projections of the second gate 14 onto the substrate do not overlap with the orthographic projections of the second connecting portion 13-2 and the third connecting portion 13-3 onto the substrate. The first gate 12, the second gate 14, and the first active layer 13 form a first transistor T1, which is a dual-gate structure. The first gate 12 and the second gate 14 are the two gate electrodes of the first transistor T1.

[0109] In an exemplary embodiment, the second gate 14 may be a single-layer structure, such as copper or molybdenum; or, the second gate 14 may be a multi-layer structure, such as a titanium / aluminum / titanium stacked structure.

[0110] In an exemplary embodiment, the fourth insulating layer may be a silicon nitride compound or a silicon oxide compound.

[0111] (105) Forming a fifth insulating layer pattern. In an exemplary embodiment, forming a fifth insulating layer pattern may include: depositing a fifth insulating film on a substrate on which the aforementioned pattern is formed, and patterning the fifth insulating film using a patterning process to form a fifth insulating layer covering the third conductive layer pattern, wherein the fifth insulating layer in each circuit unit is provided with a plurality of vias, as shown in FIG10.

[0112] In an exemplary embodiment, the plurality of vias in the fifth insulating layer of each circuit unit include a first via V1 and a second via V2. The orthographic projection of the first via V1 on the substrate is located within the orthographic projection of the third connection portion 13-3 of the first active layer 13 on the substrate. The fifth and fourth insulating layers within the first via V1 are etched away, exposing the surface of the second connection portion 13-2 of the first active layer 13. The first via V1 is configured to allow the subsequently formed second electrode plate 15-1 to be connected to the second connection portion 13-2 of the first active layer 13 through the via.

[0113] In an exemplary embodiment, the orthographic projection of the second via V2 on the substrate is located within the orthographic projection of the first connection portion 11-1 of the data signal line 11 on the substrate. The fifth, fourth, third, and second insulating layers within the second via V2 are etched away, exposing the surface of the first connection portion 11-1 of the data signal line 11. The second via V2 is configured to allow the subsequently formed first connection electrode 15-2 to be connected to the first connection portion 11-1 of the data signal line 11 through the via.

[0114] In an exemplary embodiment, the second via V2 of the circuit cells in the m-th cell row and the (m+1)-th cell row adjacent to each other in the second direction D2 are connected as one unit.

[0115] (106) Forming a fourth conductive layer pattern. In an exemplary embodiment, forming a fourth conductive layer pattern may include: depositing a fourth conductive layer on a substrate on which the aforementioned pattern is formed, and patterning the fourth conductive layer by a patterning process, so that the fourth conductive film forms a fourth conductive layer pattern disposed on a fifth insulating layer, as shown in Figures 11a and 11b.

[0116] In an exemplary embodiment, the fourth conductive layer pattern includes a second electrode 15-1 and a first connecting electrode 15-2, both of which are rectangular blocks. The second electrode 15-1 of the circuit unit in the m-th row is located on one side of the first connecting electrode 15-2 in the m-th row of the circuit unit, and the second electrode 15-1 of the circuit unit in the (m+1)-th row of the circuit unit is located on the opposite side of the first connecting electrode 15-2 in the (m+1)-th row of the circuit unit. The first connecting electrodes 15-2 of the circuit units adjacent to each other in the second direction D2 in the m-th and (m+1)-th rows are connected as a single unit.

[0117] In an exemplary embodiment, the orthographic projection of the first portion of the second electrode plate 15-1 onto the substrate overlaps with the orthographic projection of the second gate 14 onto the substrate, forming a capacitor C. The second gate 14 serves as the first electrode plate of the capacitor C.

[0118] In an exemplary embodiment, a second portion of the second electrode plate 15-1 is connected to a second connection portion 13-2 of the first active layer 13 via a first via V1. The second portion of the second electrode plate 15-1 forms a recessed region in the first via V1.

[0119] In an exemplary embodiment, the first connection electrode 15-2 is connected to the first connection portion 11-1 of the data signal line 11 through the second via V2.

[0120] In an exemplary embodiment, both the second electrode 15-1 and the first connecting electrode 15-2 can be single-layer structures, such as copper or molybdenum; or, both the second electrode 15-1 and the first connecting electrode 15-2 can be multi-layer structures, such as titanium / aluminum / titanium stacked structures.

[0121] In an exemplary embodiment, the fifth insulating layer may be a silicon nitride compound or a silicon oxide compound.

[0122] (107) Forming a dielectric layer. In an exemplary embodiment, forming a dielectric layer may include: depositing an organic insulating film on a substrate on which the aforementioned pattern is formed; patterning the organic insulating film through an exposure and development process to form a dielectric pattern disposed on the pattern of the fourth conductive layer; subsequently, patterning the dielectric pattern through an ashing process to form a dielectric layer 20, as shown in Figures 12a and 12b. Figure 12b may be a cross-sectional view along the a-a' direction in Figure 12a.

[0123] In an exemplary embodiment, the orthographic projection of the dielectric layer 20 on the substrate is located within the orthographic projection of the second electrode plate 15-1 on the substrate. The orthographic projection of the dielectric layer 20 on the substrate overlaps with the orthographic projection of the first via V1 on the substrate. The dielectric layer 20 fills the recessed area formed by the second electrode plate 15-1 at the first via V1. The dielectric layer 20 is in contact with the entire surface of the second electrode plate 15-1 located in the first via V1.

[0124] In an exemplary embodiment, the surface of the dielectric layer 20 away from the substrate is substantially flush with the surface of the second electrode plate 15-1 away from the substrate, so that the surface of the dielectric layer 20 away from the substrate and the surface of the second electrode plate 15-1 away from the substrate form a plane.

[0125] In an exemplary embodiment, the material of the dielectric layer 20 may include organic materials, such as resin.

[0126] (108) Forming a sixth insulating layer pattern. In an exemplary embodiment, forming a sixth insulating layer pattern may include: depositing a sixth insulating film on a substrate on which the aforementioned pattern is formed, and patterning the sixth insulating film using a patterning process to form a sixth insulating layer covering the fourth conductive layer pattern and the dielectric layer, wherein the sixth insulating layer in each circuit unit is provided with a plurality of vias, as shown in FIG13.

[0127] In an exemplary embodiment, the plurality of vias in the sixth insulating layer of each circuit unit include a third via V3 and a fourth via V4. The orthographic projection of the third via V3 on the substrate is located within the orthographic projection of the second gate 14 on the substrate. The sixth and fifth insulating layers within the third via V3 are etched away, exposing a portion of the surface of the second gate 14. The third via V3 is configured to allow a subsequently formed first transition electrode to be connected to the second gate 14 through the via.

[0128] In an exemplary embodiment, the orthographic projection of the fourth via V4 on the substrate is located within the orthographic projection of the first connecting electrode 15-2 on the substrate. The sixth insulating layer within the fourth via V4 is etched away, exposing a portion of the surface of the first connecting electrode 15-2. The fourth via V4 is configured to allow a subsequently formed second adapter electrode to be connected to the first connecting electrode 15-2 through the via.

[0129] In an exemplary embodiment, the sixth insulating layer may be a silicon nitride compound or a silicon oxide compound.

[0130] (109) Forming a fifth conductive layer pattern. In an exemplary embodiment, forming a fifth conductive layer pattern may include: depositing a fifth conductive film on a substrate on which the aforementioned pattern is formed, and patterning the fifth conductive film by a patterning process to form a fifth conductive layer pattern disposed on a sixth insulating layer, as shown in Figures 14a and 14b.

[0131] In an exemplary embodiment, the fifth conductive layer pattern includes a first transition electrode 16-1 and a second transition electrode 16-2, both of which are rectangular blocks. The first transition electrode 16-1 of the circuit unit in the m-th unit row is located on one side of the second transition electrode 16-2 of the circuit unit in the m-th unit row, and the first transition electrode 16-1 of the circuit unit in the (m+1)-th unit row is located on the opposite side of the second transition electrode 16-2 of the circuit unit in the (m+1)-th unit row. The second transition electrodes 16-2 of the circuit units adjacent to each other in the second direction D2 in the m-th and (m+1)-th unit rows are connected as a single unit.

[0132] In an exemplary embodiment, both the first transfer electrode 16-1 and the second transfer electrode 16-2 can be multi-layer structures, such as titanium nitride / molybdenum stacked structures or titanium / aluminum / titanium stacked structures.

[0133] (110) Forming a second semiconductor layer pattern. In an exemplary embodiment, forming a second semiconductor layer pattern may include: depositing a second semiconductor thin film on a substrate on which the aforementioned pattern is formed, and patterning the second semiconductor thin film using a patterning process to form a second semiconductor layer pattern disposed on a fifth conductive layer pattern, as shown in Figures 15a, 15b, and 15c. Figure 15c is a cross-sectional view along the b-b' direction in Figure 15a.

[0134] In an exemplary embodiment, the second semiconductor layer pattern may include a second active layer 17. The second active layer 17 includes a second main body portion 17-1 extending along the second direction D2, and a fourth connecting portion 17-2 and a fifth connecting portion 17-3 disposed on one side of the second main body portion 17-1 in the first direction D1. The second main body portion 17-1 may be strip-shaped, and the fourth connecting portion 17-2 and the fifth connecting portion 17-3 may be rectangular blocks. The fourth connecting portion 17-2 and the fifth connecting portion 17-3 are located at opposite ends of the second main body portion 17-1 in the second direction D2. The orthographic projection of the fourth connecting portion 17-2 on the substrate includes the orthographic projection of the first transition electrode 16-1 on the substrate, and the fourth connecting portion 17-2 is in direct contact with the first transition electrode 16-1. The orthographic projection of the fifth connecting portion 17-3 on the substrate includes the orthographic projection of the second transition electrode 16-2 on the substrate, and the fifth connecting portion 17-3 is in direct contact with the second transition electrode 16-2. The fifth connection part 17-3 can serve as the first terminal of the second transistor T2 and be connected to the data signal line 11; the fourth connection part 17-2 can serve as the second terminal of the second transistor T2 and be connected to the second gate 14 of the first transistor T1.

[0135] In an exemplary embodiment, the orthogonal projection of the first transition electrode 16-1 on the substrate includes the orthogonal projection of the third via V3 on the substrate, and the first transition electrode 16-1 is connected to the second gate 14 through the third via V3; the orthogonal projection of the second transition electrode 16-2 on the substrate includes the orthogonal projection of the fourth via V4 on the substrate, and the second transition electrode 16-2 is connected to the first connection electrode 15-2 through the fourth via V4, and the first connection electrode 15-2 is connected to the data signal line 11 through the second via V2.

[0136] In an exemplary embodiment, the orthographic projection of the second active layer 17 on the substrate does not overlap with the orthographic projection of the second electrode plate 15-1 on the substrate.

[0137] (111) Forming a sixth conductive layer pattern. In an exemplary embodiment, forming a sixth conductive layer pattern may include: depositing a seventh insulating film and a sixth conductive film sequentially on a substrate on which the aforementioned pattern is formed, patterning the sixth conductive film using a patterning process to form a seventh insulating layer from the seventh insulating film, and forming a sixth conductive layer pattern disposed on the seventh insulating layer from the sixth conductive film, as shown in Figures 16a and 16b.

[0138] In an exemplary embodiment, the sixth conductive layer pattern includes a third gate 18, the shape of which includes a rectangular strip. The orthographic projection of the first region of the third gate 18 onto the substrate includes the orthographic projection of the dielectric layer 20 onto the substrate. The first region of the third gate 18 is configured as the gate of the subsequently formed third transistor T3. The orthographic projection of the second region of the third gate 18 onto the substrate overlaps with the orthographic projection of the second active layer 17 onto the substrate. The second region of the third gate 18 serves as the gate of the first transistor T1. The second portions of the second active layer 17 and the third gate 18 form the second transistor T2.

[0139] In an exemplary embodiment, the orthogonal projection of the third gate 18 on the substrate does not overlap with the orthogonal projections of the first transition electrode 16-1 and the second transition electrode 16-2 on the substrate.

[0140] In an exemplary embodiment, the third gate 18 of the circuit unit in the m-th unit row is connected as a whole to form a strip extending along the first direction, and the third gate 18 of the circuit unit in the (m+1)-th unit row is connected as a whole to form a strip extending along the first direction.

[0141] In an exemplary embodiment, the third gate 18 may be a multi-layer structure, such as a titanium nitride / molybdenum stacked structure or a titanium / aluminum / titanium stacked structure.

[0142] In an exemplary embodiment, the seventh insulating layer may be a silicon oxide compound.

[0143] (112) Forming a third semiconductor layer pattern. In an exemplary embodiment, forming a third semiconductor layer pattern may include: sequentially depositing an eighth insulating film and a third semiconductor film on a substrate on which the aforementioned pattern is formed; patterning the third semiconductor film using a patterning process to form an eighth insulating layer covering the pattern of the sixth conductive layer; and forming a third semiconductor layer pattern disposed on the eighth insulating layer using the third semiconductor film, as shown in Figures 17a, 17b, and 17c. Figure 17c is a cross-sectional view along the c-c' direction in Figure 17a.

[0144] In an exemplary embodiment, the third semiconductor layer pattern may include a third active layer 19, which may be rectangular in shape. The orthographic projection of the third active layer 19 onto the substrate overlaps with the orthographic projection of the second region of the third gate 18 onto the substrate. The orthographic projection of the third active layer 19 onto the substrate also overlaps with the orthographic projection of the first active layer 13 onto the substrate. The orthographic projection of the third active layer 19 onto the substrate includes the orthographic projection of the dielectric layer 20 onto the substrate, and also includes the orthographic projection of the recessed region of the second electrode 15-1 onto the substrate. The orthographic projection of the third active layer 19 onto the substrate does not overlap with the orthographic projection of the second active layer 17 onto the substrate. The third active layer 19 and the third gate 18 form the third transistor T3.

[0145] (113) Forming an eighth insulating layer pattern. In an exemplary embodiment, forming an eighth insulating layer pattern may include: patterning the eighth insulating layer using a patterning process to form multiple vias in the eighth insulating layer of each circuit unit, as shown in FIG18.

[0146] In an exemplary embodiment, the plurality of vias in the eighth insulating layer of each circuit unit include a fifth via V5 and a sixth via V6. The orthographic projection of the fifth via V5 on the substrate is located within the orthographic projection of the third connection portion 13-3 of the first active layer 13 on the substrate. The eighth, seventh, sixth, fifth and fourth insulating layers within the fifth via V5 are etched away, exposing a portion of the surface of the third connection portion 13-3 of the first active layer 13. The fifth via V5 is configured to allow a subsequently formed first power line (VDD) to be connected to the third connection portion 13-3 of the first active layer 13 through the via.

[0147] In an exemplary embodiment, the orthographic projection of the sixth via V6 onto the substrate lies within the orthographic projection of the second electrode plate 15-1 onto the substrate. The eighth, seventh, and sixth insulating layers within the sixth via V6 are etched away, exposing a portion of the surface of the second electrode plate 15-1. The sixth via V6 is configured to allow a subsequently formed second connection electrode to connect to the second electrode plate 15-1 through this via. The orthographic projection of the sixth via V6 onto the substrate does not overlap with the orthographic projection of the dielectric layer 20 onto the substrate.

[0148] (114) Forming a seventh conductive layer pattern. In an exemplary embodiment, forming a seventh conductive layer pattern may include: depositing a seventh conductive film on a substrate on which the aforementioned pattern is formed, and patterning the seventh conductive film by a patterning process to form a seventh conductive layer pattern disposed on an eighth insulating layer, as shown in Figures 19a and 19b.

[0149] In an exemplary embodiment, the seventh conductive layer pattern includes a first power signal line 21, a second connection electrode 22, and a sensing signal line 23. The first power signal line 21 of the circuit unit in the m-th unit row is located on one side of the second direction D2 of the second connection electrode 22 of the circuit unit in the m-th unit row, and the first power signal line 21 of the circuit unit in the (m+1)-th unit row is located on the opposite side of the second direction D2 of the second connection electrode 22 of the circuit unit in the (m+1)-th unit row. The shape of the first power signal line 21 of each circuit unit includes a strip extending along the first direction D1. The first power signal lines 21 of adjacent circuit units in the m-th unit row are connected together to form a line extending along the first direction D1, and the first power signal lines 21 of adjacent circuit units in the (m+1)-th unit row are connected together to form a line extending along the first direction D1. The first power signal line 21 is connected to the third connection portion 13-3 of the first active layer 13 through a fifth via V5.

[0150] In an exemplary embodiment, the second connection electrode 22 is located between the first power signal line 21 and the sensing signal line 23, and the shape of the second connection electrode 22 includes a rectangular block shape. The second connection electrode 22 is connected to the second electrode plate 15-1 through the sixth via V6. The orthographic projection of the second connection electrode 22 on the substrate overlaps with the orthographic projection of the second end of the third active layer 19 on the substrate, and the second connection electrode 22 is in contact with the surface of the second end of the third active layer 19 away from the substrate. The second end of the third active layer 19 serves as the second end of the third transistor T3, and is connected to the second end of the first transistor T1, the first electrode of the light-emitting device, and the second electrode plate 15-1 of the capacitor C.

[0151] In an exemplary embodiment, the sensing signal line 23 of the circuit unit in the m-th row is located on the side opposite to the second direction D2 of the second connection electrode 22 of the circuit unit in the m-th row, and the sensing signal line 23 of the circuit unit in the (m+1)-th row is located on the side of the second direction D2 of the second connection electrode 22 of the circuit unit in the (m+1)-th row. The sensing signal line 23 includes a third main body portion 23-1 and a sixth connecting portion 23-2. The shape of the third main body portion 23-1 includes a strip extending along the first direction D1. The third main body portions 23-1 of the plurality of circuit units in the m-th row are connected as one unit to form a line extending along the first direction D1, and the third main body portions 23-1 of the plurality of circuit units in the (m+1)-th row are connected as one unit to form a line extending along the first direction D1. The sixth connecting part 23-2 has a rectangular block shape. The sixth connecting part 23-2 of the circuit unit in the m-th unit row is located on the side opposite to the second direction D2 of the third main body 23-1. Multiple circuit units in the m-th unit row can share one sixth connecting part 23-2. The sixth connecting part 23-2 of the circuit unit in the m+1-th unit row is located on the side of the second direction D2 of the third main body 23-1. Multiple circuit units in the m+1-th unit row can share one sixth connecting part 23-2. The sixth connecting part 23-2 shared by multiple circuit units in the m-th unit row and the sixth connecting part 23-2 shared by multiple circuit units in the m+1-th unit row are connected as one unit.

[0152] In an exemplary embodiment, the orthographic projection of the third main body portion 23-1 onto the substrate overlaps with the orthographic projection of the first end of the third active layer 19 onto the substrate, and the second connecting electrode 22 contacts the surface of the first end of the third active layer 19 away from the substrate. The first end of the third active layer 19 serves as the first end of the third transistor T3 and is connected to the sensing signal line SL.

[0153] In an exemplary embodiment, the first power signal line 21, the second connection electrode 22, and the sensing signal line 23 can all be single-layer structures, such as copper or molybdenum; or, the first power signal line 21, the second connection electrode 22, and the sensing signal line 23 can all be multi-layer structures, such as titanium / aluminum / titanium stacked structures.

[0154] (115) Forming a ninth insulating layer pattern. In an exemplary embodiment, forming a ninth insulating layer pattern may include: depositing a ninth insulating film on a substrate on which the aforementioned pattern is formed, and patterning the ninth insulating film by a patterning process to form a ninth insulating layer covering the pattern of the seventh conductive layer, as shown in FIG20.

[0155] In an exemplary embodiment, a seventh via V7 is provided in the ninth insulating layer. The orthographic projection of the seventh via V7 on the substrate is located within the orthographic projection of the sixth connection portion 23-2 of the sensing signal line 23 on the substrate. The ninth insulating layer in the seventh via V7 is etched away, exposing a portion of the surface of the sixth connection portion 23-2. The seventh via V7 is configured to allow the subsequently formed third connection electrode to be connected to the sixth connection portion 23-2 through the via.

[0156] In an exemplary embodiment, multiple circuit units in the m-th unit row can share a seventh via V7, and multiple circuit units in the (m+1)-th unit row can share a seventh via V7. The seventh via V7 shared by multiple circuit units in the m-th unit row and the seventh via V7 shared by multiple circuit units in the (m+1)-th unit row are connected as one unit.

[0157] In an exemplary embodiment, the ninth insulating layer may be a silicon oxide compound or a silicon nitride compound.

[0158] (116) Forming an eighth conductive layer pattern. In an exemplary embodiment, forming an eighth conductive layer pattern may include: depositing an eighth conductive film on a substrate on which the aforementioned pattern is formed, and patterning the eighth conductive film by a patterning process to form an eighth conductive layer pattern disposed on a ninth insulating layer, as shown in Figures 21a and 21b.

[0159] In an exemplary embodiment, the eighth conductive layer pattern includes a third connecting electrode 24, which includes a fourth main body portion 24-1 and a seventh connecting portion 24-2. The fourth main body portion 24-1 is shaped like a line extending along the second direction D2, and the seventh connecting portion 24-2 is shaped like a rectangular block. The seventh connecting portion 24-2 of the circuit unit in the m-th unit row is disposed at one end of the fourth main body portion 24-1 in the opposite direction of the second direction D2, and the seventh connecting portion 24-2 extends out of the fourth main body portion 24-1 on one side in the opposite direction of the first direction D1; the seventh connecting portion 24-2 of the circuit unit in the m+1-th unit row is disposed at one end of the fourth main body portion 24-1 in the second direction D2, and the seventh connecting portion 24-2 extends out of the fourth main body portion 24-1 on one side in the opposite direction of the first direction D1. Multiple circuit units in the m-th row share a third connection electrode 24, and multiple circuit units in the (m+1)-th row share a third connection electrode 24. The third connection electrode 24 shared by the m-th row and the third connection electrode 24 shared by the (m+1)-th row are located in the same column of circuit units, and the seventh connection portion 24-2 of the third connection electrode 24 shared by the m-th row and the seventh connection portion 24-2 of the third connection electrode 24 shared by the (m+1)-th row are connected as one unit.

[0160] In an exemplary embodiment, the seventh connection portion 24-2 of the third connection electrode 24 is connected to the sixth connection portion 23-2 of the sensing signal line 23 through the seventh via V7.

[0161] In an exemplary embodiment, the third connecting electrode 24 may be a single-layer structure, such as copper or molybdenum; or, the third connecting electrode 24 may be a multi-layer structure, such as a titanium / aluminum / titanium stacked structure.

[0162] At this point, the driving circuit layer of this embodiment is fabricated on the substrate. Subsequent fabrication processes may include forming a tenth insulating layer covering the pattern of the eighth conductive layer, an eleventh insulating layer disposed on the tenth insulating layer, forming an eighth via exposing the second connection electrode 22 in the tenth and eleventh insulating layers, forming a first electrode of the light-emitting device on the eleventh insulating layer, and forming a pixel definition layer on the first electrode. The first electrode is connected to the second connection electrode 22 through the eighth via, and a pixel opening is formed in the pixel definition layer, exposing at least a portion of the surface of the first electrode. After the pixel definition layer is fabricated, subsequent fabrication processes may sequentially form the light-emitting functional layer and the second electrode to complete the fabrication of the light-emitting structure layer, which will not be elaborated further here.

[0163] This disclosure discloses the substrate fabrication process. The second electrode plate 15-1 of the capacitor is filled with a first via V1 that connects to the first active layer 13 of the first transistor through the first via V1. This makes the surface of the second electrode plate 15-1 flat, thereby making the orthographic projection of the subsequently formed third active layer 19 on the substrate overlap with the orthographic projection of the first active layer 13 on the substrate. This ensures the flatness of the third active layer 19 and avoids the via connecting the second electrode plate 15-1 and the first active layer 13 from affecting the flatness of the third active layer 19.

[0164] The present disclosure shows the substrate fabrication process by placing the data signal line 11 in the first conductive layer and the second electrode plate 15-1 in the fourth conductive layer, thereby reducing the crosstalk effect of the data signal line 11 and reducing the effect of the parasitic capacitance of the first transistor during light emission.

[0165] The present disclosure shows the substrate fabrication process. By overlapping the orthographic projection of the third active layer 19 on the substrate with the orthographic projection of the first active layer 13 on the substrate, the space utilization can be improved, the orthographic projection area of ​​the second electrode plate 15-1 on the substrate can be increased, thereby increasing the capacitance.

[0166] The present disclosure shows the substrate fabrication process. By overlapping the orthographic projection of the third active layer 19 on the substrate with the orthographic projection of the first active layer 13 on the substrate, the space utilization can be improved, the size of the first active layer 13 can be increased, the short channel effect can be reduced, and the subthreshold swing (SS) can be increased, thereby improving the grayscale resolution.

[0167] The present disclosure discloses the substrate fabrication process, in which a first transition electrode 16-1 and a second transition electrode 16-2 are formed on the surface of the second active layer 17 near the substrate, so that the orthogonal projections of the first transition electrode 16-1 and the second transition electrode 16-2 on the substrate can both be located within the orthogonal projection of the second active layer 17 on the substrate, thereby reducing the space occupied by the first transition electrode 16-1 and the second transition electrode 16-2.

[0168] The present invention discloses the substrate fabrication process, in which the first transfer electrode 16-1 and the second transfer electrode 16-2 are in direct contact with the second active layer 17, without the need for via connection, thus avoiding over-etching during the via etching process and preventing damage to the second active layer 17.

[0169] The present disclosure embodiment shows the substrate fabrication process, by including the orthogonal projection of the first transition electrode 16-1 and the second transition electrode 16-2 on the substrate with the orthogonal projection of the via below them on the substrate, realizing full-hole connection, reducing the difficulty of deep hole etching, and improving connection stability.

[0170] In an exemplary embodiment, the present disclosure shows the substrate fabrication process. The orthographic projection of at least one of the aforementioned vias V1, V2, V3, V4, V5, V6, and V7 onto the substrate can be a polygon, such as a rectangle, pentagon, or hexagon. The length of at least one side of the polygon is less than or equal to 1 micrometer. Alternatively, the orthographic projection of at least one of the aforementioned vias V1, V2, V3, V4, V5, V6, and V7 onto the substrate can be a circle, with a diameter less than or equal to 1 micrometer. Alternatively, the orthographic projection of at least one of the aforementioned vias V1, V2, V3, V4, V5, V6, and V7 onto the substrate can be an ellipse, with the length of the minor axis of the ellipse less than or equal to 1 micrometer.

[0171] In an exemplary embodiment, taking the first via V1 as an example, the fabrication process of each via of the display substrate in this disclosure embodiment will be described. Forming the first via V1 may include the following operations.

[0172] As shown in Figure 5a, a first hole V1-1 is first formed in the fifth insulating layer 205. The first hole V1-1 extends to the surface of the first active layer 13, exposing part of the surface of the first active layer 13.

[0173] As shown in Figure 5b, an inorganic dielectric layer 301 is then deposited on the fifth insulating layer 205, and the inorganic dielectric layer 301 covers the inner wall of the first hole V1-1; wherein, the inorganic dielectric layer 301 and the fifth insulating layer 205 have different etching ratios.

[0174] As shown in Figure 5c, the inorganic dielectric layer 301 is then patterned through exposure, development, and etching processes to form a second via V1-2. The second via V1-2 exposes one sidewall of the first via V1-1 and part of the surface of the first active layer 13. A portion of the surface of the first active layer 13 exposed by the first via V1-1 is covered by the inorganic dielectric layer 301, and another portion of the surface of the first active layer 13 exposed by the first via V1-1 is exposed by the second via V1-2. The region of the first active layer 13 exposed by the first via V1-1 and the second via V1-2 is designated as the first via V1. The orthographic projection of the first via V1 onto the substrate 101 has a length a in the second direction D2 that is less than or equal to 1 micrometer.

[0175] The manufacturing process of the display substrate in this embodiment achieves high pixel density by controlling the size of each via of the display substrate to be less than or equal to 1 micrometer. For example, the pixel density of the display substrate can reach 1800 PPI.

[0176] This disclosure also provides a method for preparing a display substrate, including:

[0177] A driving circuit layer is formed on a substrate. The driving circuit layer includes at least a plurality of circuit units, at least one of which includes a pixel driving circuit. The pixel driving circuit includes a third transistor, a first transistor, and a capacitor. The first transistor includes a first active layer, the third transistor includes a third active layer, and the capacitor includes a second electrode plate. The third active layer is disposed on the side of the first active layer away from the substrate. The second electrode plate is disposed between the first active layer and the third active layer. The second electrode plate is connected to a second end of the first active layer through a first via. A recessed region is formed in the first via on the second electrode plate. A dielectric layer is disposed on the side of the second electrode plate away from the substrate. At least a portion of the dielectric layer is disposed in the recessed region. The orthographic projection of the third active layer on the substrate overlaps with the orthographic projection of the recessed region on the substrate.

[0178] This disclosure also provides a display device, including any of the display substrates described above. The display device can be any product or component with display functionality, such as a mobile phone, wearable device, AR or VR display device, in-vehicle display device, tablet computer, television, monitor, laptop computer, digital photo frame, or navigator; however, this invention is not limited to these categories.

[0179] In the description of this application, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", "axial", "radial", "circumferential", etc., indicating the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this application.

[0180] Furthermore, the terms "first," "second," etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined with "first," "second," etc., may explicitly or implicitly include at least one of those features.

[0181] In the description of this application, "multiple" means at least two, such as two, three, etc., unless otherwise expressly and specifically limited.

[0182] In this application, unless otherwise expressly specified and limited, the terms "installation," "connection," "joining," "fixing," etc., should be interpreted broadly. For example, "connection" can be a fixed connection, a detachable connection, or an integral part; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium; it can be the internal communication of two components or the interaction between two components, unless otherwise expressly limited. Those skilled in the art can understand the specific meaning of the above terms in this application according to the specific circumstances.

[0183] In this application, unless otherwise expressly specified and limited, "above" or "below" the second feature can mean that the first and second features are in direct contact, or that the first and second features are in indirect contact through an intermediate medium. Furthermore, "above," "over," and "on top" of the second feature can mean that the first feature is directly above or diagonally above the second feature, or simply that the first feature is at a higher horizontal level than the second feature. "Below," "below," and "under" the second feature can mean that the first feature is directly below or diagonally below the second feature, or simply that the first feature is at a lower horizontal level than the second feature.

[0184] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of this application. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. Moreover, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described in this specification, as well as the features of different embodiments or examples.

[0185] Although embodiments of this application have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting this application. Those skilled in the art can make changes, modifications, substitutions and variations to the above embodiments within the scope of this application.

Claims

1. A display substrate, comprising a driving circuit layer disposed on a substrate, the driving circuit layer comprising at least a plurality of circuit units, at least one circuit unit comprising a pixel driving circuit, the pixel driving circuit comprising a driving transistor, a second switching transistor, and a capacitor; the driving transistor comprising a first active layer, the second switching transistor comprising a third active layer, the capacitor comprising a second electrode plate, the third active layer being disposed on the side of the first active layer away from the substrate, the second electrode plate being disposed between the first active layer and the third active layer, the second electrode plate being connected to a second end of the first active layer through a first via, the second electrode plate forming a recessed region in the first via, a dielectric layer being disposed on the side of the second electrode plate away from the substrate, at least a portion of the dielectric layer being disposed in the recessed region, and the orthographic projection of the third active layer on the substrate overlapping the orthographic projection of the recessed region on the substrate.

2. The display substrate according to claim 1, wherein, The surface of the dielectric layer away from the substrate forms a plane with the surface of the second electrode plate away from the substrate.

3. The display substrate according to claim 1, wherein, The orthographic projection of the third active layer onto the substrate includes the orthographic projection of the recessed region onto the substrate.

4. The display substrate according to claim 1, wherein, The orthographic projection of the third active layer on the substrate overlaps with the orthographic projection of the first active layer on the substrate.

5. The display substrate according to claim 1, wherein, The first via is polygonal in shape, and the length of at least one side of the first via is less than or equal to 1 micrometer; or, the first via is circular in shape, and the diameter of the first via is less than or equal to 1 micrometer; or, the first via is elliptical in shape, and the length of the minor axis of the first via is less than or equal to 1 micrometer.

6. The display substrate according to any one of claims 1 to 5, wherein, The driving transistor further includes a second gate, which is disposed between the first active layer and the second electrode. The orthographic projection of the second gate on the substrate overlaps with the orthographic projection of the first active layer on the substrate. The capacitor includes a first electrode, with the second gate serving as the first electrode. The orthographic projection of the second gate on the substrate overlaps with the orthographic projection of the second electrode on the substrate.

7. The display substrate according to any one of claims 1 to 5, wherein, The driving transistor further includes a first gate, which is located on the side of the first active layer near the substrate, and the orthographic projection of the first gate on the substrate overlaps with the orthographic projection of the first active layer on the substrate.

8. The display substrate according to any one of claims 1 to 5, wherein, The pixel driving circuit further includes a first power line, which is disposed on the side of the third active layer away from the substrate, and is connected to the first end of the first active layer through a fifth via.

9. The display substrate according to any one of claims 1 to 5, wherein, The second switching transistor further includes a third gate, which is located between the third active layer and the second electrode plate, and the orthographic projection of the third gate on the substrate overlaps with the orthographic projection of the third active layer on the substrate.

10. The display substrate according to any one of claims 1 to 5, wherein, It also includes a light-emitting structure layer disposed on the side of the driving circuit layer away from the substrate. The light-emitting structure layer includes a light-emitting device. The light-emitting device includes a first electrode, a light-emitting functional layer and a second electrode disposed sequentially along the direction away from the substrate. The pixel driving circuit also includes a second connection electrode. The second connection electrode is located between the third active layer and the first electrode. At least a portion of the second connection electrode is in contact with the surface of the second end of the third active layer away from the substrate. The second connection electrode is connected to the second electrode plate through a sixth via. The second connection electrode is connected to the first electrode.

11. The display substrate according to any one of claims 1 to 5, wherein, The pixel driving circuit further includes a sensing signal line located on the side of the third active layer away from the substrate, and at least a portion of the sensing signal line is in contact with the surface of the first end of the third active layer away from the substrate.

12. The display substrate according to any one of claims 1 to 5, wherein, The pixel driving circuit further includes a first switching transistor, the first switching transistor including a second active layer, the second active layer being located between the second electrode and the third active layer, a first transition electrode being disposed on the surface of the second active layer near the substrate, the first transition electrode being in contact with the second active layer, a second gate being disposed on the side of the first transition electrode near the substrate, the first transition electrode being connected to the second gate through a third via; the second gate serving as the gate electrode of the driving transistor.

13. The display substrate according to claim 12, wherein, The orthographic projection of the second active layer onto the substrate includes the orthographic projection of the first transition electrode onto the substrate.

14. The display substrate according to claim 12, wherein, The orthographic projection of the first adapter electrode on the substrate includes the orthographic projection of the third via on the substrate.

15. The display substrate according to any one of claims 1 to 5, wherein, The pixel driving circuit further includes a first switching transistor, the first switching transistor including a second active layer, the second active layer being located between the second electrode and the third active layer, a second transition electrode being disposed on the surface of the second active layer near the substrate, the second transition electrode being in contact with the second active layer, a data signal line being disposed on the side of the second transition electrode near the substrate, and the second transition electrode being connected to the data signal line through a fourth via.

16. The display substrate according to claim 15, wherein, The orthographic projection of the second active layer on the substrate includes the orthographic projection of the second transfer electrode on the substrate.

17. The display substrate according to claim 15, wherein, The orthographic projection of the second adapter electrode on the substrate includes the orthographic projection of the fourth via on the substrate.

18. The display substrate according to claim 15, wherein, The pixel driving circuit further includes a first connecting electrode, which is located on the same film layer as the second electrode plate. The first connecting electrode is located between the data signal line and the second adapter electrode. The second adapter electrode is connected to the first connecting electrode through the fourth via, and the first connecting electrode is connected to the data signal line through the second via.

19. A method for preparing a display substrate, comprising: A driving circuit layer is formed on a substrate. The driving circuit layer includes at least a plurality of circuit units, at least one of which includes a pixel driving circuit. The pixel driving circuit includes a second switching transistor, a driving transistor, and a capacitor. The driving transistor includes a first active layer, the second switching transistor includes a third active layer, and the capacitor includes a second electrode plate. The third active layer is disposed on the side of the first active layer away from the substrate. The second electrode plate is disposed between the first active layer and the third active layer. The second electrode plate is connected to a second end of the first active layer through a first via. A recessed region is formed in the first via on the second electrode plate. A dielectric layer is disposed on the side of the second electrode plate away from the substrate. At least a portion of the dielectric layer is disposed in the recessed region. The orthographic projection of the third active layer on the substrate overlaps with the orthographic projection of the recessed region on the substrate.

20. A display device comprising a display substrate as described in any one of claims 1 to 18.

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