Systems and methods for convolutional encoding for a-iot devices

Abstract

In accordance with implementations, an apparatus obtains a first bit sequence of a first sequence length. The first bit sequence comprises a first portion of a first portion length and a second portion. The apparatus obtains a second bit sequence of a second sequence length generated from the first bit sequence. The apparatus encodes an input sequence to generate an encoded sequence. An ordering of the input sequence comprises the second portion, the second bit sequence, and the first portion. An encoder for the encoding comprises a state. An initial value of the state before the encoding is set according to the first portion. The apparatus transmits the encoded sequence.

Description

SYSTEMS AND METHODS FOR CONVOLUTIONAL ENCODING FOR A-IoT DEVICESCROSS-REFERENCE TO RELATED APPLICATION

[0001] This patent application claims priority to U.S. Provisional Application No. 63 / 755,037, filed on February 6, 2025, and entitled “Methods for Convolutional Encoding for A-IoT Devices,” application of which is hereby incorporated by reference herein as if reproduced in its entirety.TECHNICAL FIELD

[0002] The present disclosure relates generally to wireless communications, and, in particular embodiments, to systems and methods for convolutional encoding.BACKGROUND

[0003] There are generally two classes of convolutional codes: systematic recursive (SR) and non-systematic non-recursive (NSNR). With systematic codes, at least one output sequence of the convolutional encoder is a copy of the input sequence. With non- systematic codes, no output sequence is a copy of the input sequence. A non-recursive code has no feedback loop present in the encoder while a recursive code has a feedback loop in the encoder.

[0004] For example, consider a rate R-1 / 2, 8 state (=2L-1) with L=4 representing the constraint length of the code. The generator polynomials g1(x) and g2(x) in this example are g1(x) = 1 + x2+ x3g2(x)= 1 + x + x2+ x3SUMMARY

[0005] Technical advantages are generally achieved, by implementations of this disclosure which describe methods, apparatus, and system.

[0006] In accordance with implementations, an apparatus obtains a first bit sequence of a first sequence length. The first bit sequence comprises a first portion of a first portion length and a second portion. The apparatus obtains a second bit sequence of a second sequence length generated from the first bit sequence. The apparatus encodes an input sequence to generate an encoded sequence. An ordering of the input sequence comprises the second portion, the second bit sequence, and the first portion. An encoderfor the encoding comprises a state. An initial value of the state before the encoding is set according to the first portion. The apparatus transmits the encoded sequence.

[0007] In some implementations, a length of the input sequence may be a sum of the first sequence length and the second sequence length.

[0008] In some implementations, the first sequence length may be a sum of the first portion length and a second portion length of the second portion.

[0009] In some implementations, the state may be represented by a shift register with a length of the shift register equaling the first portion length. A corresponding initial value of each register bit of the shift register may be set to a different bit of the first portion.

[0010] In some implementations, the encoder may obtain the first portion before the encoder obtains the second portion. The second portion maybe encoded before the second bit sequence. The second bit sequence maybe encoded before the first portion.[oon] In some implementations, the second bit sequence may be a cyclic redundancy check (CRC) of the first bit sequence.

[0012] In some implementations, a final value of the state after the encoder encodes the input sequence may be equal to the initial value of the state.

[0013] In some implementations, the apparatus may encode the second portion before obtaining the second bit sequence.

[0014] In some implementations, after the encoding the input sequence and before the transmitting the encoded sequence, the apparatus may reorder the encoded sequence. An ordering of the encoded sequence before the reordering may comprise a second portion output bits corresponding to encoding the second portion, a second output bit sequence corresponding to encoding the second bit sequence, and a first portion output bits corresponding to encoding the first portion. An ordering of the encoded sequence after the reordering may comprise the first portion output bits, the second portion output bits, and the second output bit sequence.BRIEF DESCRIPTION OF THE DRAWINGS

[0015] For a more complete understanding of the present disclosure, and the advantages thereof, reference is now made to the following descriptions taken in conjunction with the accompanying drawings, in which:

[0016] FIG. 1 illustrates an example NSNR encoder, in accordance with some implementations ;

[0017] FIG. 2 illustrates an example encoding process, in accordance with some implementations;

[0018] FIG. 3 depicts an example of CRC encoder and CC encoder with a tail sequence, in accordance with some implementations;

[0019] FIG. 4 shows an example of CRC encoder and CC encoder with tail-biting, in accordance with some implementations;

[0020] FIG. 5 shows an example of CRC encoder and CC encoder with tail-biting with a different initial state, in accordance with some implementations;

[0021] FIG. 6 shows an example trellis for £=4 (8 states) for a tailed code, in accordance with some implementations;

[0022] FIG. 7 shows an example trellis for £=4 (8 states) for a tail-biting code, in accordance with some implementations;

[0023] FIGs. 8A-8C illustrate examples of decoding operations, in accordance with some implementations;

[0024] FIGs. 9A-9D illustrate examples of sequences, in accordance with some implementations ;

[0025] FIGs. 10A-10B illustrate examples of encoding operations, in accordance with some implementations;

[0026] FIG. 11 shows an example of selecting the encoder, in accordance with some implementations;

[0027] FIGs. 12A-12E illustrate four topologies for AIoT deployment under development in 3GPP, in accordance with some implementations;

[0028] FIG. 13A shows an example of block level repetition type, in accordance with some implementations;

[0029] FIG. 13B shows an example of bit level repetition type 1, in accordance with some implementations;

[0030] FIG. 13C shows an example of bit level repetition type 2, in accordance with some implementations;

[0031] FIG. 14 shows an example diagram of equivalent processing with block level repetition and tail-biting encoding, in accordance with some implementations;

[0032] FIG. 15 illustrates an example of flowchart of operations performed by a device, in accordance with some implementations;

[0033] FIG. 16A shows an example LTE encoding sequence, in accordance with some implementations;

[0034] FIG. 16B shows an example of bit ordering, in accordance with some implementations;

[0035] FIG. 16C shows an example LTE encoding sequence with alternate encoder initialization, in accordance with some implementations;

[0036] FIG. 16D shows an example of bit ordering, in accordance with some implementations;

[0037] FIG. 17 illustrates an example of a communications system, in accordance with some implementations;

[0038] FIG. 18 illustrates another example of a communications system, in accordance with some implementations;

[0039] FIGs. 19A and 19B illustrate example devices that may implement the methods and teachings according to this disclosure, in accordance with some implementations; and

[0040] FIG. 20 illustrates an example of a computing system that may be used for implementing the devices and methods described herein, in accordance with some implementations.

[0041] Corresponding numerals and symbols in the different figures generally refer to corresponding parts unless otherwise indicated. The figures are drawn to clearly illustrate the relevant aspects of the embodiments and are not necessarily drawn to scale.DETAILED DESCRIPTIONS

[0042] The present disclosure relates to systems and methods for tail-biting convolutional encoding that reduce processing complexity and memory requirements for resource-constrained devices such as Ambient Internet of Things (A-IoT) devices. In conventional tail-biting encoding systems where a systematic encoder, such as a CRC encoder, precedes a convolutional encoder, the convolutional encoder must wait until the entire CRC encoding is complete to determine its initial state from the last L-1 bits of the CRC output, requiring significant memory storage (e.g., N-p bits) and processing time (e.g., 2N-p clocks). Implementations of the present disclosure address this technical problem by reordering the input sequence and initializing the convolutional encoder state using the first L-1 bits of the input data sequence, rather than the last L-1 bits of the CRC output. This technical approach enables parallel processing of CRC and convolutional encoding operations, reduces memory requirements (e.g., L-1 bits ofstorage), and decreases processing time (e.g., N+L-1 clocks), while maintaining the tail biting property where the initial and final encoder states are equal.

[0043] For an NSNR code, the encoder transfer function can be expressed as[g1(x),g2(x)] while for an SR code, the encoder function can be expressed as . Animplementation of the NSNR encoder is shown in FIG. 1. The binary input sequence is u and the binary output sequences o1and o2correspond to generator polynomials gi(x) and g2(x), respectively. The binary shift registers are denoted as Si, i=o, L-2. The state of the encoder s is given by the shift register contents and can be represented as a vector s = [s0,s1, ••• , sL_2]. The s=O state is when si=o, for i=o, ..., L-2.

[0044] The shift registers can be initialized to any value. A typical initialization is the state s0=o, where s, represents the state when input bit i enters the encoder. For a tailbiting code, the initial state of the encoder s0is the same as the final state of the encoder sf. Sfrepresents the final state after / bits have been encoded.

[0045] To assist decoding, a sequence of L-1 zeroes (tail sequence f) can be appended after iz. The tail sequence causes the final state to be sf=o after encoding the zero-valued tail sequence. Adding a tail sequence increases the overhead of the code. If the length of the input sequence is N, then the number of bits after encoding is (N + L — 1) / R. When L is large or when N is small, the overhead, expressed as a ratio (L - 1) / N, can be significant. For example, the overhead for the control channel when N=40 bits (a typical N for 3GPP LTE control channels) and L=7 is approximately 15%. For 3GPP LTE, the polynomials are:

[0046] An approach to eliminate the tail sequence overhead is to use a tail-biting code. A drawback is increased decoder complexity. One possible decoder for a tail biting code is to process multiple copies of the received codeword to estimate the sequence u. The decoder should also check whether the initial and final states are the same. In addition to the increased decoding complexity, the encoder is only able to start once the entire input sequence is available because the initial state sois based on the final state sf. Using FIG. 1, as an example, the final state sNis given by the bits u(N-1), u(N-2), ..., u(N- L+1).

[0047] To illustrate tailed and tail biting codes, consider the length N=32 sequence u (left to right)1101 1110 1010 1101 1111 1010 1100 1110

[0048] For a tailed code, when the initial state is so= o, the outputs for g1and g2are: o1111 100 101 101 001 100 111 011 001 001 000 10 o2100 111 011 000 010 111 000 110 010 000 110 10

[0049] The outputs also include a 3-bit tail sequence that follows the input sequence.

[0050] For a tail biting code, using the notation above, the initial state s0is [1 / (31), u(30) u

[0029] )

[0011] . The outputs for g1and g2are given by o3and o4, respectively. o3101 100 101 101 001 100 111 011 001 001 00 o4110 111 011 000 010 111 000 110 010 000 11

[0051] Comparing o1and o3, the first L-1 bits will be different due to the initial state. o1will have L-1 extra bits. The bolded and italicized section below shows the common portion of the output o1111 100 101 101 001 100 111 011 001 001 000 1003 101 100 101 101 001 100 111 011 001 001 00

[0052] Likewise, for o2and o402(i ) 100 111 011 000 010 111 000 110 010 000 110 1004( i ) = 110 111 011 000 010 111 000 110 010 000 11

[0053] When considering convolutional codes for Ambient Internet of Things (A-IoT) devices, an A-IoT device is both energy and complexity constrained: the A-IoT device may need to minimize its energy consumption and how much memory the A-IoT device is using (complexity and energy). Due to a tail sequence, a tailed code increases the length of transmission (which consumes energy) and increases system latency due to the transmission of extra encoded bits. A tail biting code can increase memory requirements as the entire sequence must be stored before encoding can start. This also can increase processing time as a device is unable to process the input sequence and encode in parallel. Consider the general encoding process where cyclic redundancy check (CRC) encoder operates on an information sequence d (length N-p) to produce a length p parity check sequence c. The input into the convolutional (CC) encoder, labeled u, is a concatenation of sequences d and c and has a length N. The output sequence o has length (N + z(L-1)) / R, where z is a flag with z=i indicating tail bits are used and z=o for tailbiting, and R is the code rate (e.g., V2).

[0054] Following the encoding process in FIG. 2, one example of a low latency implementation using a CRC encoder and convolutional encoder with a tail sequence is shown in FIG. 3. The sequence that is CC encoded is also depicted in FIG. 3.

[0055] To estimate the processing time, a streaming implementation where a processing block can immediately process the input is used, and one bit per clock is used.

[0056] In FIG. 3, the CRC encoder 302 and CC encoder 304 can process the N-p bits of input sequence d in parallel. The CC encoder 304 then processes the p bits of c, the parity sequence from the CRC encoder 302. Depending on implementation, storage of p bits may not be needed. Finally, the L-1 bits of the tail sequence t are processed by the CC encoder 304. The overall processing time is N+L-1. No additional memory units are needed. The initial and final states of the CC encoder 304 are s0=sN+L-1=O.

[0057] With a tail-biting CC encoder, there is a dependency in that the initial state s0is determined by the final state SN -1. However, with the encoding procedure shown in FIG. 2, the final state sN -1is based on the last L-1 bits of the parity sequence c when p≥L- 1. When p<L-1, the final state is based on the p bits of the parity sequence c and the last L-1-p bits of the input sequence d. For ease of explanation, this disclosure may assume p≥L-1 but is not limited so.

[0058] In FIG. 4, the CRC encoder 402 and CC encoder 404 process the N-p bits of input sequence d sequentially. Before the CC encoder 404 can process input sequence d, the CC encoder 404 initializes the initial state of the CC encoder 404 with the last L-1 bits of the parity sequence c, which are only available after the CRC encoder 402 processes the entire input sequence d. With the streaming implementation, a storage 406 of N-p bits is used.

[0059] Based on the analysis, CRC encoding first processes N-p bits, and the CC encoder 404 then processes N bits, resulting in a total of 2N-p clocks. In addition, at least N-p bits of storage are needed.[oo6o] A technical problem is how to support a tail-biting code given that the convolutional encoder follows the CRC encoder while minimizing the complexity (e.g., throughput, memory, delay).

[0061] From an NSNR encoder’s perspective, state s is a memory / shift register of L-1 bits. Once a bit enters the (non-recursive) encoder, its effects are only over L-1 bits. Consider a tail-biting code using L=4 and p≥L-1 as an example, the first several states of the encoder are shown in Table 1. State s3is not based on any parity bit. The state at bit number N represents the final state after the N input bits are encoded.Table 1. Initial states of encoder in FIG. 4.

[0062] It is possible to define a different initial state that preserves the tail-biting property while reducing the amount of storage (complexity) used. Instead of initializing the CC encoder with CRC bits available only after the CRC encoding, the initial state of the CC encoder is set to the initial data bits of the input sequence, and these initial bits are then saved and CC encoded last (after the CRC bits) to preserve the tail-biting property. This allows the CRC and the CC encoders to both run at the same time without having to store the entire input while waiting to determine the initial state of the CC encoder from the CRC bits. In detail, instead of starting to encode bit uowith an initial state so=cp-1, ... cp-L+1, bit dL-1is processed first with an initial state so=dL-2, ..., do, as shown in Table 2.Table 2. Initial states of encoder

[0063] A block diagram showing a possible implementation is presented in FIG. 5.

[0064] From a processing complexity perspective, while the CRC encoder 502 is processing all N-p bits of d, the CC encoder 504 can encode N-p-L+1 bits of d after skipping the first L-1 bits. Then the length p parity sequence c is CC encoded. Finally, the first L-1 bits of d are encoded. The total time for processing is N+L-1. Due to placing the first L-1 bits of d at the end, a storage 506 of L-1 can be used. Due to the low complexity nature of A-IoT devices, it is possible that the first L-1 elements of d are known beforehand, and storage may not be necessary. For a generalized tail-biting code as shown in FIG. 9C further explained below, the amount of storage is increased to the size of the first portion.

[0065] Table 3 summarizes the complexity estimates.Table 3. Complexity comparison for encoding

[0066] Some typical values for the range of N are from 16 to 1000 bits, the range of p is o to 16 bits, and the range of L is from 4 to 8. The rate R is typically 1 / 2, 1 / 3, 1 / 4, 1 / 5, and 1 / 6. In addition, there might be repetition, which can increase the overhead.

[0067] For completeness, the CC encoding operations when p=o and when o<p<L-1 are provided. When p=o, there is no CRC added to the sequence d. For a streaming implementation, initializing the CC encoder with the last L-1 bits of d may require N bits of storage. It is possible to use the first L-1 bits of d to initialize the CC encoder and then encode the last N-L+1 bits of d followed by the first L-1 bits of d. The first L-1 bits of d are stored until they are used. When o<p<L-1, there is a CRC encoding operation. In this case, L-1 bits of d are stored. In an implementation with ap>o CRC length and ap=o (no CRC), the initialization of the CC encoder is performed similarly. Alternatively, the p=o option is initialized with the last L-1 bits.

[0068] Typically, a maximum likelihood sequence estimator (MLSE) is used to decode an NSNR code. SR codes are generally associated with turbo codes. A maximum aposterior (MAP) estimator can be used in decoding turbo codes. A MAP estimator can also be used in decoding NSNR codes. An illustration of an MLSE decoder (e.g., Viterbi decoder) is used with the L =4 example. There are 8 states labeled in binary from ooo to 111 (7). FIG. 6 shows the trellis for a tailed code (so=sf=o). In FIG. 6, a solid line indicates the state transition due to a '1' while a dashed line indicates the state transition due to a ‘o.’

[0069] A decoding complexity estimate can be expressed as (N+L-1) x 2L-1kernel operations where 2L-1is the number of states in the encoder and the term (N+L-1) is the number of bits encoded. The kernel operation is the add-compare-select operation sequence, where there are two additions with each addition being the sum of the log likelihood ratio (LLR) associated the state transition and the path metric; the compare is a comparison of the two sums, and the select is choosing the better sum.

[0070] FIG. 7 is one example of the trellis used for decoding tail-biting codes. Since the decoder is unaware of the initial state, r iterations are typically implemented (e.g., circular Viterbi algorithm (CVA)). The number of iterations may be a function of the number of bits and the constraint length. For example, if N>5L, two iterations maybe adequate to converge the most likely sequence in the first iteration. An estimated complexity is rxNx 2L-1kernel operations.

[0071] FIG. 8A shows one example of the decoding operations for tailed and tailbiting codes (where the initial state is initialized with the last L-1 bits of the input sequence). LLRs are generated for the decoder. Typically, the ordering of the LLRs follows the ordering of the input sequence into the encoder. The decoder (e.g., Viterbi decoder) and traceback recover the estimated bit sequence. A CRC decoder processes the estimated bit sequence for error-detection purposes. When a tail-biting code (where the initial state is initialized with the first L-1 bits of the input sequence) is used, one possible implementation can increase the number of iterations (e.g., by 1 or 2) and recover the bits starting from d0. Increasing the number of iterations can increase the decoding complexity. It is possible to implement stopping rules for the number of iterations based on CRC decoding of recovered bits.

[0072] FIG. 8B and FIG. 8C show possible approaches to recover the estimated bit sequence for a tail-biting code where the initial state is initialized with the first L-1 bits of the input sequence is used. In FIG. 8B, a circular shift is used so that the last L-1 bits of the output sequence from the traceback step become the first bits (i.e., dois the first bit). The output sequence has dL-1being the first bit. Alternatively, the last L-1 bits are removed from the end and placed at the beginning. In FIG. 8C, the LLRs corresponding to do, ..., dL-2(which are last) are reordered so that those LLRs are first. This reorderingtransforms the sequence to a tail-biting code where the initial state is initialized with the last L-1 bits of the input sequence. One of the benefits of the LLR reordering is that some implementations of CVA decoders and CRC decoders can operate in parallel.

[0073] For Ambient loT devices, one implementation can be based on FIG. 5, where L-1 bits of d are stored regardless of the value of N and p (assuming p>L-1 or p=o). When o<p<L-1, fewer bits of d can be stored. An example pseudo-algorithm to encode is provided.

[0074] The notation a(k) can also be used for ak. The initial state of the CC encoder is denoted as so=[so, ..., SL-2].

[0075] Let the input sequence to the CC encoder be denoted as u=dL-1, dL, ..., dN-p-1, co, C1, ..., cp-1, do, d1, ..., dL-2and p≥o.To set the initial state so: For k=o, ..., L-2- Sk=dL-2-k

[0076] Let the input sequence to the CC encoder be denoted as u=dL-1, dL, ..., dN-p-1, do, d1, ..., dL-2and p=o.To set the initial state so: For k=o, ..., L-2.-. sk=dL-2-ks=so

[0077] Then, the output sequence or(k), with r=o, ..., 1 / R-1, is generated asFor k=o, N-1:[oo(k), ..., or-1(k), s] = cc_encode(uk, s)

[0078] In FIG. 9A, an input sequence d (first sequence) is split into a first portion of length L-1 and a second portion of length N-(L-1) assuming p, the length of parity sequence c, is zero (no parity sequence). The input sequence u into the encoder is shown with the second portion followed by the first portion. The first portion is used to initialize the encoder. In FIG. 9B, an input sequence d is split into a first portion of length L-1 and a second portion of length N-(L-1). It is assumed that p is greater than o. The input sequence u is shown with the following ordering: second portion, parity sequence c (second sequence) followed by the first portion. The first portion is used to initialize the encoder.[007g] FIG. gC and FIG. gD show a generalization of the implementations. An input sequence d (first sequence) is split into a first portion of length Lp1with Lp1>L-1, and a second portion of length Lp2where Lp2=N-p- Lp1. The first portion can be further split into a length Lp1— (L-1) section and a length L-1 section. The length L-1 section is used toinitialize the encoder. In the generalization, the storage is the first Lplbits of d. In FIG. 9C, it is assumed that p, the length of parity sequence c, is zero (no parity sequence). The input sequence u into the encoder is shown with the second portion followed by the first portion. The last L-1 bits of the first portion are used to initialize the encoder. In FIG. 9D, an input sequence d is split into a first portion and a second portion. It is assumed that p is greater than o. The input sequence u is shown with the following ordering: second portion, parity sequence c (second sequence) followed by the first portion. The last L-1 bits of the first portion are used to initialize the encoder.[oo8o] Examples of encoding processing are shown in FIGs. 10A-10B. FIG. 10A shows an example of sequential processing with a CRC encoder, while FIG. 10B shows an example of parallel processing with a CRC encoder. In FIG. 10A, at the operation 1001, the A-IoT device (or reader) generates (provides) an input sequence d to be encoded and transmitted. In other words, the encoding module obtains (receives) the input sequence from higher layers, such as the medium access layer (MAC) or even from the physical layer itself. At the operation 1002, the encoding module partitions the input sequence into two portions: the first portion containing at least the first L-1 bits of d, and the second portion containing the remaining bits of d. For notation purposes, let lp1denote the length of the first portion and lp2denote the length of the second portion with lp1+lp2=N-p. The first portion corresponds to the first lp1bits of d while the second portion corresponds to the last N-p- lp1bits of d. In the algorithm above, lp1= L-1 (representing the least storage and processing time), but in general, lp1≥ L-1. Similarly, in the algorithm above, Zp2= N-p-L+1, but in general Zp2≤ N-p-L+1. At the operation 1003, the last L-1 bits of the first portion are used to initialize the tail-biting CC encoder. At the operation 1004, if the encoding module performs CRC processing, a parity sequence c with length p is generated based on the input sequence d. At the operation 1005, the input sequence for CC encoding is obtained by the following sequence ordering: second portion, parity sequence, first portion. After the input sequence is CC encoded at the operation 1006, the encoded sequence is prepared for transmission at the operation 1007. Some operations between encoding and transmission can include interleaving, scrambling, repetition, line coding, and modulation. Interleaving reorders the encoder output.

[0081] FIG. 10B includes operations 1051-1057. FIG. 10B has similar steps to FIG. 10A, with the following differences. As the CC encoder is encoding the second portion at the operation 1058, a parity sequence c is generated at the operation 1054 at the same time (e.g., in parallel). Once the parity sequence is obtained, it is CC encoded at the operation 1055. The final CC encoder state at the operation 1058 is the initial CC state atthe operation 1055. The operation 1056 completes the encoding process by CC encoding the first portion. The final CC encoder state at the operation 1055 is the initial CC state at the operation 1056.

[0082] Another implementation is based on FIG. 5, where L-1 bits of d are stored when N < T (or N≤ T) where T is a threshold, otherwise the encoding operations in FIG. 3 are followed. Because decoders for tail-biting codes are iterative, to lower decoding complexity, using tailed codes can be utilized for a large N. The percentage of overhead is small with a large N.

[0083] Another implementation can be based on the combined length of the input sequence d (length N-p) and parity bits c (length p) or just the length of the input sequence d. If no CRC encoding is used, p-o. Let z denote the length used in a comparison. As an example, depending on the criterion, z=N or z=N-p. When the comparison of z to a threshold length T [is z < T or z ≤ T] is true, a tail-biting code is used, as shown in FIG. 11. FIG. 11 shows an example flowchart 1100 for selecting an encoding method based on a threshold comparison, in accordance with some implementations. At block 1102, an input sequence d is obtained. At block 1104, the length of a parity sequence c is determined, which may be zero if no CRC encoding is used. At decision block 1106, the length z of the parity sequence c+d (or alternatively, just the length of c or d) is compared to a threshold T. If the length is less than the threshold T, the process proceeds to block 1108 where encoding with a tailed code is performed. If the length is greater than or equal to the threshold T, the process proceeds to block 1110 where encoding with a tail-biting code is performed. In some alternative implementations, if the length is less than the threshold T, the process proceeds to perform encoding with a tail-biting code. If the length is greater than or equal to the threshold T, the process proceeds to perform encoding with a tailed code. Such alternative implementations may be utilized if overhead for the tailed code is too large for short-length sequence. In addition, if the complexity (e.g., delay, memory) associated with the tail-biting code is large for long-length sequences, a tailed code can be used. After either encoding operation, at block 1112, the encoded sequence is transmitted. The change of tailing based on the threshold could also handle the change of the tailing based on the CRC length, assuming shorter or no CRC length corresponds to the shorter length. Depending on standards, a tail-biting code initialized with the last L-1 bits of c or with the first L-1 bits of d can be used. When z>T (or z≥T), tailed codes at used.

[0084] FIGs. 12A-12E illustrate several topologies showing a reader (e.g. base station (BS), UE, intermediate node) and an A-IoT device. The intermediate node can be a UE. Uu can represent a cellular link. There are two types of links between the device andreader: the reader-to-device (R2D) and device-to-reader (D2R) link, On the D2R link, a physical device to reader channel (PDRCH) is used to convey bits from the device to the reader. The encoder operations in FIG. 2 prepare the bits for modulation on the D2R link.

[0085] For Ambient loT devices, the processing for the PDRCH could utilize the following options: CRC attachment (encoding), FEC (forward error correction) (i.e., convolutional encoding), and repetition. An example of block type repetition in FIG. 13A is that the block of N bits is repeated Rblocktimes. As an example, the sequence into the FEC encoder is {uo, u1, ..., uN-0} ; {uo, u1, ..., uN-1}; ... {u0, u1, ..., uN-1}. With bit level type 1 repetition in FIG. 13B, each bit Ukis repeated Rbittimes. As an example, the sequence into the FEC encoder is {uo, uo, ..., uo}, { u1, u1, ..., u1}; ... {uN-1, UN-1, uN-1}. With bit level type 2 repetition in FIG. 13C, each bit okis repeated Rbittimes. As an example, the sequence generated by the FEC encoder is {oo, oo, ..., oo}, {o1, o1, ..., o1}; ... {oZ-1, oZ-1, ..., oZ-1}, where Z is the number of output bits which accounts for the input sequence length N, the number of tail bits, and coding rate. An example of the coding rate is 1 / 3 where one input bit generates 3 output bits.[oo86] With block level repetition, the number of bits encoded is Rblock×N+t, where t-o for tail-biting codes. Using the property that the final state after N bits are encoded is equal to the initial state for tail-biting codes, it can be shown that the state after Rblock×N bits are encoded is the same as the initial state. An equivalent block diagram to FIG. 13A when tail-biting codes are used is shown in FIG. 14. A benefit of this block diagram in FIG. 14 is that a possible receiver implementation can combine LLRs of the corresponding output bits together before decoding. Thus, combining effectively improves the SNR and reduces the decoding complexity as fewer bits are decoded. With tailed codes, a similar benefit is possible if the block repetition applies to N+t bits, not N bits.

[0087] A possible drawback for block type repetition is the increase in memory usage for Ambient loT devices. For example, since the output of the FEC encoder has length Z, an implementation storing Z bits can be used to support repetition. Following the diagram in Fig. 13a), a storage of Rblock×N bits can be used. Depending on the values of Rblockand the coding rate, the storage for the input can be larger than the output.Alternatively, if the input sequence is encoded Rblocktimes, the storage can be N bits. This is a tradeoff between processing and storage. One advantage of the preferred embodiment is that processing can be reduced due to the parallel processing. Instead of storing the input sequence and then CC encoding repeatedly, the CRC and first CCencoding can occur in parallel. As the first CC encoding is happening, the bit sequence can be stored.

[0088] FIG. 15 illustrates an example of a flowchart of a method 1500 performed by an apparatus (e.g., an AIoT device or a chip on the AIoT device), in accordance with some implementations. The device may include computer-readable code or instructions executing on one or more processors of the device. Coding of the software for carrying out or performing the method 1500 is well within the scope of a person of ordinary skill in the art having regard to the present disclosure. The method 1500 may include additional or fewer operations than those shown and described and may be carried out or performed in a different order. Computer-readable code or instructions of the software executable by the one or more processors may be stored on at least one non-transitory computer-readable medium, such as for example, at least one memory of the apparatus. In some embodiments, the method 1500 may be performed by one or more of units or modules (e.g., an integrated circuit) of the apparatus, such as field programmable gate arrays (FPGAs) or application-specific integrated circuits (ASICs).

[0089] The method 1500 starts at the operation 1502, where the apparatus obtains a first bit sequence of a first sequence length. The first bit sequence comprises a first portion of a first portion length and a second portion. At the operation 1504, the apparatus obtains a second bit sequence of a second sequence length generated from the first bit sequence. At the operation 1506, the apparatus encodes an input sequence to generate an encoded sequence. An ordering of the input sequence comprises the second portion, the second bit sequence, and the first portion. An encoder for the encoding comprises a state. An initial value of the state before the encoding is set according to the first portion. At the operation 1508, the apparatus transmits the encoded sequence.

[0090] In some implementations, a length of the input sequence may be a sum of the first sequence length and the second sequence length.

[0091] In some implementations, the first sequence length may be a sum of the first portion length and a second portion length of the second portion.

[0092] In some implementations, the state may be represented by a shift register with a length of the shift register equaling the first portion length. A corresponding initial value of each register bit of the shift register may be set to a different bit of the first portion.

[0093] In some implementations, the encoder may obtain the first portion before the encoder obtains the second portion. The second portion may be encoded before the second bit sequence. The second bit sequence may be encoded before the first portion.

[0094] In some implementations, the second bit sequence may be a cyclic redundancy check (CRC) of the first bit sequence.

[0095] In some implementations, a final value of the state after the encoder encodes the input sequence may be equal to the initial value of the state.

[0096] In some implementations, the apparatus may encode the second portion before obtaining the second bit sequence.

[0097] In some implementations, after the encoding the input sequence and before the transmitting the encoded sequence, the apparatus may reorder the encoded sequence. An ordering of the encoded sequence before the reordering may comprise a second portion output bits corresponding to encoding the second portion, a second output bit sequence corresponding to encoding the second bit sequence, and a first portion output bits corresponding to encoding the first portion. An ordering of the encoded sequence after the reordering may comprise the first portion output bits, the second portion output bits, and the second output bit sequence.

[0098] An implementation describes the how to use the modified encoding order to reduce the time to encode when an interleaver follows tail-biting convolutional encoder. FIG. 16A shows an example of a CRC encoder 1602 that produces a length p parity sequence c, with bits labeled c0, c1, ..., cp-1operating on sequence d of length N-p, with bits labeled do, di, ..., dN-p-1. The sequence [d, c] is then encoded by the tail-biting convolutional encoder 1604 where the initial state of the encoder is based on the last L-1 bits of sequence [d, c], i.e., Cp-L+1, cp -L+2, ... cp-2, cp_1when p≥L-1. In LTE, a rate R=1 / 3 code is used to produce three output bits for each input bit. In general, lower code rates, such as R=1 / 4 and R=1 / 5, can be used by adding more generator polynomials (e.g., 4 total for R=1 / 4, 5 total for R=1 / 5). For notation, let oirepresent the output stream corresponding to the polynomial. Each output stream is individually interleaved. For this example, the LTE sub-block interleaver is used, where the filling (write) operation is row by row and the pulling (read) operation is column by column. The ordering of the 32 columns read is based on a table (e.g., the entries can be the bit reversed representation of the column numbers). The interleaver 1606 (including e.g., sub-interleavers i6o6a-i6o6c) outputs aggregated in the bit collection block 1608.

[0099] The number of rows in each of sub-block interleavers (e.g., i6o6a-i6o6c) is the smallest integer greater than or equal to the quotient of the length output sequence and the number of columns (e.g., 32). For example, if the length of output sequence is 34, then there are two rows. If the length of output sequence is 64, then there are also two rows. FIG. 16B shows an input sequence d of length N-p=28, the parity sequence c oflength p=6 appended to the input sequence d after CRC encoding. The convolutional encoder has a constraint length L=7 and is initialized with the last p bits of c (for this example the entire sequence c). The output sequence for one of the constituent encoders is denoted by o. The shading is used to indicate the bit ordering. The contents of the subblock interleaver after the write operation are shown.

[0100] As shown in FIG. 16C, the reordering aspects of the implementation can be used in conjunction with the interleaver. The CRC encoding can be performed in parallel with tail-biting encoding. The write operation of the sub-block interleaver can place the bits into the correct order for the read operation.

[0101] For example, a pointer (ptr) can be used during the write process to identify the address where to store the bits of o. Normally, the pointer can be initialized to the address 0, and the following pointer update is ptr = ptr + 1. With the embodiment, the pointer can be initialized to the address L-1 with the pointer update is ptr = (ptr + i)mod TV, where mod is the modulus operator.

[0102] In FIG. 16C, block 1620 illustrates how an input bit sequence d can be split so that the CRC encoder 1622 operates in parallel with the tail-biting encoder 1624. The order of bits into sub-block interleavers i626a-c is different than the ordering of bits into sub-block interleaver i6o6a-c in FIG. 16A. By modifying the write operation in i626a-c (such as using the pointer), the ordering of bits into bit collection 1628 is maintained.

[0103] FIG. 16D shows an example of bit ordering, in accordance with some implementations. In contrast to FIG. 16B, for the input to the convolutional encoder, the beginning (length (L-1) = 6) of the input sequence d is moved to the end after the parity sequence c for encoding, and the first L-1 bits of input sequence d is used for initialization of the conventional encoder. Also in contrast to FIG. 16B, for the input to the sub-block interleaver, the beginning (length (L-1) = 6) of the output sequence o is moved to the end, and the 7th bit of the output sequence becomes the start for the subblock interleaver.

[0104] It should be appreciated that the techniques described in this disclosure use certain types of devices, such as readers and A-IoT devices, as examples for illustration purposes. However, the described techniques are applicable to any device, apparatus, or entity capable of performing CRC encoding followed by convolutional encoding, including but not limited to base stations, user equipment, relay nodes, network entities, and other wireless communication devices / systems.

[0105] While the claims presented herein are directed to operations performed by an encoding device on the encoding side, it should be understood that correspondingcomplementary operations are performed by a decoding device. For each encoding-side operation described in the claims, there is a corresponding decoding-side operation.

[0106] The network entity described in this disclosure may include a base station, a network relay node, or a plurality of base stations each configured to perform at least one of the network entity operations described above. The network entity operations may be distributed among different base stations in any combination or configuration, without limitation to the specific examples provided herein.

[0107] FIG. 17 illustrates an example communications system 1700. Communications system 1700 includes an access node 1710 serving user equipments (UEs) with coverage 1701, such as UEs 1720. In a first operating mode, communications to and from a UE passes through access node 1710 with a coverage area 1701. The access node 1710 is connected to a backhaul network 1715 for connecting to the internet, operations and management, and so forth. In a second operating mode, communications to and from a UE do not pass through access node 1710, however, access node 1710 typically allocates resources used by the UE to communicate when specific conditions are met. Communications between a pair of UEs 1720 can use a sidelink connection (shown as two separate one-way connections 1725). In FIG. 17, the sidelink communication is occurring between two UEs operating inside of coverage area 1701. However, sidelink communications, in general, can occur when UEs 1720 are both outside coverage area 1701, both inside coverage area 1701, or one inside and the other outside coverage area 1701. Communication between a UE and access node pair occur over uni-directional communication links, where the communication links between the UE and the access node are referred to as uplinks 1730, and the communication links between the access node and UE is referred to as downlinks 1735.[oio8] Access nodes may also be commonly referred to as Node Bs, evolved Node Bs (eNBs), next generation (NG) Node Bs (gNBs), master eNBs (MeNBs), secondary eNBs (SeNBs), master gNBs (MgNBs), secondary gNBs (SgNBs), network controllers, control nodes, base stations, access points, transmission points (TPs), transmission-reception points (TRPs), cells, carriers, macro cells, femtocells, pico cells, and so on, while UEs may also be commonly referred to as mobile stations, mobiles, terminals, users, subscribers, stations, and the like. Access nodes may provide wireless access in accordance with one or more wireless communication protocols, e.g., the Third Generation Partnership Project (3GPP) long term evolution (LTE), LTE advanced (LTE- A), 5G, 5G LTE, 5G NR, sixth generation (6G), High Speed Packet Access (HSPA), the IEEE 802.11 family of standards, such as 802.na / b / g / n / ac / ad / ax / ay / be, etc. While it is understood that communications systems may employ multiple access nodes capable ofcommunicating with a number of UEs, only one access node and two UEs are illustrated for simplicity.

[0109] FIG. 18 illustrates an example communication system 1800. In general, the system 1800 enables multiple wireless or wired users to transmit and receive data and other content. The system 1800 may implement one or more channel access methods, such as code division multiple access (CDMA), time division multiple access (TDMA), frequency division multiple access (FDMA), orthogonal FDMA (OFDMA), single-carrier FDMA (SC-FDMA), or non-orthogonal multiple access (NOMA).

[0110] In this example, the communication system 1800 includes electronic devices (ED) 1810a- 1810c, radio access networks (RANs) i82oa-i82ob, a core network 1830, a public switched telephone network (PSTN) 1840, the Internet 1850, and other networks i860. While certain numbers of these components or elements are shown in FIG. 18, any number of these components or elements may be included in the system 1800.

[0111] The EDs 1810a-1810c are configured to operate or communicate in the system 1800. For example, the EDs i8ioa-i8ioc are configured to transmit or receive via wireless or wired communication channels. Each ED i8ioa-i8ioc represents any suitable end user device and may include such devices (or may be referred to) as a user equipment or device (UE), wireless transmit or receive unit (WTRU), mobile station, fixed or mobile subscriber unit, cellular telephone, personal digital assistant (PDA), smartphone, laptop, computer, touchpad, wireless sensor, AIoT device (e.g., for asset management), or consumer electronics device.[oii2] The RANs 1820a-1820b here include base stations 1870a-1870b, respectively. Each base station 1870a-1870b is configured to wirelessly interface with one or more of the EDs i8ioa-i8ioc to enable access to the core network 1830, the PSTN 1840, the Internet 1850, or the other networks i860. For example, the base stations 1870a-1870b may include (or be) one or more of several well-known devices, such as a base transceiver station (BTS), a Node-B (NodeB), an evolved NodeB (eNB), a Next Generation (NG) NodeB (gNB), a gNB centralized unit (gNB-CU), a gNB distributed unit (gNB-DU), a Home NodeB, a Home eNodeB, a site controller, an access point (AP), or a wireless router. The EDs 1810a-1810c are configured to interface and communicate with the Internet 1850 and may access the core network 1830, the PSTN 1840, or the other network1 i860.

[0113] In the embodiment shown in FIG. 18, the base station 1870a forms part of the RAN 1820a, which may include other base stations, elements, or devices. Also, the base station 1870b forms part of the RAN 1820b, which may include other base stations,elements, or devices. Each base station 1870a-1870b operates to transmit or receive wireless signals within a particular geographic region or area, sometimes referred to as a “cell.” In some embodiments, multiple-input multiple-output (MIMO) technology may be employed having multiple transceivers for each cell.

[0114] The base stations 1870a-1870b communicate with one or more of the EDs i8ioa-i8ioc over one or more air interfaces 1890 using wireless communication links. The air interfaces 1890 may utilize any suitable radio access technology.

[0115] It is contemplated that the system 1800 may use multiple channel access functionality, including such schemes as described above. In particular embodiments, the base stations and EDs implement 5G New Radio (NR), LTE, LTE-A, or LTE-B. Of course, other multiple access schemes and wireless protocols may be utilized.

[0116] The RANs i82oa-i82ob are in communication with the core network 1830 to provide the EDs i8ioa-i8ioc with voice, data, application, Voice over Internet Protocol (VoIP), or other services. Understandably, the RANs 1820a-1820b or the core network 1830 may be in direct or indirect communication with one or more other RANs (not shown). The core network 1830 may also serve as a gateway access for other networks (such as the PSTN 1840, the Internet 1850, and the other networks i860). In addition, some or all of the EDs 1810a-1810c may include functionality for communicating with different wireless networks over different wireless links using different wireless technologies or protocols. Instead of wireless communication (or in addition thereto), the EDs may communicate via wired communication channels to a service provider or switch (not shown), and to the Internet 1850.

[0117] Although FIG. 18 illustrates one example of a communication system, various changes maybe made to FIG. 18. For example, the communication system 1800 could include any number of EDs, base stations, networks, or other components in any suitable configuration.[o118] FIGs. 19A and 19B illustrate example devices that may implement the methods and teachings according to this disclosure. In particular, FIG. 19A illustrates an example ED 1910, and FIG. 19B illustrates an example base station 1970. The ED 1910 and the base station 1970 may communicate over the air interface 1990. These components could be used in the system 1800 or in any other suitable system.

[0119] As shown in FIG. 19A, the ED 1910 includes at least one processing unit 1900. The processing unit 1900 implements various processing operations of the ED 1910. For example, the processing unit 1900 could perform signal coding, data processing, power control, input / output processing, or any other functionality enabling the ED 1910 tooperate in the system 1800. The processing unit 1900 also supports the methods and teachings described in more detail above. Each processing unit 1900 includes any suitable processing or computing device configured to perform one or more operations. Each processing unit 1900 could, for example, include a microprocessor, microcontroller, digital signal processor, field programmable gate array, or application specific integrated circuit.

[0120] The ED 1910 also includes at least one transceiver 1902. The transceiver 1902 is configured to modulate data or other content for transmission by at least one antenna or NIC (Network Interface Controller) 1904. The transceiver 1902 is also configured to demodulate data or other content received by the at least one antenna 1904. Each transceiver 1902 includes any suitable structure for generating signals for wireless or wired transmission or processing signals received wirelessly or by wire. Each antenna 1904 includes any suitable structure for transmitting or receiving wireless or wired signals. One or multiple transceivers 1902 could be used in the ED 1910, and one or multiple antennas 1904 could be used in the ED 1910. Although shown as a single functional unit, a transceiver 1902 could also be implemented using at least one transmitter and at least one separate receiver.

[0121] The ED 1910 further includes one or more input / output devices 1906 or interfaces (such as a wired interface to the Internet 1850). The input / output devices 1906 facilitate interaction with a user or other devices (network communications) in the network. Each input / output device 1906 includes any suitable structure for providing information to or receiving information from a user, such as a speaker, microphone, keypad, keyboard, display, or touch screen, including network interface communications.

[0122] In addition, the ED 1910 includes at least one memory 1908. The memory 1908 stores instructions and data used, generated, or collected by the ED 1910. For example, the memory 1908 could store software or firmware instructions executed by the processing unit(s) 1900 and data used to reduce or eliminate interference in incoming signals. Each memory 1908 includes any suitable volatile or non-volatile storage and retrieval device(s). Any suitable type of memory may be used, such as random access memory (RAM), read only memory (ROM), hard disk, optical disc, subscriber identity module (SIM) card, memory stick, secure digital (SD) memory card, and the like.

[0123] As shown in FIG. 19B, the base station 1970 includes at least one processing unit 1950, at least one transceiver 1952, which includes functionality for a transmitter and a receiver, one or more antennas 1956, at least one memory 1958, and one or more input / output devices or interfaces 1176. A scheduler, which would be understood by one skilled in the art, is coupled to the processing unit 1950. The scheduler could be includedwithin or operated separately from the base station 1970. The processing unit 1950 implements various processing operations of the base station 1970, such as signal coding, data processing, power control, input / output processing, or any other functionality. The processing unit 1950 can also support the methods and teachings described in more detail above. Each processing unit 1950 includes any suitable processing or computing device configured to perform one or more operations. Each processing unit 1950 could, for example, include a microprocessor, microcontroller, digital signal processor, field programmable gate array, or application specific integrated circuit.

[0124] Each transceiver 1952 includes any suitable structure for generating signals for wireless or wired transmission to one or more EDs or other devices. Each transceiver 1952 further includes any suitable structure for processing signals received wirelessly or by wire from one or more EDs or other devices. Although shown combined as a transceiver 1952, a transmitter and a receiver could be separate components. Each antenna 1956 includes any suitable structure for transmitting or receiving wireless or wired signals. While a common antenna 1956 is shown here as being coupled to the transceiver 1952, one or more antennas 1956 could be coupled to the transceiver(s) 1952, allowing separate antennas 1956 to be coupled to the transmitter and the receiver if equipped as separate components. Each memory 1958 includes any suitable volatile or non-volatile storage and retrieval device(s). Each input / output device 1176 facilitates interaction with a user or other devices (network communications) in the network. Each input / output device 1176 includes any suitable structure for providing information to or receiving / providing information from a user, including network interface communications.

[0125] FIG. 20 is a block diagram of a computing system 2000 that may be used for implementing the devices and methods disclosed herein. For example, the computing system can be any entity of UE, access network (AN), mobility management (MM), session management (SM), user plane gateway (UPGW), or access stratum (AS). Specific devices may utilize all of the components shown or only a subset of the components, and levels of integration may vary from device to device. Furthermore, a device may contain multiple instances of a component, such as multiple processing units, processors, memories, transmitters, receivers, etc. The computing system 2000 includes a processing unit 2002. The processing unit includes a central processing unit (CPU) 2014, memory 2008, and may further include a mass storage device 2004, a video adapter 2010, and an I / O interface 2012 connected to a bus 2020.

[0126] The bus 2020 may be one or more of any type of several bus architectures including a memory bus or memory controller, a peripheral bus, or a video bus. The CPU2014 may comprise any type of electronic data processor. The memory 2008 may comprise any type of non-transitory system memory such as static random access memory (SRAM), dynamic random access memory (DRAM), synchronous DRAM (SDRAM), read-only memory (ROM), or a combination thereof. In an embodiment, the memory 2008 may include ROM for use at boot-up, and DRAM for program and data storage for use while executing programs.

[0127] The mass storage 2004 may comprise any type of non-transitory storage device configured to store data, programs, and other information and to make the data, programs, and other information accessible via the bus 2020. The mass storage 2004 may comprise, for example, one or more of a solid state drive, hard disk drive, a magnetic disk drive, or an optical disk drive.

[0128] The video adapter 2010 and the I / O interface 2012 provide interfaces to couple external input and output devices to the processing unit 2002. As illustrated, examples of input and output devices include a display 2018 coupled to the video adapter 2010 and a mouse, keyboard, or printer 2016 coupled to the I / O interface 2012. Other devices may be coupled to the processing unit 2002, and additional or fewer interface cards maybe utilized. For example, a serial interface such as Universal Serial Bus (USB) (not shown) may be used to provide an interface for an external device.

[0129] The processing unit 2002 also includes one or more network interfaces 2006, which may comprise wired links, such as an Ethernet cable, or wireless links to access nodes or different networks. The network interfaces 2006 allow the processing unit 2002 to communicate with remote units via the networks. For example, the network interfaces 2006 may provide wireless communication via one or more transmitters / transmit antennas and one or more receivers / receive antennas. In an embodiment, the processing unit 2002 is coupled to a local-area network 2022 or a wide-area network for data processing and communications with remote devices, such as other processing units, the Internet, or remote storage facilities.

[0130] It should be appreciated that not all components in the devices described in FIGs. 17-20 are required. In a non-limiting example, the ED 1910 maybe implemented as an AIoT device 1910. But, the AIoT device 1910 may not include an input / output devices 1906 for providing information to or receiving information from a user, such as a speaker, microphone, keypad, keyboard, display, or touch screen. The transceiver 1902 of the AIoT device 1910 may be capable of transmitting by backscattering a radio wave received, instead of by generating the radio wave, for wireless communication purpose. In another non-limiting example, the system 2000 may be implemented as an AIoTdevice 2000 that does not include or use the mass storage device 2004, the video adapter 2010, the mouse, keyboard, or printer 2016, or the display 2018.

[0131] It should be appreciated that one or more steps of the embodiment methods provided herein may be performed by corresponding units or modules. For example, a signal may be transmitted by a transmitting unit or a transmitting module. A signal may be received by a receiving unit or a receiving module. A signal may be processed by a processing unit or a processing module. Other steps may be performed by a performing unit or module, a generating unit or module, an obtaining unit or module, a setting unit or module, an adjusting unit or module, an increasing unit or module, a decreasing unit or module, a determining unit or module, a modifying unit or module, a reducing unit or module, a removing unit or module, or a selecting unit or module. The respective units or modules maybe hardware, software, or a combination thereof. For instance, one or more of the units or modules may be an integrated circuit, such as field programmable gate arrays (FPGAs) or application-specific integrated circuits (ASICs).

[0132] Although the description has been described in detail, it should be understood that various changes, substitutions and alterations can be made without departing from the spirit and scope of this disclosure as defined by the appended claims. Moreover, the scope of the disclosure is not intended to be limited to the particular embodiments described herein, as one of ordinary skill in the art will readily appreciate from this disclosure that processes, machines, manufacture, compositions of matter, means, methods, or steps, presently existing or later to be developed, may perform substantially the same function or achieve substantially the same result as the corresponding embodiments described herein. Accordingly, the appended claims are intended to include within their scope such processes, machines, manufacture, compositions of matter, means, methods, or steps.

Claims

WHAT IS CLAIMED IS:

1. A method comprising: obtaining, by a device, a first bit sequence of a first sequence length, wherein the first bit sequence comprises a first portion of a first portion length and a second portion; obtaining, by the device, a second bit sequence of a second sequence length generated from the first bit sequence; encoding, by an encoder of the device, an input sequence to generate an encoded sequence, wherein an ordering of the input sequence comprises the second portion, the second bit sequence, and the first portion, wherein before the encoding, a state of the encoder is set to an initial value according to the first portion; and transmitting, by the device, the encoded sequence.

2. The method of claim 1, wherein a length of the input sequence is a sum of the first sequence length and the second sequence length.3- The method of any of claims 1-2, wherein the first sequence length is a sum of the first portion length and a second portion length of the second portion.4- The method of any of claims 1-3, wherein the state is represented by a shift register with a length of the shift register equaling the first portion length, and a corresponding initial value of each register bit of the shift register is set to a different bit of the first portion.5- The method of claim 4, wherein the encoder is a non-systematic non-recursive (NSNR) convolutional encoder.

6. The method of any of claims 1-5, wherein the encoder obtains the first portion before the encoder obtains the second portion, wherein the second portion is encoded before the second bit sequence, and wherein the second bit sequence is encoded before the first portion.7- The method of any of claims 1-6, wherein the second bit sequence is a cyclic redundancy check (CRC) of the first bit sequence.

8. The method of any of claims 1-7, wherein a final value of the state after the encoder encodes the input sequence is equal to the initial value of the state.9- The method of any of claims 1-8, the encoding further comprising: encoding the second portion before obtaining the second bit sequence.

10. The method of any of claims 1-9, further comprising: after the encoding and before the transmitting, reordering, by the device, the encoded sequence, wherein an ordering of the encoded sequence before the reordering comprises a second portion output bits corresponding to encoding the second portion, a second output bit sequence corresponding to encoding the second bit sequence, and a first portion output bits corresponding to encoding the first portion, and wherein an ordering of the encoded sequence after the reordering comprises the first portion output bits, the second portion output bits, and the second output bit sequence.

11. A device comprising: at least one processor; and a non-transitory computer readable storage medium storing programming, the programming including instructions that, when executed by the at least one processor, cause the device to perform a method according to any of claims 1-10.

12. A non-transitory computer-readable medium having instructions stored thereon that, when executed by a device, cause the device to perform a method according to any of claims 1-10.

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