Multi-commodity flow-based synchronous escape routing method and apparatus, and medium

Abstract

A multi-commodity flow-based synchronous escape routing method and apparatus, and a medium. The method comprises: creating a grid pin array (GPA) routing graph on the basis of a chip GPA, and creating an irregular pin array routing graph on the basis of an array having a miss pin; creating escape boundary nodes in synchronous escape routing on the basis of the created GPA routing graph; creating an overall synchronous escape routing graph on the basis of the created escape boundary nodes; on the basis of the created overall synchronous escape routing graph, creating a multi-commodity flow-based synchronous escape routing model; solving the synchronous escape routing model to obtain a routing result, and designing a constraint for grouping and same-layer arrangement in the synchronous escape routing; and optimizing routing paths of the synchronous escape routing model, and accelerating the synchronous escape routing on the basis of an optimization result. By modeling routing constraints and path optimization methods, the present invention supports the simultaneous action of multiple acceleration methods, thereby improving system efficiency.

Description

A method, apparatus and medium for synchronous escape cabling based on multi-commodity flow Technical Field

[0001] This invention belongs to the field of integrated circuit technology, and more specifically, relates to a synchronous escape wiring method, apparatus and medium based on multi-commodity flow. Background Technology

[0002] Routing, as a crucial part of PCB design, significantly impacts design cycle time and system reliability. BGA (Block Grid Array) is a widely used chip packaging method, typically in the form of a pin array. Escape routing primarily addresses BGA routing scenarios, requiring the determination of escape paths from pads within the BGA to its boundaries, making it a critical stage in the PCB routing process. Synchronous escape routing is a refined scenario of escape routing, involving the coordinated routing of multiple BGAs. The escape order between two BGAs needs to be matched to avoid net crossings. The escape order affects the escape paths of nets within the BGA and the final routing result, potentially rendering a previously solvable problem unsolvable.

[0003] Existing synchronous escape routing methods typically involve two steps: determining the escape order and completing the routing path. If the first BGA is escaped out of order, and the second BGA is then escaped in an ordered manner to match the order of the first BGA, the second BGA will likely fail to escape. If the escape order is determined first, and then the two BGAs are escaped in an ordered manner, the final routing quality is largely affected by the escape order determined in the previous step, and may even cause synchronous escape routing to fail. Furthermore, a high-quality escape order consumes a significant amount of time. Therefore, a method is needed that considers both the escape order and the routing path simultaneously and completes synchronous escape routing in the same step. Summary of the Invention

[0004] The purpose of this section is to outline some aspects of embodiments of the present invention and to briefly describe some preferred embodiments. Simplifications or omissions may be made in this section, as well as in the abstract and title of this application, to avoid obscuring the purpose of these documents; however, such simplifications or omissions should not be construed as limiting the scope of the invention.

[0005] In view of the problems of the above-mentioned or existing synchronous escape routing methods based on multi-commodity flow, the present invention is proposed.

[0006] To solve the above-mentioned technical problems, the present invention provides the following technical solution:

[0007] This invention provides a synchronous escape routing method based on multi-commodity flow, including: creating a GPA routing graph based on a chip grid pin array, and creating an irregular pin array routing graph based on the array of missing pins;

[0008] Based on the created GPA wiring graph, create escape boundary nodes in the synchronous escape wiring;

[0009] Based on the creation of escape boundary nodes, a synchronous escape overall wiring graph is created.

[0010] Based on the creation of the synchronous escape overall routing graph, a synchronous escape routing model based on multi-product flow is created;

[0011] By solving the synchronous escape routing model, the routing results are obtained, and constraints for grouped same-layer routing in synchronous escape routing are designed.

[0012] The routing path of the synchronous escape routing model is optimized, and the synchronous escape routing is accelerated based on the optimization results.

[0013] As a preferred embodiment of the synchronous escape routing method based on multi-commodity flow described in this invention, the step of creating a GPA routing graph based on a chip grid pin array, and creating an irregular pin array routing graph based on the array of missing pins, includes:

[0014] Based on the pin arrangement characteristics of GPA, every four adjacent pins of GPA are taken as a tile. The line width and line spacing constraints of synchronous escape routing are converted into the capacity constraints of the tile. The adjacent capacity and diagonal capacity of GPA are divided.

[0015] Create intermediate nodes and edges corresponding to capacity constraints in the tile, and create edges between nodes corresponding to adjacent tiles;

[0016] Based on the positional relationship between missing pins and pins to be connected or other pins, three basic types of missing pins are proposed to improve the pin array wiring diagram and make full use of wiring resources.

[0017] As a preferred embodiment of the synchronous escape routing method based on multi-commodity flow described in this invention, the step of creating escape boundary nodes in the synchronous escape routing according to the created routing graph includes:

[0018] For a block tile located at the escape boundary of the grid pin array GPA, create an escape boundary node corresponding to the intermediate node of the block tile, and interconnect the intermediate node with the node.

[0019] As a preferred embodiment of the synchronous escape routing method based on multi-commodity flow described in this invention, the step of creating the overall synchronous escape routing graph based on the creation of escape boundary nodes includes:

[0020] Determine the relationship between the escape boundary nodes of the left and right BGAs and the number of pins to be connected:

[0021] When the number of escape boundary nodes of both is greater than the number of pins to be connected, the escape boundary nodes are first sorted according to the clockwise or counterclockwise rule, all escape boundary nodes of the left BGA are taken as the first column, and a virtual node with one less column of nodes than the current column is created as the next column.

[0022] Simultaneously, create virtual edges from the i-th and i+1-th nodes in the current column to the i-th virtual node in the next column, until the number of virtual nodes in the current column is the same as the number of escape boundary nodes in the right-hand BGA.

[0023] Finally, a virtual edge is created between the j-th virtual node in this column and the j-th escape boundary node of the BGA on the right, completing the creation of the overall wiring graph.

[0024] As a preferred embodiment of the synchronous escape routing method based on multi-product flow described in this invention, the step of creating a synchronous escape routing model based on multi-product flow according to the creation of the overall synchronous escape routing graph includes:

[0025] The decision variable x(n,e) is determined to take values ​​of 0 or 1.

[0026] When the decision variable is 1, it means that the wire mesh n uses edge e in the wiring graph graph for wiring;

[0027] When the decision variable is 0, it means that edge e was not used when the net n was wired;

[0028] Meanwhile, the value of n is in the range of all nets, and the value of e is in the range of all directed edges in the wiring diagram.

[0029] As a preferred embodiment of the synchronous escape routing method based on multi-commodity flow described in this invention, the step of solving the synchronous escape routing model to obtain the routing result and designing constraints for grouped layers in the synchronous escape routing includes:

[0030] The optimization objective is to minimize the bus length and avoid loops in the routing path of the network. The routing results are obtained by solving the model.

[0031] Based on the flow demand constraints, flow conservation constraints, and edge capacity constraints of multi-product flow, node capacity constraints are added to limit the total usage of nodes to no more than the node's capacity limit, thus avoiding crossover of wireline cabling paths.

[0032] Create a bottom-level routing graph below the top layer where the pin is located, and assign vias as edges in the overall routing graph to the pin to be connected. The vias connect the nodes of the top-level routing graph to the nodes of the bottom layer.

[0033] By adding any two nets n located in the same group, and using the constraint that the total number of vias is equal, the same-layer constraint of the group is achieved, and a set of candidate vias is specified for net n.

[0034] If a via is not in the candidate via set of the net n, then add a constraint in the model where the corresponding decision variable is 0.

[0035] As a preferred embodiment of the synchronous escape routing method based on multi-commodity flow described in this invention, the step of optimizing the routing path of the synchronous escape routing model and accelerating the synchronous escape routing based on the optimization result includes:

[0036] Taking nodes in the wiring graph as objects, we add terms related to the angles of the incoming and outgoing edges at nodes to the optimization objective, and transform the optimization objective from a quadratic term to a linear term by adding new decision variables, thus achieving the linearization transformation and minimizing path deflection.

[0037] The direct connection between the start and end points of net n is used as the heuristic edge. On the basis of the basic cost, the heuristic cost related to the distance and angle of the heuristic edge is added to the edge in the routing graph, thereby improving the optimization objective function and accelerating routing.

[0038] A synchronous escape wiring device based on multi-commodity flow, characterized in that it comprises:

[0039] The BGA routing diagram creation module is used to create a GPA routing diagram graph based on the chip grid pin array, create an irregular pin array routing diagram graph based on the array of missing pins, and create escape boundary nodes in synchronous escape routing based on the created GPA routing diagram graph.

[0040] The overall routing diagram creation module is used to create a synchronous escape overall routing diagram (graph) based on the escape boundary node creation module.

[0041] The model building module is used to create a synchronous escape routing model based on multiple commodity flows, according to the creation of the synchronous escape overall routing graph.

[0042] The constraint design module is used to solve the synchronous escape routing model to obtain the routing results and design the constraints of the same layer in the synchronous escape routing.

[0043] The model path optimization module optimizes the routing path of the synchronous escape routing model and accelerates the synchronous escape routing based on the optimization results.

[0044] A computing device, the computing device comprising:

[0045] At least one processor, memory, and input / output unit;

[0046] The memory is used to store computer programs, and the processor is used to call the computer programs stored in the memory to execute the steps of the synchronous escape wiring method based on multi-commodity flow.

[0047] A computer-readable storage medium includes instructions that, when executed on a computer, cause the computer to perform steps of a synchronous escape wiring method based on a multi-commodity flow.

[0048] The beneficial effects of this invention are as follows: This invention provides a synchronous escape routing method based on multi-commodity flow. Its advantage is that it completes the determination of escape order and routing path in the same step. By modeling multi-layer synchronous escape routing constraints and path optimization methods, it can minimize the overall routing path deflection while ensuring the synchronization rate. In addition, the synchronous escape routing method supports the simultaneous application of multiple acceleration methods to improve system efficiency. Attached Figure Description

[0049] To more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings used in the following description of the embodiments will be briefly introduced. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0050] Figure 1 is a flowchart of a synchronous escape routing method based on multi-commodity flow provided by an embodiment of the present invention.

[0051] Figure 2 is a schematic diagram of a synchronous escape wiring device based on multi-commodity flow provided in an embodiment of the present invention.

[0052] Figure 3 schematically illustrates the structure of a medium according to an embodiment of the present invention.

[0053] Figure 4 schematically illustrates the structure of a computing device according to an embodiment of the present invention.

[0054] Figure 5 is a GPA wiring diagram with adjacent capacity of 1 and diagonal capacity of 2 in an embodiment of the synchronous escape wiring method based on multi-commodity flow provided by the present invention.

[0055] Figure 6 is a wiring diagram of GPA with adjacent capacity of 2 and diagonal capacity of 3 in an embodiment of the synchronous escape wiring method based on multi-commodity flow provided by the present invention.

[0056] Figure 7 is a schematic diagram of three basic types of missing pins in an embodiment of a synchronous escape routing method based on multi-commodity flow provided by the present invention.

[0057] Figure 8 is a schematic diagram of virtual nodes and virtual edges between pin arrays in an embodiment of a synchronous escape routing method based on multi-commodity flow provided by the present invention.

[0058] Figure 9 is a schematic diagram of the through-hole edge of an embodiment of a synchronous escape wiring method based on multiple commodity flows provided by the present invention.

[0059] Figure 10 is a schematic diagram of the wire mesh heuristic edge of an embodiment of the synchronous escape routing method based on multi-commodity flow provided by the present invention.

[0060] In the accompanying drawings, the same or corresponding reference numerals indicate the same or corresponding parts. Detailed Implementation

[0061] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, the specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0062] Many specific details are set forth in the following description in order to provide a full understanding of the invention. However, the invention may also be practiced in other ways different from those described herein, and those skilled in the art can make similar extensions without departing from the spirit of the invention. Therefore, the invention is not limited to the specific embodiments disclosed below.

[0063] Secondly, the term "one embodiment" or "embodiment" as used herein refers to a specific feature, structure, or characteristic that may be included in at least one implementation of the present invention. The phrase "in one embodiment" appearing in different places in this specification does not necessarily refer to the same embodiment, nor is it a single or selective embodiment that is mutually exclusive with other embodiments.

[0064] Example 1

[0065] Referring now to Figure 1, which is a flowchart of a synchronous escape routing method based on multi-product flow according to an embodiment of the present invention, it should be noted that the embodiments of the present invention can be applied to any applicable scenario.

[0066] Figure 1 shows a flowchart of a synchronous escape routing method based on multi-commodity flow provided by an embodiment of the present invention, including:

[0067] S1: Based on the chip grid pin array, create a GPA routing graph. Based on the array of missing pins, create an irregular pin array routing graph. Based on the created routing graph, create escape boundary nodes in the synchronous escape routing.

[0068] Preferably, as shown in Figures 5 and 6, a grid pin array (GPA) routing graph is created. Based on the pin arrangement characteristics of the GPA, every four adjacent pins of the GPA are taken as a tile. The line width and spacing constraints of the synchronous escape routing are converted into capacity constraints of the tile. The GPA is divided into adjacent capacity and diagonal capacity. In the tile, intermediate nodes and edges corresponding to the capacity constraints are created, and edges are created between the corresponding nodes of adjacent tiles.

[0069] Preferably, as shown in Figure 7, an irregular pin array wiring diagram with missing pins is created. Based on the positional relationship between the missing pins and the pins to be connected or other pins, three basic types of missing pins are proposed to improve the pin array wiring diagram and make full use of wiring resources.

[0070] Preferably, as shown in Figure 8, an escape boundary node is created in the synchronous escape routing. For a block tile located at the escape boundary of the mesh pin array GPA, an escape boundary node corresponding to the intermediate node of the block tile is created, and the intermediate node is interconnected with the node.

[0071] S2: Create the overall routing graph for synchronous escape based on the escape boundary node.

[0072] Preferably, a synchronous escape overall routing graph is created, and the relationship between the escape boundary nodes of the left and right BGAs and the number of pins to be connected is determined:

[0073] When the number of escape boundary nodes in both BGA and BGA is greater than the number of pins to be connected, the escape boundary nodes are first sorted in a clockwise or counterclockwise order. All escape boundary nodes of the left BGA are taken as the first column, and a virtual node with one less column of nodes than the current column is created as the next column. At the same time, a virtual edge is created from the i-th and i+1-th nodes of the current column to the i-th virtual node of the next column. This process continues until the number of virtual nodes in the current column is the same as the number of escape boundary nodes in the right BGA. Finally, a virtual edge is created between the j-th virtual node in this column and the j-th escape boundary node of the right BGA, thus completing the creation of the overall routing graph.

[0074] S3: Based on the created synchronous escape routing graph, create a synchronous escape routing model based on multi-product flow.

[0075] Preferably, the decision variable x(n,e) is set to a value range of 0 or 1. When the decision variable is 1, it means that the net n uses edge e in the wiring graph for wiring. When the decision variable is 0, it means that the net n does not use edge e when wiring. At the same time, the value range of n is all nets, and the value range of e is all directed edges in the wiring graph.

[0076] S4: By solving the synchronous escape routing model, the routing results are obtained, and constraints for grouped same-layer routing in synchronous escape routing are designed.

[0077] Preferably, the optimization objective is to minimize the bus length and avoid generating loops in the routing path of the network. The routing result is obtained by solving the model.

[0078] Based on the flow demand constraints, flow conservation constraints, and edge capacity constraints of multi-product flow, node capacity constraints are added to limit the total usage of nodes to no more than the node's capacity limit, thus avoiding crossover of wireline cabling paths.

[0079] As shown in Figure 9, firstly, a bottom-level routing graph is created below the top layer where the pin is located. At the same time, vias are assigned to the pins to be connected. The vias serve as edges in the overall routing graph, connecting the nodes of the top-level routing graph with the nodes of the bottom layer.

[0080] By adding any two nets n located in the same group and using the constraint that the total number of vias is equal, the same-layer constraint of the group is achieved, and a set of candidate vias is specified for net n.

[0081] If a via is not in the candidate via set of the net n, then add a constraint in the model where the corresponding decision variable is 0.

[0082] S5: Optimize the routing path of the synchronous escape routing model and accelerate the synchronous escape routing based on the optimization results.

[0083] Preferably, as shown in Figure 10, taking the node in the wiring graph as the object, the optimization objective is to add a term related to the angle of the incoming and outgoing edges at the node, and by adding a new decision variable, the optimization objective is changed from a quadratic term to a linear term, thus completing the linearization transformation and minimizing the path bend.

[0084] The direct connection between the start and end points of net n is used as the heuristic edge. On the basis of the basic cost, the heuristic cost related to the distance and angle of the heuristic edge is added to the edge in the routing graph, thereby improving the optimization objective function and accelerating routing.

[0085] Example 2

[0086] Another embodiment of the present invention:

[0087] Preferably, a Point class is designed, which includes the attributes x-coordinate, y-coordinate, and layer index; a Node class is designed, which inherits from the Point class and includes the attributes id, flow, net number, and capacity. When flow is 1 or -1, it indicates that it is the start or end point of the net, respectively, while when it is 0, it indicates other nodes.

[0088] Preferably, design an Edge class containing attributes such as start node, end node, capacity, and cost; design a Rect class containing attributes such as left boundary x-coordinate, right boundary x-coordinate, top boundary y-coordinate, and bottom boundary y-coordinate.

[0089] Preferably, the Pin class is designed, which includes the attribute column index x, row index y, net, group identifier group, whether it is a starting point flag, candidate via set availableVias, and candidate channel set availableSwitchEdges.

[0090] Preferably, a BGA class is designed and inherits from the Rect class, which includes the following attributes: the number of rows (height), the number of columns (width), the set of pins to be connected (pins), the set of missing pins (missPins), the adjacent capacity (orthogonalCapacity), the diagonal capacity (diagonalCapacity), and the escape boundary (boundary).

[0091] Preferably, the MCFSolver class is designed to include two horizontally placed BGA objects (bgas), netNum, nets, nodes, edges, flows, totalWireLength, totalViaNum, totalBendNum, and totalRuntime.

[0092] Specifically, in the main function, an MCFSolver object mcf is first constructed and its attribute bgas is initialized. Each tile of each BGA is traversed, and nodes and edges that satisfy the BGA capacity constraints are created in the current tile. If other tiles exist in the four adjacent directions of the current tile, edges are created between the corresponding nodes of the adjacent tiles and the current tile.

[0093] If the current tile is located on the escape boundary of the BGA, an escape node escnode is created on the boundary, and an edge from the corresponding node in the tile to the escape node is created. If there are pins in the current tile located in the pins or missPins properties of the BGA, nodes and edges are created or removed according to the three basic types. All escape nodes in the left BGA are sorted in a clockwise direction, and all escape nodes in the right BGA are sorted in a counterclockwise direction. The side with more escape nodes is selected and virtual nodes imgNode and virtual edges imgEdge are created in a column-decreasing manner. All created nodes and edges, as well as virtual nodes and virtual edges, are set to the nodes and edges properties respectively.

[0094] Similarly, create the underlying routing diagram and vias, traverse all nets and nodes, and if the net attribute of the current net is equal to that of the current node, set the corresponding flow to the flow attribute of the current node. Initialize the cplex model and create a decision variable x(n, e), where x(n, e) takes the value 0 or 1. Add flow demand constraints, flow conservation constraints, edge capacity constraints, node capacity constraints, and net candidate via constraints to the model, and set the optimization objective to minimize the total cost. Solve the model. If a feasible solution exists, transform the feasible solution according to the rule that when the decision variable x(n, e) is 1, net n uses edge e for routing, and when it is 0, net n does not use edge e for routing, to obtain the routing result. Finally, calculate the bus length, total number of vias, total number of bends, and total running time, and display the output.

[0095] After introducing the method of an exemplary embodiment of the present invention, the following description, with reference to FIG2, will illustrate an exemplary embodiment of the present invention of a synchronous escape wiring device based on a multi-commodity flow, the device comprising:

[0096] The BGA routing diagram creation module is used to create a GPA routing diagram graph based on the chip grid pin array, create an irregular pin array routing diagram graph based on the array of missing pins, and create escape boundary nodes in synchronous escape routing based on the created GPA routing diagram graph.

[0097] The overall routing diagram creation module is used to create a synchronous escape overall routing diagram (graph) based on the escape boundary node creation module.

[0098] The model building module is used to create a synchronous escape routing model based on multiple commodity flows, according to the creation of the synchronous escape overall routing graph.

[0099] The constraint design module is used to solve the synchronous escape routing model to obtain the routing results and design the constraints of the same layer in the synchronous escape routing.

[0100] The model path optimization module optimizes the routing path of the synchronous escape routing model and accelerates the synchronous escape routing based on the optimization results.

[0101] After introducing the method and apparatus of exemplary embodiments of the present invention, the computer-readable storage medium of exemplary embodiments of the present invention will now be described with reference to FIG3. FIG3 shows that the computer-readable storage medium is an optical disc 30, on which a computer program (i.e., a program product) is stored. When the computer program is run by a processor, it will implement the steps described in the above method embodiments. For example, based on the chip grid pin array, a GPA wiring graph is created; based on the array of missing pins, an irregular pin array wiring graph is created; based on the created GPA wiring graph, escape boundary nodes are created in the synchronous escape wiring; based on the created escape boundary nodes, an overall synchronous escape wiring graph is created; based on the created overall synchronous escape wiring graph, a synchronous escape wiring model based on multi-commodity flow is created; by solving the synchronous escape wiring model, wiring results are obtained, and constraints for grouped same-layer synchronous escape wiring are designed; the wiring path of the synchronous escape wiring model is optimized, and the synchronous escape wiring is accelerated based on the optimization results; the specific implementation of each step will not be repeated here.

[0102] It should be noted that examples of the computer-readable storage medium may also include, but are not limited to, phase-change memory (PRAM), static random access memory (SRAM), dynamic random access memory (DRAM), other types of random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory or other optical and magnetic storage media, which will not be elaborated here.

[0103] After introducing the methods, apparatus and media of exemplary embodiments of the present invention, the computing device of the present invention based on synchronous escape wiring of multi-commodity flow according to exemplary embodiments of the present invention will now be described with reference to FIG4.

[0104] Figure 4 shows a block diagram of an exemplary computing device 40 suitable for implementing embodiments of the present invention. The computing device 40 may be a computer system or a server. The computing device 40 shown in Figure 4 is merely an example and should not be construed as limiting the functionality or scope of the embodiments of the present invention.

[0105] As shown in Figure 4, the components of the computing device 40 may include, but are not limited to: one or more processors or processing units 401, system memory 402, and bus 403 connecting different system components (including system memory 402 and processing unit 401).

[0106] The computing device 40 typically includes a variety of computer system readable media. These media can be any available media that can be accessed by the computing device 40, including volatile and non-volatile media, and removable and non-removable media.

[0107] System memory 402 may include computer system readable media in the form of volatile memory, such as random access memory (RAM) 4021 and / or cache memory 4022. Computing device 40 may further include other removable / non-removable, volatile / non-volatile computer system storage media. By way of example only, ROM 4023 may be used to read and write non-removable, non-volatile magnetic media (not shown in FIG. 4, commonly referred to as a "hard disk drive"). Although not shown in FIG. 4, disk drives for reading and writing to removable non-volatile disks (e.g., "floppy disks") and optical disk drives for reading and writing to removable non-volatile optical disks (e.g., CD-ROMs, DVD-ROMs, or other optical media) may be provided. In these cases, each drive may be connected to bus 403 via one or more data media interfaces. System memory 402 may include at least one program product having a set (e.g., at least one) of program modules configured to perform the functions of the embodiments of the present invention.

[0108] A program / utility 4025 having a set (at least one) of program modules 4024 may be stored, for example, in system memory 402, and such program modules 4024 include, but are not limited to, an operating system, one or more application programs, other program modules, and program data, each or some combination of these examples may include an implementation of a network environment. Program modules 4024 typically perform the functions and / or methods described in the embodiments of the present invention.

[0109] The computing device 40 can also communicate with one or more external devices 404 (such as a keyboard, pointing device, display, etc.). This communication can be performed through the input / output (I / O) interface 405. Furthermore, the computing device 40 can also communicate with one or more networks (e.g., local area networks (LANs), wide area networks (WANs), and / or public networks, such as the Internet) via a network adapter 406. As shown in Figure 4, the network adapter 406 communicates with other modules of the computing device 40 (such as the processing unit 401, etc.) via a bus 403. It should be understood that, although not shown in Figure 4, other hardware and / or software modules can be used in conjunction with the computing device 40.

[0110] The processing unit 401 executes various functional applications and data processing by running programs stored in the system memory 402. For example, it creates a GPA wiring graph based on a chip grid pin array; creates an irregular pin array wiring graph based on an array of missing pins; creates escape boundary nodes in synchronous escape wiring based on the created GPA wiring graph; creates an overall synchronous escape wiring graph based on the created escape boundary nodes; creates a synchronous escape wiring model based on a multi-commodity flow based on the created overall synchronous escape wiring graph; obtains wiring results by solving the synchronous escape wiring model; designs constraints for grouped layers in synchronous escape wiring; optimizes the wiring path of the synchronous escape wiring model; and accelerates synchronous escape wiring based on the optimization results. The specific implementation methods of each step will not be repeated here. It should be noted that although several units / modules or sub-units / sub-modules of the synchronous escape wiring device based on a multi-commodity flow are mentioned in the detailed description above, this division is merely exemplary and not mandatory. In fact, according to embodiments of the present invention, the features and functions of two or more units / modules described above can be embodied in one unit / module. Conversely, the features and functions of one unit / module described above can be further divided and embodied by multiple units / modules.

[0111] In the description of this invention, it should be noted that the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0112] Those skilled in the art will understand that, for the sake of convenience and brevity, the specific working processes of the systems, devices, and units described above can be referred to the corresponding processes in the foregoing method embodiments, and will not be repeated here.

[0113] In the several embodiments provided by this invention, it should be understood that the disclosed systems, apparatuses, and methods can be implemented in other ways. The apparatus embodiments described above are merely illustrative. For example, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. Furthermore, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Additionally, the coupling or direct coupling or communication connection shown or discussed may be through some communication interfaces; the indirect coupling or communication connection between devices or units may be electrical, mechanical, or other forms.

[0114] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0115] In addition, the functional units in the various embodiments of the present invention can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit.

[0116] If the aforementioned functions are implemented as software functional units and sold or used as independent products, they can be stored in a processor-executable, non-volatile, computer-readable storage medium. Based on this understanding, the technical solution of the present invention, or the part that contributes to the prior art, or a portion of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of the present invention. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0117] Finally, it should be noted that the above-described embodiments are merely specific implementations of the present invention, used to illustrate the technical solutions of the present invention, and not to limit it. The scope of protection of the present invention is not limited thereto. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that any person skilled in the art can still modify or easily conceive of changes to the technical solutions described in the foregoing embodiments within the technical scope disclosed in the present invention, or make equivalent substitutions for some of the technical features; and these modifications, changes, or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention, and should all be covered within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

[0118] Furthermore, although the operations of the method of the present invention are described in a specific order in the accompanying drawings, this does not require or imply that these operations must be performed in that specific order, or that all the operations shown must be performed to achieve the desired result. Additionally or alternatively, certain steps may be omitted, multiple steps may be combined into one step, and / or one step may be broken down into multiple steps.

Claims

1. A synchronous escape routing method based on multi-commodity flow, characterized in that, include: Based on the chip grid pin array, create a GPA routing graph; based on the array of missing pins, create an irregular pin array routing graph. Based on the created GPA wiring graph, create escape boundary nodes in the synchronous escape wiring; Based on the creation of escape boundary nodes, a synchronous escape overall wiring graph is created. Based on the creation of the synchronous escape overall routing graph, a synchronous escape routing model based on multi-product flow is created; By solving the synchronous escape routing model, the routing results are obtained, and constraints for grouped same-layer routing in synchronous escape routing are designed. The routing path of the synchronous escape routing model is optimized, and the synchronous escape routing is accelerated based on the optimization results.

2. The multi-commodity flow based synchronized escape routing method of claim 1, wherein, The process of creating a GPA routing graph based on a chip grid pin array, and creating an irregular pin array routing graph based on an array of missing pins, includes: Based on the pin arrangement characteristics of GPA, every four adjacent pins of GPA are taken as a tile. The line width and line spacing constraints of synchronous escape routing are converted into the capacity constraints of the tile. The adjacent capacity and diagonal capacity of GPA are divided. Create intermediate nodes and edges corresponding to capacity constraints in the tile, and create edges between nodes corresponding to adjacent tiles; Based on the positional relationship between missing pins and pins to be connected or other pins, three basic types of missing pins are proposed to improve the pin array wiring diagram and make full use of wiring resources.

3. The multi-commodity flow based synchronized escape routing method of claim 1, wherein, The step of creating escape boundary nodes in synchronous escape routing based on the created routing graph includes: For a block tile located at the escape boundary of the grid pin array GPA, create an escape boundary node corresponding to the intermediate node of the block tile, and interconnect the intermediate node with the node.

4. The multi-commodity flow based synchronized escape routing method of claim 1, wherein, The step of creating the overall routing graph for synchronous escape based on the escape boundary node includes: Determine the relationship between the escape boundary nodes of the left and right BGAs and the number of pins to be connected: When the number of escape boundary nodes of both is greater than the number of pins to be connected, the escape boundary nodes are first sorted according to the clockwise or counterclockwise rule, all escape boundary nodes of the left BGA are taken as the first column, and a virtual node with one less column of nodes than the current column is created as the next column. Simultaneously, create virtual edges from the i-th and i+1-th nodes in the current column to the i-th virtual node in the next column, until the number of virtual nodes in the current column is the same as the number of escape boundary nodes in the right-hand BGA. Finally, a virtual edge is created between the j-th virtual node in this column and the j-th escape boundary node of the BGA on the right, completing the creation of the overall wiring graph.

5. The multi-commodity flow based synchronized escape routing method of claim 1, wherein, The step of creating a synchronous escape routing model based on a multi-product flow, according to the previously created synchronous escape overall routing graph, includes: The decision variable x(n,e) is determined to take values ​​of 0 or 1. When the decision variable is 1, it means that the wire mesh n uses edge e in the wiring graph graph for wiring; When the decision variable is 0, it means that edge e was not used when the net n was wired; Meanwhile, the value of n is in the range of all nets, and the value of e is in the range of all directed edges in the wiring diagram.

6. The multi-commodity flow based synchronized escape routing method of claim 1, wherein, The process involves solving the synchronous escape routing model to obtain the routing results, and designing constraints for grouped layers in the synchronous escape routing, including: The optimization objective is to minimize the bus length and avoid loops in the routing path of the network. The routing results are obtained by solving the model. Based on the flow demand constraints, flow conservation constraints, and edge capacity constraints of multi-product flow, node capacity constraints are added to limit the total usage of nodes to no more than the node's capacity limit, thus avoiding crossover of wireline cabling paths. Create a bottom-level routing graph below the top layer where the pin is located, and assign vias as edges in the overall routing graph to the pin to be connected. The vias connect the nodes of the top-level routing graph to the nodes of the bottom layer. By adding any two nets n located in the same group, and using the constraint that the total number of vias is equal, the same-layer constraint of the group is achieved, and a set of candidate vias is specified for net n. If a via is not in the candidate via set of the net n, then add a constraint in the model where the corresponding decision variable is 0.

7. The multi-commodity flow based synchronized escape routing method of claim 1, wherein, The optimization of the routing path in the synchronous escape routing model, and the acceleration of synchronous escape routing based on the optimization results, includes: Taking nodes in the wiring graph as objects, we add terms related to the angles of the incoming and outgoing edges at nodes to the optimization objective, and transform the optimization objective from a quadratic term to a linear term by adding new decision variables, thus achieving the linearization transformation and minimizing path deflection. The direct connection between the start and end points of net n is used as the heuristic edge. On the basis of the basic cost, the heuristic cost related to the distance and angle of the heuristic edge is added to the edge in the routing graph, thereby improving the optimization objective function and accelerating routing.

8. A multi-commodity flow based simultaneous escape routing apparatus, characterized by, include: The BGA routing diagram creation module is used to create a GPA routing diagram graph based on the chip grid pin array, create an irregular pin array routing diagram graph based on the array of missing pins, and create escape boundary nodes in synchronous escape routing based on the created GPA routing diagram graph. The overall routing diagram creation module is used to create a synchronous escape overall routing diagram (graph) based on the escape boundary node creation module. The model building module is used to create a synchronous escape routing model based on multiple commodity flows, according to the creation of the synchronous escape overall routing graph. The constraint design module is used to solve the synchronous escape routing model to obtain the routing results and design the constraints of the same layer in the synchronous escape routing. The model path optimization module optimizes the routing path of the synchronous escape routing model and accelerates the synchronous escape routing based on the optimization results.

9. A computing device, the computing device comprising: At least one processor, memory, and input / output unit; The memory is used to store a computer program, and the processor is used to call the computer program stored in the memory to execute the steps of the synchronous escape wiring method based on multiple commodity flows as described in any one of claims 1 to 7.

10. A computer-readable storage medium comprising instructions that, when executed on a computer, cause the computer to perform the steps of the synchronous escape wiring method based on a multi-commodity flow as described in any one of claims 1 to 7.

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