Array substrate, driving method and display apparatus

Abstract

The present disclosure provides an array substrate, a driving method, and a display apparatus. The array substrate comprises a base, and a driving circuit disposed on the base. The driving circuit comprises a carry signal providing circuit and a number N of driving signal providing circuits, N being a positive integer. The carry signal providing circuit is used for providing a carry signal, and the driving signal providing circuits are used for providing driving signals. The carry signal providing circuit and the driving signal providing circuits are arranged along a first direction. The array substrate further comprises scan lines disposed on the base. The driving signal providing circuits are electrically connected to corresponding scan lines, and are used for providing driving signals for the scan lines. The direction of extension of the scan lines is a second direction, and the first direction intersects the second direction. The present disclosure helps to achieve a narrow bezel.

Description

Array substrate, driving method and display device

[0001] Cross-references to related applications

[0002] This application claims priority to Chinese Patent Application No. 202411612742.X, filed in China on November 12, 2024, the entire contents of which are incorporated herein by reference. Technical Field

[0003] This disclosure relates to the field of display technology, and in particular to an array substrate, a driving method, and a display device. Background Technology

[0004] The related display devices cannot reduce the number of transistors provided by the driving circuit while simultaneously narrowing the horizontal bezel by arranging the carry signal providing circuit and the driving signal providing circuit, which is not conducive to achieving a narrow bezel. Summary of the Invention

[0005] The main objective of this disclosure is to provide an array substrate, a driving method, and a display device that solve the problem of not being able to achieve narrow bezels in related technologies.

[0006] In one aspect, embodiments of this disclosure provide an array substrate, including a substrate and a driving circuit disposed on the substrate; the driving circuit includes a carry signal providing circuit and N driving signal providing circuits; N is a positive integer;

[0007] The carry signal providing circuit is used to provide a carry signal; the drive signal providing circuit is used to provide a drive signal;

[0008] The carry signal providing circuit and the drive signal providing circuit are arranged along a first direction;

[0009] The array substrate further includes scan lines disposed on the substrate; the drive signal providing circuit is electrically connected to the corresponding scan lines and is used to provide drive signals to the scan lines.

[0010] The scanning line extends in a second direction, and the first direction intersects with the second direction.

[0011] Optionally, the carry signal providing circuit includes a carry output circuit, and the drive signal providing circuit includes a drive output circuit; the carry output circuit is used to provide a carry signal according to a carry clock signal under the control of the potential of the carry node; the drive output circuit is used to provide a drive signal according to a corresponding drive clock signal under the control of the potential of the corresponding drive node.

[0012] The channel width-to-length ratio of the transistors included in the carry output circuit is smaller than that of the channel width-to-length ratio of the drive output circuit.

[0013] Optionally, the carry output circuit includes a transistor whose gate includes p first sub-gates that are electrically connected to each other, and adjacent first sub-gates are electrically connected through a first connecting portion;

[0014] The drive output circuit includes a transistor whose gate includes m interconnected second sub-gates, and adjacent second sub-gates are electrically connected through a second connection portion;

[0015] p and m are positive integers, where m is greater than p.

[0016] Optionally, the carry-out output circuit includes at least two first sub-gates with different shapes; and / or, the carry-out output circuit includes at least two first sub-gates with different dimensions; or,

[0017] The drive output circuit includes at least two second sub-gates with different shapes; and / or, the drive output circuit includes at least two second sub-gates with different sizes.

[0018] Optionally, the carry signal providing circuit further includes a carry reset circuit, which is used to reset the carry signal under the control of the potential of the second node;

[0019] The carry-out output circuit includes a transistor with an active pattern comprising a first active pattern portion and at least one second active pattern portion.

[0020] The first active pattern portion and the active patterns of the transistors included in the carry-reset circuit are arranged along a first direction.

[0021] Optionally, the first active graphic portion and the second active graphic portion are arranged along a second direction.

[0022] Optionally, the carry signal providing circuit includes a carry energy storage circuit; the carry energy storage circuit is electrically connected to the carry node and the carry signal output terminal respectively; one plate of the capacitor included in the carry energy storage circuit is electrically connected to the corresponding cascade line through a first via.

[0023] The capacitor plates in the carry-in energy storage circuit have a first clearance space.

[0024] Optionally, the carry signal providing circuit includes a first transistor;

[0025] The first transistor is located on the side of the carry energy storage circuit away from the carry output circuit;

[0026] The active pattern of the first transistor has a second clearance space to avoid the first via.

[0027] Optionally, the first transistor and the capacitors included in the carry energy storage circuit are arranged along the second direction.

[0028] Optionally, the carry signal providing circuit includes a carry node reset circuit; the carry node reset circuit is used to reset the potential of the carry node under the control of a reset signal provided at the reset terminal.

[0029] The carry node reset circuit includes the first transistor.

[0030] Optionally, the drive signal providing circuit includes a drive energy storage circuit; the drive energy storage circuit is connected to the drive node and the drive signal output terminal respectively.

[0031] The shape of the capacitor included in the carry energy storage circuit is different from the shape of the capacitor included in the drive energy storage circuit; and / or,

[0032] The size of the capacitor plates in the carry energy storage circuit is different from the size of the capacitor in the drive energy storage circuit.

[0033] Optionally, the drive signal providing circuit includes a drive node reset circuit, which is used to reset the potential of the drive node under the control of the reset signal.

[0034] The shape of the transistor included in the carry node reset circuit is different from the shape of the transistor included in the drive node reset circuit; and / or,

[0035] The transistors included in the carry node reset circuit have different dimensions than those included in the drive node reset circuit.

[0036] Optional, N is greater than 1;

[0037] The N drive signal providing circuits include transistors of the same shape that have the same function; and / or,

[0038] The N drive signal providing circuits include transistors of the same size that have the same function.

[0039] Optionally, the carry signal providing circuit includes a carry node control circuit, a carry node reset circuit, a second node control circuit, a carry output circuit, a carry reset circuit, and a carry energy storage circuit.

[0040] The carry node control circuit is electrically connected to the input terminal, the second node, and the carry node, respectively. It is used to control the potential of the carry node under the control of the input signal provided by the input terminal, and to reset the potential of the carry node under the control of the potential of the second node.

[0041] The carry node reset circuit is electrically connected to the reset terminal and the carry node respectively, and is used to reset the potential of the carry node under the control of the reset signal provided by the reset terminal;

[0042] The second node control circuit is electrically connected to the carry node and the second node respectively, and is used to control the potential of the second node under the control of the potential of the carry node;

[0043] The carry output circuit is electrically connected to the carry node, the carry clock signal terminal and the carry signal output terminal respectively, and is used to write the carry clock signal provided by the carry clock signal terminal into the carry signal output terminal under the control of the potential of the carry node.

[0044] The carry reset circuit is electrically connected to the second node and the carry signal output terminal respectively, and is used to reset the carry signal provided by the carry signal output terminal under the control of the potential of the second node;

[0045] The carry energy storage circuit is electrically connected to the carry node and the carry signal output terminal, respectively.

[0046] Optionally, the nth driving signal providing circuit includes an nth driving node control circuit, an nth driving node reset circuit, an nth driving output circuit, an nth driving reset circuit, and an nth driving energy storage circuit; n is a positive integer less than or equal to N;

[0047] The control circuit of the nth driving node is electrically connected to the input terminal, the second node and the nth driving node respectively, and is used to control the potential of the nth driving node under the control of the input signal provided by the input terminal, and to reset the potential of the nth driving node under the control of the potential of the second node.

[0048] The nth driving node reset circuit is electrically connected to the reset terminal and the nth driving node, and is used to reset the potential of the nth driving node under the control of the reset signal provided by the reset terminal.

[0049] The nth drive output circuit is electrically connected to the nth drive node, the nth drive clock signal terminal and the nth drive signal output terminal respectively, and is used to write the nth drive clock signal provided by the nth drive clock signal terminal into the nth drive signal output terminal under the control of the potential of the nth drive node.

[0050] The nth drive reset circuit is electrically connected to the second node and the nth drive signal output terminal, respectively, and is used to reset the nth drive signal provided by the nth drive signal output terminal under the control of the potential of the second node;

[0051] The nth driving energy storage circuit is connected to the nth driving node and the nth driving signal output terminal, respectively.

[0052] Optionally, the array substrate described in at least one embodiment of this disclosure includes a driving module; the driving module is disposed on a first side of the display area, and / or a second side of the display area; the first side and the second side are opposite sides; the driving module includes A cascaded driving circuits; A is an integer greater than 1;

[0053] The input terminal of the a-th driving circuit included in the driving module is electrically connected to the carry signal output terminal of the ab-th stage driving circuit included in the driving module.

[0054] The reset terminal of the a-th driving circuit included in the driving module is electrically connected to the carry signal output terminal of the a+c-th driving circuit included in the driving module.

[0055] a, b, and c are positive integers; a is less than or equal to A.

[0056] Optionally, the drive module further includes a virtual start drive circuit;

[0057] The virtual start-up drive circuit is used to provide corresponding input signals to the input terminal of the first-stage drive circuit included in the drive module.

[0058] In a second aspect, embodiments of this disclosure provide a driving method applied to the aforementioned array substrate, the array substrate including data lines and pixel circuits disposed on a substrate; the driving cycle includes multiple frame display times; the driving method includes: during the driving cycle,

[0059] In at least two adjacent frames, the data voltage on the pixel circuit is controlled to be a first polarity data voltage;

[0060] In at least two adjacent frames, the data voltage on the pixel circuit is controlled to be the second polarity data voltage;

[0061] The first polarity is opposite to the second polarity.

[0062] In a third aspect, embodiments of this disclosure provide a driving method applied to the aforementioned array substrate. In the a-th driving circuit, a carry signal providing circuit is electrically connected to the a-th carry clock signal terminal, and the n-th driving signal providing circuit is electrically connected to the corresponding driving clock signal terminal; in the a+c-th driving circuit, the carry signal providing circuit is electrically connected to the a+c-th carry clock signal terminal; n is a positive integer less than or equal to N; the driving method includes:

[0063] During the driving cycle of the a-th driving circuit, the N driving clock signal terminals electrically connected to the a-th driving circuit sequentially begin to output valid driving clock signals.

[0064] After the potential of the drive clock signal output from the Nth drive clock signal terminal electrically connected to the ath drive circuit changes from an effective voltage to an ineffective voltage, after a first predetermined time interval, the a+cth carry clock signal terminal is controlled to provide an effective carry clock signal.

[0065] Optionally, the first predetermined time is greater than or equal to 0.5H and less than or equal to 5H, where 1H is the scan time for one line.

[0066] In a fourth aspect, embodiments of this disclosure provide a display device including the array substrate described above.

[0067] In the array substrate, driving method, and display device described in the embodiments of this disclosure, the carry signal providing circuit and the driving signal providing circuit are horizontally separated and vertically arranged side by side, so as to narrow the horizontal space occupied by the array substrate and facilitate the realization of a narrow bezel. Attached Figure Description

[0068] Figure 1 is a structural diagram of at least one embodiment of the driving circuit;

[0069] Figure 2 is a structural diagram of at least one embodiment of the driving circuit;

[0070] Figure 3 is a circuit diagram of at least one embodiment of the driving circuit;

[0071] Figures 4 and 5A are layout diagrams of at least one embodiment of the drive circuit shown in Figure 3;

[0072] Figure 5B is a layout diagram of the semiconductor layer in Figure 5A;

[0073] Figure 5C is a layout diagram of the gate metal layer in Figure 5A;

[0074] Figure 5D is a layout diagram of the source and drain metal layers in Figure 5A;

[0075] Figure 5E is a layout diagram of the conductive layer in Figure 5A;

[0076] Figure 5F is a stack-up diagram of the gate metal layer and semiconductor layer in Figure 5A;

[0077] Figure 5G is a stack-up diagram of the semiconductor layer and source / drain metal layers in Figure 5A;

[0078] Figure 5H is a stack-up diagram of the source / drain metal layer and conductive layer in Figure 5A;

[0079] Figure 6 is a layout diagram of the carry signal providing circuit;

[0080] Figure 7A is a layout diagram of the circuit providing the first drive signal;

[0081] Figure 7B is a layout diagram of the gate metal layer in Figure 7A;

[0082] Figure 7C is a layout diagram of the source and drain metal layers in Figure 7A;

[0083] Figure 7D is a layout diagram of the semiconductor layer in Figure 7A;

[0084] Figure 7E is a layout diagram of the conductive layer in Figure 7A;

[0085] Figure 7F is a stack-up diagram of the gate metal layer and semiconductor layer in Figure 7A;

[0086] Figure 7G is a stack-up diagram of the semiconductor layer and source / drain metal layers in Figure 7A;

[0087] Figure 7H is a stack-up diagram of the source / drain metal layer and conductive layer in Figure 7A;

[0088] Figure 8 is a layout diagram of the semiconductor layer in Figure 6;

[0089] Figure 9 is a layout diagram of the gate metal layer in Figure 6;

[0090] Figure 10 is a layout diagram of the source and drain metal layers in Figure 6;

[0091] Figure 11 is a layout diagram of the conductive layer in Figure 6;

[0092] Figure 12 is a stack-up diagram of the gate metal layer and semiconductor layer in Figure 6;

[0093] Figure 13 is a layout diagram of the semiconductor layer and source / drain metal layers in Figure 6;

[0094] Figure 14 is a stack-up diagram of the source / drain metal layer and conductive layer in Figure 6;

[0095] Figure 15 is a timing diagram of at least one embodiment of the driving module;

[0096] Figure 16 is a timing diagram of at least one embodiment of the driving module;

[0097] Figure 17 shows the operating timing of the array substrate according to at least one embodiment of this disclosure. Detailed Implementation

[0098] The technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this disclosure, and not all embodiments. Based on the embodiments of this disclosure, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of this disclosure.

[0099] In all embodiments of this disclosure, the transistors used can be thin-film transistors, field-effect transistors, or other devices with similar characteristics. In the embodiments of this disclosure, to distinguish the two terminals of the transistor other than the gate, one terminal is referred to as the first terminal and the other as the second terminal.

[0100] In actual operation, when the transistor is a thin-film transistor or a field-effect transistor, the first electrode can be the drain and the second electrode can be the source; or, the first electrode can be the source and the second electrode can be the drain.

[0101] The array substrate described in this embodiment includes a substrate and a driving circuit disposed on the substrate; the driving circuit includes a carry signal providing circuit and N driving signal providing circuits; N is a positive integer;

[0102] The carry signal providing circuit is used to provide a carry signal; the drive signal providing circuit is used to provide a drive signal;

[0103] The carry signal providing circuit and the drive signal providing circuit are arranged along a first direction;

[0104] The array substrate further includes scan lines disposed on the substrate; the drive signal providing circuit is electrically connected to the corresponding scan lines and is used to provide drive signals to the scan lines.

[0105] The scanning line extends in a second direction, and the first direction intersects with the second direction.

[0106] In at least one embodiment of this disclosure, the array substrate may include a carry signal providing circuit and N drive signal providing circuits. The carry signal providing circuit and the drive signal providing circuit may be arranged along a first direction, and the scan line may extend along a second direction. The first direction intersects with the second direction.

[0107] Optionally, the first direction can be a vertical direction, and the second direction can be a horizontal direction.

[0108] In a specific implementation, the carry signal providing circuit and the drive signal providing circuit are horizontally separated and vertically arranged side by side, so as to narrow the horizontal space occupied by the array substrate and facilitate the realization of a narrow bezel.

[0109] In at least one embodiment of this disclosure, when N is greater than 1, the carry signal providing circuit can be disposed above or below the N drive signal providing circuits; or,

[0110] The carry signal providing circuit can be located in the middle of the N drive signal providing circuits to minimize the load difference caused by the inconsistent distance from the second node to each drive signal providing circuit.

[0111] For example, when N equals 4, the first drive signal providing circuit and the second drive signal providing circuit can be located above the carry signal providing circuit, and the third drive signal providing circuit and the fourth drive signal providing circuit can be located below the carry signal providing circuit.

[0112] In at least one embodiment of this disclosure, the carry signal providing circuit includes a carry output circuit, and the drive signal providing circuit includes a drive output circuit; the carry output circuit is used to provide a carry signal according to a carry clock signal under the control of the potential of the carry node; the drive output circuit is used to provide a drive signal according to a corresponding drive clock signal under the control of the potential of the corresponding drive node.

[0113] The channel width-to-length ratio of the transistors included in the carry output circuit is smaller than that of the channel width-to-length ratio of the drive output circuit.

[0114] In practical implementation, the horizontal space occupied by the carry signal providing circuit and the horizontal space occupied by the drive signal providing circuit are basically the same to ensure maximum space utilization. For the carry signal providing circuit, although a large number of transistors are used, the load at the rear end of the carry signal output terminal is small. Therefore, the channel width-to-length ratio of the transistors included in the carry output circuit can be set to be smaller than the channel width-to-length ratio of the drive output circuit, and the capacitance value of the capacitors included in the carry energy storage circuit can be set to be smaller than the capacitance value of the capacitors included in each drive energy storage circuit.

[0115] As shown in Figure 1, the array substrate of at least one embodiment of the present disclosure includes a substrate and a driving circuit disposed on the substrate; the driving circuit includes a carry signal providing circuit, a first driving signal providing circuit, a second driving signal providing circuit, a third driving signal providing circuit and a fourth driving signal providing circuit;

[0116] The carry signal providing circuit includes a carry node control circuit 11, a carry node reset circuit 12, a second node control circuit 13, a carry output circuit 14, a carry reset circuit 15, and a carry energy storage circuit 10.

[0117] The carry node control circuit 11 is electrically connected to the input terminal SR, the second node PD, and the carry node PUC, respectively. It is used to control the potential of the carry node PUC under the control of the input signal provided by the input terminal SR, and to reset the potential of the carry node PUC under the control of the potential of the second node PD.

[0118] The carry node reset circuit 12 is electrically connected to the reset terminal RST and the carry node PUC, respectively, and is used to reset the potential of the carry node PUC under the control of the reset signal provided by the reset terminal RST.

[0119] The second node control circuit 13 is electrically connected to the carry node PUC and the second node PD respectively, and is used to control the potential of the second node PD under the control of the potential of the carry node PUC;

[0120] The carry output circuit 14 is electrically connected to the carry node PUC, the carry clock signal terminal CLKC and the carry signal output terminal OUTC respectively, and is used to write the carry clock signal provided by the carry clock signal terminal CLKC into the carry signal output terminal OUTC under the control of the potential of the carry node PUC.

[0121] The carry reset circuit 15 is electrically connected to the second node PD and the carry signal output terminal OUTC, respectively, and is used to reset the carry signal provided by the carry signal output terminal OUTC under the control of the potential of the second node PD.

[0122] The carry energy storage circuit 10 is electrically connected to the carry node PUC and the carry signal output terminal OUTC respectively, and is used to store electrical energy.

[0123] The first drive signal providing circuit includes a first drive node control circuit 21, a first drive node reset circuit 22, a first drive output circuit 23, a first drive reset circuit 24, and a first drive energy storage circuit 20.

[0124] The first driving node control circuit 21 is electrically connected to the input terminal SR, the second node PD and the first driving node PU1 respectively. It is used to control the potential of the first driving node PU1 under the control of the input signal provided by the input terminal SR, and to reset the potential of the first driving node PU1 under the control of the potential of the second node PD.

[0125] The first drive node reset circuit 22 is electrically connected to the reset terminal RST and the first drive node PU1 respectively, and is used to reset the potential of the first drive node PU1 under the control of the reset signal provided by the reset terminal RST.

[0126] The first drive output circuit 23 is electrically connected to the first drive node PU1, the first drive clock signal terminal CLK1 and the first drive signal output terminal OT1 respectively, and is used to write the first drive clock signal provided by the first drive clock signal terminal CLK1 into the first drive signal output terminal OT1 under the control of the potential of the first drive node PU1.

[0127] The first drive reset circuit 24 is electrically connected to the second node PD and the first drive signal output terminal OT1 respectively, and is used to reset the first drive signal provided by the first drive signal output terminal OT1 under the control of the potential of the second node PD.

[0128] The first drive energy storage circuit 20 is electrically connected to the first drive node PU1 and the first drive signal output terminal OT1 respectively, and is used to store electrical energy;

[0129] The second drive signal providing circuit includes a second drive node control circuit 31, a second drive node reset circuit 32, a second drive output circuit 33, a second drive reset circuit 34, and a second drive energy storage circuit 30.

[0130] The second drive node control circuit 31 is electrically connected to the input terminal SR, the second node PD, and the second drive node PU2, respectively. It is used to control the potential of the second drive node PU2 under the control of the input signal provided by the input terminal SR, and to reset the potential of the second drive node PU2 under the control of the potential of the second node PD.

[0131] The second drive node reset circuit 32 is electrically connected to the reset terminal RST and the second drive node PU2 respectively, and is used to reset the potential of the second drive node PU2 under the control of the reset signal provided by the reset terminal RST;

[0132] The second drive output circuit 33 is electrically connected to the second drive node PU2, the second drive clock signal terminal CLK2, and the second drive signal output terminal OT2, respectively, and is used to write the second drive clock signal provided by the second drive clock signal terminal CLK2 into the second drive signal output terminal OT2 under the control of the potential of the second drive node PU2.

[0133] The second drive reset circuit 34 is electrically connected to the second node PD and the second drive signal output terminal OT2 respectively, and is used to reset the second drive signal provided by the second drive signal output terminal OT2 under the control of the potential of the second node PD.

[0134] The second drive energy storage circuit 30 is electrically connected to the second drive node PU2 and the second drive signal output terminal OT2 respectively, and is used to store electrical energy;

[0135] The third drive signal providing circuit includes a third drive node control circuit 41, a third drive node reset circuit 42, a third drive output circuit 43, a third drive reset circuit 44, and a third drive energy storage circuit 40.

[0136] The third driving node control circuit 41 is electrically connected to the input terminal SR, the second node PD and the third driving node PU3 respectively. It is used to control the potential of the third driving node PU3 under the control of the input signal provided by the input terminal SR, and to reset the potential of the third driving node PU3 under the control of the potential of the second node PD.

[0137] The third driving node reset circuit 42 is electrically connected to the reset terminal RST and the third driving node PU3 respectively, and is used to reset the potential of the third driving node PU3 under the control of the reset signal provided by the reset terminal RST.

[0138] The third drive output circuit 43 is electrically connected to the third drive node PU3, the third drive clock signal terminal CLK3 and the third drive signal output terminal OT3 respectively, and is used to write the third drive clock signal provided by the third drive clock signal terminal CLK3 into the third drive signal output terminal OT3 under the control of the potential of the third drive node PU3.

[0139] The third drive reset circuit 44 is electrically connected to the second node PD and the third drive signal output terminal OT3 respectively, and is used to reset the third drive signal provided by the third drive signal output terminal OT3 under the control of the potential of the second node PD.

[0140] The third drive energy storage circuit 40 is electrically connected to the third drive node PU3 and the third drive signal output terminal OT3 respectively, and is used to store electrical energy.

[0141] The fourth drive signal providing circuit includes a fourth drive node control circuit 51, a fourth drive node reset circuit 52, a fourth drive output circuit 53, a fourth drive reset circuit 54, and a fourth drive energy storage circuit 50.

[0142] The fourth driving node control circuit 51 is electrically connected to the input terminal SR, the second node PD and the fourth driving node PU4 respectively. It is used to control the potential of the fourth driving node PU4 under the control of the input signal provided by the input terminal SR, and to reset the potential of the fourth driving node PU4 under the control of the potential of the second node PD.

[0143] The fourth drive node reset circuit 52 is electrically connected to the reset terminal RST and the fourth drive node PU4 respectively, and is used to reset the potential of the fourth drive node PU4 under the control of the reset signal provided by the reset terminal RST.

[0144] The fourth drive output circuit 53 is electrically connected to the fourth drive node PU4, the fourth drive clock signal terminal CLK4 and the fourth drive signal output terminal OT4 respectively, and is used to write the fourth drive clock signal provided by the fourth drive clock signal terminal CLK4 into the fourth drive signal output terminal OT4 under the control of the potential of the fourth drive node PU4.

[0145] The fourth drive reset circuit 54 is electrically connected to the second node PD and the fourth drive signal output terminal OT4 respectively, and is used to reset the fourth drive signal provided by the fourth drive signal output terminal OT4 under the control of the potential of the second node PD.

[0146] The fourth drive energy storage circuit 50 is electrically connected to the fourth drive node PU4 and the fourth drive signal output terminal OT4, respectively, and is used to store electrical energy.

[0147] In at least one embodiment of the driving circuit shown in Figure 1, N equals 4. Optionally, N can also be 1, 2, 3, 5, 6, 7, 8, etc., which are not limited here.

[0148] As shown in Figure 2, based on at least one embodiment of the driving circuit shown in Figure 1, the carry node control circuit 11 is also electrically connected to the frame reset line STV0, and is used to reset the potential of the carry node PUC under the control of the frame reset signal provided by the frame reset line STV0.

[0149] The first drive node control circuit 21 is also electrically connected to the frame reset line STV0, and is used to reset the potential of the first drive node PU1 under the control of the frame reset signal.

[0150] The second drive node control circuit 31 is also electrically connected to the frame reset line STV0, and is used to reset the potential of the second drive node PU2 under the control of the frame reset signal;

[0151] The third drive node control circuit 41 is also electrically connected to the frame reset line STV0, and is used to reset the potential of the third drive node PU3 under the control of the frame reset signal.

[0152] The fourth drive node control circuit 51 is also electrically connected to the frame reset line STV0, and is used to reset the potential of the fourth drive node PU4 under the control of the frame reset signal.

[0153] In at least one embodiment of this disclosure, the carry signal providing circuit includes a carry node control circuit, a carry node reset circuit, a second node control circuit, a carry output circuit, a carry reset circuit, and a carry energy storage circuit.

[0154] The carry node control circuit is electrically connected to the input terminal, the second node, and the carry node, respectively. It is used to control the potential of the carry node under the control of the input signal provided by the input terminal, and to reset the potential of the carry node under the control of the potential of the second node.

[0155] The carry node reset circuit is electrically connected to the reset terminal and the carry node respectively, and is used to reset the potential of the carry node under the control of the reset signal provided by the reset terminal;

[0156] The second node control circuit is electrically connected to the carry node and the second node respectively, and is used to control the potential of the second node under the control of the potential of the carry node;

[0157] The carry output circuit is electrically connected to the carry node, the carry clock signal terminal and the carry signal output terminal respectively, and is used to write the carry clock signal provided by the carry clock signal terminal into the carry signal output terminal under the control of the potential of the carry node.

[0158] The carry reset circuit is electrically connected to the second node and the carry signal output terminal respectively, and is used to reset the carry signal provided by the carry signal output terminal under the control of the potential of the second node;

[0159] The carry energy storage circuit is electrically connected to the carry node and the carry signal output terminal, respectively.

[0160] In at least one embodiment of this disclosure, the nth driving signal providing circuit includes an nth driving node control circuit, an nth driving node reset circuit, an nth driving output circuit, an nth driving reset circuit, and an nth driving energy storage circuit; n is a positive integer less than or equal to N;

[0161] The control circuit of the nth driving node is electrically connected to the input terminal, the second node and the nth driving node respectively, and is used to control the potential of the nth driving node under the control of the input signal provided by the input terminal, and to reset the potential of the nth driving node under the control of the potential of the second node.

[0162] The nth driving node reset circuit is electrically connected to the reset terminal and the nth driving node, and is used to reset the potential of the nth driving node under the control of the reset signal provided by the reset terminal.

[0163] The nth drive output circuit is electrically connected to the nth drive node, the nth drive clock signal terminal and the nth drive signal output terminal respectively, and is used to write the nth drive clock signal provided by the nth drive clock signal terminal into the nth drive signal output terminal under the control of the potential of the nth drive node.

[0164] The nth drive reset circuit is electrically connected to the second node and the nth drive signal output terminal, respectively, and is used to reset the nth drive signal provided by the nth drive signal output terminal under the control of the potential of the second node;

[0165] The nth driving energy storage circuit is connected to the nth driving node and the nth driving signal output terminal, respectively.

[0166] As shown in Figure 3, based on at least one embodiment of the driving circuit shown in Figure 2, the carry node reset circuit includes a first transistor M1; the carry node control circuit includes a second transistor M2 and a third transistor M3, the second node control circuit includes a fourth transistor M4, a fifth transistor M5, a sixth transistor M6 and a seventh transistor M7, the carry output circuit includes a carry output transistor MC, the carry reset circuit includes a carry reset transistor MCR, the carry energy storage circuit includes a first capacitor C1; and the carry node control circuit further includes an eighth transistor M8.

[0167] The gate of M1 is electrically connected to the reset terminal RST, the source of M1 is electrically connected to the carry node PUC, and the drain of M1 is electrically connected to the low voltage line VGL.

[0168] The gate and source of M2 are both electrically connected to the input terminal SR, and the drain of M2 is electrically connected to the carry node PUC.

[0169] The gate of M3 is electrically connected to the second node PD, the source of M3 is electrically connected to the carry node PUC, and the drain of M3 is electrically connected to the low voltage line VGL.

[0170] The gate and source of M4 are electrically connected to the high voltage line GCH, and the drain of M4 is electrically connected to the pull-down control node PDCN.

[0171] The gate of M5 is electrically connected to the pull-down control node PDCN, the source of M5 is electrically connected to the high voltage line GCH, and the drain of M5 is electrically connected to the second node PD.

[0172] The gate of M6 is electrically connected to the carry node PUC, the source of M6 is electrically connected to the second node PD, and the drain of M6 is electrically connected to the low voltage line VGL.

[0173] The gate of M7 is electrically connected to the carry node PUC, the source of M7 is electrically connected to the pull-down control node PDCN, and the drain of M7 is electrically connected to the low voltage line VGL.

[0174] The gate of M8 is electrically connected to the frame reset line STV0, the source of M8 is electrically connected to the carry node PUC, and the drain of M8 is electrically connected to the low voltage line VGL.

[0175] The gate of MC is electrically connected to the carry node PUC, the source of MC is electrically connected to the carry clock signal terminal CLKC, and the drain of MC is electrically connected to the carry signal output terminal OUTC.

[0176] The gate of the MCR is electrically connected to the second node PD, the source of the MCR is electrically connected to the carry signal output terminal OUTC, and the drain of the MCR is electrically connected to the low voltage line VGL.

[0177] The first end of C1 is electrically connected to the carry node PUC, and the second end of C1 is electrically connected to the carry signal output terminal OUTC.

[0178] The first drive node control circuit includes a first ninth transistor M19 and a first tenth transistor M110; the first drive node reset circuit includes a first eleventh transistor M111; the first drive node control circuit also includes a first twelfth transistor M112; the first drive output circuit includes a first drive output transistor MO1; the first drive reset circuit includes a first drive reset transistor MR1; and the first drive energy storage circuit includes a first second capacitor C12.

[0179] The gate and source of M19 are both electrically connected to the input terminal SR, and the drain of M19 is electrically connected to the first driving node PU1.

[0180] The gate of M110 is electrically connected to the second node PD, the source of M110 is electrically connected to the first driving node PU1, and the drain of M110 is electrically connected to the low voltage line VGL.

[0181] The gate of M111 is electrically connected to the reset terminal RST, the source of M111 is electrically connected to the first drive node PU1, and the drain of M111 is electrically connected to the low voltage line VGL.

[0182] The gate of M112 is electrically connected to the frame reset line STV0, the source of M112 is electrically connected to the first drive node PU1, and the drain of M112 is electrically connected to the low voltage line VGL.

[0183] The gate of MO1 is electrically connected to the first driving node PU1, the source of MO1 is electrically connected to the first driving clock signal terminal CLK1, and the drain of MO1 is electrically connected to the first driving signal output terminal OT1.

[0184] The gate of MR1 is electrically connected to the second node PD, the source of MR1 is electrically connected to the first drive signal output terminal OT1, and the drain of MR1 is electrically connected to the low voltage line VGL.

[0185] The first end of C12 is electrically connected to the first driving node PU1, and the second end of C12 is electrically connected to the first driving signal output terminal OT1.

[0186] The second drive node control circuit includes a second ninth transistor M29 and a second tenth transistor M210; the second drive node reset circuit includes a second eleventh transistor M211; the second drive node control circuit also includes a second twelfth transistor M212; the second drive output circuit includes a second drive output transistor MO2; the second drive reset circuit includes a second drive reset transistor MR2; and the second drive energy storage circuit includes a second second capacitor C22.

[0187] The gate and source of M29 are both electrically connected to the input terminal SR, and the drain of M29 is electrically connected to the second driving node PU2.

[0188] The gate of M210 is electrically connected to the second node PD, the source of M210 is electrically connected to the second driving node PU2, and the drain of M210 is electrically connected to the low voltage line VGL.

[0189] The gate of M211 is electrically connected to the reset terminal RST, the source of M211 is electrically connected to the second drive node PU2, and the drain of M211 is electrically connected to the low voltage line VGL.

[0190] The gate of M212 is electrically connected to the frame reset line STV0, the source of M212 is electrically connected to the second drive node PU2, and the drain of M212 is electrically connected to the low voltage line VGL.

[0191] The gate of MO2 is electrically connected to the second driving node PU2, the source of MO2 is electrically connected to the second driving clock signal terminal CLK2, and the drain of MO2 is electrically connected to the second driving signal output terminal OT2.

[0192] The gate of MR2 is electrically connected to the second node PD, the source of MR2 is electrically connected to the second drive signal output terminal OT2, and the drain of MR2 is electrically connected to the low voltage line VGL.

[0193] The first end of C22 is electrically connected to the second drive node PU2, and the second end of C22 is electrically connected to the second drive signal output terminal OT2.

[0194] The third drive node control circuit includes a third ninth transistor M39 and a third tenth transistor M310; the third drive node reset circuit includes a third eleventh transistor M311; the third drive node control circuit also includes a third twelfth transistor M312; the third drive output circuit includes a third drive output transistor MO3; the third drive reset circuit includes a third drive reset transistor MR3; and the third drive energy storage circuit includes a third second capacitor C32.

[0195] The gate and source of M39 are both electrically connected to the input terminal SR, and the drain of M39 is electrically connected to the third driving node PU3.

[0196] The gate of M310 is electrically connected to the second node PD, the source of M310 is electrically connected to the third driving node PU3, and the drain of M310 is electrically connected to the low voltage line VGL.

[0197] The gate of M311 is electrically connected to the reset terminal RST, the source of M311 is electrically connected to the third drive node PU3, and the drain of M311 is electrically connected to the low voltage line VGL.

[0198] The gate of M312 is electrically connected to the frame reset line STV0, the source of M312 is electrically connected to the third drive node PU3, and the drain of M312 is electrically connected to the low voltage line VGL.

[0199] The gate of MO3 is electrically connected to the third driving node PU3, the source of MO3 is electrically connected to the third driving clock signal terminal CLK3, and the drain of MO3 is electrically connected to the third driving signal output terminal OT3.

[0200] The gate of MR3 is electrically connected to the second node PD, the source of MR3 is electrically connected to the third drive signal output terminal OT3, and the drain of MR3 is electrically connected to the low voltage line VGL.

[0201] The first terminal of C32 is electrically connected to the third drive node PU3, and the second terminal of C32 is electrically connected to the third drive signal output terminal OT3.

[0202] The fourth drive node control circuit includes a fourth ninth transistor M19 and a fourth tenth transistor M410; the fourth drive node reset circuit includes a fourth eleventh transistor M411; the fourth drive node control circuit also includes a fourth twelfth transistor M412; the fourth drive output circuit includes a fourth drive output transistor MO4; the fourth drive reset circuit includes a fourth drive reset transistor MR4; and the fourth drive energy storage circuit includes a fourth second capacitor C42.

[0203] The gate and source of M49 are electrically connected to the input terminal SR, and the drain of M49 is electrically connected to the fourth drive node PU4.

[0204] The gate of M410 is electrically connected to the second node PD, the source of M410 is electrically connected to the fourth driving node PU4, and the drain of M410 is electrically connected to the low voltage line VGL.

[0205] The gate of M411 is electrically connected to the reset terminal RST, the source of M411 is electrically connected to the fourth drive node PU4, and the drain of M411 is electrically connected to the low voltage line VGL.

[0206] The gate of M412 is electrically connected to the frame reset line STV0, the source of M412 is electrically connected to the fourth drive node PU4, and the drain of M412 is electrically connected to the low voltage line VGL.

[0207] The gate of MO4 is electrically connected to the fourth driving node PU4, the source of MO4 is electrically connected to the fourth driving clock signal terminal CLK4, and the drain of MO4 is electrically connected to the fourth driving signal output terminal OT4.

[0208] The gate of MR4 is electrically connected to the second node PD, the source of MR4 is electrically connected to the fourth drive signal output terminal OT4, and the drain of MR4 is electrically connected to the low voltage line VGL.

[0209] The first end of C42 is electrically connected to the fourth drive node PU4, and the second end of C42 is electrically connected to the fourth drive signal output terminal OT4.

[0210] When at least two drive output circuits are set in this case, such as the case of setting four drive output circuits as illustrated in Figure 3, that is, one drive circuit contains at least two drive signal output terminals, which can be electrically connected to at least two gate lines in the display panel. With this design, one drive circuit can drive multiple gate lines. The second node PD is used in the drive circuit to reduce the number of GOA (Gate Driver On Array) circuit transistors and reduce the display bezel effect.

[0211] In at least one embodiment of the driving circuit shown in Figure 3, all transistors are n-type transistors, but this is not a limitation.

[0212] In at least one embodiment of this disclosure, the drive signal output terminal and the carry signal output terminal for cascading are designed separately, so that the output is controllable without affecting the input and reset of other drive circuits.

[0213] Furthermore, the carry signal output terminal of the first-level driving circuit simultaneously inputs one carry signal output terminal and four driving signal output terminals of the adjacent next-level driving circuit, and simultaneously resets one carry signal output terminal and four driving signal output terminals of the adjacent previous-level driving circuit, ensuring that the outputs of each carry output transistor and each driving output transistor are identical and that the bias voltage time is consistent.

[0214] In the first-stage driving circuit, the carry node, the first driving node, the second driving node, the third driving node and the fourth driving node are designed separately and simultaneously accept charging from the input terminal, which can ensure that the output is as consistent as possible.

[0215] In the driving circuit, the frame reset line STV0 is used to reduce noise at the carry signal output terminal and each driving signal output terminal during the blank time period between two frames.

[0216] In the first-stage driver circuit, a second node PD is used to control the pull-down carry signal output terminal and the output terminals of each driver signal to be reset, which will not cause output differences and can reduce the number of transistors used in the driver circuit.

[0217] In related technologies, when the display panel is in standby mode, only a small part of the display area in the middle of the screen (i.e., the dynamic area) displays the image, while other display areas (i.e., the static area) do not display. However, at this time, both the dynamic and static areas require gate lines and data lines to provide signals, resulting in high power consumption. In this case, by using the driving circuit of this case, it is possible to turn on the gate lines only in the areas where display is needed, and turn off the gate lines in the areas where display is not needed, thereby reducing display power consumption.

[0218] In at least one embodiment of this disclosure, the carry signal output terminal for cascading is separated from the drive signal output terminal for driving. The input terminal of the drive circuit can be electrically connected to the carry signal output terminal of the adjacent previous stage or multiple stages of the drive circuit, and the reset terminal of the drive circuit can be electrically connected to the carry signal output terminal of the adjacent next stage or multiple stages of the drive circuit. By controlling whether the CLK signal of the drive output circuit is a valid signal, the gate line electrically connected to the drive output circuit can be controlled to open. This allows the drive output of any stage to stop without affecting the drive output of other stages of the drive circuit. Therefore, it can be a local display or a partial area display of the display panel, reducing display power consumption.

[0219] In at least one embodiment of the driving circuit shown in Figure 3, during operation, the first-level driving circuit drives four gate lines located in the display area. The input signal provided by the input terminal SR is provided by the carry signal generation terminal of the upper-level (or higher-level) driving circuit, charging the carry node PUC, the first driving node PU1, the second driving node PU2, the third driving node PU3, and the fourth driving node PU4 in this level of driving circuit. When CLKC, CLK1, CLK2, CLK3, and CLK4 output high-voltage signals, the potentials of PUC, PU1, PU2, PU3, and PU4 are respectively bootstrap-raised, realizing the outputs of OUTC, OT1, OT2, OT3, and OT4. In this circuit, the carry signal provided by OUTC is used as a cascaded output. OT1 provides the m-th drive signal for the m-th row pixel circuit, OT2 provides the m+1-th drive signal for the m+1-th row pixel circuit, OT3 provides the m+2-th drive signal for the m+2-th row pixel circuit, and OT4 provides the m+3-th drive signal for the m+3-th row pixel circuit; where m is a positive integer. The reset terminal RST provides a reset signal, which is provided by the carry signal output terminal of the next stage (or multiple stages below) drive circuit. When RST provides a high voltage signal, PUC, PU1, PU2, PU3, and PU4 are discharged, the potential of PD is gradually pulled up, and OUTC, OT1, OT2, OT3, and OT4 are discharged, and the current stage drive circuit stops outputting.

[0220] In at least one embodiment of this disclosure, the carry signal providing circuit and the four drive signal providing circuits do not share a pull-up node to avoid inconsistent pre-charge times of the signals provided by each output terminal. The carry node PUC, the first drive node PU1, the second drive node PU2, the third drive node PU3, and the fourth drive node PU4 are charged simultaneously through the input signal provided by SR, and then output is achieved through CLKC, CLK1, CLK2, CLK3, and CLK4. In this case, the gate of M2 can be electrically connected to the source and simultaneously connected to the input signal provided by SR, and the drain of M2 can be electrically connected to PUC. Alternatively, the gate of M2 can be connected to the input signal provided by SR, the source of M2 can be connected to a DC voltage, such as a high voltage signal provided by VGH, and the drain of M2 can be electrically connected to PUC. This is not limited here.

[0221] The carry signal providing circuit and the four drive signal providing circuits share the second node, which can reduce the number of transistors used. When the carry signal output terminal of the lower-level drive circuit provides a valid carry signal, PUC, PU1, PU2, PU3 and PU4 are discharged, which then pulls the potential of PD high, and further discharges PUC, PU1, PU2, PU3, PU4, OUTC, OT1, OT2, OT3 and OT4.

[0222] Figures 4 and 5A are layout diagrams of at least one embodiment of the drive circuit shown in Figure 3.

[0223] As shown in Figure 4, the carry signal providing circuit SC, the first drive signal providing circuit S1, the second drive signal providing circuit S2, the third drive signal providing circuit S3, and the fourth drive signal providing circuit S4 are arranged vertically in sequence. In the carry signal providing circuit SC, the second node is electrically connected to the corresponding transistors in the first drive signal providing circuit S1, the second drive signal providing circuit S2, the third drive signal providing circuit S3, and the fourth drive signal providing circuit S4 through wiring. This layout scheme can save layout space as much as possible and is conducive to achieving a narrow bezel.

[0224] This example illustrates the use of four drive signal supply circuits. However, other numbers could be used, such as at least two. This allows each drive circuit to correspond to at least two gate lines in the display area, reducing the number of transistors in the drive circuit and achieving a narrow bezel effect.

[0225] Compared to the structure of the traditional 11T1C driving circuit, at least one embodiment of this disclosure can reduce the number of circuit units controlling the potential of the second node by 4 and reduce the number of transistors by 16, but requires the addition of six transistors and one capacitor in the carry signal providing unit; compared to the driving circuit of a large-size dual second node, at least one embodiment of this disclosure reduces the number of transistors and can narrow the bezel.

[0226] As shown in Figure 4, a scheme is adopted in which the first-level carry signal providing circuit and the fourth-level drive signal providing circuit are horizontally separated and vertically arranged side by side. The carry signal providing circuit includes a circuit unit for controlling the second node and a circuit unit for providing the carry signal. When the display device adopts the first drive module and the second drive module with alternating bilateral drive, the height occupied by the carry signal providing circuit is the height of the eight-row pixel circuit / 5, and the height occupied by the drive signal providing circuit is the height of the eight-row pixel circuit / 5.

[0227] In at least one embodiment of this disclosure, the carry output circuit includes a transistor whose gate includes p first sub-gates that are electrically connected to each other, and adjacent first sub-gates are electrically connected through a first connection portion;

[0228] The drive output circuit includes a transistor whose gate includes m interconnected second sub-gates, and adjacent second sub-gates are electrically connected through a second connection portion;

[0229] p and m are positive integers, where m is greater than p.

[0230] In a specific implementation, the channel width-to-length ratio of the transistor included in the carry output circuit is smaller than that of the transistor included in the drive output circuit. The gate of the transistor included in the carry output circuit is configured to include p first sub-gates that are electrically connected to each other, and the gate of the transistor included in the drive output circuit includes m second sub-gates that are electrically connected to each other, where m is set to be greater than p.

[0231] Figure 5B is a layout diagram of the semiconductor layer in Figure 5A; Figure 5C is a layout diagram of the gate metal layer in Figure 5A; Figure 5D is a layout diagram of the source / drain metal layers in Figure 5A; Figure 5E is a layout diagram of the conductive layer in Figure 5A; Figure 5F is a stacked diagram of the gate metal layer and semiconductor layer in Figure 5A; Figure 5G is a stacked diagram of the semiconductor layer and source / drain metal layers in Figure 5A; Figure 5H is a stacked diagram of the source / drain metal layers and conductive layer in Figure 5A.

[0232] Optionally, the conductive layer can be made of ITO (indium tin oxide).

[0233] As shown in Figure 5A, the transistor labeled MC is the carry output transistor, the transistor labeled MO1 is the first drive output transistor, the transistor labeled MO2 is the second drive output transistor, the transistor labeled MO3 is the third drive output transistor, and the transistor labeled MO4 is the fourth drive transistor.

[0234] The transistor labeled PD is the second node, MCR is the carry reset transistor, M3 is the third transistor, MR1 is the first drive reset transistor, M110 is the first tenth transistor, MR2 is the second drive reset transistor, M210 is the second tenth transistor, MR3 is the third drive reset transistor, M310 is the third tenth transistor, MR4 is the fourth drive reset transistor, and M410 is the fourth tenth transistor.

[0235] As shown in Figure 5C, the second node PD is electrically connected to the gates GCR of MCR, G3 of M3, GR1 of MR1, G110 of M110, GR1 of MR2, G210 of M210, GR3 of MR3, G310 of M310, GR4 of MR4, and G410 of M410.

[0236] As shown in Figure 5A, since the load of OUTC is relatively small, the channel width-to-length ratio of MC can be smaller than that of MO1, MO2, MO3, and MO4. The capacitance value of C1 can be smaller than that of C12, C22, C32, and C42. Simultaneously, a first via H1 exists between C1 and M1. To match the layout space, the active pattern A1 of M1, the first electrode C1a of C1, and the second electrode C1b of C1 are set to a non-rectangular design different from that in the drive signal supply circuit. A portion of MC is also placed above MCR to fully utilize the space and increase the channel width-to-length ratio of MC.

[0237] As shown in Figures 5A and 5C, the second node PD uses interconnects formed on the gate metal layer to electrically connect with the gates of MCR, M3, MR1, M110, MR2, M210, MR3, M310, MR4, and M410, without needing to pass through the vias in the conductive layer, resulting in minimal signal attenuation.

[0238] The carry signal providing circuit and the four drive signal providing circuits are arranged vertically side by side. When the display device adopts the first drive module and the second drive module with alternating double-sided drive, the carry signal providing circuit and the four drive signal providing circuits equally divide the vertical layout space of the 8 rows of pixel circuits.

[0239] In the carry signal providing circuit, a first via is provided that is electrically connected to the cascaded line. The shape of C1 and the shape of M1 are adjusted according to the setting position of the first via. At the same time, there are no traces output to the display area in the carry signal providing circuit, so that there is space to set the first via and it does not affect the horizontal border.

[0240] In the carry signal providing circuit, in order to improve space utilization, M2, M3, M8 and MCR can be designed with different shapes than the corresponding transistors in each drive signal providing circuit;

[0241] The frame reset line STV0 is positioned close to the drive circuit and controls M8, M112, M212, M312, and M412 respectively. STV0 can be formed on the gate metal layer, as shown in Figure 5C. STV0 can be directly connected to the gate G8 of M8, the gate G112 of M112, the gate G212 of M212, the gate G312 of M312, and the gate G412 of M412 through the connecting lines formed on the gate metal layer. There is no need to use vias to bridge the gap, which can reduce the bezel and facilitate the realization of a narrow bezel.

[0242] In Figure 5B, the active pattern labeled AC is MC, the active pattern labeled A1 is M1, the active pattern labeled AO1 is MO1, the active pattern labeled A111 is M111; the active pattern labeled AO2 is MO2, the active pattern labeled A211 is M211; the active pattern labeled AO3 is MO3, the active pattern labeled A311 is M311; the active pattern labeled AO4 is MO4, and the active pattern labeled A411 is M411.

[0243] In Figure 5C, the gate labeled G3 is the gate of M3, the gate labeled GC is the gate of MC, the gate labeled G1 is the gate of M1, the gate labeled GCR is the gate of MCR, the gate labeled G110 is the gate of M110, and the first plate labeled C1a is the first plate of C1.

[0244] The gate labeled G112 is the gate of M112, the gate labeled G110 is the gate of M110, the gate labeled GR1 is the gate of MR1, the gate labeled GO1 is the gate of MO1, the gate labeled G111 is the gate of M111, and the first plate labeled C12a is the first plate of C12.

[0245] The gate labeled G212 is the gate of M212, the gate labeled G210 is the gate of M210, the gate labeled GR2 is the gate of MR2, the gate labeled GO2 is the gate of MO2, the gate labeled G211 is the gate of M211, and the first plate labeled C22a is the first plate of C22.

[0246] The gate labeled G312 is the gate of M312, the gate labeled G310 is the gate of M310, the gate labeled GR3 is the gate of MR3, the gate labeled GO3 is the gate of MO3, the gate labeled G311 is the gate of M311, and the first plate labeled C32a is the first plate of C32.

[0247] The gate labeled G412 is the gate of M412, the gate labeled G410 is the gate of M410, the gate labeled GR4 is the gate of MR4, the gate labeled GO4 is the gate of MO4, the gate labeled G411 is the gate of M411, and the first plate labeled C42a is the first plate of C42.

[0248] As shown in Figure 5D, the plate labeled C1b is the second plate of C1, the plate labeled C12b is the second plate of C12, the plate labeled C22b is the second plate of C22, the plate labeled C32b is the second plate of C32, and the plate labeled C42b is the second plate of C42.

[0249] In Figure 5E, the first conductive pattern is labeled DX1, the second conductive pattern is labeled DX2, the third conductive pattern is labeled DX3, the fourth conductive pattern is labeled DX4, the fifth conductive pattern is labeled DX5, the sixth conductive pattern is labeled DX6, the seventh conductive pattern is labeled DX7, the eighth conductive pattern is labeled DX8, the ninth conductive pattern is labeled DX9, and the tenth conductive pattern is labeled DX10.

[0250] Figure 6 is a layout diagram of the carry signal providing circuit, and Figure 7A is a layout diagram of the first drive signal providing circuit. Figure 8 is a layout diagram of the semiconductor layer in Figure 6, Figure 9 is a layout diagram of the gate metal layer in Figure 6, and Figure 10 is a layout diagram of the source / drain metal layers in Figure 6. Figure 11 is a layout diagram of the conductive layer in Figure 6, Figure 12 is a stack-up diagram of the gate metal layer and semiconductor layer in Figure 6, Figure 13 is a layout diagram of the semiconductor layer and source / drain metal layers in Figure 6, and Figure 14 is a stack-up diagram of the source / drain metal layers and conductive layer in Figure 6.

[0251] Figure 7B is a layout diagram of the gate metal layer in Figure 7A; Figure 7C is a layout diagram of the source / drain metal layer in Figure 7A; Figure 7D is a layout diagram of the semiconductor layer in Figure 7A; Figure 7E is a layout diagram of the conductive layer in Figure 7A; Figure 7F is a stacked diagram of the gate metal layer and semiconductor layer in Figure 7A; Figure 7G is a stacked diagram of the semiconductor layer and source / drain metal layer in Figure 7A; and Figure 7H is a stacked diagram of the source / drain metal layer and conductive layer in Figure 7A.

[0252] As shown in Figure 9, the carry output transistor includes a first sub-gate GZ11, a second first sub-gate GZ21, and a third first sub-gate GZ31.

[0253] GZ11 and GZ21 are electrically connected via the first first connecting part L11;

[0254] GZ21 and GZ31 are electrically connected via a second first connecting part L21.

[0255] As shown in Figure 7B, the first drive output transistor includes a first second sub-gate GZ12, a second second sub-gate GZ22, a third second sub-gate GZ32 and a fourth second sub-gate GZ42.

[0256] GZ12 is electrically connected to GZ22 via the first second connection part L12, GZ22 is electrically connected to GZ32 via the second second connection part L22, and GZ32 is electrically connected to GZ42 via the third second connection part L32.

[0257] As shown in Figures 9 and 7B, the first drive output transistor includes four large-area second sub-gates, and the carry output transistor includes two large-area first sub-gates and one small-area first sub-gate.

[0258] In at least one embodiment of this disclosure, the carry-out output circuit includes at least two first sub-gates with different shapes; and / or, the carry-out output circuit includes at least two first sub-gates with different dimensions; or,

[0259] The drive output circuit includes at least two second sub-gates with different shapes; and / or, the drive output circuit includes at least two second sub-gates with different sizes.

[0260] As shown in Figure 9, the dimensions of GZ31 are different from those of GZ21, and the area of ​​GZ21 is larger than that of GZ31. The dimensions of GZ11 are also different from those of GZ31, and the area of ​​GZ11 is larger than that of GZ31. The dimensions of GZ11 are also different from those of GZ21, and the area of ​​GZ11 is larger than that of GZ21.

[0261] In at least one embodiment of this disclosure, the shapes of the at least two first sub-gates included in the carry-out transistor may also be different.

[0262] As shown in Figure 7B, the dimensions of GZ42 are different from those of GZ32, and the area of ​​GZ32 is larger than that of GZ42.

[0263] In Figure 7B, the first plate of C12 is labeled C12a.

[0264] In at least one embodiment of this disclosure, the shapes of the at least two second sub-gates included in each drive output transistor may also be different.

[0265] In at least one embodiment of this disclosure, the carry signal providing circuit further includes a carry reset circuit, which is used to reset the carry signal under the control of the potential of the second node;

[0266] The carry-out output circuit includes a transistor with an active pattern comprising a first active pattern portion and at least one second active pattern portion.

[0267] The first active pattern portion and the active patterns of the transistors included in the carry-reset circuit are arranged along a first direction.

[0268] Optionally, the first active graphic portion and the second active graphic portion are arranged along a second direction.

[0269] As shown in Figure 6, the carry reset circuit includes a carry reset transistor MCR;

[0270] As shown in Figure 8, the active pattern of the carry output transistor MC includes a first active pattern part AC1, a first second active pattern part AC12 and a second second active pattern part AC22.

[0271] The first active pattern AC1 and the active pattern ACR of the carry reset transistor MCR are arranged vertically to utilize the space above ACR to set AC1, thereby making full use of the space to increase the channel width-to-length ratio of MC.

[0272] As shown in Figure 8, the first active graphic unit AC1 and the first second active graphic unit AC12 are arranged in a horizontal direction, and the first active graphic unit AC1 and the second second active graphic unit AC22 are arranged in a horizontal direction.

[0273] In at least one embodiment of this disclosure, the carry signal providing circuit includes a carry energy storage circuit; the carry energy storage circuit is electrically connected to the carry node and the carry signal output terminal respectively; one plate of the capacitor included in the carry energy storage circuit is electrically connected to the corresponding cascade line through a first via.

[0274] The carry-in energy storage circuit includes capacitor plates with a first clearance space to avoid interconnects and / or a first via.

[0275] Optionally, the carry signal providing circuit includes a first transistor;

[0276] The first transistor is located on the side of the carry energy storage circuit away from the carry output circuit;

[0277] The active pattern of the first transistor has a second clearance space to avoid the first via.

[0278] In Figure 9, the line labeled JL is the cascade line, and the line labeled C1a is the first plate of C1.

[0279] In Figure 10, the plate labeled C1b is the second plate of C1.

[0280] As shown in Figures 6, 9 and 10, the cascade line JL is electrically connected to the second plate C1b of C1 through the first via H1.

[0281] As shown in Figures 9 and 10, the first electrode plate C1a of C1 has a first first clearance space B11, and the second electrode plate C1b of C1 has a second first clearance space B21 to avoid the first through hole H1 and the cascade line JL.

[0282] As shown in Figure 6, M1 is the first transistor, C1 is the first capacitor included in the carry energy storage circuit, and M1 is located on the side of C1 away from the carry output transistor MC included in the carry output circuit.

[0283] Optionally, the first transistor and the capacitors included in the carry energy storage circuit are arranged along the second direction.

[0284] As shown in Figure 6, the first transistor M1 and the first capacitor C1 included in the carry energy storage circuit are arranged in a horizontal direction.

[0285] As shown in Figure 6, the first transistor M1 is located on the side of the carry-out energy storage circuit that is away from the first capacitor C1 of the carry-out output circuit.

[0286] As shown in Figure 8, the active pattern A1 of the first transistor M1 has a second clearance space B2 to avoid the first via H1.

[0287] In at least one embodiment of this disclosure, the carry signal providing circuit includes a carry node reset circuit; the carry node reset circuit is used to reset the potential of the carry node under the control of a reset signal provided at the reset terminal;

[0288] The carry node reset circuit includes the first transistor.

[0289] In at least one embodiment of this disclosure, the drive signal providing circuit includes a drive energy storage circuit; the drive energy storage circuit is connected to the drive node and the drive signal output terminal respectively.

[0290] The shape of the capacitor included in the carry energy storage circuit is different from the shape of the capacitor included in the drive energy storage circuit; and / or,

[0291] The size of the capacitor plates in the carry energy storage circuit is different from the size of the capacitor in the drive energy storage circuit.

[0292] As shown in Figure 6, the carry energy storage circuit includes a first capacitor C1. As shown in Figure 7A, the first drive energy storage circuit in the first drive signal providing circuit includes a first second capacitor C12.

[0293] In Figure 9, the first plate of C1 is labeled C1a, and in Figure 10, the second plate of C1 is labeled C1b.

[0294] In Figure 7B, the first plate of C12 is labeled C12a, and in Figure 7C, the second plate of C12 is labeled C12b.

[0295] As shown in Figures 9 and 7B, C1a has a first clearance space, while C12a does not have a clearance space. The shapes of C1a and C12a are different, and the areas of C1a and C12a are different.

[0296] As shown in Figures 10 and 7C, C1b has a second first clearance space, while C12b does not have a clearance space. The shapes of C1b and C12b are different, and the areas of C1b and C12b are different.

[0297] In at least one embodiment of this disclosure, the drive signal providing circuit includes a drive node reset circuit, which is used to reset the potential of the drive node under the control of the reset signal.

[0298] The shape of the transistor included in the carry node reset circuit is different from the shape of the transistor included in the drive node reset circuit; and / or,

[0299] The transistors included in the carry node reset circuit have different dimensions than those included in the drive node reset circuit.

[0300] As shown in Figure 8, the active pattern A1 of the first transistor M1 has a second clearance space B2 to avoid the first via H1.

[0301] As shown in Figure 7D, the active pattern A111 of the first eleventh transistor M111 included in the first drive node reset circuit does not have clearance space.

[0302] The shape of A1 is different from the shape of A111, and the area of ​​A1 is different from the area of ​​A111.

[0303] The area of ​​A111 is greater than the area of ​​A1.

[0304] Optional, N is greater than 1;

[0305] The N drive signal providing circuits include transistors of the same shape that have the same function; and / or,

[0306] The N drive signal providing circuits include transistors of the same size that have the same function.

[0307] As shown in Figure 5A, the shapes of MO1, MO2, and MO3 are the same as those of MO4; the dimensions of MO1, MO2, MO3, and MO4 are the same.

[0308] The shapes of M111, M211, and M311 are the same as those of M411; the dimensions of M111, M211, M311, and M411 are the same.

[0309] In at least one embodiment of this disclosure, the first drive node control circuit includes a first ninth transistor and a first tenth transistor, the first drive node reset circuit includes a first eleventh transistor, the first drive node control circuit further includes a first twelfth transistor, the first drive output circuit includes a first drive output transistor, and the first drive reset circuit includes a first drive reset transistor.

[0310] The second drive node control circuit includes a second ninth transistor and a second tenth transistor; the second drive node reset circuit includes a second eleventh transistor; the second drive node control circuit also includes a second twelfth transistor; the second drive output circuit includes a second drive output transistor; and the second drive reset circuit includes a second drive reset transistor.

[0311] The fact that the transistors with the same function in the first drive node control circuit and the second drive node control circuit have the same shape can mean that:

[0312] The shape of the first ninth transistor is the same as that of the second ninth transistor, the shape of the first tenth transistor is the same as that of the second tenth transistor, the shape of the first eleventh transistor is the same as that of the second eleventh transistor, the shape of the first twelfth transistor is the same as that of the second ninth transistor, the shape of the first drive output transistor is the same as that of the second drive output transistor, and the shape of the first drive reset transistor is the same as that of the second drive reset transistor.

[0313] The fact that the transistors with the same function included in the first and second drive node control circuits have the same area can mean:

[0314] The area of ​​the first ninth transistor is the same as the area of ​​the second ninth transistor, the area of ​​the first tenth transistor is the same as the area of ​​the second tenth transistor, the area of ​​the first eleventh transistor is the same as the area of ​​the second eleventh transistor, the area of ​​the first twelfth transistor is the same as the area of ​​the second ninth transistor, the area of ​​the first drive output transistor is the same as the area of ​​the second drive output transistor, and the area of ​​the first drive reset transistor is the same as the area of ​​the second drive reset transistor.

[0315] The array substrate of at least one embodiment of this disclosure includes a driving module; the driving module is disposed on a first side of the display area, and / or a second side of the display area; the first side and the second side are opposite sides; the driving module includes A cascaded driving circuits; A is an integer greater than 1;

[0316] The input terminal of the a-th driving circuit included in the driving module is electrically connected to the carry signal output terminal of the ab-th stage driving circuit included in the driving module.

[0317] The reset terminal of the a-th driving circuit included in the driving module is electrically connected to the carry signal output terminal of the a+c-th driving circuit included in the driving module.

[0318] a, b, and c are positive integers; a is less than or equal to A.

[0319] Optionally, the first side can be the left side and the second side can be the right side.

[0320] In at least one embodiment of this disclosure, b and c may be equal to 1, but are not limited thereto.

[0321] In at least one embodiment of this disclosure, the driving module further includes a virtual start driving circuit;

[0322] The virtual start-up drive circuit is used to provide corresponding input signals to the input terminal of the first-stage drive circuit included in the drive module.

[0323] In specific implementation, the array substrate described in at least one embodiment of this disclosure may include a driving module, that is, a driving module is provided on one side, and the driving module may be provided on the left or right side of the display area;

[0324] The array substrate may include a first driving clock signal line CK1, a second driving clock signal line CK2, a third driving clock signal line CK3, a fourth driving clock signal line CK4, a fifth driving clock signal line CK5, a sixth driving clock signal line CK6, a seventh driving clock signal line CK7, an eighth driving clock signal line CK8, a first carry clock signal line CLKC1, and a second carry clock signal line CLKC2.

[0325] In the 2d-1 stage drive circuit, the carry clock signal terminal is electrically connected to the first carry clock signal line CLKC1, the first drive clock signal terminal is electrically connected to the first drive clock signal line CK1, the second drive clock signal terminal is electrically connected to the second drive clock signal line CK2, the third drive clock signal terminal is electrically connected to the third drive clock signal line CK3, and the fourth drive clock signal terminal is electrically connected to the fourth drive clock signal line CK4; d is a positive integer;

[0326] In the 2d-stage drive circuit, the carry clock signal terminal is electrically connected to the second carry clock signal line CLKC2, the first drive clock signal terminal is electrically connected to the fifth drive clock signal line CK5, the second drive clock signal terminal is electrically connected to the sixth drive clock signal line CK6, the third drive clock signal terminal is electrically connected to the seventh drive clock signal line CK7, and the fourth drive clock signal terminal is electrically connected to the eighth drive clock signal line CK8; d is a positive integer;

[0327] The input terminal of the driving circuit is electrically connected to the carry signal output terminal of the adjacent upper-level driving circuit, and the reset terminal of the driving circuit is electrically connected to the carry signal output terminal of the adjacent lower-level driving circuit.

[0328] Figure 15 is a timing diagram of at least one embodiment of the drive module when the drive module adopts single-sided drive.

[0329] In Figure 15, the time labeled 5H represents the five-line scan time, and the time labeled 3H represents the three-line scan time.

[0330] As shown in Figure 15, STV1 is the first starting voltage terminal. The input terminal of the first-stage driving circuit can be electrically connected to the first starting voltage terminal STV1. CLKC1 and CLKC2 alternately control the carry signal supply circuit in the corresponding stage driving circuit to output the corresponding carry signal. CK1, CK2, CK3 and CK4 control the four-stage driving signal supply circuit in the odd-numbered stage driving circuit to output the corresponding driving signal. CK5, CK6, CK7 and CK8 control the four-stage driving signal supply circuit in the even-numbered stage driving circuit to output the corresponding driving signal.

[0331] When STV1 provides a high-voltage signal, it charges the carry node, first drive node, second drive node, third drive node, and fourth drive node in the first-stage drive circuit. CK1, CK2, CK3, and CK4 sequentially start outputting high-voltage signals, and OT1, OT2, OT3, and OT4 in the first-stage drive circuit sequentially output valid drive signals (i.e., sequentially outputting high-voltage signals). When CLKC1 outputs a high-voltage signal, OUTC in the first-stage drive circuit outputs a high-voltage signal, which is input to the second-stage drive circuit, charging the carry node, first drive node, second drive node, third drive node, and fourth drive node in the second-stage drive circuit. CK5, CK6, CK7, and CK8 sequentially start outputting high-voltage signals, and OT1, OT2, OT3, and OT4 in the second-stage drive circuit sequentially output valid drive signals (i.e., sequentially outputting high-voltage signals). When CLKC2 outputs a high-voltage signal, OUTC in the second-stage drive circuit outputs a high-voltage signal, which is input to the third-stage drive circuit, and simultaneously resets the first-stage drive circuit. This process continues, with each stage of the drive circuit transmitting downwards.

[0332] In at least one embodiment shown in Figure 15, the duty cycle of the first carry clock signal provided by CLKC1, the duty cycle of the second carry clock signal provided by CLKC2, the duty cycle of the clock signal provided by CK1, the duty cycle of the clock signal provided by CK2, the duty cycle of the clock signal provided by CK3, the duty cycle of the clock signal provided by CK4, the duty cycle of the clock signal provided by CK5, the duty cycle of the clock signal provided by CK6, the duty cycle of the clock signal provided by CK7, and the duty cycle of the clock signal provided by CK8 can all be 5 / 16, that is, 31.25%. The rising edge of the second carry clock signal provided by CLKC2 is aligned with the falling edge of the clock signal provided by CK4, and the rising edge of the first carry clock signal provided by CLKC1 is aligned with the falling edge of the clock signal provided by CK8.

[0333] When the single-sided driving module operates according to the working timing shown in Figure 15, the carry signal output terminal of the 2d-level driving circuit needs to reset the fourth driving signal output terminal in the 2d-1-level driving circuit. As a result, the potential of the fourth driving signal provided by the fourth driving signal output terminal in the 2d-1-level driving circuit decreases under the control of the carry signal provided by the 2d-level driving circuit, rather than being affected by the falling edge of the clock signal provided by the fourth driving clock signal terminal in the 2d-1-level driving circuit. This results in a long fall time for the fourth driving signal provided by the fourth driving signal output terminal in the 2d-level driving circuit, and the potential of the fourth driving signal decreases slowly, which may lead to incorrect charging of the corresponding row pixel circuit. Therefore, in at least one embodiment of this disclosure, a delayed reset method can be adopted, that is, the rising edge of CLKC2 is delayed, and the falling edge of the clock signal provided by the fourth driving clock signal terminal in the 2d-1 stage driving circuit pulls the potential of the fourth driving signal to drop and reset. Therefore, for a single-sided 8CLK display product (an 8CLK display product is a display product that uses 8 driving clock signal lines), the duty cycle of the carry clock signal needs to be less than 31.25.

[0334] In specific implementation, the array substrate described in at least one embodiment of this disclosure may include a first driving module and a second driving module, that is, driving modules are provided on both sides, the first driving module may be provided on the left side of the display area, and the second driving module may be provided on the right side of the display area;

[0335] The array substrate may include a first driving clock signal line CK1, a second driving clock signal line CK2, a third driving clock signal line CK3, a fourth driving clock signal line CK4, a fifth driving clock signal line CK5, a sixth driving clock signal line CK6, a seventh driving clock signal line CK7, an eighth driving clock signal line CK8, a ninth driving clock signal line CK9, a tenth driving clock signal line CK10, an eleventh driving clock signal line CK11, a twelfth driving clock signal line CK12, a thirteenth driving clock signal line CK13, a fourteenth driving clock signal line CK14, a fifteenth driving clock signal line CK15, a sixteenth driving clock signal line CK16, a first carry clock signal line CLKC1, a second carry clock signal line CLKC2, a third carry clock signal line CLKC3, and a fourth carry clock signal line CLKC4.

[0336] Among them, CK1, CK3, CK5, CK7, CLKC1 and CLKC3 can be set on the left side of the display area, and CK2, CK4, CK6, CK8, CLKC2 and CLKC4 can be set on the right side of the display area;

[0337] In the first drive module, in the 2d-1 stage drive circuit, the carry clock signal terminal is electrically connected to the first carry clock signal line CLKC1, the first drive clock signal terminal is electrically connected to the first drive clock signal line CK1, the second drive clock signal terminal is electrically connected to the third drive clock signal line CK3, the third drive clock signal terminal is electrically connected to the fifth drive clock signal line CK5, and the fourth drive clock signal terminal is electrically connected to the seventh drive clock signal line CK7; d is a positive integer;

[0338] In the first drive module, in the 2d-1 stage drive circuit, the first drive signal output terminal is electrically connected to the 16d-15th gate line, the second drive signal output terminal is electrically connected to the 16d-13th gate line, the third drive signal output terminal is electrically connected to the 16d-11th gate line, and the fourth drive signal output terminal is electrically connected to the 16d-9th gate line.

[0339] In the first drive module, in the 2d-stage drive circuit, the carry clock signal terminal is electrically connected to the third carry clock signal line CLKC3, the first drive clock signal terminal is electrically connected to the ninth drive clock signal line CK9, the second drive clock signal terminal is electrically connected to the eleventh drive clock signal line CK11, the third drive clock signal terminal is electrically connected to the thirteenth drive clock signal line CK13, and the fourth drive clock signal terminal is electrically connected to the fifteenth drive clock signal line CK15; d is a positive integer;

[0340] In the first drive module, in the 2d-stage drive circuit, the first drive signal output terminal is electrically connected to the 16d-7 gate line, the second drive signal output terminal is electrically connected to the 16d-5 gate line, the third drive signal output terminal is electrically connected to the 16d-3 gate line, and the fourth drive signal output terminal is electrically connected to the 16d-1 gate line.

[0341] In the second drive module, in the 2d-1 stage drive circuit, the carry clock signal terminal is electrically connected to the second carry clock signal line CLKC2, the first drive clock signal terminal is electrically connected to the second drive clock signal line CK2, the second drive clock signal terminal is electrically connected to the fourth drive clock signal line CK4, the third drive clock signal terminal is electrically connected to the sixth drive clock signal line CK6, and the fourth drive clock signal terminal is electrically connected to the eighth drive clock signal line CK8; d is a positive integer;

[0342] In the second drive module, in the 2d-1 stage drive circuit, the first drive signal output terminal is electrically connected to the 16d-14th gate line, the second drive signal output terminal is electrically connected to the 16d-12th gate line, the third drive signal output terminal is electrically connected to the 16d-10th gate line, and the fourth drive signal output terminal is electrically connected to the 16d-8th gate line.

[0343] In the second drive module, in the 2d-stage drive circuit, the carry clock signal terminal is electrically connected to the fourth carry clock signal line CLKC4, the first drive clock signal terminal is electrically connected to the tenth drive clock signal line CK10, the second drive clock signal terminal is electrically connected to the twelfth drive clock signal line CK12, the third drive clock signal terminal is electrically connected to the fourteenth drive clock signal line CK14, and the fourth drive clock signal terminal is electrically connected to the sixteenth drive clock signal line CK16; d is a positive integer;

[0344] In the second drive module, in the 2d-stage drive circuit, the first drive signal output terminal is electrically connected to the 16d-6th gate line, the second drive signal output terminal is electrically connected to the 16d-4th gate line, the third drive signal output terminal is electrically connected to the 16d-2th gate line, and the fourth drive signal output terminal is electrically connected to the 16d gate line.

[0345] Figure 16 is a timing diagram of at least one embodiment of the driving module.

[0346] As shown in Figure 16, the duty cycle of the first carry clock signal provided by CLKC1, the duty cycle of the second carry clock signal provided by CLKC2, the duty cycle of the third carry clock signal provided by CLKC3, and the duty cycle of the fourth carry clock signal provided by CLKC4 are all 25%.

[0347] During the low-frequency display phase (SL), each drive clock signal line stops outputting clock signals, the data lines stop providing data voltage, the corresponding row pixels do not charge or discharge and remain in a holding state, and each carry clock signal line outputs normally to ensure the transmission of carry signals used for cascading and prevent interference with the display of normal display rows.

[0348] In Figure 16, STV1 is the first starting voltage terminal, STV2 is the second starting voltage terminal, STV0 is the frame reset line, VCOM is the common electrode voltage, and DL is the data line.

[0349] As shown in Figure 16, in at least one embodiment of this disclosure, a first virtual start-up drive circuit can be set before the first-stage drive circuit in the first drive module.

[0350] In the first virtual start-up drive circuit, the carry clock signal terminal is electrically connected to the third carry clock signal line CLKC3, the first drive clock signal terminal is electrically connected to the ninth drive clock signal line CK9, the second drive clock signal terminal is electrically connected to the eleventh drive clock signal line CK11, the third drive clock signal terminal is electrically connected to the thirteenth drive clock signal line CK13, and the fourth drive clock signal terminal is electrically connected to the fifteenth drive clock signal line CK15; the input terminal of the first virtual start-up drive circuit can be electrically connected to STV1.

[0351] A second virtual start drive circuit can be set before the first stage drive circuit in the second drive module;

[0352] In the second virtual start-up drive circuit, the carry clock signal terminal is electrically connected to the fourth carry clock signal line CLKC4, the first drive clock signal terminal is electrically connected to the tenth drive clock signal line CK10, the second drive clock signal terminal is electrically connected to the twelfth drive clock signal line CK12, the third drive clock signal terminal is electrically connected to the fourteenth drive clock signal line CK14, and the fourth drive clock signal terminal is electrically connected to the sixteenth drive clock signal line CK16; the input terminal of the second virtual start-up drive circuit can be electrically connected to STV2.

[0353] A first virtual end drive circuit can be set after the last stage drive circuit in the first drive module;

[0354] In the first virtual end drive circuit, the carry clock signal terminal is electrically connected to the first carry clock signal line CLKC1, the first drive clock signal terminal is electrically connected to the first drive clock signal line CK1, the second drive clock signal terminal is electrically connected to the third drive clock signal line CK3, the third drive clock signal terminal is electrically connected to the fifth drive clock signal line CK5, and the fourth drive clock signal terminal is electrically connected to the seventh drive clock signal line CK7.

[0355] A second virtual end drive circuit can be set after the last stage drive circuit in the second drive module;

[0356] In the second virtual end drive circuit, the carry clock signal terminal is electrically connected to the third carry clock signal line CLKC3, the first drive clock signal terminal is electrically connected to the second drive clock signal line CK2, the second drive clock signal terminal is electrically connected to the fourth drive clock signal line CK4, the third drive clock signal terminal is electrically connected to the sixth drive clock signal line CK6, and the fourth drive clock signal terminal is electrically connected to the eighth drive clock signal line CK8.

[0357] As shown in Figure 16, 2H after the falling edge of the clock signal provided by CK15, the potential of the first carry clock signal provided by CLKC1 rises to reset after a delay of 2H, where 2H is the two-line scan time.

[0358] During the blank period SK, STV0 provides a high voltage signal;

[0359] After the falling edge of the clock signal provided by CK8, and after 1H (1H is the scan time of one line), STV0 provides a high voltage signal;

[0360] One hour before STV1 provides a high voltage signal, STV0 provides a low voltage signal;

[0361] During the blank period SK, GCH provides a low voltage signal;

[0362] After the falling edge of the clock signal provided by CK8, and after 1H (1H is the scan time of one line), GCH provides a low voltage signal;

[0363] One hour before STV1 provides a high voltage signal, STV0 provides a high voltage signal.

[0364] The above settings reduce the characteristic drift of the transistor controlling the potential of the second node.

[0365] As shown in Figure 16, the high-level pulse width of the first start voltage provided by STV1 is 4H, and the high-level pulse width of the second start voltage provided by STV2 is 4H, where 4H is the four-line scan time.

[0366] The time interval between the rising edge of the first start voltage provided by STV1 and the rising edge of the second start voltage provided by STV2 is 1H, where 1H is the scan time of one line.

[0367] The high-level pulse width of the first carry clock signal provided by CLKC1, the high-level pulse width of the second carry clock signal provided by CLKC2, the high-level pulse width of the third carry clock signal provided by CLKC3, and the high-level pulse width of the fourth carry clock signal provided by CLKC4 can all be 4H;

[0368] The high-level pulse widths of the clock signals provided by CK1, CK2, CK3, CK4, CK5, CK6, CK7, CK8, CK9, CK10, CK11, CK12, CK13, CK14, CK15, and CK16 can all be 4H.

[0369] The period of each carry clock signal is 16H, and the period of each drive clock signal is 16H.

[0370] The time interval between the rising edge of the clock signal provided by CK9 and the rising edge of the clock signal provided by CK10 is 1H; the time interval between the rising edge of the clock signal provided by CK10 and the rising edge of the clock signal provided by CK11 is 1H; the time interval between the rising edge of the clock signal provided by CK11 and the rising edge of the clock signal provided by CK12 is 1H; the time interval between the rising edge of the clock signal provided by CK12 and the rising edge of the clock signal provided by CK13 is 1H; the time interval between the rising edge of the clock signal provided by CK13 and the rising edge of the clock signal provided by CK14 is 1H; the time interval between the rising edge of the clock signal provided by CK14 and the rising edge of the clock signal provided by CK15 is 1H; and the time interval between the rising edge of the clock signal provided by CK15 and the rising edge of the clock signal provided by CK16 is 1H.

[0371] The time interval between the rising edge of the clock signal provided by CK16 and the rising edge of the clock signal provided by CK1 is 1H; the time interval between the rising edge of the clock signal provided by CK1 and the rising edge of the clock signal provided by CK2 is 1H; the time interval between the rising edge of the clock signal provided by CK2 and the rising edge of the clock signal provided by CK3 is 1H; the time interval between the rising edge of the clock signal provided by CK3 and the rising edge of the clock signal provided by CK4 is 1H; the time interval between the rising edge of the clock signal provided by CK4 and the rising edge of the clock signal provided by CK5 is 1H; the time interval between the rising edge of the clock signal provided by CK5 and the rising edge of the clock signal provided by CK6 is 1H; the time interval between the rising edge of the clock signal provided by CK6 and the rising edge of the clock signal provided by CK7 is 1H; the time interval between the rising edge of the clock signal provided by CK7 and the rising edge of the clock signal provided by CK8 is 1H.

[0372] The rising edge of the first carry clock signal provided by CLKC1 is spaced 1H apart from the rising edge of the second carry clock signal provided by CLKC2, and the rising edge of the third carry clock signal provided by CLK3 is spaced 1H apart from the rising edge of the fourth carry clock signal provided by CLK4.

[0373] As shown in Figure 16, the interval between the first falling edge of the clock signal provided by CK15 and the first rising edge of the clock signal provided by CLKC1 is 2H, where 2H is the two-line scan time.

[0374] The first falling edge of the clock signal provided by CK7 is spaced 2H away from the second rising edge of the third carry clock signal provided by CLKC3;

[0375] To achieve delayed reset.

[0376] In at least one embodiment shown in Figure 16, in the first driving module, the carry signal output terminal of the previous stage driving circuit is electrically connected to the input terminal of the next stage driving circuit, and the carry signal output terminal of the next stage driving circuit is electrically connected to the reset terminal of the next stage driving circuit.

[0377] In the second drive module, the carry signal output terminal of the previous stage drive circuit is electrically connected to the input terminal of the next stage drive circuit, and the carry signal output terminal of the next stage drive circuit is electrically connected to the reset terminal of the next stage drive circuit.

[0378] In at least one embodiment shown in Figure 16, in the first drive module, the odd-numbered drive circuits are electrically connected to CLKC1, CK1, CK3, CK5 and CK7 respectively, and the even-numbered drive circuits are electrically connected to CLKC3, CK9, CK11, CK13 and CK15 respectively.

[0379] In the second drive module, the odd-numbered drive circuits are electrically connected to CLKC2, CK2, CK4, CK6 and CK8 respectively, and the even-numbered drive circuits are electrically connected to CLKC4, CK10, CK12, CK14 and CK16 respectively.

[0380] The driving method described in this embodiment is applied to the aforementioned array substrate, which includes data lines and pixel circuits disposed on a substrate; the driving cycle includes multiple frame display times; the driving method includes: during the driving cycle,

[0381] In at least two adjacent frames, the data voltage on the pixel circuit is controlled to be a first polarity data voltage;

[0382] In at least two adjacent frames, the data voltage on the pixel circuit is controlled to be the second polarity data voltage;

[0383] The first polarity is opposite to the second polarity.

[0384] Optionally, the first polarity can be positive, and the second polarity can be negative.

[0385] In at least one embodiment of this disclosure, for non-display areas or low-frequency areas, clock signal lines and data lines are not supplied, or the display is refreshed once every multiple frames.

[0386] As shown in Figure 17, F1 is the time of the first frame, F2 is the time of the second frame, F3 is the time of the third frame, and F4 is the time of the fourth frame.

[0387] During the first frame time F1 and the second frame time F2, the data voltage on the data line DL is a positive data voltage.

[0388] During the third frame time F3 and the fourth frame time F4, the data voltage on the data line DL is a negative polarity data voltage.

[0389] In Figure 17, the lines labeled GL are scan lines.

[0390] As shown in Figure 17, when two-frame refresh is used, the polarity of the low-frequency region will be flipped with each refresh, which can reduce the risk of flicker.

[0391] In practice, a suitable flip mode is matched according to the refresh frequency of the low-frequency area to prevent pixels from always being in the same polarity.

[0392] The driving method described in this embodiment is applied to the array substrate described above. In the a-th driving circuit, the carry signal providing circuit is electrically connected to the a-th carry clock signal terminal, and the n-th driving signal providing circuit is electrically connected to the corresponding driving clock signal terminal; in the a+c-th driving circuit, the carry signal providing circuit is electrically connected to the a+c-th carry clock signal terminal; n is a positive integer less than or equal to N; the driving method includes:

[0393] During the driving cycle of the a-th driving circuit, the N driving clock signal terminals electrically connected to the a-th driving circuit sequentially begin to output valid driving clock signals.

[0394] After the potential of the drive clock signal output from the Nth drive clock signal terminal electrically connected to the ath drive circuit changes from an effective voltage to an ineffective voltage, after a first predetermined time interval, the a+cth carry clock signal terminal is controlled to provide an effective carry clock signal.

[0395] In practical implementation, a delayed reset method can be adopted, so that the driving signal provided by the Nth driving signal output terminal of the a-th driving circuit is pulled down and reset by the Nth driving clock signal, so that the fall time of the driving signal provided by the Nth driving signal output terminal of the a-th driving circuit is small, and the potential of the driving signal can drop quickly, avoiding incorrect charging of the corresponding row pixel circuit.

[0396] Optionally, the first predetermined time is greater than or equal to 0.5H and less than or equal to 5H, where 1H is the scan time for one line.

[0397] The display device described in this disclosure includes the array substrate described above.

[0398] The above description represents the preferred embodiments of this disclosure. It should be noted that those skilled in the art can make various improvements and modifications without departing from the principles described herein, and these improvements and modifications should also be considered within the scope of protection of this disclosure.

Claims

An array substrate, wherein, It includes a substrate and a driving circuit disposed on the substrate; the driving circuit includes a carry signal providing circuit and N driving signal providing circuits; N is a positive integer; The carry signal providing circuit is used to provide a carry signal; the drive signal providing circuit is used to provide a drive signal; The carry signal providing circuit and the drive signal providing circuit are arranged along a first direction; The array substrate further includes scan lines disposed on the substrate; the drive signal providing circuit is electrically connected to the corresponding scan lines and is used to provide drive signals to the scan lines. The scanning line extends in a second direction, and the first direction intersects with the second direction. The array substrate as claimed in claim 1, wherein, The carry signal providing circuit includes a carry output circuit, and the drive signal providing circuit includes a drive output circuit; the carry output circuit is used to provide a carry signal according to a carry clock signal under the control of the potential of the carry node; the drive output circuit is used to provide a drive signal according to a corresponding drive clock signal under the control of the potential of the corresponding drive node. The channel width-to-length ratio of the transistors included in the carry output circuit is smaller than that of the channel width-to-length ratio of the drive output circuit. The array substrate according to any one of claims 1 or 2, wherein, The carry-out output circuit includes a transistor whose gate includes p interconnected first sub-gates, and adjacent first sub-gates are electrically connected through a first connection portion; The drive output circuit includes a transistor whose gate includes m interconnected second sub-gates, and adjacent second sub-gates are electrically connected through a second connection portion; p and m are positive integers, where m is greater than p. The array substrate as claimed in claim 3, wherein, The carry-out output circuit includes at least two first sub-gates with different shapes; and / or, the carry-out output circuit includes at least two first sub-gates with different dimensions; or, The drive output circuit includes at least two second sub-gates with different shapes; and / or, the drive output circuit includes at least two second sub-gates with different sizes. The array substrate according to claim 1 or 2, wherein, The carry signal providing circuit also includes a carry reset circuit, which is used to reset the carry signal under the control of the potential of the second node; The carry-out output circuit includes a transistor with an active pattern comprising a first active pattern portion and at least one second active pattern portion. The first active pattern portion and the active patterns of the transistors included in the carry-reset circuit are arranged along a first direction. The array substrate as claimed in claim 5, wherein, The first active graphic portion and the second active graphic portion are arranged along the second direction. The array substrate according to claim 1 or 2, wherein, The carry signal providing circuit includes a carry energy storage circuit; the carry energy storage circuit is electrically connected to the carry node and the carry signal output terminal respectively; one plate of the capacitor included in the carry energy storage circuit is electrically connected to the corresponding cascade line through a first via. The capacitor plates in the carry-in energy storage circuit have a first clearance space. The array substrate as claimed in claim 7, wherein, The carry signal providing circuit includes a first transistor; The first transistor is located on the side of the carry energy storage circuit away from the carry output circuit; The active pattern of the first transistor has a second clearance space to avoid the first via. The array substrate as claimed in claim 8, wherein, The first transistor and the capacitors included in the carry energy storage circuit are arranged along the second direction. The array substrate according to claim 8 or 9, wherein, The carry signal providing circuit includes a carry node reset circuit; the carry node reset circuit is used to reset the potential of the carry node under the control of the reset signal provided at the reset terminal; The carry node reset circuit includes the first transistor. The array substrate as claimed in claim 7, wherein, The drive signal providing circuit includes a drive energy storage circuit; the drive energy storage circuit is connected to the drive node and the drive signal output terminal respectively. The shape of the capacitor included in the carry energy storage circuit is different from the shape of the capacitor included in the drive energy storage circuit; and / or, The size of the capacitor plates in the carry energy storage circuit is different from the size of the capacitor in the drive energy storage circuit. The array substrate as claimed in claim 10, wherein, The drive signal providing circuit includes a drive node reset circuit, which is used to reset the potential of the drive node under the control of the reset signal. The shape of the transistor included in the carry node reset circuit is different from the shape of the transistor included in the drive node reset circuit; and / or, The transistors included in the carry node reset circuit have different dimensions than those included in the drive node reset circuit. The array substrate according to any one of claims 1 to 9, wherein, N is greater than 1; The N drive signal providing circuits include transistors of the same shape that have the same function; and / or, The N drive signal providing circuits include transistors of the same size that have the same function. The array substrate as claimed in claim 1, wherein, The carry signal providing circuit includes a carry node control circuit, a carry node reset circuit, a second node control circuit, a carry output circuit, a carry reset circuit, and a carry energy storage circuit. The carry node control circuit is electrically connected to the input terminal, the second node, and the carry node, respectively. It is used to control the potential of the carry node under the control of the input signal provided by the input terminal, and to reset the potential of the carry node under the control of the potential of the second node. The carry node reset circuit is electrically connected to the reset terminal and the carry node respectively, and is used to reset the potential of the carry node under the control of the reset signal provided by the reset terminal; The second node control circuit is electrically connected to the carry node and the second node respectively, and is used to control the potential of the second node under the control of the potential of the carry node; The carry output circuit is electrically connected to the carry node, the carry clock signal terminal and the carry signal output terminal respectively, and is used to write the carry clock signal provided by the carry clock signal terminal into the carry signal output terminal under the control of the potential of the carry node. The carry reset circuit is electrically connected to the second node and the carry signal output terminal respectively, and is used to reset the carry signal provided by the carry signal output terminal under the control of the potential of the second node; The carry energy storage circuit is electrically connected to the carry node and the carry signal output terminal, respectively. The array substrate as claimed in claim 1, wherein The circuit providing the nth driving signal includes the nth driving node control circuit, the nth driving node reset circuit, the nth driving output circuit, the nth driving reset circuit, and the nth driving energy storage circuit. n is a positive integer less than or equal to N; The control circuit of the nth driving node is electrically connected to the input terminal, the second node and the nth driving node respectively, and is used to control the potential of the nth driving node under the control of the input signal provided by the input terminal, and to reset the potential of the nth driving node under the control of the potential of the second node. The nth driving node reset circuit is electrically connected to the reset terminal and the nth driving node, and is used to reset the potential of the nth driving node under the control of the reset signal provided by the reset terminal. The nth drive output circuit is electrically connected to the nth drive node, the nth drive clock signal terminal and the nth drive signal output terminal respectively, and is used to write the nth drive clock signal provided by the nth drive clock signal terminal into the nth drive signal output terminal under the control of the potential of the nth drive node. The nth drive reset circuit is electrically connected to the second node and the nth drive signal output terminal, respectively, and is used to reset the nth drive signal provided by the nth drive signal output terminal under the control of the potential of the second node; The nth driving energy storage circuit is connected to the nth driving node and the nth driving signal output terminal, respectively. The array substrate as claimed in claim 1, 2, 3, 4, 5, 6, 7, 8, 9, 14 or 15, wherein, It includes a driving module; the driving module is disposed on a first side of the display area, and / or a second side of the display area; the first side and the second side are opposite sides; the driving module includes A cascaded driving circuits; A is an integer greater than 1; The input terminal of the a-th driving circuit included in the driving module is electrically connected to the carry signal output terminal of the ab-th stage driving circuit included in the driving module. The reset terminal of the a-th driving circuit included in the driving module is electrically connected to the carry signal output terminal of the a+c-th driving circuit included in the driving module. a, b, and c are positive integers; a is less than or equal to A. The array substrate of claim 16, wherein, The drive module also includes a virtual start drive circuit; The virtual start-up drive circuit is used to provide corresponding input signals to the input terminal of the first-stage drive circuit included in the drive module. A driving method applied to the array substrate as claimed in any one of claims 15 to 17, the array substrate comprising data lines and pixel circuits arranged on a substrate; The driving cycle includes multiple frame display times; the driving method includes: during the driving cycle, In at least two adjacent frames, the data voltage on the pixel circuit is controlled to be a first polarity data voltage; In at least two adjacent frames, the data voltage on the pixel circuit is controlled to be the second polarity data voltage; The first polarity is opposite to the second polarity. The driving method is applied to the array substrate as claimed in claim 16. In the a driving circuit, the carry signal providing circuit is electrically connected with the a carry clock signal terminal, and the n driving signal providing circuit is electrically connected with the corresponding driving clock signal terminal. In the a+c driving circuit, the carry signal providing circuit is electrically connected to the a+c carry clock signal terminal; n is a positive integer less than or equal to N; the driving method includes: During the driving cycle of the a-th driving circuit, the N driving clock signal terminals electrically connected to the a-th driving circuit sequentially begin to output valid driving clock signals. After the potential of the drive clock signal output from the Nth drive clock signal terminal electrically connected to the ath drive circuit changes from an effective voltage to an ineffective voltage, after a first predetermined time interval, the a+cth carry clock signal terminal is controlled to provide an effective carry clock signal. The driving method as claimed in claim 19, wherein, The first predetermined time is greater than or equal to 0.5H and less than or equal to 5H, where 1H is the scan time for one line. A display device comprising the array substrate as claimed in any one of claims 1 to 17.

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