Wiring board

Abstract

A wiring board (10) is provided with a core layer (11) having a through hole (14), and build-up layers (12, 13) laminated on both sides of the core layer (11). The through hole (14) includes a through hole (PTHX) for transmitting a signal, and a plurality of through holes (PTH1, PTH2) for connecting a power supply. The through hole (PTHX) for transmitting a signal overlaps, in plan view, a via hole (15) of the build-up layer (12) adjacent to the core layer (11), and the plurality of through holes (PTH1, PTH2) for connecting a power supply do not overlap, in plan view, the via hole (15) of the build-up layer (12) adjacent to the core layer (11).

Description

Wiring board

[0001] The present disclosure relates to a wiring board for mounting a semiconductor integrated circuit device or the like.

[0002] In order to mount a semiconductor integrated circuit device or the like, a wiring board configured to stack one or more relatively thin insulating substrates (referred to as build-up layers) above and below a relatively thick insulating substrate (referred to as a core layer) may be used.

[0003] In such a wiring board, through holes (PTH: Plated Through Hole) are provided in the core layer and via holes are provided in the build-up layer for electrical connection. The semiconductor integrated circuit device or the like mounted on the wiring board and the circuit board or the like on which the wiring board is mounted are electrically connected by conductors provided on the inner surface of the through hole, conductors provided in the via hole, and wirings provided on the surface and inside of the build-up layer.

[0004] Patent Document 1 discloses the configuration of through holes, via holes, and wirings in a wiring board for transmitting differential signals and connecting a power supply.

[0005] Japanese Patent Application Laid-Open No. 2021-158131

[0006] In recent years, as semiconductor integrated circuit devices have increased in scale, their power consumption has increased, and in wiring boards, the current flowing through the through holes connecting the power supply has increased. This is particularly prominent in the through holes provided directly under the semiconductor integrated circuit device. When the current flowing through the through hole increases, the current flowing through the via holes in the build-up layer connected thereto also increases. Generally, since the diameter of the via holes in the build-up layer is smaller than the diameter of the through holes, the allowable current is small. Therefore, as the current flowing through the through hole increases, the risk of the via holes in the build-up layer being damaged due to a current exceeding the allowable value increases.

[0007] The present disclosure provides a configuration that can prevent the destruction of via holes and the like associated with an increase in the current flowing through the through holes connecting the power supply in a wiring board on which a semiconductor integrated circuit device or the like is mounted.

[0008] A first aspect of the present disclosure is a wiring board comprising: a core layer having through-holes penetrating in a first direction which is the thickness direction of the wiring board; and build-up layers, one or more layers each laminated on both sides of the core layer in the first direction, each layer having via holes penetrating in the first direction, wherein the through-holes in the core layer include a first through-hole for transmitting signals and a plurality of second through-holes for connecting power supplies; the via holes in a first build-up layer adjacent to the core layer include a first via hole electrically connected to the first through-hole and a plurality of second via holes electrically connected to the plurality of second through-holes, wherein the first through-holes overlap with the first via holes in a plan view, and the plurality of second through-holes do not overlap with the plurality of second via holes in a plan view.

[0009] In this embodiment, the wiring board has through-holes in the core layer that penetrate in a first direction, which is the thickness direction of the wiring board, and each layer of the build-up layer has via holes that penetrate in the first direction. The through-holes in the core layer include a first through-hole for transmitting signals and a plurality of second through-holes for connecting power supplies. The first through-holes overlap with the via holes in the build-up layer adjacent to the core layer in a plan view. On the other hand, the plurality of second through-holes do not overlap with the via holes in the build-up layer adjacent to the core layer in a plan view. As a result, the resistance between the through-holes for connecting power supplies and the via holes becomes large, which can suppress the increase in current flowing through the via holes, thereby preventing damage to the via holes, etc.

[0010] According to this disclosure, it is possible to prevent damage to via holes and other issues caused by increased current flowing through through-holes connected to power supplies in wiring boards on which semiconductor integrated circuit devices and the like are mounted.

[0011] Cross-sectional view showing the schematic configuration of a wiring board according to the embodiment. Example of planar arrangement of through-holes and via holes in a wiring board. Cross-sectional view of the configuration in Figure 2 (a) to (d) are detailed diagrams of the wiring patterns in each wiring layer in Figure 3. Example of planar arrangement of through-holes and via holes according to a modified example. Cross-sectional view of the configuration in Figure 5.

[0012] The embodiments will be described below with reference to the drawings. In the following description, the thickness direction of the wiring board, in other words, the direction perpendicular to the surface of the wiring board, is referred to as the Z direction (corresponding to the first direction).

[0013] Figure 1 is a cross-sectional view showing the schematic configuration of a wiring board according to an embodiment. As shown in Figure 1, the wiring board 10 is connected to a semiconductor integrated circuit device 20 mounted at the top of the drawing via bumps 21. The bumps 21 are formed by solder, for example, but are not limited to this. The wiring board 10 is also connected to a circuit board (not shown) at the bottom of the drawing via solder balls 22.

[0014] The wiring board 10 comprises a core layer 11 and build-up layers 12 and 13 stacked above and below the core layer. The core layer 11 has a relatively thick insulating substrate 11a and has a plated through hole 14 that penetrates the insulating substrate 11a in the Z direction. The through hole 14 has a metal 14a plated on its inner surface and is further filled with resin 14b inside. Note that the resin does not have to be filled inside the through hole 14, and metal may be filled instead of resin.

[0015] Each of the build-up layers 12 and 13 consists of two layers of insulating substrate 12a, which is thinner than the insulating substrate 11a of the core layer 11. Each layer of the build-up layers 12 and 13 has via holes 15 that penetrate the insulating substrate 12a in the Z direction. The inside of the via holes 15 is filled with metal. Metal wiring 16 is also provided on the surface of the build-up layers 12 and 13 and between the layers. Note that the build-up layers 12 and 13 are not limited to two layers, but may consist of one layer or three or more layers.

[0016] On the wiring board 10, a multilayer wiring structure is formed by through-holes 14, via holes 15, and metal wiring 16. The semiconductor integrated circuit device 20 located at the top of the diagram of the wiring board 10 and the circuit board located at the bottom of the diagram of the wiring board 10 are connected to each other by the multilayer wiring structure formed on the wiring board 10.

[0017] Figure 2 is a plan view showing an example of the configuration of a multilayer wiring structure for power and signals on a wiring board 10. Figure 2 illustrates through-holes for power and signals, and via holes (in the build-up layer closest to the core layer). In Figure 2, there are three through-holes for transmitting signals (including PTHX), six through-holes for connecting VDD (including PTH1 and PTH2), and six through-holes for connecting VSS (including PTH3 and PTH4). Note that two types of power supplies, VDD and VSS, are assumed here, but the power supplies are not limited to these two types.

[0018] Figure 3 is a cross-sectional view of the configuration in Figure 2, showing the cross-sectional structure along the line Y1-Y1'. Figure 4 is a detailed view of the wiring patterns, through-holes, and via holes in the wiring layers (layers A to F) shown in Figure 3. In Figure 4, (a) is the via hole between layer A and layers A-B, (b) is the via hole between layer B and layers B-C, and the via hole between layer E and layers D-E, (c) is the via hole between layers C and D, and (d) is the via hole between layer F and layers E-F. In Figures 3(a), (b), and (d), the location of the through-holes is indicated by dashed circles. Note that the via holes shown in Figure 2 correspond to the via holes between layers B-C and layers D-E.

[0019] As shown in Figure 3, the solder ball 22A is connected to the VDD from the circuit board. The solder ball 22A is connected to the through-holes 14 (PTH1, PTH2) of the core layer 11 via via holes 15 and wiring 16 formed in the build-up layer 13 located below the core layer 11. PTH1 and PTH2 of the core layer 11 are further connected to via holes 15 and wiring 16 formed in the build-up layer 12 located above the core layer 11. From the wiring 16, the semiconductor integrated circuit device 20 is connected by bumps 21.

[0020] The solder ball 22B is connected to the VSS from the circuit board. The solder ball 22B is connected to the through-holes 14 (PTH3, PTH4) of the core layer 11 via via holes 15 and wiring 16 formed in the build-up layer 13 located below the core layer 11. PTH3 and PTH4 of the core layer 11 are further connected to via holes 15 and wiring 16 formed in the build-up layer 12 located above the core layer 11. From the wiring 16, the semiconductor integrated circuit device 20 is connected by bumps 21.

[0021] The solder balls 22C transmit signals to or from the circuit board. The solder balls 22C are connected to through-holes 14 (PTHX) in the core layer 11 via via holes 15 and wiring 16 formed in the build-up layer 13 located below the core layer 11. The PTHX in the core layer 11 are further connected to via holes 15 and wiring 16 formed in the build-up layer 12 located above the core layer 11. From the wiring 16, the semiconductor integrated circuit device 20 is connected by bumps 21.

[0022] The through-holes PTH1 and PTH2 for VDD are connected to the wiring 16 of the E layer via multiple via holes 15 between the D and E layers, and are also connected to the wiring 16 of the B layer via multiple via holes 15 between the B and C layers. Each via hole 15 formed between the D and E layers and between the B and C layers, which is electrically connected to the through-holes PTH1 and PTH2, is positioned so as not to overlap with the through-holes PTH1 and PTH2 in a plan view. Similarly, the through-holes PTH3 and PTH4 for VSS are connected to the wiring 16 of the E layer via multiple via holes 15 between the D and E layers, and are also connected to the wiring 16 of the B layer via multiple via holes 15 between the B and C layers. Each via hole 15 formed between the D and E layers and between the B and C layers, which is electrically connected to the through-holes PTH3 and PTH4, is positioned so as not to overlap with the through-holes PTH3 and PTH4 in a plan view.

[0023] In this embodiment, if a via hole 15 electrically connected to a power supply through-hole 14 is placed in a position that overlaps with the through-hole 14 in a plan view, the resistance between the through-hole 14 and the via hole 15 becomes small. As a result, current concentrates in the via hole 15, increasing the likelihood of current exceeding the allowable limit. This can lead to problems such as damage to the via hole 15. This problem is particularly pronounced in through-holes 14 that are placed in a position that overlaps with the semiconductor integrated circuit device 20 in a plan view. In this embodiment, the via hole 15 electrically connected to the power supply through-hole 14 is placed in a position that does not overlap with the through-hole 14 in a plan view. This avoids the above-mentioned problem.

[0024] Furthermore, as shown in Figure 2, the through-holes PTH1 and PTH2 for VDD each have four via holes 15 laid at the closest position in a plan view, and the distance to each via hole 15 is equal. Similarly, the through-holes PTH3 and PTH4 for VSS each have four via holes 15 laid at the closest position in a plan view, and the distance to each via hole 15 is equal. In other words, the distance between the power supply through-hole 14 and the multiple via holes 15 laid around it in a plan view is equal. This makes it possible to make the resistance value from the power supply through-hole 14 to each via hole 15 equal, thus preventing current from concentrating in a particular via hole 15. Therefore, the possibility of current exceeding the allowable value flowing through the via hole 15 can be suppressed, and problems such as damage to the via hole 15 can be avoided.

[0025] On the other hand, the signal through-hole PTHX is connected to the wiring 16 of the E layer via a single via hole 15 between the D and E layers, and also connected to the wiring 16 of the B layer via a single via hole 15 between the B and C layers. The via holes 15 formed between the D and E layers and between the B and C layers, which are electrically connected to the through-hole PTHX, are positioned to overlap with the through-hole PTHX in a plan view.

[0026] In this case, if the electrically connected via hole 15 is placed in a position that overlaps the through hole 14 in a plan view with the signal through hole 14, the area occupied by the wiring can be reduced. In this case, the inductance and resistance of the signal path can be reduced, improving the electrical characteristics and signal quality. Generally, the current flowing through signal wiring is smaller than that of power wiring, so even if the electrically connected via hole 15 is placed in a position that overlaps the signal through hole 14 in a plan view, the problem of the current flowing through the via hole 15 exceeding the allowable value does not occur.

[0027] As described above, according to this embodiment, the wiring board 10 comprises a core layer 11 having through-holes 14 penetrating in the Z direction, and build-up layers 12 and 13, each of which are stacked on both sides of the core layer 11 in the Z direction, with one or more layers stacked on each side, and each layer having via holes 15 penetrating in the Z direction. The through-holes 14 of the core layer 11 include through-holes PTHX for transmitting signals and a plurality of through-holes PTH1 and PTH2 for connecting VDD. The through-holes PTHX overlap in a plan view with the via holes 15 in the build-up layers 12 and 13 adjacent to the core layer 11. On the other hand, the plurality of through-holes PTH1 and PTH2 do not overlap in a plan view with the via holes 15 in the build-up layers 12 and 13 adjacent to the core layer 11. Therefore, it is possible to prevent the current flowing through the through-holes PTH1 and PTH2 for connecting VDD from concentrating in a specific via hole 15, thereby reducing the possibility of current exceeding the allowable value flowing through the via hole 15 and avoiding problems such as damage to the via hole 15.

[0028] Furthermore, the multiple through-holes PTH3 and PTH4 for connecting the VSS do not overlap in a plan view with the via holes 15 in the build-up layers 12 and 13 adjacent to the core layer 11. Therefore, it is possible to prevent the current flowing through the through-holes PTH3 and PTH4 for connecting the VSS from concentrating in a specific via hole 15, thereby reducing the possibility of current exceeding the allowable value flowing through the via hole 15 and avoiding problems such as damage to the via hole 15.

[0029] Furthermore, as shown in the modified examples described later, it is not necessary for the electrically connected via holes 15 to overlap with the signal through-holes 14 in a plan view.

[0030] (Modified Version) Figure 5 is a plan view showing an example of the configuration of a multilayer wiring structure for power and signals in a wiring board 10 according to a modified version. Figure 6 is a cross-sectional view of the configuration in Figure 5, showing the cross-sectional structure along line Y1-Y1'. In Figures 5 and 6, components common to Figures 2 and 3 are denoted by the same reference numerals, and dashed lines are used to indicate parts where the configuration differs from Figures 2 and 3.

[0031] In this modified example, some of the through-holes 14 for the VSS (including the three in the bottom row of Figure 5, PTH4) do not overlap with the semiconductor integrated circuit device 20 in a plan view. However, some of the electrically connected via holes 15 overlap these through-holes 14 in a plan view.

[0032] Here, the through-holes 14 that do not overlap the semiconductor integrated circuit device 20 in a plan view have a smaller current flowing through them compared to the through-holes 14 that do overlap the semiconductor integrated circuit device 20 in a plan view. For this reason, even if via holes 15 are provided at positions where the through-holes 14 that do not overlap the semiconductor integrated circuit device 20 in a plan view would overlap, problems such as current concentration and damage to those via holes 15 will not occur.

[0033] Furthermore, in this modified example, the via hole 15 does not overlap with a portion of the signal through-hole 14 (the rightmost through-hole in the central column of Figure 5) in a plan view. In other words, for a portion of the signal through-hole 14, the electrically connected via hole 15 does not need to overlap with the through-hole 14 in a plan view.

[0034] In this modified example, it is not necessary to provide via holes 15 at the positions where the through-holes 14 for power supply, which do not overlap with the semiconductor integrated circuit device 20 in a plan view, overlap with the semiconductor integrated circuit device 20 in a plan view.

[0035] This disclosure describes how, in a wiring board on which semiconductor integrated circuit devices and the like are mounted, it is possible to prevent damage to via holes caused by increased current flowing through power supply connections, and thus it is useful, for example, for improving the performance of semiconductor products.

[0036] 10 Wiring board 11 Core layer 12, 13 Build-up layer 14 Through-hole (PTH) 15 Via hole 20 Semiconductor integrated circuit equipment PTH1, PTH2, PTH3, PTH4, PTHX Through-hole

Claims

1. A wiring board comprising: a core layer having through-holes penetrating in a first direction which is the thickness direction of the wiring board; and build-up layers, one or more layers stacked on each side of the core layer in the first direction, each layer having via holes penetrating in the first direction, wherein the through-holes in the core layer include a first through-hole for transmitting signals and a plurality of second through-holes for connecting power supplies; the via holes in the first build-up layer adjacent to the core layer include a first via hole electrically connected to the first through-hole and a plurality of second via holes electrically connected to the plurality of second through-holes, wherein the first through-holes overlap with the first via holes in a plan view, and the plurality of second through-holes do not overlap with the plurality of second via holes in a plan view.

2. A wiring board according to claim 1, wherein at least one of the plurality of second through-holes is such that, in a plan view, two or more of the plurality of second via holes are arranged at the position closest to the second through-hole and at an equidistant distance from the second through-hole.

3. A wiring board according to claim 1, wherein the through-holes in the core layer include a third through-hole for connecting the power supply, the via-holes in the first build-up layer include a third via-hole electrically connected to the third through-hole, and the third through-hole is superimposed on the third via-hole in a plan view.

4. A wiring board according to claim 3, wherein a semiconductor integrated circuit device is laminated on the wiring board, the plurality of second through-holes overlap with the semiconductor integrated circuit device in a plan view, and the third through-holes do not overlap with the semiconductor integrated circuit device in a plan view.

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