Impedance calibration for serdes transmitter driver

The calibration circuit in SERDES interfaces adjusts current flow through driver segments to maintain impedance matching, addressing variability in transmission speed and voltage, enhancing reliability and reducing power consumption.

WO2026111896A1 Publication Date: 2026-05-28QUALCOMM INC
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Patent Information

Application Number
PCT/US2025/054397
Authority / Receiving Office
WO · WO
Patent Type
Applications
Current Assignee / Owner
Priority Date
2024-11-22
Filing Date
2025-11-06
Publication Date
2026-05-28

AI Technical Summary

Technical Problem

There is a need for improved performance, accuracy, and reliability in serializer/deserializer (SERDES) interfaces to accommodate changes in transmission speed, supply voltage variances, and other factors that impact high-speed data links, particularly in mobile electronic devices.

Method used

A calibration circuit with multiple sections, including error amplifiers and current comparators, is used to adjust the current flowing through driver segments to match impedance and maintain voltage across a replica driver stage, ensuring precise impedance matching across varying process, voltage, and temperature conditions.

Benefits of technology

The solution enhances the flexibility and reliability of SERDES interfaces by maintaining impedance matching and reducing power consumption, thereby improving data integrity and compatibility across different operating conditions.

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Abstract

A method for calibrating an output driver includes generating a first current representative of current flowing through a termination impedance of an output driver, generating a second current representative of current flowing through a replica driver stage comprising one or more replicas of a driver stage in a driver segment in the output driver, and comparing the first current and the second current using a current comparator. Generating the second current includes controlling gate voltage of first transistors configured to provide a reference current to the replica driver stage to maintain a predefined voltage across the replica driver stage. The gates of the first transistors are coupled to gates of second transistors that are configured to provide a scaled version of the reference current to third transistors that are included in a current mirror. The second current is received from the current comparator.
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