Display apparatus, and display panel and driving method therefor

Abstract

Disclosed in the present application are a display apparatus, and a display panel and a driving method therefor. The display panel comprises a first light-emitting module, a second light-emitting module, and a pixel driving circuit. The first light-emitting module is disposed in a first display area, and comprises a first light-emitting unit and a privacy protection unit, wherein the privacy protection unit is configured to limit the light-emergent angle of the first light-emitting unit. The second light-emitting module is disposed in a second display area, and comprises a second light-emitting unit, wherein the second light-emitting unit is connected in series to the first light-emitting unit. The pixel driving circuit is configured to output driving signals for driving the first light-emitting unit and the second light-emitting unit. In the present application, the first light-emitting unit is connected in series to the second light-emitting unit, and the light-emergent angle of the first light-emitting unit is limited by means of the privacy protection unit, thereby enabling an active privacy protection function of the display panel.

Description

Display device, display panel and its driving method Technical Field

[0001] This invention relates to the field of display technology, and in particular to a display device, a display panel, and a driving method thereof. Background Technology

[0002] A display device is a device that displays images to a user to provide visual information. Display devices are typically manufactured to achieve wide viewing angles, but sometimes it may be necessary to temporarily configure a display device to have a narrow viewing angle so that the image cannot be seen by anyone other than the user in public places. Summary of the Invention

[0003] The purpose of this application is to provide a display device, display panel and driving method thereof that can selectively implement privacy protection function.

[0004] This application discloses a display panel, which includes:

[0005] A first light-emitting module is disposed in a first display area. The first light-emitting module includes a first light-emitting unit and a privacy unit. The privacy unit is configured to limit the light emission angle of the first light-emitting unit.

[0006] A second light-emitting module is disposed in a second display area. The second light-emitting module includes a second light-emitting unit, which is connected in series with the first light-emitting unit.

[0007] A pixel driving circuit, disposed in the first display area and / or the second display area, is configured to output driving signals for driving the first light-emitting unit and the second light-emitting unit.

[0008] Optionally, the display panel further includes:

[0009] The shorting module, connected to the control signal terminal, is configured to selectively short-circuit the second light-emitting unit under the control of the control signal.

[0010] Optionally, the pixel driving circuit includes a first power signal terminal, a second power signal terminal, and a light-emitting control transistor. The potential of the first power signal terminal is higher than the potential of the second power signal terminal. The first light-emitting unit and the second light-emitting unit are disposed between the light-emitting control transistor and the first power signal terminal.

[0011] Optionally, the pixel driving circuit includes a first power signal terminal, a second power signal terminal, and a light-emitting control transistor. The potential of the first power signal terminal is higher than the potential of the second power signal terminal. The first light-emitting unit and the second light-emitting unit are disposed between the light-emitting control transistor and the second power signal terminal.

[0012] Optionally, the shorting module includes a shorting transistor, the first terminal of which is connected to the anode of the second light-emitting unit, the second terminal of which is connected to the cathode of the second light-emitting unit, and the control terminal of which is connected to a control signal terminal.

[0013] Optionally, the control signal terminal is connected to a chip, and the chip is configured to:

[0014] When the display panel is adjusted to privacy mode, the chip sends a control signal to turn on the short-circuit transistor, causing the second light-emitting unit to short-circuit.

[0015] When the display panel is adjusted to the sharing mode, the chip sends a control signal to control the shorting transistor to disconnect, so that the second light-emitting unit can emit light normally.

[0016] Optionally, the control signal terminal is connected to a shift register module, and the shift register module is configured to:

[0017] When the display panel is adjusted to privacy mode, the shift register module sends a control signal to control the short-circuit transistor to turn on, causing the second light-emitting unit to short-circuit.

[0018] When the display panel is adjusted to the sharing mode, the shift register module sends a control signal to control the shorting transistor to disconnect, so that the second light-emitting unit can emit light normally.

[0019] Optionally, the pixel driving circuit includes:

[0020] The driving module is configured to control the first light-emitting unit and the second light-emitting unit to emit light under the control of a data signal;

[0021] The data writing module is configured to write data signals to the driving module;

[0022] The compensation module is configured to compensate the data signal written by the data writing module;

[0023] The light emission control module is configured to control the first light emission unit and the second light emission unit to emit light under the control of the light emission control signal;

[0024] The reset module is configured to reset the pixel driving circuit.

[0025] Optionally, the driving module includes a first transistor, a first terminal of the first transistor is connected to a second node, a second terminal of the first transistor is connected to a third node, and the first transistor includes a top control terminal and a bottom control terminal, the top control terminal is connected to the first node, and the bottom control terminal is connected to the second node;

[0026] The compensation module includes a second transistor and a third transistor; the first terminal of the second transistor is connected to the third node, the second terminal of the second transistor is connected to the first node, and the control terminal of the second transistor is connected to the first gate signal terminal; the first terminal of the third transistor is connected to the first reference signal terminal, the second terminal of the third transistor is connected to the second node, and the control terminal of the third transistor is connected to the first gate signal terminal.

[0027] The data writing module includes a fourth transistor and a first capacitor. The first electrode of the fourth transistor is connected to the data signal terminal, the second electrode of the fourth transistor is connected to the fifth node, and the control electrode of the fourth transistor is connected to the second gate signal terminal.

[0028] The first terminal of the first capacitor is connected to the fifth node, and the second terminal is connected to the first node.

[0029] Optionally, the light-emitting control module includes a fifth transistor and a sixth transistor;

[0030] The first electrode of the fifth transistor is connected to the fourth node, the second electrode of the fifth transistor is connected to the third node, and the control electrode of the fifth transistor is connected to the light emission control signal terminal.

[0031] The first electrode of the sixth transistor is connected to the second node, the second electrode of the sixth transistor is connected to the second power signal terminal, and the control electrode of the sixth transistor is connected to the light emission control signal terminal.

[0032] Optionally, the reset module includes a seventh transistor, an eighth transistor, and a ninth transistor;

[0033] The first terminal of the seventh transistor is connected to the first power signal terminal, the second terminal of the seventh transistor is connected to the first node, and the control terminal of the seventh transistor is connected to the second reset signal terminal.

[0034] The first terminal of the eighth transistor is connected to the first power supply signal terminal, the second terminal of the eighth transistor is connected to the fourth node, and the control terminal of the eighth transistor is connected to the first gate signal terminal or the second reset signal terminal.

[0035] The first terminal of the ninth transistor is connected to the first reference signal terminal, the second terminal of the ninth transistor is connected to the fifth node, and the control terminal of the ninth transistor is connected to the first reset signal terminal.

[0036] A second capacitor is provided between the fifth node and the first reference signal terminal.

[0037] Optionally, the first light-emitting module includes a third light-emitting unit connected in series with the first light-emitting unit, and the third light-emitting unit is stacked with the first light-emitting unit.

[0038] Optionally, the second light-emitting module includes a fourth light-emitting unit connected in series with the second light-emitting unit, and the fourth light-emitting unit is stacked with the second light-emitting unit.

[0039] Optionally, the short-circuiting module is configured to selectively short-circuit the second light-emitting unit and the fourth light-emitting unit together under the control of a control signal.

[0040] This application also discloses a driving method for a display panel, which is used to drive the aforementioned display panel, comprising:

[0041] The control shift register unit outputs a first reset signal, a second reset signal, a first gate signal, a second gate signal, and a light emission control signal; wherein, the first reset signal at least covers the second reset signal and the first gate signal, the first gate signal lags behind the second reset signal, the second gate signal lags behind the first gate signal, and the light emission control signal lags behind the second gate signal.

[0042] Optionally, the pulse width of the first reset signal is 2H, the pulse width of the second reset signal is 1H, the pulse width of the first gate signal is 1H, the pulse width of the second gate signal is 1H, and the pulse width of the light emission control signal is 1H; the first gate signal lags behind the second reset signal 1H, the second gate signal lags behind the first gate signal 1H, and the light emission control signal lags behind the second gate signal 1H.

[0043] Optionally, the pulse width of the first reset signal is 3H, the pulse width of the second reset signal is 1H, the pulse width of the first gate signal is 1H, the pulse width of the second gate signal is 1H, and the pulse width of the light emission control signal is 1H; the first gate signal lags behind the second reset signal 1H, the end edge of the first gate signal overlaps with the end edge of the first reset signal, and the end edge is a rising edge or a falling edge; the second gate signal lags behind the first gate signal 1H, and the light emission control signal lags behind the second gate signal 1H.

[0044] This application also provides a display device, which includes the display panel described above.

[0045] Compared with related technologies, the first light-emitting unit and the second light-emitting unit of this application are connected in series, and the light emission angle of the first light-emitting unit is limited by the privacy unit, thus realizing the active privacy requirement of the display panel through a simple structure.

[0046] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this specification. Attached Figure Description

[0047] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this specification and, together with the description, serve to explain the principles of this specification.

[0048] Figure 1 is a perspective view of the display panel in one embodiment of this application.

[0049] Figure 2 is a cross-sectional schematic diagram of a portion of the display panel in one embodiment of this application.

[0050] Figure 3 is a cross-sectional schematic diagram of a portion of the display panel in one embodiment of this application.

[0051] Figure 4 is a cross-sectional schematic diagram of a portion of the display panel in one embodiment of this application.

[0052] Figure 5 is a schematic diagram of the pixel driving circuit of the display panel in one embodiment of this application.

[0053] Figure 6 is a timing diagram of the pixel driving circuit shown in Figure 5 in one embodiment of this application.

[0054] Figure 7 is a timing diagram of the pixel driving circuit shown in Figure 5 in one embodiment of this application.

[0055] Figure 8 is a schematic diagram of the pixel driving circuit of the display panel in one embodiment of this application. Detailed Implementation

[0056] The technical solutions in the embodiments (or "implementations") of this application will be clearly and completely described herein with reference to the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements.

[0057] If the embodiments of this application contain terms relating to directional indications or positional relationships (such as up, down, left, right, front, back, inside, outside, top, bottom, center, vertical, horizontal, longitudinal, transverse, length, width, counterclockwise, clockwise, axial, radial, circumferential, etc.), such terms are only used to explain the relative positional relationships and movements between components in a specific posture (as shown in the attached figures); if the specific posture changes, the directional indications or positional relationships will also change accordingly. Furthermore, the terms "first" and "second" used in the embodiments of this application are only for descriptive convenience and should not be construed as indicating or implying relative importance.

[0058] As shown in Figures 1, 2, and 5, this application provides a display panel including a pixel driving circuit 100, a first light-emitting module 200, and a second light-emitting module 300. Optionally, the display panel may further include a shorting module 400.

[0059] The first light-emitting module 200 is disposed in the first display area DA1 of the display panel. The first light-emitting module 200 includes a first light-emitting unit 210 and a privacy unit 220. The privacy unit 220 is configured to limit the light emission angle of the first light-emitting unit 210.

[0060] The second light-emitting module 300 is disposed in the second display area DA2. The second light-emitting module 300 includes a second light-emitting unit 310, which is connected in series with the first light-emitting unit 210.

[0061] The pixel driving circuit 100 is disposed in the first display area DA1 and / or the second display area DA2, and is configured to output driving signals for driving the first light-emitting unit 210 and the second light-emitting unit 310.

[0062] The shorting module 400 is connected to the control signal terminal PC and is configured to selectively short-circuit the second light-emitting unit 310 under the control of the control signal PC.

[0063] The first light-emitting unit and the second light-emitting unit of this application are connected in series. The light emission angle of the first light-emitting unit is limited by the privacy unit, and the active privacy requirement of the display panel is realized through a simple structure.

[0064] The following will provide a detailed description of various embodiments of this application that conform to the above-described inventive concept.

[0065] As shown in Figures 1 and 2, the display panel of this application includes a display area DA and a non-display area NDA surrounding the display area DA, wherein the non-display area NDA may not completely surround the display area DA. The display area DA includes a plurality of first display areas DA1 and a plurality of second display areas DA2 arranged in an array, and each first display area DA1 or second display area DA2 is provided with a pixel. A pixel may include one of a first light-emitting module 200 or a second light-emitting module 300. The first light-emitting module 200 includes a first light-emitting unit 210, which can be configured to emit light of different colors. For example, some first light-emitting units 210 can be configured to emit red light, some first light-emitting units 210 can be configured to emit green light, and some first light-emitting units 210 can be configured to emit blue light. The second light-emitting module 300 includes a second light-emitting unit 310, which can be configured to emit light of different colors. For example, some second light-emitting units 310 can be configured to emit red light, some second light-emitting units 310 can be configured to emit green light, and some second light-emitting units 310 can be configured to emit blue light.

[0066] A first light-emitting unit 210 can be connected in series with a second light-emitting unit 310. The series-connected first light-emitting unit 210 and second light-emitting unit 310 are configured to emit light of the same color. The series-connected first light-emitting unit 210 and second light-emitting unit 310 can be connected to the same pixel driving circuit 100. The series-connected first light-emitting unit 210 and second light-emitting unit 310 can be arranged adjacent to each other, for example, adjacent to each other in the row direction of the display panel, adjacent to each other in the column direction of the display panel, or adjacent to each other in any direction where the display panel forms an angle of 0-90° with the row direction. The series-connected first light-emitting unit 210 and second light-emitting unit 310 can also be arranged non-adjacently, for example, other light-emitting units can be arranged between the series-connected first light-emitting unit 210 and second light-emitting unit 310.

[0067] In some optional embodiments, the number of first light-emitting modules 200 and second light-emitting modules 300 on the display panel is the same, and the entire panel is filled with first light-emitting units 210 and second light-emitting units 310 connected in series. This means the entire display panel can be selectively adjusted to either a privacy mode or a sharing mode. In other optional embodiments, the number of first light-emitting modules 200 on the display panel is greater than the number of second light-emitting modules 300. Part of the display panel is filled with first light-emitting units 210 and second light-emitting units 310 connected in series, while another part is filled with individual first light-emitting modules 200. This means a part of the display panel can be selectively adjusted to either a privacy mode or a sharing mode, while another part remains in a constant privacy mode. Similarly, a part of the display panel can also be selectively adjusted to either a privacy mode or a sharing mode, while another part remains in a constant sharing mode. Alternatively, all three modes can coexist on the display panel simultaneously.

[0068] As shown in Figure 2, the display panel, from the non-display side to the display side in its thickness direction, may include a substrate PI, an active layer Poly, a first gate insulating layer GI1, a first gate layer Gate1, a second gate insulating layer GI2, a second gate layer Gate2, an interlayer insulating layer ILD, a first source / drain metal layer SD1, a passivation layer PVX, a first planarization layer PLN1, a second source / drain metal layer SD2, a second planarization layer PLN2, a first light-emitting module 200 and a second light-emitting module 300, as well as encapsulation or touch structures thereon.

[0069] In some embodiments, the substrate PI can be a rigid substrate or a flexible substrate. The material of the flexible substrate may include one or more of polyimide, polyethylene terephthalate, polycarbonate, and organic resin materials, such as epoxy resin, triazine, silicone resin, or polyimide. The rigid substrate includes any of the following: glass substrate, quartz substrate, sapphire substrate, ceramic substrate, etc.; or any of the following of the following semiconductor substrates: single-crystal semiconductor substrate or polycrystalline semiconductor substrate made of silicon or silicon carbide, compound semiconductor substrate such as silicon-germanium, SOI (Silicon on Insulator) substrate, etc.

[0070] In some embodiments, the substrate PI includes both a rigid substrate and a flexible substrate, wherein the flexible substrate is disposed between the rigid substrate and the driving circuit layer. Furthermore, the rigid substrate can be removed after or during device fabrication to give the entire device high flexibility. The rigid substrate primarily serves to support the flexible substrate and the driving circuit layer during fabrication.

[0071] The active layer, Poly, can be made of amorphous silicon or polycrystalline silicon, etc.

[0072] The first gate insulating layer GI1 and the first gate layer Gate1 are disposed above the active layer Poly. The first gate insulating layer GI1 can be a complete single layer, or it can have a shape and pattern that are basically the same as the first gate layer Gate1, as long as it can effectively isolate the first gate layer Gate1 from the active layer Poly. The material of the first gate insulating layer GI1 can be silicon oxide, silicon nitride, or silicon oxynitride, etc. The material of the first gate layer Gate1 can be a metal material such as aluminum, copper, or silver.

[0073] The first gate insulating layer GI1 and the first gate layer Gate1 are disposed above the active layer Poly. The first gate insulating layer GI1 can be a complete single layer, or it can have a shape and pattern that are basically the same as the first gate layer Gate1, as long as it can effectively isolate the first gate layer Gate1 from the active layer Poly. The material of the first gate insulating layer GI1 can be silicon oxide, silicon nitride, or silicon oxynitride, etc. The material of the first gate layer Gate1 can be a metal material such as aluminum, copper, or silver.

[0074] The second gate insulating layer GI2 and the second gate layer Gate2 are disposed above the first gate layer Gate1. The material of the second gate insulating layer GI2 can be silicon oxide, silicon nitride, or silicon oxynitride, etc. The material of the second gate layer Gate2 can be a metal material such as aluminum, copper, or silver.

[0075] The material of the interlayer insulation layer (ILD) can be insulating materials such as silicon oxide, silicon nitride, and silicon oxynitride.

[0076] The first source / drain electrode layer SD1 and the second source / drain metal layer SD2 can be made of conductive metals such as aluminum, copper, and silver.

[0077] The passivation layer PVX can be made of insulating materials such as silicon oxide, silicon nitride, and silicon oxynitride.

[0078] The upper surfaces of the first planarization layer PLN1 and the second planarization layer PLN2 can be flat surfaces. The material of the planarization layer can be silicon oxide, silicon nitride, silicon oxynitride, or organic materials.

[0079] A pixel delimiting layer (PDL) is provided on the second flattening layer PLN2 to define a number of light-emitting modules, some of which are the first light-emitting modules 200 and the other part are the second light-emitting modules 300.

[0080] The first light-emitting module 200 includes, from bottom to top, a first lower electrode 250, a first light-emitting unit 210, a first upper electrode 240, and a privacy unit 220. One of the first lower electrode 250 and the first upper electrode 240 is the anode of the first light-emitting unit 210, and the other is the cathode. The first light-emitting unit 210 can be an OLED (Organic Light-Emitting Diode), a QLED (Quantum Dot Light-Emitting Diode), or an LED (Light Emitting Diode), etc. The privacy unit 220 can be a lens structure of a certain shape, which can partially cover the first light-emitting unit 210 in the light-emitting direction; or the privacy unit 220 can be a barrier structure surrounding the first light-emitting unit 210; or the privacy unit 220 can be an electrochromic layer, etc.; as long as it satisfies the requirement of limiting the light-emitting angle of the first light-emitting unit 210.

[0081] The second light-emitting module 300 includes, from bottom to top, a second lower electrode 340, a second light-emitting unit 310, and a second upper electrode 330. One of the second lower electrode 340 and the second upper electrode 330 serves as the anode of the second light-emitting unit 310, and the other as the cathode. The second light-emitting unit 310 can be an OLED (Organic Light-Emitting Diode), a QLED (Quantum Dot Light-Emitting Diode), or an LED (Light Emitting Diode), etc. Optionally, in the series-connected first light-emitting unit 210 and second light-emitting unit 310, the first lower electrode 250 of the first light-emitting unit 210 can be connected to the second upper electrode 330 of the second light-emitting unit 310. Of course, in other embodiments, other connection methods are also possible, as long as the first light-emitting unit 210 and the second light-emitting unit 310 are connected in series.

[0082] When only the first light-emitting module 200 emits light in a certain area of ​​the panel, that area is in privacy mode, and the content on the display panel can only be seen from a certain angle on the front of the display panel. When both the first light-emitting module 200 and the second light-emitting module 300 emit light in a certain area of ​​the panel, that area is in sharing mode, and the content on the display panel can be seen from any angle on the front of the display panel.

[0083] As shown in Figure 3, in an optional embodiment, the light-emitting unit is an OLED light-emitting unit. The first light-emitting module 200 includes a third light-emitting unit 230 connected in series with the first light-emitting unit 210. The third light-emitting unit 230 and the first light-emitting unit 210 are stacked to form a Tandem OLED. In this way, the luminous efficiency of the first light-emitting module 200 can be improved, and the overall luminous efficiency loss of the display panel when the second light-emitting module 300 is short-circuited can be reduced.

[0084] As shown in Figure 4, in an optional embodiment, the light-emitting unit is an OLED light-emitting unit, and the first light-emitting module 200 includes a third light-emitting unit 230 stacked with the first light-emitting unit 210. Simultaneously, the second light-emitting module 300 includes a fourth light-emitting unit 320 connected in series with the second light-emitting unit 310, and the fourth light-emitting unit 320 and the second light-emitting unit 310 are stacked to form a Tandem OLED. This improves the overall luminous efficiency of the panel. At this time, when the display panel is in privacy mode, the short-circuit module 400 is configured to short-circuit the second light-emitting unit 310 and the fourth light-emitting unit 320 together under the control of the control signal pc.

[0085] As shown in Figures 2 and 5, a pixel driving circuit 100 and a shorting module 400 are disposed in the active layer Poly to the second source-drain metal layer SD2 of the display panel.

[0086] The signal terminals connected to the pixel driving circuit 100 provided in this application include a first power supply signal terminal VDD, a second power supply signal terminal VSS, a first reference signal terminal VREF, a light emission control signal terminal EM, a data signal terminal DATA, a first gate signal terminal GATE1, a second gate signal terminal GATE2, a first reset signal terminal RESET1, and a second reset signal terminal RESET2. The first power supply signal terminal VDD is configured to output a first power supply signal vdd to the pixel driving circuit 100. The second power supply signal terminal VSS is configured to output a second power supply signal vss to the pixel driving circuit 100. The potential of the first power supply signal vdd is higher than the potential of the second power supply signal vss. The first reference signal terminal VREF is configured to output a first reference signal vref to the pixel driving circuit 100. The first reference signal vref can be a constant high-level signal, a constant low-level signal, or a clock signal, etc., depending on the actual needs of the circuit. The light emission control signal terminal EM is configured to output a light emission control signal em to the pixel driving circuit 100. A set of shift register units located in the non-display area NDA of the display panel are respectively connected to the light emission control signal terminals EM of different pixel driving circuits 100, so as to provide a set of shifted light emission control signals em to the pixel driving circuits 100 located at different positions on the display panel. The first gate signal terminal GATE1 is configured to output a first gate signal gate1 to the pixel driving circuit 100. A set of shift register units located in the non-display area NDA of the display panel are respectively connected to the first gate signal terminals GATE1 of different pixel driving circuits 100, so as to provide a set of shifted first gate signals gate1 to the pixel driving circuits 100 located at different positions on the display panel. The second gate signal terminal GATE2 is configured to output a second gate signal gate2 to the pixel driving circuit 100. A set of shift register units located in the non-display area NDA of the display panel are respectively connected to the second gate signal terminals GATE2 of different pixel driving circuits 100, so as to provide a set of shifted second gate signals gate2 to the pixel driving circuits 100 located at different positions on the display panel. The first reset signal terminal RESET1 and the second reset signal terminal RESET2 are configured to output a first reset signal reset1 and a second reset signal reset2 to the pixel driving circuit 100, respectively. The first reset signal reset1 and the second reset signal reset2 can be provided in a manner similar to the first gate signal gate1 and the second gate signal gate2. The data signal terminal DATA is configured to output a data signal data to the pixel driving circuit 100.

[0087] The signal terminal connected to the shorting module 400 provided in this application includes a control signal terminal PC, which is configured to output a control signal pc to the shorting module 400. The control signal terminal PC can be connected to the chip of the display panel, or, similar to the first gate signal gate1 and the second gate signal gate2, the control signal terminal PC can be connected to a set of separate shift register units.

[0088] Unless otherwise specified, the transistors used in this application can be bipolar junction transistors (BJTs), thin-film transistors (TFTs), field-effect transistors (FETs), or other devices with similar characteristics. In the embodiments of this disclosure, to distinguish the two terminals of a transistor other than the control terminal, one terminal is referred to as the first terminal and the other as the second terminal.

[0089] In actual operation, when the transistor is a bipolar junction transistor (BJT), the control electrode can be the base, the first electrode can be the collector, and the second electrode can be the emitter; or, the control electrode can be the base, the first electrode can be the emitter, and the second electrode can be the collector.

[0090] In practical operation, when the transistor is a thin-film transistor or a field-effect transistor, the control electrode can be the gate, the first electrode can be the drain, and the second electrode can be the source; or, the control electrode can be the gate, the first electrode can be the source, and the second electrode can be the drain. In the embodiments of this application, the transistor is a thin-film transistor.

[0091] As shown in Figures 2 and 2, in an optional embodiment, the pixel driving circuit 100 includes a driving module 110, a data writing module 120, a compensation module 130, a light emission control module 140, and a reset module 150.

[0092] The driving module 110 is configured to control the first light-emitting unit 210 and the second light-emitting unit 310 to emit light under the control of the data signal data. The data writing module 120 is configured to write the data signal data to the driving module 110. The compensation module 130 is configured to compensate for the data signal data written by the data writing module 120. The light emission control module 140 is configured to control the first light-emitting unit 210 and the second light-emitting unit 310 to emit light under the control of the light emission control signal em. The reset module 150 is configured to reset the pixel driving circuit 100.

[0093] Optionally, the driving module 110 may include a first transistor T1, the first terminal of which is connected to the second node N2, and the second terminal of which is connected to the third node N3. The first transistor T1 includes a top control terminal and a bottom control terminal, wherein the top control terminal is connected to the first node N1, and the bottom control terminal is connected to the second node N2. The first transistor T1 is a driving transistor.

[0094] Optionally, the compensation module 130 may include a second transistor T2 and a third transistor T3. The first terminal of the second transistor T2 is connected to the third node N3, the second terminal of the second transistor T2 is connected to the first node N1, and the control terminal of the second transistor T2 is connected to the first gate signal terminal GATE1. The first terminal of the third transistor T3 is connected to the first reference signal terminal VREF, the second terminal of the third transistor T3 is connected to the second node N2, and the control terminal of the third transistor T3 is connected to the first gate signal terminal GATE1.

[0095] Optionally, the data writing module 120 may include a fourth transistor T4 and a first capacitor C1. The first terminal of the fourth transistor T4 is connected to the data signal terminal DATA, the second terminal of the fourth transistor T4 is connected to the fifth node N5, and the control terminal of the fourth transistor T4 is connected to the second gate signal terminal GATE2. The first terminal of the first capacitor C1 is connected to the fifth node N5, and the second terminal is connected to the first node N1.

[0096] Optionally, the light-emitting control module 140 may include a fifth transistor T5 and a sixth transistor T6. The first terminal of the fifth transistor T5 is connected to the fourth node N4, the second terminal of the fifth transistor T5 is connected to the third node N3, and the control terminal of the fifth transistor T5 is connected to the light-emitting control signal terminal EM. The first terminal of the sixth transistor T6 is connected to the second node N2, the second terminal of the sixth transistor T6 is connected to the second power supply signal terminal VSS, and the control terminal of the sixth transistor T6 is connected to the light-emitting control signal terminal EM. The fifth transistor T5 and the sixth transistor T6 are the light-emitting control transistors.

[0097] Optionally, the reset module 150 may include a seventh transistor T7, an eighth transistor T8, and a ninth transistor T9. The first terminal of the seventh transistor T7 is connected to the first power supply signal terminal VDD, the second terminal of the seventh transistor T7 is connected to the first node N1, and the control terminal of the seventh transistor T7 is connected to the second reset signal terminal RESET2. The first terminal of the eighth transistor T8 is connected to the first power supply signal terminal VDD, the second terminal of the eighth transistor T8 is connected to the fourth node N4, and the control terminal of the eighth transistor T8 is connected to either the first gate signal terminal GATE1 or the second reset signal terminal. The first terminal of the ninth transistor T9 is connected to the first reference signal terminal VREF, the second terminal of the ninth transistor T9 is connected to the fifth node N5, and the control terminal of the ninth transistor T9 is connected to the first reset signal terminal RESET1. A second capacitor C2 is provided between the fifth node N5 and the first reference signal terminal VREF.

[0098] The first light-emitting unit 210 and the second light-emitting unit 310 are disposed between the light-emitting control transistor, i.e., the fifth transistor, and the first power supply signal terminal VDD.

[0099] The shorting module 400 includes a shorting transistor T10, the first electrode of which is connected to the anode of the second light-emitting unit 310, the second electrode of which is connected to the cathode of the second light-emitting unit 310, and the control electrode of which is connected to the control signal terminal PC.

[0100] As shown in Figure 6, Figure 6 is a timing diagram of the circuit shown in Figure 5 in one embodiment. The following description takes the connection between the control electrode of the eighth transistor T8 and the first gate signal terminal GATE1 as an example.

[0101] During time S1, the first reset signal reset1 and the second reset signal reset2 are at high potentials. The seventh transistor T7 and the ninth transistor T9 are turned on, the first power supply signal terminal VDD resets the first node N1, and the first reference signal terminal VREF resets the fifth node N5.

[0102] During period S2, the first reset signal reset1 and the first gate signal gate1 are at high potentials. The first transistor T1, the second transistor T2, the third transistor T3, the eighth transistor T8, and the ninth transistor T9 are turned on, and the first power supply signal VDD resets the fourth node N4. Simultaneously, compensation begins for the first transistor T1 until the potential of the first node N1 changes to the potential of the first reference signal vref plus the threshold voltage Vth of the first transistor T1.

[0103] During period S3, the second gate signal gate2 is at a high potential. The fourth transistor T4 turns on, and the data signal data begins to be written to the fifth node N5 and coupled to the first node N1 through the first capacitor C1. The potential of the first node N1 becomes the potential of the data signal data + the threshold voltage Vth of the first transistor T1.

[0104] During period S4, the light emission control signal em is at a high potential. The fifth transistor T5 and the sixth transistor T6 are turned on, and the first transistor T1 is turned on under the control of the first node N1. The first light emission unit 210 and the second light emission unit 310 begin to emit light.

[0105] The pixel then repeats the above steps to display different frames. For pixels in other rows, each signal is shifted by 1H in the next row to achieve line-by-line scanning.

[0106] When the pixel area of ​​the display panel is in sharing mode, the control signal pc controls the short-circuit transistor T10 to turn off, thereby allowing the first light-emitting unit 210 and the second light-emitting unit 310 to emit light normally. When the pixel area of ​​the display panel is in privacy mode, the control signal pc controls the short-circuit transistor T10 to turn on, short-circuiting the second light-emitting unit 310, causing the first light-emitting unit 210 to emit light normally while the second light-emitting unit 310 does not emit light.

[0107] As shown in Figure 7, which is a timing diagram of the circuit shown in Figure 5 in one embodiment, in this embodiment, a cascaded set of shift register units sends a signal to the second reset signal terminal RESET2 of the pixel driving circuit. The pixel array in the display panel is arranged and operates in a row scanning manner. The second reset signal terminal RESET2 of the pixel driving circuit of adjacent rows can be connected to the same shift register unit, that is, the second reset signal terminal RESET2 of the pixel driving circuit of adjacent rows can share a signal, and this signal is shifted backward by 2H for each row. This can reduce the number of shift register units at the bezel and achieve a narrow bezel. Specifically, as shown in Figure 7, compared with the first reset signal reset1 in Figure 6, this embodiment widens the first reset signal reset1 forward by 1H. Since the second reset signal terminal RESET2 of the pixel driving circuit of adjacent rows can share a signal in this embodiment, one of the second reset signals reset2 of the pixel driving circuit of two adjacent rows is in the H2 time period and the other is in the H1 time period. In this embodiment, H1+H2 is equivalent to the S1 time period mentioned above, and H3 to H5 time periods are equivalent to the S2 to S4 time periods mentioned above, respectively. Their operating principles are basically the same, so they will not be elaborated on here.

[0108] As shown in Figure 8, in an optional embodiment, the pixel driving circuit 100 can also be the 7T1C pixel driving circuit illustrated. The driving transistor of this pixel driving circuit 100 is T1, the data writing transistor is T4, the compensation transistor is T2, the light-emitting control transistors are T5 and T6, and the reset transistors are T7 and T8. The operating logic of this circuit is largely the same as in the above embodiment, so it will not be described in detail here. In this embodiment, the first light-emitting unit 210 and the second light-emitting unit 310 are disposed between the light-emitting control transistor T6 and the second power supply signal terminal VSS. Of course, in other optional embodiments, the pixel driving circuit can also have other structures, such as 8T1C, as long as it can perform normal pixel driving functions.

[0109] As shown in Figures 6 and 7, this application also provides a driving method for a display panel, which includes controlling a shift register unit to output a first reset signal reset1, a second reset signal reset2, a first gate signal gate1, a second gate signal gate2, and a light emission control signal em. The first reset signal reset1 at least covers the second reset signal reset2 and the first gate signal gate1, the first gate signal gate1 lags behind the second reset signal reset2, the second gate signal gate2 lags behind the first gate signal gate1, and the light emission control signal em lags behind the second gate signal gate2.

[0110] In an optional embodiment, as shown in FIG6, the pulse width of the first reset signal reset1 is 2H, the pulse width of the second reset signal reset2 is 1H, the pulse width of the first gate signal gate1 is 1H, the pulse width of the second gate signal gate2 is 1H, and the pulse width of the light emission control signal em is 1H. The first gate signal gate1 lags behind the second reset signal reset2 by a width of 1H, the second gate signal gate2 lags behind the first gate signal gate1 by a width of 1H, and the light emission control signal em lags behind the second gate signal gate2 by a width of 1H.

[0111] In an optional embodiment, as shown in FIG7, the pulse width of the first reset signal reset1 is 3H, the pulse width of the second reset signal reset2 is 1H, the pulse width of the first gate signal gate1 is 1H, the pulse width of the second gate signal gate2 is 1H, and the pulse width of the light emission control signal em is 1H. The first gate signal gate1 lags behind the second reset signal reset2 by a width of 1H, the end edge of the first gate signal gate1 overlaps with the end edge of the first reset signal reset2, and this end edge is a rising edge or a falling edge. The second gate signal gate2 lags behind the first gate signal gate1 by a width of 1H, and the light emission control signal em lags behind the second gate signal gate2 by a width of 1H.

[0112] This application also provides a display device, which includes the display panel described above. In one embodiment, the display device further includes a housing, and the display panel is disposed within the housing. The display device provided in this application embodiment can be, for example, any device with display functionality such as a mobile phone, tablet computer, television, laptop computer, or in-vehicle device.

[0113] It should be noted that the technical solutions or features described in the above embodiments can be combined or supplemented with each other without conflict. The scope of protection of this application is not limited to the precise structures described in the above embodiments and shown in the accompanying drawings; all modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the scope of protection of this application.

Claims

1. A display panel, characterized in that, include: A first light-emitting module is disposed in a first display area. The first light-emitting module includes a first light-emitting unit and a privacy unit. The privacy unit is configured to limit the light emission angle of the first light-emitting unit. A second light-emitting module is disposed in a second display area. The second light-emitting module includes a second light-emitting unit, which is connected in series with the first light-emitting unit. A pixel driving circuit, disposed in the first display area and / or the second display area, is configured to output driving signals for driving the first light-emitting unit and the second light-emitting unit.

2. The display panel according to claim 1, characterized in that, The display panel also includes: The shorting module, connected to the control signal terminal, is configured to selectively short-circuit the second light-emitting unit under the control of the control signal.

3. The display panel according to claim 1, characterized in that, The pixel driving circuit includes a first power signal terminal, a second power signal terminal, and a light-emitting control transistor. The potential of the first power signal terminal is higher than that of the second power signal terminal. The first light-emitting unit and the second light-emitting unit are disposed between the light-emitting control transistor and the first power signal terminal.

4. The display panel according to claim 1, characterized in that, The pixel driving circuit includes a first power signal terminal, a second power signal terminal, and a light-emitting control transistor. The potential of the first power signal terminal is higher than the potential of the second power signal terminal. The first light-emitting unit and the second light-emitting unit are disposed between the light-emitting control transistor and the second power signal terminal.

5. The display panel according to claim 2, characterized in that, The shorting module includes a shorting transistor, the first electrode of which is connected to the anode of the second light-emitting unit, the second electrode of which is connected to the cathode of the second light-emitting unit, and the control electrode of which is connected to a control signal terminal.

6. The display panel according to claim 5, characterized in that, The control signal terminal is connected to the chip, and the chip is configured to: When the display panel is adjusted to privacy mode, the chip sends a control signal to turn on the short-circuit transistor, causing the second light-emitting unit to short-circuit. When the display panel is adjusted to the sharing mode, the chip sends a control signal to control the shorting transistor to disconnect, so that the second light-emitting unit can emit light normally.

7. The display panel according to claim 5, characterized in that, The control signal terminal is connected to a shift register module, which is configured as follows: When the display panel is adjusted to privacy mode, the shift register module sends a control signal to control the short-circuit transistor to turn on, causing the second light-emitting unit to short-circuit. When the display panel is adjusted to the sharing mode, the shift register module sends a control signal to control the shorting transistor to disconnect, so that the second light-emitting unit can emit light normally.

8. The display panel according to claim 1, characterized in that, The pixel driving circuit includes: The driving module is configured to control the first light-emitting unit and the second light-emitting unit to emit light under the control of a data signal; The data writing module is configured to write data signals to the driving module; The compensation module is configured to compensate the data signal written by the data writing module; The light emission control module is configured to control the first light emission unit and the second light emission unit to emit light under the control of the light emission control signal; The reset module is configured to reset the pixel driving circuit.

9. The display panel according to claim 8, characterized in that, The driving module includes a first transistor, the first terminal of the first transistor is connected to a second node, the second terminal of the first transistor is connected to a third node, and the first transistor includes a top control terminal and a bottom control terminal, the top control terminal is connected to the first node, and the bottom control terminal is connected to the second node. The compensation module includes a second transistor and a third transistor; The first terminal of the second transistor is connected to the third node, the second terminal of the second transistor is connected to the first node, and the control terminal of the second transistor is connected to the first gate signal terminal; the first terminal of the third transistor is connected to the first reference signal terminal, the second terminal of the third transistor is connected to the second node, and the control terminal of the third transistor is connected to the first gate signal terminal. The data writing module includes a fourth transistor and a first capacitor. The first electrode of the fourth transistor is connected to the data signal terminal, the second electrode of the fourth transistor is connected to the fifth node, and the control electrode of the fourth transistor is connected to the second gate signal terminal. The first terminal of the first capacitor is connected to the fifth node, and the second terminal is connected to the first node.

10. The display panel according to claim 9, characterized in that, The light-emitting control module includes a fifth transistor and a sixth transistor; The first electrode of the fifth transistor is connected to the fourth node, the second electrode of the fifth transistor is connected to the third node, and the control electrode of the fifth transistor is connected to the light emission control signal terminal. The first electrode of the sixth transistor is connected to the second node, the second electrode of the sixth transistor is connected to the second power signal terminal, and the control electrode of the sixth transistor is connected to the light emission control signal terminal.

11. The display panel according to claim 10, characterized in that, The reset module includes a seventh transistor, an eighth transistor, and a ninth transistor; The first terminal of the seventh transistor is connected to the first power signal terminal, the second terminal of the seventh transistor is connected to the first node, and the control terminal of the seventh transistor is connected to the second reset signal terminal. The first terminal of the eighth transistor is connected to the first power supply signal terminal, the second terminal of the eighth transistor is connected to the fourth node, and the control terminal of the eighth transistor is connected to the first gate signal terminal or the second reset signal terminal. The first terminal of the ninth transistor is connected to the first reference signal terminal, the second terminal of the ninth transistor is connected to the fifth node, and the control terminal of the ninth transistor is connected to the first reset signal terminal. A second capacitor is provided between the fifth node and the first reference signal terminal.

12. The display panel according to claim 2, characterized in that, The first light-emitting module includes a third light-emitting unit connected in series with the first light-emitting unit, and the third light-emitting unit is stacked with the first light-emitting unit.

13. The display panel according to claim 12, characterized in that, The second light-emitting module includes a fourth light-emitting unit connected in series with the second light-emitting unit, and the fourth light-emitting unit and the second light-emitting unit are stacked together.

14. The display panel according to claim 13, characterized in that, The short-circuit module is configured to selectively short-circuit the second light-emitting unit and the fourth light-emitting unit together under the control of a control signal.

15. A driving method for a display panel, characterized in that, For driving the display panel as described in any one of claims 1-14, comprising: The control shift register unit outputs a first reset signal, a second reset signal, a first gate signal, a second gate signal, and a light emission control signal; wherein, the first reset signal at least covers the second reset signal and the first gate signal, the first gate signal lags behind the second reset signal, the second gate signal lags behind the first gate signal, and the light emission control signal lags behind the second gate signal.

16. The driving method for a display panel according to claim 15, characterized in that, The pulse width of the first reset signal is 2H, the pulse width of the second reset signal is 1H, the pulse width of the first gate signal is 1H, the pulse width of the second gate signal is 1H, and the pulse width of the light emission control signal is 1H; the first gate signal lags behind the second reset signal 1H, the second gate signal lags behind the first gate signal 1H, and the light emission control signal lags behind the second gate signal 1H.

17. The driving method for a display panel according to claim 15, characterized in that, The pulse width of the first reset signal is 3H, the pulse width of the second reset signal is 1H, the pulse width of the first gate signal is 1H, the pulse width of the second gate signal is 1H, and the pulse width of the light emission control signal is 1H; the first gate signal lags behind the second reset signal 1H, the end edge of the first gate signal overlaps with the end edge of the first reset signal, and the end edge is either a rising edge or a falling edge; the second gate signal lags behind the first gate signal 1H, and the light emission control signal lags behind the second gate signal 1H.

18. A display device, characterized in that, The display device includes a display panel as described in any one of claims 1-14.

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