Design support method, program, and information processing device

Abstract

The present invention provides a design support method for supporting physical design of a semiconductor integrated circuit by deriving a process for performing the physical design. The method involves causing a computer to execute processing of: acquiring a performance index required for the semiconductor integrated circuit; acquiring a register-transfer-level code generated according to the performance index; and deriving, on the basis of the performance index and the code which are acquired, a circuit design process for performing the physical design.

Description

Design Support Method, Program, and Information Processing Apparatus 【0001】 The present invention relates to a design support method, a program, and an information processing apparatus. This application claims priority based on U.S. Application No. 63 / 727,574 filed on December 3, 2024, and incorporates by reference all the descriptions in the U.S. application. 【0002】 Conventionally, general-purpose semiconductors that can be mounted on various products have been mass-produced. General-purpose semiconductors include, for example, CPUs (Central Processing Units) mounted on personal computers. General-purpose semiconductors based on the conventional von Neumann architecture were designed to have high sequential processing performance. According to Moore's law, it is considered that the production cost of semiconductors can be reduced by increasing the integration density. Therefore, the main goal of conventional semiconductors has been to increase the production volume of general-purpose semiconductors and reduce the production cost. However, a large amount of equipment investment is required to increase the production volume of semiconductors. For this reason, the fabless production method in which the operator mainly responsible for semiconductor design outsources semiconductor production to an external operator has become the mainstream. Patent Document 1 discloses a technique related to lithography-based pattern optimization. 【0003】 U.S. Patent No. 11,449,659 【0004】 However, in the technique disclosed in Patent Document 1, no consideration is given to deriving a circuit design process for physical design of a semiconductor integrated circuit based on the obtained performance指标 and the code at the register transfer level. 【0005】 An object of the present disclosure is to provide a design support method or the like that can derive a circuit design process for physical design of a semiconductor integrated circuit based on the obtained performance指标 and the code at the register transfer level. 【0006】A design support method according to one aspect of the present disclosure is a design support method that supports physical design of a semiconductor integrated circuit by deriving a process for performing the physical design of the semiconductor integrated circuit, wherein the method involves obtaining performance indicators required for the semiconductor integrated circuit, obtaining register transfer level code generated according to the performance indicators, and causing a computer to execute a process to derive a circuit design process for performing the physical design based on the obtained performance indicators and the code. 【0007】 A program according to one aspect of the present disclosure is a program that causes a computer that performs processing to support the physical design of a semiconductor integrated circuit to execute processing by deriving a process for performing the physical design of the semiconductor integrated circuit, the program obtains performance indicators required for the semiconductor integrated circuit, obtains register transfer level code generated according to the performance indicators, and executes processing to derive a circuit design process for performing the physical design based on the obtained performance indicators and the code. 【0008】 An information processing apparatus according to one aspect of the present disclosure is an information processing apparatus comprising a control unit that performs processing to support physical design by deriving a process for performing physical design of a semiconductor integrated circuit, wherein the control unit acquires performance indicators required for the semiconductor integrated circuit, acquires register transfer level code generated according to the performance indicators, and derives a circuit design process for performing the physical design based on the acquired performance indicators and the code. 【0009】 According to one aspect of this disclosure, a design support method can be provided that derives a circuit design process for performing physical design of a semiconductor integrated circuit based on acquired performance indicators and codes at the register transfer level. 【0010】This is a schematic diagram illustrating the overview of the semiconductor design support system according to Embodiment 1. This is a block diagram showing the configuration of the information processing device. This is a functional block diagram illustrating the functional units included in the control unit of the information processing device. This is an explanatory diagram showing a change in the steps in the process. This is a flowchart illustrating the processing procedure by the control unit of the information processing device. This is a flowchart illustrating the processing procedure by the control unit of the information processing device according to Embodiment 2 (multiple PPAs). This is an explanatory diagram showing a change in the steps in the process. 【0011】 (Embodiment 1) Hereinafter, embodiments will be described based on the drawings. Figure 1 is a schematic diagram illustrating the overview of the semiconductor design support system S according to Embodiment 1. Figure 2 is a block diagram showing the configuration of the information processing device 1. The semiconductor design support system S is configured with an information processing device 1, which functions as a semiconductor design support server, as the main device. The information processing device 1 (semiconductor design support server) is connected to a terminal device 2 (designer PC) used by a semiconductor integrated circuit designer, for example, via a network such as the Internet or an intranet, so as to be able to communicate. 【0012】 As will be explained in detail later, the terminal device 2 (designer's PC) transmits logic design data such as register transfer level (RTL), performance indicators (PPA: Power / Performance / Area), and timing constraints (SDC: Synopsys Design Constraints) for the semiconductor integrated circuit that is the target of physical design to the information processing device 1 (semiconductor design support server). Based on the logic design data acquired from the terminal device 2, the information processing device 1 outputs a process (physical design flow) for performing physical design of the semiconductor integrated circuit. This process (physical design flow) is derived by the AI ​​analysis engine (process derivation model 101, process database 121, processing database 122, and performance indicator estimation model 102) implemented in the information processing device 1, and corresponds to a circuit design process (optimal process) optimized for physical design. As will be explained in detail later, the circuit design process includes multiple steps, and these steps are arranged in chronological order according to the processing order, corresponding to a physical design flow. 【0013】 A designer using terminal device 2 performs the physical design of a semiconductor integrated circuit using the circuit design process output from information processing device 1, and outputs the result of applying the circuit design process to the physical design (application result data) to information processing device 1. This enables efficient support for the physical design of semiconductor integrated circuits. Information processing device 1 can improve the accuracy of circuit design process derivation by registering or performing additional learning on all data acquired, generated, and derived up to the point of deriving the circuit design process, including the application result data finally acquired from terminal device 2, into the AI ​​analysis engine. 【0014】 The information processing device 1 is a computer capable of various information processing and information transmission / reception, such as a server device or a personal computer. The server device includes not only a single server device but also a cloud server device or a virtual server device composed of multiple computers. The information processing device 1 includes a control unit 11, a storage unit 12, a communication unit 13, and an input / output interface 14. 【0015】 The control unit 11 has one or more arithmetic processing units equipped with timing functions, such as a CPU (Central Processing Unit), an MPU (Micro-Processing Unit), and a GPU (Graphics Processing Unit), and performs various information processing, control processing, etc., by reading and executing a program P (program product) stored in the storage unit 12. Furthermore, the control unit 11 may include a semiconductor chip (AI chip) specialized for AI processing such as machine learning and deep learning. 【0016】The storage unit 12 includes volatile storage areas such as SRAM (Static Random Access Memory), DRAM (Dynamic Random Access Memory), and flash memory, as well as non-volatile storage areas such as EEPROM or hard disk. The storage unit 12 pre-stores programs P (program products) and data referenced during processing, and also stores various data, including intermediate data generated during processing. The programs P (program products) stored in the storage unit 12 may be programs P (program products) read from a recording medium M that the information processing device 1 can read. Alternatively, programs P (program products) may be downloaded from an external computer (not shown) connected to a communication network (not shown) and stored in the storage unit 12. As will be described in detail later, the storage unit 12 stores actual files such as a process database 121 and a processing database 122. 【0017】 The communication unit 13 is a communication module or communication interface for communicating with an information terminal T, etc., via wired or wireless connection such as Ethernet (registered trademark), and is, for example, a narrow-area wireless communication module such as Wi-Fi (registered trademark) or Bluetooth (registered trademark), or a wide-area wireless communication module such as 4G or 5G. The control unit 11 communicates with a terminal device 2 such as a personal computer used by a designer, etc., via the communication unit 13, for example, through an external network such as the Internet or a LAN, and may also communicate with an external server (AI cloud server) on which LLM, etc., is implemented. 【0018】 The input / output interface 14 includes terminals such as USB or serial cables, to which a display unit such as a monitor or an input / output device such as a keyboard is connected. 【0019】Figure 3 is a functional block diagram illustrating the functional units included in the control unit 11 of the information processing device 1. The control unit 11 of the information processing device 1 functions as the acquisition unit 111, target design generation unit 112, prototype process derivation unit 113, similar process derivation unit 114, candidate process derivation unit 115, metrics evaluation unit 116, suitability determination unit 117, and output unit 118, etc., by executing the program P stored in the storage unit 12. The control unit 11 of the information processing device 1 functions as an AI analysis engine (learning model) including the process derivation model 101 and the performance indicator estimation model 102, etc., by reading the actual files of the process derivation model 101 and the performance indicator estimation model 102 stored in the storage unit 12. 【0020】 The AI ​​analysis engine (learning model) that functions as a process derivation model 101 or a performance indicator estimation model 102, etc., is not limited to being implemented in the information processing device 1, but may also be implemented in a cloud server (AI cloud server), for example, and may consist of a large-scale language model (LLM) that has been fine-tuned with various design information (corpus) related to semiconductor integrated circuits. In this case, the information processing device 1 that functions as a semiconductor design support server may communicate with the AI ​​cloud server via an API (Application Programming Interface) and perform various processing using the large-scale language model implemented in the AI ​​cloud server. 【0021】The acquisition unit 111 acquires logic design data, including performance indicators (PPA: Power / Performance / Area) required for the semiconductor integrated circuit, register transfer level codes (RTL: Register Transfer Level) generated according to the performance indicators (PPA), and timing constraints (SDC: Synopsys Design Constraints), from, for example, the terminal device 2 (designer PC) of a designer performing the logic design of a semiconductor integrated circuit. Alternatively, the acquisition unit 111 may acquire a netlist synthesized using the register transfer level codes (RTL), etc., as logic design data. The acquisition unit 111 stores this acquired logic design data in the storage unit 12 and outputs it to a functional unit that handles subsequent processes, such as the target design generation unit 112. 【0022】 The target design generation unit 112 generates the target design (design data) by, for example, packaging the register transfer level code (RTL), performance metrics (PPA), and timing constraints (SDC). Alternatively, the target design generation unit 112 may generate the target design (design data) by performing a provisional logic synthesis (provisional logic synthesis) using these codes (RTL), etc., and generating a netlist. 【0023】 The prototype process derivation unit 113 uses a commercially available general-purpose EDA (Electronic Design Automation) tool, for example, to derive a physical design process (physical design flow) for performing physical design based on the generated target design (logic design data) as a prototype process. The prototype process derived in this way using a general-purpose EDA tool becomes the process (flow) to be improved in subsequent processing. 【0024】The similar process derivation unit 114 searches for designs similar to the generated target design (similar designs) and derives the physical design processes (similar processes) applied to the extracted similar designs. In this case, the similar process derivation unit 114 may derive similar designs and similar processes using a process derivation model 101 composed of, for example, a large-scale language model (LLM), and a process database 121 composed of RAG (Retrieval-Augmented Generation). 【0025】 The process derivation model 101 may be a LLM that has already learned general-purpose items such as natural language interpretation, and may be fine-tuned using self-supervised learning or the like based on various design information (corpus) related to semiconductor integrated circuits. The process database 121 stores sentence embedding vectors or image embedding vectors that are vectorized versions of various technical information such as design information, test information, manufacturing information, evaluation information, and implementation information for a large number of diverse semiconductor integrated circuits that have been designed and manufactured in the past. In this case, the design information includes HDL code (source file), RTL code (source file), netlist, circuit diagram, and design data in GDSII (Graphic Data System 2) format for each of the diverse semiconductor integrated circuits, and various information related to the physical design process (circuit design process) for physical design is associated with this design information. That is, the design information stored in the process database 121 includes the physical design process. The process database 121 outputs search results in response to a search process (query) from the process derivation model 101. 【0026】 The similar process derivation unit 114 inputs the target design into the process derivation model 101 and may also input fixed prompts, such as searching for similar designs. The process derivation model 101 interprets the various information contained in the input target design, for example by vectorizing it, and derives similar designs and similar processes that are similar to the target design by performing a vector search using cosine similarity, etc., against the process database 121. 【0027】The candidate process derivation unit 115 identifies the similarities and differences between the derived original process and similar processes, and based on these similarities and differences, identifies the processes (in-process steps) to be changed in the original process. The candidate process derivation unit 115 searches the process database 122, which contains a large number of processes (in-process steps) and programs, modules, or tools used to execute those processes, for the identified processes (in-process steps) to be changed, and extracts the modified processes (in-process steps) and tools, etc. 【0028】 The processing database 122 stores a large variety of processes (in-process steps) used in the physical design process, as well as tools used in those processes. The candidate process derivation unit 115 derives candidate processes that improve upon the prototype process by replacing the processes (in-process steps) and tools extracted in this way with the processes (in-process steps) to be changed in the prototype process, or by adding them to the prototype process. 【0029】 The candidate process derivation unit 115, in performing the derivation process, may input, for example, the target design, prototype process, similar designs, and similar processes into the process derivation model 101, as well as input fixed prompts, for example, to extract the processes (in-process steps) to be changed. The process derivation model 101 may interpret the input target design, prototype process, similar designs, and similar processes by, for example, vectorizing them, and derive the processes (in-process steps) to be changed based on the similarities and differences between the prototype process and the similar processes. Furthermore, the process derivation model 101 may derive the processes (in-process steps) to be changed based on the differences (design differences) and similarities between the target design and similar designs. The process derivation model 101 may use the derived processes (in-process steps) to search the process database 122 and obtain the modified processes (in-process steps) and tools, etc. The candidate process derivation unit 115 may derive an improved candidate process from the original process by applying the modified processes (in-process steps) and tools output from the process derivation model 101 to the original process by replacing, adding, or deleting unnecessary processes. 【0030】 The metrics evaluation unit 116 derives performance indicators (predicted performance indicators) expected when physical design is performed using the prototype process and performance indicators (predicted performance indicators) expected when physical design is performed using the candidate process. In deriving the predicted performance indicators, the metrics evaluation unit 116 may use a performance indicator estimation model 102 that estimates performance indicators based on input of the physical design process and the design (logic design data). 【0031】 The performance indicator estimation model 102 takes a physical design process and a design (logic design data) as input, estimates the performance indicators of a semiconductor integrated circuit when a physical design corresponding to the design is performed based on the physical design process, and outputs the estimated performance indicators (predicted performance indicators). The performance indicator estimation model 102 may be composed of a large-scale language model (LLM) trained by self-supervised learning using design information consisting of a combination of logic design data, a physical design process, and performance indicators of a semiconductor integrated circuit manufactured in the physical design process. Alternatively, the performance indicator estimation model 102 may be composed of a simulator that performs a simulation based on the input physical design process and design to estimate performance indicators. 【0032】The metrics evaluation unit 116 compares the predicted performance index of the derived prototype process with the predicted performance index of the candidate process and determines whether the predicted performance index of the candidate process is superior to the predicted performance index of the prototype process, that is, whether each index (PPA) included in the performance index is higher. If the predicted performance index of the candidate process is less than or equal to the predicted performance index of the prototype process, that is, if it is not higher, the metrics evaluation unit 116 may generate an iteration (repeated processing) to perform the processing again in the candidate process derivation unit 115. When the candidate process derivation unit 115 performs reprocessing due to the generation of an iteration, it may determine the processing to be changed (in-process steps) to be different from the previously derived candidate process and derive the candidate process again. If the predicted performance index of the candidate process is higher than the predicted performance index of the prototype process, the metrics evaluation unit 116 may determine that the performance index has been improved. 【0033】 The conformity determination unit 117 is a functional unit that evaluates or determines the appropriateness of a candidate process, similar to the metrics evaluation unit 116. In this embodiment, it is located after the metrics evaluation unit 116, but is not limited to this, and may be an earlier process of the metrics evaluation unit 116 or process the metric evaluation unit 116 in parallel. The conformity determination unit 117 determines whether it is possible to select a process (in-process step) or tool that has been changed from the original process in the candidate process, that is, it determines the conformity (tool selectability) to the process (in-process step, tool used in that step) that has been changed in the candidate process. 【0034】The conformity determination unit 117 may, for example, determine the selectability of the tool by referring to a prohibited table pre-stored in the storage unit 12. The prohibited table is a table that defines prohibited combinations of processes (in-process steps, tools used in those steps) in multiple processes (in-process steps) included in the physical design process (physical design free). The conformity determination unit 117 refers to the prohibited table, expands all combinations of processes (in-process steps) or tools that are replaced or added in the candidate process and other processes (in-process steps), and determines whether any of the combinations fall under any of the combinations (prohibited combinations) defined in the prohibited table. 【0035】 The conformance determination unit 117 may generate an iteration (repeated processing) to perform the processing in the candidate process derivation unit 115 again if the combination of processing in the candidate process matches any of the combinations defined in the prohibition table. When the candidate process derivation unit 115 performs reprocessing due to the generation of an iteration, it may determine the processing to be changed (in-process steps) to be different from the previously derived candidate process and derive the candidate process again. If the combination of processing in the candidate process does not match any of the combinations defined in the prohibition table, the conformance determination unit 117 derives the candidate process as a circuit design process (flow) optimized for physical design. 【0036】The output unit 118 outputs the derived circuit design process to, for example, the terminal device 2 (designer's PC). This allows the designer performing the physical design to be provided with an appropriate physical design process. Furthermore, the output unit 118 may register the derived circuit design process and intermediate data such as the target design, candidate processes, and metrics evaluation results for the candidate processes acquired or generated during the process of deriving the circuit design process in the process database 121. Furthermore, if result data obtained when the circuit design process is applied to the physical design is transmitted from the terminal device 2 (designer's PC) to the information processing device 1 and fed back, this result data may also be registered in the process database 121 in association with information about the circuit design process, or additionally used to train the process derivation model 101. This result data may include, for example, the processing time, required resources, and final performance indicator (PPA) when the circuit design process is applied to the physical design. 【0037】 In this embodiment, the process derivation model 101 and the performance indicator estimation model 102 are described as separate instances of LLM, etc., but are not limited to this. The process derivation model 101 and the performance indicator estimation model 102 may be implemented as a single instance of LLM, etc. Also, the process database 121, processing database 122, and prohibition table have been described as separate repositories, etc., but are not limited to this. The various content data included in the process database 121, processing database 122, and prohibition table may be stored in a single vector database such as RAG. Thus, the AI ​​analysis engine environment in the semiconductor design support system S may be composed of an LLM and RAG, etc., that comprehensively include the necessary processing and data. 【0038】Figure 4 is an explanatory diagram showing the changes in the steps of the process. In this explanatory diagram, the process derivation model 101 explains the outline of the process of improving from the prototype process to the candidate process, and corresponds to the process by the candidate process derivation unit 115 described above. The physical design process (prototype process) derived using a general-purpose EDA tool based on register transfer level code (RTL) or netlist, etc., is shown, for example, by multiple steps (steps within the physical design process) included in the overall main process of the physical design. 【0039】 The steps of the main process (processing within the main process) include, for example, logic synthesis, equivalence verification, DFT (design for testability), placement and routing, RC extraction, STA (Static Timing Analysis), Irdrop / EM, and physical verification, and each step is executed in this order. Furthermore, the physical design process (prototype process) includes sub-steps (sub-processing) for each step of the main process, forming a hierarchical structure of main and sub-processes. In this embodiment, the steps of the placement and routing process (steps within the placement and routing process), which is a sub-process, are the subject of modification. 【0040】 In the prototype process, the steps within the placement and routing process include, for example, floor planning, cell placement, CTS (Cloud Testing Service), Post CTS opt, routing, Post route opt, and Chip Finish, with each step executed in this order. These prototype processes can be derived based on logic design data (RTL SDC PAA metrics, etc.) using, for example, commercially available general-purpose EDA tools. 【0041】The process derivation model 101 (AI analysis engine) identifies the steps (processes and tools) to be changed in the prototype process by searching the process database 121 and the processing database 122 (Opentool database) based on logic design data (RTL SDC PAA metrics, etc.) or design data such as a netlist obtained by provisional logic synthesis of RTL. The processing database 122 stores modules for executing various steps (processes and tools), such as multiple floor plans (A, B), cell placement (A, B, C), CTS (A, B), routing (A, B), routing repair (A, B), Post route opt (A, B), or SI / EM repair (A, B), with different processing content. The process derivation model 101 (AI analysis engine) may derive one or more candidate processes by replacing (program changing) or adding the steps (processes and tools) identified as targets for change in the prototype process, and then derive the most suitable candidate process from among the derived candidate processes as the circuit design process. In this embodiment, the process derivation model 101 modifies the program by replacing the Post CTS opt step with the Post CTS opt A step, and further derives an improved candidate process by adding the wiring repair B step after the wiring step. 【0042】 Figure 5 is a flowchart illustrating the processing procedure performed by the control unit 11 of the information processing device 1. The control unit 11 of the information processing device 1 receives, for example, operator input from the terminal device 2 (designer PC) or operator input via a keyboard connected to the input / output I / F 14, and performs the following processing based on the received operation. 【0043】 The control unit 11 of the information processing device 1 acquires code and performance indicators at the register transfer level (S101). The control unit 11 of the information processing device 1 acquires logic design data such as code (RTL), performance indicators (PAA), and timing constraints (SDC) at the register transfer level of the semiconductor integrated circuit that is the target of physical design, from the terminal device 2 (designer PC). 【0044】The control unit 11 of the information processing apparatus 1 generates a target design to be subject to physical design (S102). The control unit 11 of the information processing apparatus 1 generates a target design (design data) to be subject to physical design by packaging logic design data such as code (RTL) at the acquired register transfer level, or by temporarily synthesizing the code (RTL) or the like to generate a netlist. 【0045】 The control unit 11 of the information processing apparatus 1 derives a prototype process (S103). The control unit 11 of the information processing apparatus 1 derives, as a prototype process, the physical design process acquired by using, for example, a general-purpose EDA tool based on the generated target design (design data). 【0046】 The control unit 11 of the information processing apparatus 1 derives a similar process (S104). The control unit 11 of the information processing apparatus 1 uses, for example, a process derivation model 101 configured by an LLM or the like and a process database 121 configured by a RAG (vector database) or the like to derive a similar design similar to the target design (design data) and a similar process that is a physical design process applied to the similar design. 【0047】 The control unit 11 of the information processing apparatus 1 derives candidate processes by selecting tools used in the processes (S105). The control unit 11 of the information processing apparatus 1 derives candidate processes obtained by changing the processing (steps within the process) included in the prototype process based on the generated or derived target design (design data), prototype process, similar design, and similar process. The control unit 11 of the information processing apparatus 1 derives, for example, the differences (process differences) and common points (process common points) between the prototype process and the similar process, and the differences (design differences) and common points (design common points) between the target design and the similar design. Then, the control unit 11 of the information processing apparatus 1 may determine the processing (steps within the process) to be changed in the prototype process and the processing (steps within the process) after the change based on these process differences, process common points, design differences, and design common points. The control unit 11 of the information processing apparatus 1 may use the process derivation model 101 and the processing database 122 as described above when deriving the candidate processes. 【0048】 The control unit 11 of the information processing apparatus 1 executes a metrics evaluation for the prototype process and the candidate process (S106). As described above, the control unit 11 of the information processing apparatus 1 uses the performance index estimation model 102 to derive the performance index (predicted performance index) expected when each of the prototype process and the candidate process is used, thereby executing a metrics evaluation for the prototype process and the candidate process. 【0049】 The control unit 11 of the information processing apparatus 1 determines whether the metrics of the candidate process have been improved (S107). The control unit 11 of the information processing apparatus 1 compares the derived predicted performance index of the prototype process with the predicted performance index of the candidate process, and determines whether the metrics of the candidate process have been improved, that is, whether the predicted performance index of the candidate process is superior to the predicted performance index of the prototype process. 【0050】 If it is determined that the metrics have not been improved (S107: NO), the control unit 11 of the information processing apparatus 1 performs a loop process to execute the process from S105 again. When deriving the candidate process again, the control unit 11 of the information processing apparatus 1 derives a candidate process different from the candidate process derived until the previous time by varying the process to be changed (steps within the process) or the tool to be used. 【0051】 If it is determined that the metrics have been improved (S107: YES), the control unit 11 of the information processing apparatus 1 determines whether the tool included in the candidate process can be selected (S108). The control unit 11 of the information processing apparatus 1 identifies the process (steps within the process) or tool changed from the prototype process in the candidate process for which it is determined that the metrics improvement has been implemented, and determines the selectability of the process (step, tool) from the perspective of the appropriateness of the combination of the changed process and other processes. 【0052】The control unit 11 of the information processing device 1 determines the selectability of the tool by, for example, referring to a prohibited table pre-stored in the storage unit 12. The control unit 11 of the information processing device 1 may determine that the selectability exists if the combination of processing (step, tool) in the candidate process does not fall under any combination defined as prohibited in the prohibited table, and may determine that the selectability is insufficient if it falls under any combination defined as prohibited. 【0053】 If it is determined that a tool cannot be selected (S108: NO), the control unit 11 of the information processing device 1 performs loop processing to execute the process from S105 again. If it is determined that a tool cannot be selected, that is, that the possibility of selection is insufficient, the control unit 11 of the information processing device 1 performs loop processing to execute the process from S105 again, and repeats the process of deriving candidate processes. When deriving candidate processes again, the control unit 11 of the information processing device 1 derives different candidate processes from those derived previously by changing the process to be changed (steps within the process) or the tool used. 【0054】 If it is determined that a tool can be selected (S108: YES), the control unit 11 of the information processing device 1 derives a candidate process as a circuit design process (S109). If it is determined that a tool can be selected, that is, that the possibility of selection is present, the control unit 11 of the information processing device 1 derives the candidate process with the possibility of selection as a circuit design process and outputs the circuit design process to the terminal device 2 (designer PC), for example. Alternatively, the control unit 11 of the information processing device 1 may output the derived circuit design process to a display or the like via the input / output I / F 14. 【0055】The control unit 11 of the information processing device 1 acquires the results of applying the circuit design process to the actual design (S110). The control unit 11 of the information processing device 1 acquires information regarding the application results from terminal devices 2, etc., used by the designer who performed the physical design, when the outputted circuit design process is applied to the actual design, i.e., used in physical design and tapeped out, and the design data in GDSII (Graphic Data System 2) format is provided to a semiconductor foundry for manufacturing. The information regarding the application results may include, for example, the processing time when the circuit design process was applied to the physical design, the resources required, and the final performance indicator (PPA). 【0056】 The control unit 11 of the information processing device 1 registers the circuit design process and application results, etc., in the process database 121 (S111). The control unit 11 of the information processing device 1 registers the circuit design process, all intermediate data acquired, generated, or derived in the process of deriving the circuit design process, and the application results, etc., of applying the circuit design process to the actual design in the process database 121. 【0057】According to this embodiment, the information processing device 1 acquires performance indicators (PPA: Performance / Power / Area) that define the functional requirements specifications of a semiconductor integrated circuit, and register transfer level codes. The performance indicators (PPA) define the processing performance, power consumption, and mounting area on the silicon die in the functional requirements specifications of a semiconductor integrated circuit. The register transfer level codes are written in, for example, HDL (Hardware Description Language) or C++, and include RTL (Register Transfer Level), SDC (Synopsys Design Constraints), or a netlist obtained by logic synthesis of the RTL. These performance indicators (PPA) and codes (RTL, etc.) correspond to logic design data in the design process of a semiconductor integrated circuit. Based on the input performance indicators (PPA) and codes (RTL, etc.), the information processing device 1 derives a optimized circuit design process for performing the physical design of the semiconductor integrated circuit, and outputs the circuit design process to, for example, a terminal device 2 used by a physical designer performing the physical design of a semiconductor integrated circuit. This allows us to provide physical designers with supportive information for carrying out physical design, thereby improving or ensuring the efficiency, accuracy, and quality of physical design. 【0058】According to this embodiment, the information processing device 1 defines a target design to be physical designed based on the input performance indicators (PPA) and codes (RTL, etc.). That is, the target design is data consisting of a combination of the input performance indicators (PPA) and codes (RTL, etc.), and corresponds to logic design data (logic design data). Alternatively, the information processing device 1 may derive a circuit diagram, for example using circuit symbols, as the target design to be physical designed from a netlist. The information processing device 1 derives the target design by inputting the defined or derived target design into, for example, a commercially available general-purpose EDA tool, and obtaining the prototype process which is the output result of the general-purpose EDA tool. Furthermore, the information processing device 1 searches a process DB in which designs (logic design data) and processes (physical design processes) are associated, extracts designs similar to the derived target design (similar designs), and derives the processes (similar processes) of the extracted similar designs. The information processing device 1 derives the differences (design differences) between the target design and similar designs, and based on these design differences, modifies the processes (in-process steps) included in the prototype process derived using a general-purpose EDA tool by adding, replacing, or deleting them. In this case, the information processing device 1 may also consider not only the differences (design differences) between the target design and similar designs, but also the similarities (design similarities) when modifying the in-process steps. This allows the information processing device 1 to derive a more efficient and optimized circuit design process (physical design flow) for the target design (logic design data) that is the subject of physical design, compared to a general process (physical design flow) output by, for example, a commercially available general-purpose EDA tool, and provide it to the physical designer to support physical design. 【0059】According to this embodiment, the storage unit 12 of the information processing device 1 stores a processing database 122 (Open_Tool_DB) in which a plurality of processes (steps) used in the physical design process are registered. The processing database 122 (Open_Tool_DB) stores programs, modules, or tools corresponding to the plurality of processes (steps) used in the physical design process. By using the processing database 122, the information processing device 1 can apply tools, etc., corresponding to the steps to be changed, and efficiently derive the circuit design process. 【0060】According to this embodiment, the information processing device 1 has a performance index estimation model 102 implemented that estimates predictive performance indices for a semiconductor integrated circuit designed by a physical design process when a design (logic design data) and a process for performing physical design for the design (physical design process) are input to the information processing device 1. The performance index estimation model 102 may be composed of a large-scale language model (LLM) learned by self-supervised learning using design information consisting of a combination of logic design data, a physical design process, and performance indices of a semiconductor integrated circuit manufactured by the physical design process. By using the performance index estimation model 102, performance index metrics can be evaluated. The information processing device 1 inputs a provisionally derived candidate process based on the target design (PAA + RTL) into the performance index estimation model 102 along with the target design, thereby obtaining the predictive performance indices (predictive performance indices of the candidate process) estimated by the performance index estimation model 102. The information processing device 1 inputs the prototype process derived using a general-purpose EDA tool based on the target design (PAA + RTL) into the performance indicator estimation model 102 along with the target design, thereby obtaining the predicted performance indicator (predicted performance indicator of the prototype process) estimated by the performance indicator estimation model 102. The information processing device 1 compares the predicted performance indicator of the candidate process with the predicted performance indicator of the prototype process. If the predicted performance indicator of the candidate process is superior to the predicted performance indicator of the prototype process, that is, if the performance indicator (PPA) when physically designed in the candidate process is higher than the performance indicator (PPA) when physically designed in the prototype process, the information processing device 1 derives the candidate process as the circuit design process. If the performance indicator (PPA) when physically designed in the candidate process is less than or equal to the performance indicator (PPA) when physically designed in the prototype process, that is, if no improvement in the performance indicator is expected in the candidate process compared to the prototype process, the information processing device 1 repeats the process of deriving the candidate process by changing the processes (in-process steps) included in the prototype process. In this way, based on the performance metric evaluation, it is possible to derive a candidate process from among multiple candidate processes that is expected to improve performance metrics as the circuit design process, and the reliability of the derived circuit design process can be guaranteed. 【0061】According to this embodiment, the information processing device 1, in verifying the feasibility of a provisionally derived candidate process based on the target design (PAA + RTL), performs a suitability determination of the modified process (tool) in the candidate process relative to the original process. At this time, the storage unit 12 of the information processing device 1 may store a prohibition table that defines prohibited combinations of processes (in-process steps, tools used in those steps) in multiple processes (in-process steps) included in the physical design process (physical design free). Then, the information processing device 1 may refer to the prohibition table to determine whether the modified process (in-process step, tools used in those steps) in the candidate process is compatible with other groups of processes. If the combination of these processes is not prohibited in the prohibition table, the information processing device 1 outputs a positive result as the suitability determination, and if the combination is prohibited, it outputs a negative result as the suitability determination. If the provisionally derived candidate process yields a positive result, the information processing device 1 derives the candidate process as the circuit design process. If the provisionally derived candidate process yields a negative result, the information processing device 1 repeats the process of deriving a candidate process by changing the processes (in-process steps) included in the prototype process. By evaluating the suitability (tool selectability) of the modified processes (in-process steps, tools used in those steps) in the derived candidate process, the device can derive a candidate process from among multiple candidate processes whose feasibility is guaranteed as the circuit design process, thereby ensuring the reliability of the derived circuit design process. 【0062】 (Embodiment 2) Figure 6 is a flowchart illustrating the processing procedure by the control unit 11 of the information processing device 1 according to Embodiment 2 (multiple PPAs). The control unit 11 of the information processing device 1 receives, for example, an operator's operation from the terminal device 2 (designer PC) or an operator's operation from a keyboard connected to the input / output I / F 14, and performs the following processing based on the received operation. 【0063】The control unit 11 of the information processing device 1 acquires the code at the register transfer level and multiple performance indicators (S201). Similar to Embodiment 1, the control unit 11 of the information processing device 1 acquires logic design data such as the code at the register transfer level (RTL), performance indicators (PAA), and timing constraints (SDC) of the semiconductor integrated circuit that is the target of physical design from the terminal device 2 (designer PC). In this case, the performance indicators (PAA) are composed of multiple different performance indicators (PAA), and these multiple performance indicators (PAA) may include, for example, a performance indicator that emphasizes power consumption (Power), a performance indicator that emphasizes mounting area (Area), or a performance indicator that emphasizes processing performance (Performance). The control unit 11 of the information processing device 1 may assign a sequential number (PPA-1, PPA-2, PPA-3, PPA-n) to each of these multiple performance indicators (PAA) and store them in the storage unit 12. 【0064】 The control unit 11 of the information processing device 1 generates a target design for physical design based on one of the performance indicators (S202). The control unit 11 of the information processing device 1 selects a performance indicator from a plurality of performance indicators (PAAs) in the order of the assigned sequential numbers, and generates a target design for physical design based on the selected performance indicator, similar to the process S102 of Embodiment 1. 【0065】 The control unit 11 of the information processing device 1 derives a prototype process (S203). The control unit 11 of the information processing device 1 derives a similar process (S204). The control unit 11 of the information processing device 1 derives a candidate process by selecting the tools to be used in the process (S205). The control unit 11 of the information processing device 1 performs a metrics evaluation on the prototype process and the candidate process (S206). The control unit 11 of the information processing device 1 determines whether or not metrics improvements have been made to the candidate process (S207). The control unit 11 of the information processing device 1 determines whether or not it is possible to select tools to be included in the candidate process (S208). The control unit 11 of the information processing device 1 derives the candidate process as a circuit design process (S209). The control unit 11 of the information processing device 1 performs the processes from 203 to S209 in the same manner as S103 to S109 of Embodiment 1. 【0066】 The control unit 11 of the information processing device 1 determines whether processing for all performance indicators has been completed (S210). For each of the multiple performance indicators (PAA), the control unit 11 of the information processing device 1 selects a performance indicator (PPA-k) in the order of the assigned sequential numbers and derives the circuit design process corresponding to the selected performance indicator (PPA-k). When the control unit 11 of the information processing device 1 derives the circuit design process corresponding to the performance indicators in the order of the assigned sequential numbers, it determines whether the performance indicator (PPA-k) processed this time is the last performance indicator, i.e., whether all performance indicators have been processed. Since the circuit design process corresponding to each performance indicator (PPA-k) is stored in the storage unit 12 in association with the performance indicator (PPA-k), the control unit 11 of the information processing device 1 can determine whether all performance indicators have been processed based on the derived circuit design process. 【0067】 If processing for all performance indicators is not completed (S210: NO), the control unit 11 of the information processing device 1 performs a loop process to re-execute the processing from S202 based on the performance indicator (PPA-k+1) that follows the performance indicator (PPA-k) for which the circuit design process derivation process has been completed. In this way, the control unit 11 of the information processing device 1 can repeatedly perform the process of deriving the circuit design process for each of the multiple performance indicators (PAAs) in the order of the assigned sequential numbers. 【0068】 When processing for all performance indicators is completed (S210: YES), the control unit 11 of the information processing device 1 acquires the results of applying the circuit design process to the actual design (S211). The control unit 11 of the information processing device 1 registers the circuit design process and application results, etc., in the process database 121 (S212). The control unit 11 of the information processing device 1 performs the process of acquiring the results of applying the circuit design process to the actual design, and registering the circuit design process and application results, etc., in the process database 121, according to each circuit design process corresponding to each of the multiple performance indicators (PAA), in the same manner as the processes S110 to S111 of Embodiment 1. 【0069】Figure 7 is an explanatory diagram showing the changes in the steps of the process. In this embodiment, the multiple performance indicators (PAAs) include a performance indicator (PPA-1) that emphasizes mounting area (for highly congested designs), a performance indicator (PPA-2) that emphasizes power consumption (for low power designs), and a performance indicator (PPA-3) that emphasizes design cost. The circuit design process (flow 1, flow 2, flow 3) derived based on these three performance indicators (PPA-1, PPA-2, PPA-3) is modified from the original process according to the characteristics of each performance indicator. For example, in the circuit design process (flow 1) for the performance indicator (PPA-1) that emphasizes mounting area (for highly congested designs), the tool used in the Post CTS opt process (step) is changed, and a wiring repair process (step) is added. For example, in the circuit design process (flow 2) for the performance indicator (PPA-2) that prioritizes power consumption (for low power applications), the tools used in the floor plan processing (step) are changed, and a power optimization process (step) is added. For example, in the performance indicator (PPA-3) that prioritizes design cost, the tools used in floor plan, cell placement, CTS, Post CTS opt, wiring, and Post route opt are changed. In this way, the control unit 11 of the information processing device 1 derives individual circuit design processes according to each individual performance indicator (PAA). 【0070】According to this embodiment, the performance indicator (PPA) includes multiple performance indicators, for example, a performance indicator that emphasizes power consumption, a performance indicator that emphasizes area, or a performance indicator that emphasizes processing performance. In this case, each indicator belonging to the performance indicator (P: processing performance, P: power, A: area) may be assigned a weighting coefficient indicating the degree of emphasis (1P:3P:1A [performance indicator that emphasizes power consumption suppression]). The information processing device 1 may set the weighting coefficients for each indicator in each performance indicator based on the acquired multiple performance indicators (PPA). For example, the information processing device 1 generates multiple target designs (logic design data) by applying multiple performance indicators to code (RTL) at the same register transfer level. Then, the information processing device 1 derives a circuit design process (physical design flow) optimized for the physical design of each of the multiple target designs according to the multiple performance indicators, thereby efficiently supporting physical design according to the multiple performance indicators. 【0071】 The embodiments disclosed herein should be considered in all respects to be illustrative and not restrictive. The scope of this disclosure is indicated by the claims, not in the sense described above, and all modifications within the sense and scope equivalent to the claims are intended. 【0072】 With respect to the multiple claims described in the claims, they can be combined with each other regardless of the form of reference. Multiple dependent claims that depend on multiple claims may be described in the claims. Multiple dependent claims that depend on multiple dependent claims may also be described. Even if multiple dependent claims that depend on multiple dependent claims are not described, this does not limit the description of multiple dependent claims that depend on multiple dependent claims. 【0073】S Semiconductor Design Support System 1 Information Processing Device (Semiconductor Design Support Server) 11 Control Unit 111 Acquisition Unit 112 Target Design Generation Unit 113 Prototype Process Derivation Unit 114 Similar Process Derivation Unit 115 Candidate Process Derivation Unit 116 Metrics Evaluation Unit 117 Suitability Judgment Unit 118 Output Unit 12 Storage Unit 121 Process Database 122 Processing Database M Recording Medium P Program (Program Product) 13 Communication Unit 14 Input / Output I / F 101 Process Derivation Model 102 Performance Index Estimation Model 2 Terminal Device (Designer PC)

Claims

1. A design support method that supports physical design of a semiconductor integrated circuit by deriving a process for performing the physical design of the semiconductor integrated circuit, the method comprising: obtaining performance indicators required for the semiconductor integrated circuit; obtaining register transfer level code generated according to the performance indicators; and causing a computer to execute a process to derive a circuit design process for performing the physical design based on the obtained performance indicators and the code.

2. The design support method according to claim 1, comprising: deriving a similar design that is similar to the target design subject to the physical design, defined by the combination of the acquired performance indicators and the code; deriving a prototype process based on the target design; deriving a similar process applied to the derived similar design; deriving a design difference which is the difference between the target design and the similar design; and deriving the circuit design process by changing the processing included in the prototype process based on the derived design difference and the similar process.

3. The design support method according to claim 2, wherein the performance indicators include a plurality of performance indicators, and a plurality of circuit design steps are derived for a plurality of target designs defined by each of the plurality of performance indicators.

4. The design support method according to claim 2, wherein the process to be added or replaced when changing a similar process is derived by referring to a process database in which multiple processes used in the process are registered.

5. The design support method according to claim 2, wherein the acquired performance indicators and codes are associated with the derived circuit design process and registered in a process database for storing similar processes.

6. The design support method according to claim 2, comprising: deriving candidate processes for performing the physical design based on the acquired performance indicators and the code; estimating a predicted performance indicator for the candidate processes; estimating a predicted performance indicator for the prototype processes; and deriving the candidate processes as the circuit design processes if the predicted performance indicators for the candidate processes are superior to the predicted performance indicators for the prototype processes.

7. The design support method according to claim 2, wherein candidate processes for performing the physical design are derived based on the acquired performance indicators and the code, and if the suitability judgment of the modified process in the candidate process is positive, the candidate process is derived as the circuit design process.

8. A program that causes a computer to perform processing to support the physical design of a semiconductor integrated circuit by deriving a process for performing the physical design of the semiconductor integrated circuit, the program to obtain performance indicators required for the semiconductor integrated circuit, obtain register transfer level code generated according to the performance indicators, and execute a process to derive a circuit design process for performing the physical design based on the obtained performance indicators and the code.

9. An information processing apparatus comprising a control unit that performs processing to support physical design by deriving a process for performing physical design of a semiconductor integrated circuit, wherein the control unit acquires performance indicators required for the semiconductor integrated circuit, acquires register transfer level code generated according to the performance indicators, and derives a circuit design process for performing the physical design based on the acquired performance indicators and the code.

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