Mitigating sample-interleaving distortion through decorrelated waveform averaging

Abstract

Methods and systems for optimally detuning the ratio of analog-to-digital (ADC) sample rate and trigger rate during waveform averaging to minimize the deleterious effects from sample interleaving are described. In some examples, the optimal detuning factor is based on the number of ADC cores used and the limited tuning resolution of the clock rates. An example method includes providing, by a clock generation circuit, an analog-to-digital (ADC) clock to a bank of ADCs, and adjusting at least one parameter of the ADC clock or a signal clock such that (a) a ratio of a frequency of an ADC sample rate to a frequency of a waveform repetition rate and (b) a number of ADCs in the bank of ADCs are relatively prime.

Description

International Patent ApplicationAttorney Docket No.: 077518.8195.WO00 / IL-13987-02MITIGATING SAMPLE-INTERLEAVING DISTORTION THROUGH DECORRELATED WAVEFORM AVERAGINGSTATEMENT REGARDING FEDERALLY SPONSORED RESEARCH OR DEVELOPMENT

[0001] This invention was made with Government support under Contract No. DE-AC52- 07NA27344 awarded by the United States Department of Energy. The Government has certain rights in the invention.CROSS-REFERENCE TO RELATED APPLICATION

[0002] This patent document claims priority to and benefits of U.S. Provisional Patent Application No. 63 / 729,253, entitled “METHODS AND SYSTEMS FOR DECORRELATED WAVEFORM AVERAGING,” filed on December 6, 2024. The entire content of the aforementioned patent application is incorporated by reference as part of the disclosure of this patent document.TECHNICAL FIELD

[0003] This patent document generally relates to digitization of analog signals, and more particularly, to high-speed decorrelated digitization and averaging of analog signals.BACKGROUND

[0004] Sample-interleaved analog-to-digital conversion (SI-ADC) is a technique used to increase the effective sampling rate of an ADC system. In SLADC, multiple ADCs are employed in parallel, each sampling the input signal at staggered intervals. This interleaving process allows the full system to achieve a combination of high overall sampling rate and high resolution better than any single ADC could provide. SI-ADC is widely used in high-speed data acquisition systems, communications, and instrumentation where high-resolution and high-speed conversion are critical. As bandwidths in these systems increase, there remains a need for even greater speed conversion with high fidelity.SUMMARY

[0005] The disclosed methods and systems enable high-fidelity characterization of repetitiveInternational Patent ApplicationAttorney Docket No.: 077518.8195.WO00 / IL-13987-02 analog signals by synchronizing the ADC sample clock and signal trigger while optimally detuning their ratio to decorrelate sample-interleaving artifacts across averaged captures. By configuring the number of ADC samples per trigger period, N = fs / fr, to be coprime with the number of interleaved ADC cores, M, each point on the waveform is sampled by all cores over successive acquisitions, and interleaving-induced distortion is averaged out rather than reinforced. The described embodiments preserve the benefits of phase locking — low trigger jitter and consistent sampling alignment — while requiring only minimal ppm-scale adjustments to the sample rate and / or repetition rate. Some embodiments address finite tuning resolution by selecting achievable N values and, as needed, adjusting trigger period multiples. Numerical and experimental results show substantial suppression of interleaving spurs and reduction of correlated noise, yielding clean spectra and accurate time-domain reconstructions for various applications.

[0006] In an example aspect, an ADC conversion system is described. The ADC conversion system includes a bank of analog-to-digital converters (ADCs), a synchronized averaging circuit, a timing detector, and a clock generation circuit. The bank of analog-to-digital converters (ADCs) comprises a first input to receive an analog repetitive signal comprising repeated waveforms, a second input to receive an ADC clock that is phase locked with a signal clock with a waveform repetition rate, and an output operable to provide a digitized repetitive signal. Here, the ADC clock is used to generate an ADC sample rate. The synchronized averaging circuit comprises a first input, coupled to the output of the bank of ADCs, to receive the digitized repetitive signal, a second input to receive a waveform timing information, and an output operable to provide a digital averaged waveform generated by aligning, based on the waveform timing information, each waveform of the digitized repetitive signal. The timing detector comprises an output, coupled to the second input of the synchronized averaging circuit, operable to provide the waveform timing information associated with the repeated waveforms of the analog repetitive signal. The clock generation circuit comprises a first output, coupled to the second input of the bank of ADCs, operable to provide the ADC clock. Here, the clock generation circuit is configured to adjust at least one parameter of the signal clock or the ADC clock such that (a) a ratio of a frequency of the ADC sample rate and a frequency of theInternational Patent ApplicationAttorney Docket No.: 077518.8195.WO00 / IL-13987-02 waveform repetition rate and (b) a number of ADCs in the bank of ADCs are relatively prime.

[0007] In another example aspect, a clock generation circuit is described. The clock generation circuit includes an output configured to be coupled to an input of a bank of analog-to- digital converters (ADCs) to provide an ADC clock associated with an ADC sample rate, and one or more processors, coupled to the output, configured to adjust at least one parameter of the ADC clock or a signal clock with a waveform repetition rate such that (a) a ratio of a frequency of the ADC sample rate to a frequency of the waveform repetition rate and (b) a number of ADCs in the bank of ADCs are relatively prime. Here, the signal clock is phase locked to the ADC clock, a digitized repetitive signal is generated based on the ADC clock and an analog repetitive signal, and a digital averaged waveform is generated, based on a waveform timing information, by aligning each waveform of the digitized repetitive signal.

[0008] In yet another example aspect, a method for generating a clock signal for improved waveform processing is described. The method includes providing, by a clock generation circuit, an analog-to-digital (ADC) clock to a bank of ADCs, wherein the ADC clock is associated with an ADC sample rate, and adjusting at least one parameter of the ADC clock or a signal clock with a waveform repetition rate such that (a) a ratio of a frequency of the ADC sample rate to a frequency of the waveform repetition rate and (b) a number of ADCs in the bank of ADCs are relatively prime. In this example method, the signal clock is phase locked to the ADC clock, a digitized repetitive signal is generated based on the ADC clock and an analog repetitive signal, and a digital averaged waveform is generated, based on a waveform timing information, by aligning each waveform of the digitized repetitive signal.

[0009] In yet another example aspect, a method for producing an improved digital waveform is described. The method includes generating, by a bank of analog-to-digital converters (ADCs), a digitized repetitive signal based on an analog repetitive signal and an ADC clock that is phase locked with a signal clock with a waveform repetition rate, the ADC clock being used to generate an ADC sample rate. The method further includes generating, by a timing detector, a waveform timing information, adjusting, by a clock generation circuit, at least one parameter of the signal clock or the ADC clock such that (a) a ratio of a frequency of the ADC sample rate and a frequency of the waveform repetition rate and (b) a number of ADCs in the bank of ADCsInternational Patent ApplicationAttorney Docket No.: 077518.8195.WO00 / IL-13987-02 are relatively prime, and generating, by a synchronized averaging circuit subsequent to the adjusting, a digital averaged waveform by aligning, based on the waveform timing information, each waveform of the digitized repetitive signal.

[0010] The above and other aspects and features of the disclosed technology are described in greater detail in the drawings, the description and the claims.BRIEF DESCRIPTION OF THE DRAWINGS

[0011] FIG. 1 is a block diagram illustrating an example system for the improved high-speed digitization of an analog repetitive signal.

[0012] FIG. 2 is a block diagram illustrating another example system for the improved highspeed digitization of an analog repetitive signal.

[0013] FIG. 3 is a block diagram illustrating yet another example system for the improved high-speed digitization of an analog repetitive signal.

[0014] FIG. 4 is a block diagram illustrating yet another example system for the improved high-speed digitization of an analog repetitive signal.

[0015] FIG. 5A illustrates an example of sampling a repeated waveform using multiple analog-to-digital converter (ADC) cores.

[0016] FIG. 5B illustrates an example of digitally combining portions of the repeated waveform illustrated in FIG. 5A.

[0017] FIG. 6A illustrates another example of sampling a repeated waveform using multiple analog-to-digital converter (ADC) cores.

[0018] FIG. 6B illustrates an example of digitally combining portions of the repeated waveform illustrated in FIG. 6A.

[0019] FIGS. 7A and 7B illustrate examples of waveform averaging for the worst case and optimal case of interleaving distortion, respectively.

[0020] FIGS. 8A and 8B illustrate examples of waveform averaging of a square pulse input signal for the worst case and optimal case of interleaving distortion, respectively.

[0021] FIGS. 9A and 9B illustrate examples of waveform averaging of a sine wave input signal for the worst case and optimal case of interleaving distortion, respectively.

[0022] FIGS. 10A-10D illustrate examples of averaging with no input signal for the worstInternational Patent ApplicationAttorney Docket No.: 077518.8195.WO00 / IL-13987-02 case and optimal case of interleaving distortion, respectively.

[0023] FIGS. 11 A and 1 IB illustrate zoomed-in time-domain plots of the example averaging in FIGS. 10A and 10B, respectively.

[0024] FIG. 12 is a flowchart illustrating an example method for generating a clock signal for improved waveform processing, in accordance with the disclosed embodiments.

[0025] FIG. 13 is a flowchart illustrating an example method for producing an improved digital waveform, in accordance with the disclosed embodiments.DETAILED DESCRIPTION

[0026] High fidelity characterization of repetitive signals, with the goal of determining the common signal shared across multiple repeating waveforms, is critical for various applications, including telecommunications and optical pulse shaping. With digital waveform averaging, multiple digitized waveforms are temporally aligned, and the corresponding values from each waveform are averaged. This approach reduces the root mean square deviation of uncorrelated error as the square root of the number of averaged waveforms. The result is a high signal-to- noise ratio (SNR) measurement of the common waveform on the repetitive signal-under-test.

[0027] While conventional digital waveform averaging is effective at reducing uncorrelated error, it cannot distinguish the common waveform of interest from correlated errors, i.e., noise and distortion common across all waveforms. One source of correlated error can arise in the digitization process itself as a result of non-idealities in the sample interleaving process used in high-speed analog-to-digital converters (ADCs). Sample interleaving is a widely used technique to achieve high-sample rate digitization by employing multiple sub-sample rate ADC cores in parallel. The ADC cores of sample interleaved ADCs synchronously sample the same input signal, but with the sampling clock of each core delayed, or phase shifted, with respect to each other. In this way, each core samples a unique point in time on the input signal, so that when the samples from each core are interleaved together, the result is a digitized signal with a higher effective sample rate. Though effective at achieving high sample rates, this interleaving technique also comes with some drawbacks. If mismatches in gain or offset exist between the ADC cores, or if the phase-shifted sample times of each core do not fall at uniform sampling intervals, sample interleaving artifacts, or spurs, can arise, distorting the signal. When digitizingInternational Patent ApplicationAttorney Docket No.: 077518.8195.WO00 / IL-13987-02 a repetitive signal-under-test, if the waveform repetition rate and the sample rate of the ADC are synchronized, these interleaving artifacts can become correlated across the repeating waveforms and will therefore not be mitigated by waveform averaging.

[0028] One existing method to avoid correlating the sample interleaving artifacts with the repeating waveforms is to run the ADC sample rate asynchronously with the waveform repetition rate. If the ADC and signal clocks randomly drift with respect to each other during the waveform averaging, or if the clock frequencies happen to be detuned (e.g., due to different crystal oscillator temperatures), then the interleaving artifacts will vary across the different waveform captures and thus become decorrelated.

[0029] However, there are drawbacks to not synchronizing the signal and sampling clocks. Simply relying on drift in the clocks, or random detuning, is not always sufficient to guarantee the two clocks are asynchronous; it is possible that they may drift in phase with each other during waveform averaging long enough to correlate the interleaving artifacts. In addition, asynchronous waveform sampling can lead to increased trigger jitter as well as inconsistent sampling points across waveforms and therefore may not be an option in some applications.

[0030] Embodiments of the disclosed technology relate to methods and systems for the improved detuning of the ADC and signal clocks while maintaining synchronization between the two. The disclosed embodiments maintain synchronization between the two clocks, but with suitable detuning applied such that the interleaving artifacts are substantially or maximally decorrelated across waveforms. By maintaining synchronization, the associated benefits of lower trigger jitter and a consistent sampling point are preserved.

[0031] As illustrated in the block diagrams in FIGS. 1-4, embodiments of the disclosed technology include a signal source, a sample interleaved ADC, a trigger system, a clock generation block (or clock generator, or clock generation circuit), and a synchronized waveform averaging block. In some embodiments, the signal source generates a signal-under-test in the form of repeating waveforms, which is sent to the ADC for digitization. The ADC captures and digitizes a certain number of waveforms from the repetitive input signal (e.g., as shown in FIGS. 5A and 6A). The synchronized waveform averaging block digitally overlaps the captured waveforms using information from the timing detector (e.g., as shown in FIGS. 5B and 6B,International Patent ApplicationAttorney Docket No.: 077518.8195.WO00 / IL-13987-02 respectively), and the corresponding points on each waveform are averaged to reduce the uncommon noise and distortion present on the signal. The period between overlapped signal data is typically constant and is called the trigger period. The inverse of the trigger period is called the trigger rate. For ideal waveform averaging, the trigger period should be an integer multiple of the waveform period. Depending on the trigger system, consecutive waveforms may be captured and averaged (e.g., when the trigger clock is equal to the signal clock) or non-consecutive waveforms may be captured and averaged (e g., when the trigger clock is equal to the signal clock divided by a natural number, i.e., 1, 2, 3, etc.).

[0032] FIG. 1 illustrates an example system configured for high-fidelity digitization and averaging of a repetitive analog signal while preserving phase lock between a signal clock and an ADC sampling clock and detuning their ratio to decorrelate interleaving artifacts. A signal clock source 110 provides a low-jitter signal clock that drives (a) a signal source 130 to generate an analog repetitive signal comprising repeated waveforms and (b) a clock generation circuit 120. The analog repetitive signal is delivered to a bank of ADCs 150 that implements sample interleaving across multiple ADC cores. The clock generation circuit 120 is phase locked to the signal clock source 110 and provides an ADC clock to the bank of ADCs 150. The clock generation circuit 120 is configured to adjust at least one clock parameter so that the ratio of the ADC sample rate to the trigger rate is selected such that the number of samples per trigger period is relatively prime to the number of interleaved ADC cores. In the illustrated embodiment, a trigger signal source 140 receives a trigger clock from the clock generation circuit 120, and generates a trigger signal used by a timing detector 160 to produce waveform timing information associated with the repeated waveforms. The bank of ADCs 150 outputs a digitized repetitive signal to a synchronized averaging circuit 170. The synchronized averaging circuit 170 also receives the waveform timing information from the timing detector 160 and, based on this timing information, aligns corresponding waveforms and averages them to form a digital averaged waveform with interleaving artifacts substantially mitigated through decorrelated sampling across acquisitions.

[0033] FIG. 2 shows another example system in which the signal and ADC clocks remain phase locked while the ratio between the ADC sample rate and the waveform repetition rate isInternational Patent ApplicationAttorney Docket No.: 077518.8195.WO00 / IL-13987-02 detuned to achieve a samples-per-trigger value that is relatively prime to the number of ADC cores. A signal clock source 210 outputs a signal clock to a signal source 230, which generates the analog repetitive signal for digitization by a bank of ADCs 250. A clock generation circuit 220, phase locked to the signal clock source 210, provides the ADC clock to the bank of ADCs 250 and adjusts clock parameters to attain the desired relatively-prime ratio. A timing detector 260 generates, based on the output of the bank of ADCs 250, waveform timing information for the repeated waveforms. The digitized repetitive signal from the bank of ADCs 250 and the waveform timing information from the timing detector 260 are provided to a synchronized averaging circuit 270. Using the waveform timing information, the synchronized averaging circuit 270 aligns and averages corresponding portions of the repeated waveforms to output a high-fidelity digital averaged waveform with interleaving-induced distortion reduced by decorrelation across averages.

[0034] FIG. 3 illustrates yet another system embodiment that includes a clock generation circuit 320 configured to provides a signal clock to drive a signal source 330, which outputs an analog repetitive signal to a bank of ADCs 350. The clock generation circuit 320 supplies an ADC clock, which remains phase locked to the signal clock, to the bank of ADCs 350 while detuning the sample-to-repetition-rate ratio so that the integer number of samples per trigger period is relatively prime with the number of ADC cores. A trigger signal source 340 receives a trigger clock from the clock generation circuit 320 and provides an output that is used by a timing detector 360 to produce waveform timing information tied to the repeated waveforms. The bank of ADCs 350 outputs a digitized repetitive signal to a synchronized averaging circuit 370, which, leveraging the waveform timing information from the timing detector 360, aligns each captured waveform and computes an averaged waveform in which interleaving artifacts are substantially decorrelated and thereby suppressed.

[0035] FIG. 4 presents yet another system configuration in which the clock generation circuit 420 provides a signal clock to a signal source 430 that generates an analog repetitive signal. The analog repetitive signal is digitized by a bank of ADCs 450 operating under an ADC clock supplied by the clock generation circuit 420. The ADC clock is phase locked to the signal clock and the clock generation circuit 420 adjusts one or more clock parameters to set the ratioInternational Patent ApplicationAttorney Docket No.: 077518.8195.WO00 / IL-13987-02 between the ADC sample rate and the waveform repetition rate so that the samples-per-trigger count is relatively prime to the number of ADC cores, thus maximizing decorrelation of interleaving artifacts over successive acquisitions. A timing detector 460 generates waveform timing information for the repeated waveforms, which, together with the digitized repetitive signal from the bank of ADCs 450, is provided to a synchronized averaging circuit 470. The synchronized averaging circuit 470 aligns the repeated waveforms using the timing information and averages them to produce a digital averaged waveform with reduced correlated interleaving distortion.

[0036] In some embodiments, the timing detector can take as an input an analog trigger signal synchronized with the signal-under-test (e.g., as shown in FIGS. 1 and 3). These trigger signals can take the form of square pulses, for example transistor-to-transistor logic (TTL) pulses, or a clock signal, e.g. square or sinusoidal, with period equal to the trigger period, ideally an integer multiple of the waveform period. Such a timing detector may sample the input analog trigger signal and register when the amplitude of the trigger signal crosses a threshold, for example when the rising edge of the trigger signal crosses the 50% amplitude level, or when the rising edge crosses the zero level in the case of a zero-average clock signal. In this way, the timing detector measures the trigger period. The trigger period, for example measured in seconds, is an example of the timing information which is provided at the output of the timing detector. In other embodiments, the timing detector may take as an input an analog or digitized version of the signal -under-test (e.g., as shown in FIGS. 2 and 4 for the digitized version of the signal -under- test). In this case, the timing detector may register when the level of the analog sample-under-test or one of the samples of the digitized signal -under-test crosses a threshold, for example when the rising edge of the waveform exceeds 50% of the maximum signal level. If there are multiple such threshold crossings per waveform, then the timing detector may register only the first such crossing. The timing detector may therefore measure the waveform period, in seconds or in ADC sample numbers, which is then provided at the output of the timing detector.

[0037] According to some example embodiments (e.g., FIGS. 1 to 4), the ratio of the ADC sample rate and the trigger repetition rate (or the waveform repetition rate when they are equal) is set in such a way as to maximally decorrelate the sample interleaving artifacts duringInternational Patent ApplicationAttorney Docket No.: 077518.8195.WO00 / IL-13987-02 waveform averaging. This maximal decorrelation can be achieved by using the clock generation block (e.g., clock generation circuit x20 in FIGS. 1 to 4) to set the ratio of the ADC sampling rate and the trigger repetition rate so that the number of ADC samples per trigger period is relatively prime compared with the number of ADC cores. With this desired ratio, each corresponding point on the waveforms will be sampled by all the ADC cores during waveform averaging, so any distortion induced by interleaving artifacts will be maximally averaged out.

[0038] In mathematical terms, let fr indicate the trigger repetition rate (which is equal to the waveform repetition rate divided by a natural number and phase locked to a signal clock) and fs indicate the ADC sample rate (which is phase locked to the frequency of an ADC clock), so that the number of ADC samples per trigger period is N = fslfr. Let M indicate the number of cores making up the sample interleaved ADC. The ideal configuration is for N and M to share no common factors, i.e., for N and M to be relatively prime. If N and M are not relatively prime, but instead share a greatest common divisor, gcd(lV, M) > 1, i.e., N = n gcd(A, M) and M = m x gcd(A, M), then N m = M x , and thus, after m trigger captures, the pattern of ADC cores mapped to corresponding waveform points will repeat. Since m < M, not all ADC cores will get the chance to sample every point on the waveform before the pattern repeats. In the worst case, when N is a multiple of M, then M = gcd(A, M), and m = 1, so the pattern repeats every trigger period, maximally correlating the interleaving artifacts during averaging. In the optimal case, when N and M are relatively prime, then m = M, and only after M trigger periods, or after all ADC cores sample every point on the waveform, will the interleaving pattern repeat. The interleaving artifacts due to mismatch of the ADC cores will therefore be maximally decorrelated and will be maximally reduced after averaging.

[0039] The ADC clock and signal clock must be phase locked to ensure that the ratio of ADC sample rate and trigger rate is constant in time. The system can be optimized to maximally decorrelate the interleaving spurs by adjusting this ratio. The optimal ratio can be configured by adjusting the ADC clock or the signal clock (or both). For example, in a situation where a tunable sample rate ADC is being used to characterize a signal with a fixed repetition rate, then it would be the ADC clock (and thus the ADC sample rate) that would be adjusted. In the example scenario of a user-controlled signal source in which the waveform repetition rate is tunable, itInternational Patent ApplicationAttorney Docket No.: 077518.8195.WO00 / IL-13987-02 may be more convenient to adjust the signal clock. In either case, it is generally desired (or required) to keep the sample rate of the ADC and the waveform repetition as close to their original or nominally designed values as possible. If we call the nominal ADC sample rate and trigger repetition rate fs,nom and fT,nom, respectively, then the nominal number of samples per trigger period Nnom = f S,nom / fT,nom. The goal is to find the nearest integer Nopt to Nnom which is coprime with the number of ADC cores, M. We define NOpt = Nnom + NN. The ADC sample rate and / or trigger repetition rate would then need to change by a factor of NN / Nnom (or less) to maximally decorrelate the interleaving spurs.

[0040] In some embodiments, optimizing the system is equivalent to the problem of finding the nearest integer Nopt to a number Nnom which is coprime to an integer M. This problem is related to a function in number theory called the Jacobsthal function. The Jacobsthal function g(Q) is defined as the smallest positive integer such that every sequence of ,q(Q) consecutive integers is guaranteed to contain a number coprime with Q. Herein, the smallest change in the number of ADC samples per trigger period, NN, would be equal to g(M) / 2, so that the smallest relative change in ADC sample rate or trigger repetition rate would be equal to g(M) / (2 .Nnom) . For existing systems, it is assumed that the number of ADC cores in a high-speed ADC is typically no greater than 256. The largest Jacobsthal function for M < 256 is 10 (corresponding to M = 210), which means the closest coprime integer to Nnom is guaranteed be no greater than 5 integers away. Moreso, it is common for the number of ADC cores to be a power of 2. In this case, any odd number will be coprime with M, and therefore, the closest coprime integer to Nnom will be no greater than 1 integer away. By finding this smallest NN for a particular system, we can ensure that the ADC sample rate and / or waveform repetition rate will deviate minimally from their nominal values.

[0041] In some example applications, the sample rate of the ADC, fs.nom, is many factors faster than the trigger repetition rate, fr,nom. To operate in the first Nyquist zone, the ADC sample rate must be at least double the maximum frequency content of the signal under test. Moreso, many applications use an ADC with a sample rate multiple factors above Nyquist to benefit from oversampling gain on SNR. With the highest frequency features of a waveform lying within the waveform period, and the trigger period being at least as large as the waveformInternational Patent ApplicationAttorney Docket No.: 077518.8195.WO00 / IL-13987-02 period, it is therefore common for the ADC sample rate to be multiple factors faster than the trigger repetition rate. Additionally, for many applications, for instance optical pulse characterization, the duty cycle of the signal content relative to the waveform period is typically small, leading to an even larger ratio of ADC sample rate to trigger repetition rate. The higher the sample rate of the ADC relative to the trigger repetition rate, the larger the number of ADC samples per trigger period, Nnom. With the optimal minimum AA bounded by 5 in realistic sample interleaving ADCs (because g(M) < 10 for the number of cores M < 256), and just 1 for most practical applications (with M a power of 2), this means the percentage change of the ADC sample rate and / or waveform repetition rate is bounded and will typically be small. In the case that the number of ADC samples per trigger period is not large enough, so that the fractional change in the ADC sample rate and / or waveform repetition rate is too large, the trigger period can be chosen to be a larger multiple of the waveform period. Using a longer trigger period comes at the cost of longer averaging time for the same number of averages, but in applications where fidelity is more important than averaging time, it is a viable option.

[0042] In other example applications, for optimally adjusting the ratio of ADC sample rate to trigger repetition rate, consider a system with a nominal ADC sample rate of fs,nom = 1 GSps and a nominal trigger repetition rate fr.nom = 1 MHz equal in this case to the waveform repetition rate. The nominal number of ADC samples per trigger period is Nnom = 1000. For a sample interleaving ADC with M = 16 cores, the ratio Nnom and M are not relatively prime, since they share a common factor of 8. The interleaving pattern would therefore repeat after only 2 waveforms, which would result in the even order spurs coherently averaging and thus distorting the final averaged waveform. Since M is a power of 2, only a NN of 1 is needed to maximally decorrelate the interleaving spurs (e.g. NOpt = 1001). Therefore, the ADC sample rate or the waveform repetition rate needs to be changed by just one part in a thousand, or Ik ppm. If, for instance, the system can tolerate a variation from the nominal of just 100 ppm, then the trigger rate can be chosen to be one tenth of the waveform repetition rate, with fT,nom = 100 kHz. In this case, Nnom = 10,000, NOpt = 10,001, and the necessary fractional change in clock rate is 100 ppm.

[0043] In yet other example implementations, the waveform repetition rate of the signal under test is kept fixed (e.g., locked to a low-noise quartz oscillator) and the ADC sample rateInternational Patent ApplicationAttorney Docket No.: 077518.8195.WO00 / IL-13987-02 can be controlled by accepting a variable external reference clock over a certain capture range (e.g. 10 MHz ± Ik ppm). The sample rate of the ADC is locked to this external reference clock either directly or as a fixed multiple of the reference clock via a phase-locked loop (PLL) and can be tuned by adjusting the frequency of the external reference clock. For instance, if the nominal ADC sample rate is 1 GSps and the nominal external reference clock acceptance frequency is 10 MHz, the ADC sample rate can be tuned to 1.001 GSps by using a 10.01 MHz external reference clock input to the ADC. To optimally configure this system to maximally decorrelate the sample interleaving artifacts, first the optimal ADC sample rate must be determined based on the calculations above. A clock generator which is phase locked to the signal clock then provides an external reference clock within the capture range of the ADC external clock input. The clock generator can be phase locked to the signal clock by accepting an external clock from the signal clock source (e.g., signal clock source 110 and 210 in FIGS. 1 and 2, respectively). The clock generator must then tune the external reference clock frequency from the nominal value for the ADC by the same proportional amount that the ADC sample rate must be tuned. As an example, the clock generator may consist of a fractional-N frequency synthesizer which generates the new optimally tuned external reference clock from a nominal reference clock of the signal source. Alternatively, as shown in FIGS. 3 and 4, the signal clock source is not a distinct component, and the clock generator (or clock generation circuit 320 or 420) is configured to generate both the signal clock and the ADC clock that are phase locked.

[0044] In practice, the resolution with which the clock generator can tune the ADC or signal reference clock is limited. The minimum resolution will impact the options for selecting a possible number of ADC samples per trigger period. As an example, consider an implementation in which the ADC sample rate is tunable, with a nominal sample rate of fs,nom, and the trigger repetition rate is fixed at fr,nom. Also, suppose the clock generator has finite tuning resolution such that the possible ADC sample rates are fs = fs,nom X k / D, with D fixed and k a selectable integer. For N = fs / fr,nom to be an integer, the possible values of integer k are limited to step sizes of Akmin that are given by:

[0045] Therefore, the possible values of N are limited to step sizes of Nmin that are givenInternational Patent ApplicationAttorney Docket No.: 077518.8195.WO00 / IL-13987-02 by:

[0046] Ideally, ANmin = 1, corresponding to gcd(fs.nom, fr.nom x D) = fs,nom. In this case, there are no restrictions on possible values for N, and the ADC sample rate can be kept close to the nominal value (to within 1 / Nnomif the number of ADC cores is a power of 2). This scenario can be guaranteed for any trigger rate if D is an integer multiple of fs,nom.

[0047] In some embodiments, an ADC can be codesigned with a clock generator (e.g. fractional-N PLL) with the integer fractional resolution of the clock generator a multiple of the nominal ADC sample rate so that the system can be configured for optimally performing decorrelated waveform averaging independent of the trigger rate.

[0048] In the case that AN mtn > 1, then only a subset of possible integers N can be achieved. An achievable optimal N which is both relatively prime with the number of ADC cores and as close as possible to Nnom can be found by first finding the nearest achievable integer to NnomNo= round (^°m) X ANmin.

[0049] If Nois relatively prime with the number of ADC cores, then No is the optimal value for N, with the ADC sample rate tuned to the new optimal value of fs.opt = No x fr,nom. If No is not relatively prime with the number of ADC cores, then ANmin can be added to or subtracted from No until an integer relatively prime to the number of ADC cores is reached. In the case that Nois odd, ANmin is even, and the number of ADC cores is a power of two, then there is no possibility of tuning the ADC sample rate to a value which results in N relatively prime with the number of ADC cores. In this case, the optimal value for N will be one that minimizes the gcd(N, M).

[0050] As an example, consider an implementation with an ADC composed of 16 ADC cores and nominal sample rate fs,nom = 5 GSps, a fixed trigger rate fr,nom = 960 Hz, and a clock generator with a minimum tuning resolution of Ippm (D = 1,000,000) used to tune the ADC sample rate. In this case, the nominal number of sample points per trigger period is not an integer, with Nnom = 5,208,333. 3. Because of the finite tuning parameter D, the possible valuesInternational Patent ApplicationAttorney Docket No.: 077518.8195.WO00 / IL-13987-02 of N are limited to N mtn = 125. To find the optimal ADC sample rate, we start by finding the nearest achievable integer to Nnom, which in this case is No = 5,208,375. Since No is relatively prime with the number ADC cores, this is the optimal value for N, corresponding to an optimal ADC sample rate fs.opt = 5.00004 GSps, a change of less than 10 ppm from the nominal value.

[0051] The efficacy of the described embodiments is evinced by the numerical simulation results illustrated in FIGS. 7A through 7B and the experimental results in FIGS. 8A through 1 ID. FIGS. 7A and 7B illustrate examples of waveform averaging for the worst case and optimal case of interleaving distortion, respectively. As shown in FIG. 7A, each of the ADC cores (e.g., ADC Core 0, . . ., ADC Core 3) sample at the same points of the waveform, which results in the interleaving distortion being correlated with the signal. As seen in the lower right of FIG. 7A, the interleaving distortion is present even in the averaged waveform because it was correlated with the signal and could not be averaged out. In contrast, embodiments of the disclosed technology were used to generate FIG. 7B, which illustrates the case with optimal sampling. Therein, each of the ADC cores are configured to sample the input waveform at different times in each trigger period, which results in the interleaving distortion being randomized, and mitigated with averaging. The plot in the lower right of FIG. 7B shows the sampled signal matching closely with the input analog signal.

[0052] FIGS. 8A and 8B illustrate examples of waveform averaging (5,200 averages) of a square pulse input signal for the worst case and optimal case of interleaving distortion, respectively. The plotted result for the worst case in FIG. 8A, which exhibits strong interleaving distortion on the averaged waveform, corresponds to a trigger rate of 250 Hz and a sample rate of 12.5 GSps (nominal), corresponding to 50,000,000 ADC samples per trigger period, and 64 ADC cores. The number of ADC samples per trigger is a multiple of the number of ADC cores, so the interleaving distortion is maximally correlated with the signal. In contrast, FIG. 8B shows the plotted result for the optimal case, which exhibits a high-fidelity averaged waveform with interleaving distortion optimally reduced with averaging, that corresponds to a trigger rate of 250 Hz and a detuned ADC sample rate of 12.49999875 GSps (12.5 GSps * 0.9999999), corresponding to 49,999,995 ADC samples per trigger period, which is coprime with 64, the number of ADC cores. In this optimal configuration, the interleaving distortion is optimallyInternational Patent ApplicationAttorney Docket No.: 077518.8195.WO00 / IL-13987-02 mitigated with averaging, uncovering small features on the top of the square pulse waveform that were not detectable in the worst case configuration because of the strong interleaving distortion.

[0053] FIGS. 9A and 9B illustrate examples of waveform averaging of an 892 MHz sine wave input signal for the worst case and optimal case of interleaving distortion, respectively. The plotted results are in the frequency domain with the system parameters for the worst case and optimal case being identical to those used in FIGS. 8 A and 8B. As shown for the optimal case in FIG. 9B, the spectrum has a clean main peak with minimal spurs and a low noise floor (more than 100 dB lower than the main peak). In contrast, FIG. 9A, which corresponds to the worst case, shows a spectrum with a similar main peak, but spurs across the entire bandwidth that are as high as 40 dB lower than the main peak.

[0054] FIGS. 10A-10D illustrate examples of averaging with no input signal for the worst case and optimal case of interleaving distortion, respectively. Herein, FIGS. 10A and 10B show time-domain plots with the worst case (in FIG. 10A) having a noise amplitude (in mV) that is approximately a factor of 40 greater than the noise amplitude in the optimal case (in FIG. 10B). The corresponding frequency-domain plots are shown for the worst case and the optimal case in FIGS. 10C and 10D, respectively. As shown in FIG. 10C, although the noise floor is lower than -100 dBm, there are periodic spurs that reach as high as -40 dBm, whereas in FIG. 10D, the optimal case only has a few intermittent spurs that rise above the -100 dBm noise floor.

[0055] FIGS. 11 A and 1 IB illustrate horizontal zoomed-in time-domain plots of the example averaging in FIGS. 10A and 10B, respectively. As shown therein, the plotted results of the zoomed-in portion are consistent with the time-domain plots shown for the worst case and the optimal case in FIGS. 10A and 10B, respectively, illustrating the periodic nature of the interleaving distortion in the worst case configuration.

[0056] The described embodiments provide the following preferred technical solutions that address the technical problem of the persistence of correlated interleaving artifacts and trigger- induced jitter when digitizing repetitive analog signals with sample-interleaved ADCs operated under phase-locked conditions, which prevents conventional averaging from improving fidelity.

[0057] SI. An analog-to-digital conversion system (e.g., as illustrated in FIGS. 1-4), comprising: a bank of analog-to-digital converters (ADCs) comprising: a first input to receive anInternational Patent ApplicationAttorney Docket No.: 077518.8195.WO00 / IL-13987-02 analog repetitive signal comprising repeated waveforms, a second input to receive an ADC clock that is phase locked with a signal clock with a waveform repetition rate, the ADC clock being used to generate an ADC sample rate, and an output operable to provide a digitized repetitive signal; a synchronized averaging circuit comprising: a first input, coupled to the output of the bank of ADCs, to receive the digitized repetitive signal, a second input to receive a waveform timing information, and an output operable to provide a digital averaged waveform generated by aligning, based on the waveform timing information, each waveform of the digitized repetitive signal; a timing detector comprising: an output, coupled to the second input of the synchronized averaging circuit, operable to provide the waveform timing information associated with the repeated waveforms of the analog repetitive signal; and a clock generation circuit comprising: a first output, coupled to the second input of the bank of ADCs, operable to provide the ADC clock, wherein the clock generation circuit is configured to adjust at least one parameter of the signal clock or the ADC clock such that (a) a ratio of a frequency of the ADC sample rate and a frequency of the waveform repetition rate and (b) a number of ADCs in the bank of ADCs are relatively prime.

[0058] S2. The anal og-to-digi tai conversion system of solution SI, comprising: a signal source comprising: an input to receive the signal clock; and an output, coupled to the first input of the bank of ADCs, operable to provide the analog repetitive signal generated based on the signal clock.

[0059] S3. The analog-to-digital conversion system of solution S2, comprising: a signal clock source comprising: a first output, coupled to an input of the clock generation circuit, operable to provide the signal clock; and a second output, coupled to the input of signal source, operable to provide the signal clock. This solution is illustrated, for example, in FIGS. 1 and 2.

[0060] S4. The analog-to-digital conversion system of solution S2 or S3, comprising: a trigger signal source comprising: an input, coupled to a second output of the clock generation circuit, to receive a trigger clock and generate a trigger signal based thereupon; and an output, coupled to the input of the timing detector, operable to provide the trigger signal comprising the waveform timing information. This solution is illustrated, for example, in FIGS. 1 and 3.

[0061] S5. The analog-to-digital conversion system of solution S4, wherein the timingInternational Patent ApplicationAttorney Docket No.: 077518.8195. WO00 / TL-13987-02 detector is configured to receive the trigger signal from the trigger signal source.

[0062] S6. The analog-to-digital conversion system of solution S4 or S5, wherein the timing detector is configured to generate the waveform timing information based on the trigger signal.

[0063] S7. The analog-to-digital conversion system of solution S2, wherein the clock generation circuit comprises: a second output, coupled to the input of the signal source, operable to provide the signal clock.

[0064] S8. The analog-to-digital conversion system of any of solutions SI to S7, wherein the timing detector is configured to generate the waveform timing information based on the digitized repetitive signal.

[0065] S9. The analog-to-digital conversion system of any of solutions SI to S7, wherein the timing detector is configured to generate the waveform timing information based on the analog repetitive signal.

[0066] S10. The analog-to-digital conversion system of any of solutions S I to S7, wherein a trigger repetition rate is equal to the waveform repetition rate divided by a natural number.

[0067] SI 1. The analog-to-digital conversion system of solution S10, wherein a frequency of the trigger repetition rate (fT) is configured to be adjusted based on a nominal frequency of the trigger repetition rate (fr,nom)’and wherein the frequency of the ADC sample rate (fs) is configured to be adjusted based on a nominal frequency of the ADC sample rate (Js.nom)-

[0068] S12. The analog-to-digital conversion system of solution Si l, wherein the clock generation circuit is configured to: determine a nearest integer (Aopt) to a nominal number of samples per trigger period (Nnom= fs.nom / fr.nom) such that the number of ADCs (M) and the nearest integer (Aopt) are relatively prime.

[0069] S13. The analog-to-digital conversion system of solution SI 2, wherein determining the nearest integer is based on a Jacobsthal function.

[0070] S14. A clock generation circuit, comprising: an output configured to be coupled to an input of a bank of analog-to-digital converters (ADCs) to provide an ADC clock associated with an ADC sample rate; and one or more processors, coupled to the output, configured to adjust at least one parameter of the ADC clock or a signal clock with a waveform repetition rate such that (a) a ratio of a frequency of the ADC sample rate to a frequency of the waveform repetition rateInternational Patent ApplicationAttorney Docket No.: 077518.8195.WO00 / IL-13987-02 and (b) a number of ADCs in the bank of ADCs are relatively prime, wherein the signal clock is phase locked to the ADC clock, wherein a digitized repetitive signal is generated based on the ADC clock and an analog repetitive signal, and wherein a digital averaged waveform is generated, based on a waveform timing information, by aligning each waveform of the digitized repetitive signal.

[0071] SI 5. The clock generation circuit of solution S14, wherein the analog repetitive signal is generated based on the signal clock.

[0072] SI 6. The clock generation circuit of solution S14 or S15, wherein the waveform timing information is generated based on the digitized repetitive signal.

[0073] SI 7. The clock generation circuit of solution S14 or S15, wherein the waveform timing information is generated based on the signal clock.

[0074] S18. The clock generation circuit of any of solutions S14 to S17, wherein a trigger repetition rate is the waveform repetition rate divided by a natural number,

[0075] SI 9. The clock generation circuit of solution SI 8, wherein determining the nearest integer is based on a Jacobsthal function.

[0076] S20. A method (e.g., method 1200 illustrated in FIG. 12) for generating a clock signal for improved waveform processing, comprising: providing (1210), by a clock generation circuit, an analog-to-digital (ADC) clock to a bank of ADCs, wherein the ADC clock is associated with an ADC sample rate; and adjusting (1220) at least one parameter of the ADC clock or a signal clock with a waveform repetition rate such that (a) a ratio of a frequency of the ADC sample rate to a frequency of the waveform repetition rate and (b) a number of ADCs in the bank of ADCs are relatively prime, wherein the signal clock is phase locked to the ADC clock, wherein a digitized repetitive signal is generated based on the ADC clock and an analog repetitive signal, and wherein a digital averaged waveform is generated, based on a waveform timing information, by aligning each waveform of the digitized repetitive signal.

[0077] S21. The method of solution S20, wherein the analog repetitive signal is generated based on the signal clock.

[0078] S22. The method of solution S20 or S21, wherein the waveform timing information is generated based on the digitized repetitive signal.International Patent ApplicationAttorney Docket No.: 077518.8195.WO00 / IL-13987-02

[0079] S23. The method of solution S20 or S21, wherein the waveform timing information is generated based on the analog repetitive signal.

[0080] S24. The method of solution S20 or S21, wherein the waveform timing information is generated based on the signal clock.

[0081] S25. The method of any of solutions S20 to S24, wherein a trigger repetition rate is equal to the waveform repetition rate divided by a natural number, wherein the frequency of the trigger repetition rate ( / ’r) is configured to be adjusted based on a nominal frequency of the trigger repetition rateand wherein the frequency of the ADC sample rate (fs) is configured to be adjusted based on a nominal frequency of the ADC sample rate (fs,nom),and wherein the method comprises: determining, by the clock generation circuit, a nearest integer (Nopt) to a nominal number of samples per trigger period (Nnom= fs.nom / fr.nom)such that the number of ADCs (M) and the nearest integer (Nopt) are relatively prime.

[0082] S26. The method of solution S25, wherein an integer fractional resolution of the clock generation circuit is a multiple of the nominal frequency of the ADC sample rate (fs,nom)-

[0083] S27. A method (e.g., method 1300 illustrated in FIG. 13) for producing an improved digital waveform, comprising: generating (1310), by a bank of analog-to-digital converters (ADCs), a digitized repetitive signal based on an analog repetitive signal and an ADC clock that is phase locked with a signal clock with a waveform repetition rate, the ADC clock being used to generate an ADC sample rate; generating (1320), by a timing detector, a waveform timing information; adjusting (1330), by a clock generation circuit, at least one parameter of the signal clock or the ADC clock such that (a) a ratio of a frequency of the ADC sample rate and a frequency of the waveform repetition rate and (b) a number of ADCs in the bank of ADCs are relatively prime; and generating (1340), by a synchronized averaging circuit subsequent to the adjusting, a digital averaged waveform by aligning, based on the waveform timing information, each waveform of the digitized repetitive signal.

[0084] S28. The method of solution S27, comprising: generating, by a signal source, the analog repetitive signal.

[0085] S29. The method of solution S27 or S28, comprising: generating, by a signal clock source, the signal clock.International Patent ApplicationAttorney Docket No.: 077518.8195.WO00 / IL-13987-02

[0086] S30. The method of solution S27 or S28, comprising: generating, by the clock generation circuit, the signal clock.

[0087] S31. The method of any of solutions S27 to S30, wherein generating the waveform timing information is based on the signal clock.

[0088] S32. The method of any of solutions S27 to S30, wherein generating the waveform timing information is based on the digitized repetitive signal.

[0089] S33. The method of any of solutions S27 to S30, wherein generating the waveform timing information is based on the analog repetitive signal.

[0090] In some embodiments, the above-enumerated technical solutions SI through S33 are directed to synchronized detuning of the ADC sample rate and trigger repetition rate to achieve co-prime-ness of samples-per-trigger N with number of ADC cores M, thereby decorrelating interleaving artifacts during waveform averaging.

[0091] While this document contains many specifics, these should not be construed as limitations on the scope of an invention that is claimed or of what may be claimed, but rather as descriptions of features specific to particular embodiments. Certain features that are described in this document in the context of separate embodiments can also be implemented in combination in a single embodiment. Conversely, various features that are described in the context of a single embodiment can also be implemented in multiple embodiments separately or in any suitable subcombination. Moreover, although features may be described above as acting in certain combinations and even initially claimed as such, one or more features from a claimed combination can in some cases be excised from the combination, and the claimed combination may be directed to a sub-combination or a variation of a sub-combination.

[0092] Similarly, while operations are depicted in the drawings in a particular order, this should not be understood as requiring that such operations be performed in the particular order shown or in sequential order, or that all illustrated operations be performed, to achieve desirable results. Moreover, the separation of various system components in the embodiments described in this patent document should not be understood as requiring such separation in all embodiments.

[0093] It is understood that at least some of the component of the disclosed embodiments may be implemented individually, or collectively, in devices comprised of a processor, aInternational Patent ApplicationAttorney Docket No.: 077518.8195.WO00 / IL-13987-02 memory unit, an interface that are communicatively connected to each other. The processor and / or controller can perform various disclosed operations based on execution of program code that is stored on a storage medium. The processor and / or controller can, for example, be in communication with at least one memory and with at least one communication unit that enables the exchange of data and information, directly or indirectly, through the communication link with other entities, devices and networks. The communication unit may provide wired and / or wireless communication capabilities in accordance with one or more communication protocols, and therefore it may comprise the proper transmitter / receiver antennas, circuitry and ports, as well as the encoding / decoding capabilities that may be necessary for proper transmission and / or reception of data and other information.

[0094] Various information and data processing operations described herein may be implemented in one embodiment by a computer program product, embodied in a computer- readable medium, including computer-executable instructions, such as program code, executed by computers in networked environments. A computer-readable medium may include removable and non-removable storage devices including, but not limited to, Read Only Memory (ROM), Random Access Memory (RAM), compact discs (CDs), digital versatile discs (DVD), etc. Therefore, the computer-readable media that is described in the present application comprises non-transitory storage media. Generally, program modules may include routines, programs, objects, components, data structures, etc. that perform particular tasks or implement particular abstract data types. Computer-executable instructions, associated data structures, and program modules represent examples of program code for executing steps of the methods disclosed herein. The particular sequence of such executable instructions or associated data structures represents examples of corresponding acts for implementing the functions described in such steps or processes.

[0095] Only a few implementations and examples are described, and other implementations, enhancements, and variations can be made based on what is described and illustrated in this disclosure.

Claims

International Patent ApplicationAttorney Docket No.: 077518.8195.WO00 / IL-13987-02WHAT IS CLAIMED IS:

1. An analog-to-digital conversion system, comprising: a bank of analog-to-digital converters (ADCs) comprising: a first input to receive an analog repetitive signal comprising repeated waveforms, a second input to receive an ADC clock that is phase locked with a signal clock with a waveform repetition rate, the ADC clock being used to generate an ADC sample rate, and an output operable to provide a digitized repetitive signal; a synchronized averaging circuit comprising: a first input, coupled to the output of the bank of ADCs, to receive the digitized repetitive signal, a second input to receive a waveform timing information, and an output operable to provide a digital averaged waveform generated by aligning, based on the waveform timing information, each waveform of the digitized repetitive signal; a timing detector comprising: an output, coupled to the second input of the synchronized averaging circuit, operable to provide the waveform timing information associated with the repeated waveforms of the analog repetitive signal; and a clock generation circuit comprising: a first output, coupled to the second input of the bank of ADCs, operable to provide the ADC clock, wherein the clock generation circuit is configured to adjust at least one parameter of the signal clock or the ADC clock such that (a) a ratio of a frequency of the ADC sample rate and a frequency of the waveform repetition rate and (b) a number of ADCs in the bank of ADCs are relatively prime.

2. The analog-to-digital conversion system of claim 1, comprising: a signal source comprising:International Patent ApplicationAttorney Docket No.: 077518.8195.WO00 / IL-13987-02 an input to receive the signal clock; and an output, coupled to the first input of the bank of ADCs, operable to provide the analog repetitive signal generated based on the signal clock.

3. The analog-to-digital conversion system of claim 2, comprising: a signal clock source comprising: a first output, coupled to an input of the clock generation circuit, operable to provide the signal clock; and a second output, coupled to the input of signal source, operable to provide the signal clock.

4. The analog-to-digital conversion system of claim 2 or 3, comprising: a trigger signal source comprising: an input, coupled to a second output of the clock generation circuit, to receive a trigger clock and generate a trigger signal based thereupon; and an output, coupled to the input of the timing detector, operable to provide the trigger signal comprising the waveform timing information.

5. The analog-to-digital conversion system of claim 4, wherein the timing detector is configured to receive the trigger signal from the trigger signal source.

6. The analog-to-digital conversion system of claim 4 or 5, wherein the timing detector is configured to generate the waveform timing information based on the trigger signal.

7. The analog-to-digital conversion system of claim 2, wherein the clock generation circuit comprises: a second output, coupled to the input of the signal source, operable to provide the signal clock.

8. The analog-to-digital conversion system of any of claims 1 to 7, wherein the timing detector is configured to generate the waveform timing information based on the digitized repetitive signal.International Patent ApplicationAttorney Docket No.: 077518.8195.WO00 / IL-13987-029. The analog-to-digital conversion system of any of claims 1 to 7, wherein the timing detector is configured to generate the waveform timing information based on the analog repetitive signal.

10. The analog-to-digital conversion system of any of claims 1 to 7, wherein a trigger repetition rate is equal to the waveform repetition rate divided by a natural number.11 . The analog-to-digital conversion system of claim 10, wherein a frequency of the trigger repetition rate (fT) is configured to be adjusted based on a nominal frequency of the trigger repetition rate (fr / nom)-, and wherein the frequency of the ADC sample rate (fs) is configured to be adjusted based on a nominal frequency of the ADC sample rate (fs,nOm)-12. The analog-to-digital conversion system of claim 11, wherein the clock generation circuit is configured to: determine a nearest integer ( Vopt) to a nominal number of samples per trigger period (Nnom— fs.nom / fr.nom ) such that the number of ADCs (M) and the nearest integer (Nopt) are relatively prime.

13. The analog-to-digital conversion system of claim 12, wherein determining the nearest integer is based on a Jacobsthal function.

14. A clock generation circuit, comprising: an output configured to be coupled to an input of a bank of analog-to-digital converters (ADCs) to provide an ADC clock associated with an ADC sample rate; and one or more processors, coupled to the output, configured to adjust at least one parameter of the ADC clock or a signal clock with a waveform repetition rate such that (a) a ratio of a frequency of the ADC sample rate to a frequency of the waveform repetition rate and (b) a number of ADCs in the bank of ADCs are relatively prime, wherein the signal clock is phase locked to the ADC clock, wherein a digitized repetitive signal is generated based on the ADC clock and an analog repetitive signal, andInternational Patent ApplicationAttorney Docket No.: 077518.8195.WO00 / IL-13987-02 wherein a digital averaged waveform is generated, based on a waveform timing information, by aligning each waveform of the digitized repetitive signal.

15. The clock generation circuit of claim 14, wherein the analog repetitive signal is generated based on the signal clock.

16. The clock generation circuit of claim 14 or 15, wherein the waveform timing information is generated based on the digitized repetitive signal.

17. The clock generation circuit of claim 14 or 15, wherein the waveform timing information is generated based on the signal clock.

18. The clock generation circuit of any of claims 14 to 17, wherein a trigger repetition rate is the waveform repetition rate divided by a natural number, wherein a frequency of the trigger repetition rate ( / ’r) is configured to be adjusted based on a nominal frequency of the trigger repetition rate (r Tlom),and wherein the frequency of the ADC sample rate (fs) is configured to be adjusted based on a nominal frequency of the ADC sample rate (fs,nom and wherein the clock generation circuit is configured to: determine a nearest integer (!Vopt) to a nominal number of samples per trigger period (^nom=fs.nom / fr.nom) such that the number of ADCs (M) and the nearest integer (Nopt) are relatively prime.

19. The clock generation circuit of claim 18, wherein determining the nearest integer is based on a Jacob sthal function.

20. A method for generating a clock signal for improved waveform processing, comprising: providing, by a clock generation circuit, an analog-to-digital (ADC) clock to a bank ofADCs, wherein the ADC clock is associated with an ADC sample rate; and adjusting at least one parameter of the ADC clock or a signal clock with a waveform repetition rate such that (a) a ratio of a frequency of the ADC sample rate to a frequency of the waveform repetition rate and (b) a number of ADCs in the bank of ADCs are relatively prime, wherein the signal clock is phase locked to the ADC clock,International Patent ApplicationAttorney Docket No.: 077518.8195.WO00 / IL-13987-02 wherein a digitized repetitive signal is generated based on the ADC clock and an analog repetitive signal, and wherein a digital averaged waveform is generated, based on a waveform timing information, by aligning each waveform of the digitized repetitive signal.

21. The method of claim 20, wherein the analog repetitive signal is generated based on the signal clock.

22. The method of claim 20 or 21, wherein the waveform timing information is generated based on the digitized repetitive signal.

23. The method of claim 20 or 21, wherein the waveform timing information is generated based on the analog repetitive signal.

24. The method of claim 20 or 21, wherein the waveform timing information is generated based on the signal clock.

25. The method of any of claims 20 to 24, wherein a trigger repetition rate is equal to the waveform repetition rate divided by a natural number, wherein the frequency of the trigger repetition rate (fT) is configured to be adjusted based on a nominal frequency of the trigger repetition rate (fr.nom)-. and wherein the frequency of the ADC sample rate (fs) is configured to be adjusted based on a nominal frequency of the ADC sample rate (fs,nom) and wherein the method comprises: determining, by the clock generation circuit, a nearest integer (Nopt) to a nominal number of samples per trigger period (Nnom= fs.nom / fr,nom) such that the number of ADCs (M) and the nearest integer (Nopt) are relatively prime.

26. The method of claim 25, wherein an integer fractional resolution of the clock generation circuit is a multiple of the nominal frequency of the ADC sample rate (fs.nom)-International Patent ApplicationAttorney Docket No.: 077518.8195.WO00 / IL-13987-0227. A method for producing an improved digital waveform, comprising: generating, by a bank of analog-to-digital converters (ADCs), a digitized repetitive signal based on an analog repetitive signal and an ADC clock that is phase locked with a signal clock with a waveform repetition rate, the ADC clock being used to generate an ADC sample rate; generating, by a timing detector, a waveform timing information; adjusting, by a clock generation circuit, at least one parameter of the signal clock or the ADC clock such that (a) a ratio of a frequency of the ADC sample rate and a frequency of the waveform repetition rate and (b) a number of ADCs in the bank of ADCs are relatively prime; and generating, by a synchronized averaging circuit subsequent to the adjusting, a digital averaged waveform by aligning, based on the waveform timing information, each waveform of the digitized repetitive signal.

28. The method of claim 27, comprising: generating, by a signal source, the analog repetitive signal.

29. The method of claim 27 or 28, comprising: generating, by a signal clock source, the signal clock.

30. The method of claim 27 or 28, comprising: generating, by the clock generation circuit, the signal clock.

31. The method of any of claims 27 to 30, wherein generating the waveform timing information is based on the signal clock.

32. The method of any of claims 27 to 30, wherein generating the waveform timing information is based on the digitized repetitive signal.

33. The method of any of claims 27 to 30, wherein generating the waveform timing information is based on the analog repetitive signal.

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