Display substrate and display device

Abstract

A display substrate, comprising: a base, a plurality of pixel circuits arranged on the base, a plurality of light-emitting elements, and an isolation structure (51). The light-emitting elements (ELs) each comprise a first electrode, a light-emitting functional layer, and a second electrode which are sequentially arranged in a direction away from the base. A first electrode of a light-emitting element (EL) is connected to a first power line (VDD), and a second electrode of the light-emitting element (EL) is connected to a pixel circuit. The isolation structure (51) is located on the side of the first electrodes of the light-emitting elements (ELs) away from the base. The isolation structure (51) is provided with a plurality of grids (510), and each grid (510) surrounds a light-emitting region of at least one of the light-emitting elements (EL). The isolation structure (51) is configured to isolate the second electrodes of the light-emitting elements (EL) located in adjacent grids (510).

Description

Display substrate and display device Technical Field

[0001] This article relates to, but is not limited to, the field of display technology, and in particular to a display substrate and a display device. Background Technology

[0002] Organic light-emitting diodes (OLEDs) and quantum dot light-emitting diodes (QLEDs) are active light-emitting display devices with advantages such as self-illumination, wide viewing angle, high contrast, low power consumption, extremely high response speed, thinness, flexibility, and low cost. Summary of the Invention

[0003] The following is an overview of the subject matter described in detail herein. This overview is not intended to limit the scope of the claims.

[0004] This disclosure provides a display substrate and a display device.

[0005] On one hand, this embodiment provides a display substrate, including: a substrate, a plurality of pixel circuits disposed on the substrate, a plurality of light-emitting elements, and an isolation structure. The substrate includes a display area and a peripheral area surrounding the display area. The plurality of pixel circuits and the plurality of light-emitting elements are located in the display area. At least one of the plurality of light-emitting elements includes: a first electrode, a light-emitting functional layer, and a second electrode sequentially disposed along a direction away from the substrate. The first electrode of the at least one light-emitting element is connected to a first power line, and the second electrode of the at least one light-emitting element is connected to at least one pixel circuit among the plurality of pixel circuits. The isolation structure is located on the side of the first electrode of the at least one light-emitting element away from the substrate. The isolation structure has a plurality of grids, each grid surrounding the light-emitting area of ​​the at least one light-emitting element. The isolation structure is configured to isolate the second electrodes of the light-emitting elements in adjacent grids.

[0006] In some exemplary embodiments, the isolation structure includes: a first isolation layer and a second isolation layer, the second isolation layer being located on the side of the first isolation layer away from the substrate, and the hardness of the material of the second isolation layer being greater than the hardness of the material of the first isolation layer.

[0007] In some exemplary embodiments, the material of the first isolation layer includes an organic material; the material of the second isolation layer includes at least one of the following: inorganic material, chemical mechanical polishing material, and metallic material.

[0008] In some exemplary embodiments, the first isolation layer includes an isolation body portion and an isolation extension portion, the isolation extension portion being located on the side of the isolation body portion away from the substrate, and the isolation extension portion protruding from the sidewall of the isolation body portion in a direction parallel to the substrate.

[0009] In some exemplary embodiments, the orthographic projection of the surface of the first isolation layer away from the substrate onto the substrate includes the orthographic projection of the surface of the first isolation layer near the substrate onto the substrate. The first isolation layer comprises: a plurality of cross-sectional layers parallel to the plane of the substrate along a direction away from the substrate; the area of ​​the plurality of cross-sectional layers gradually decreases and then gradually increases along the direction away from the substrate, or gradually increases along the direction away from the substrate.

[0010] In some exemplary embodiments, the display substrate further includes a plurality of first transition electrodes. The second electrode of the at least one light-emitting element is connected to the pixel circuit via the first transition electrodes; the first transition electrodes are located on the side of the second electrode closer to the substrate. Each first transition electrode includes a first end connected to the second electrode and a second end connected to the pixel circuit; the first ends of the plurality of first transition electrodes are arranged in a concentrated manner.

[0011] In some exemplary embodiments, the display substrate further includes a plurality of second transition electrodes. The second electrode of the at least one light-emitting element is connected to the first transition electrode via the second transition electrode, wherein the second transition electrode is located on the side of the first transition electrode away from the substrate and on the side of the second electrode close to the substrate.

[0012] In some exemplary embodiments, the plurality of second transfer electrodes and the first electrode of the at least one light-emitting element are in the same layer structure.

[0013] In some exemplary embodiments, the second electrode of the at least one light-emitting element is connected to the second transfer electrode via a lap electrode located on the side of the second electrode away from the substrate; the lap electrode is in direct contact with the second electrode and the second transfer electrode.

[0014] In some exemplary embodiments, the plurality of light-emitting elements includes: a plurality of light-emitting element groups. At least one of the plurality of light-emitting element groups includes: a first light-emitting element emitting a first color light, a second light-emitting element emitting a second color light, and a third light-emitting element emitting a third color light. The first light-emitting element and the second light-emitting element are located on the same side of the third light-emitting element along a first direction, and the first light-emitting element and the second light-emitting element are aligned along a second direction, wherein the first direction and the second direction intersect. A set of second transition electrodes includes: a plurality of second transition electrodes that are connected one-to-one with the first ends of the plurality of centrally arranged first transition electrodes; the set of second transition electrodes is located between two adjacent light-emitting element groups along the second direction.

[0015] In some exemplary embodiments, the plurality of light-emitting element groups include: a plurality of first-arranged light-emitting element groups and a plurality of second-arranged light-emitting element groups, wherein the arrangement order of the first and second light-emitting elements in the first-arranged light-emitting element groups along the second direction is reversed compared to the arrangement order of the first and second light-emitting elements in the second-arranged light-emitting element groups along the second direction. The plurality of first-arranged light-emitting element groups and the plurality of second-arranged light-emitting element groups are arranged at intervals along the first direction and at intervals along the second direction. The set of second transition electrodes is located between the third light-emitting elements of the adjacent first-arranged light-emitting element groups and the third light-emitting elements of the adjacent second-arranged light-emitting element groups along the second direction.

[0016] In some exemplary embodiments, the set of second transition electrodes includes six second transition electrodes arranged in an array along the first direction and the second direction.

[0017] In some exemplary embodiments, the first power line is located on the side of the conductive layer containing the plurality of first transition electrodes away from the substrate, and on the side of the conductive layer containing the plurality of second transition electrodes close to the substrate.

[0018] In some exemplary embodiments, the first power line connected to the first electrode of at least one of the plurality of light-emitting elements overlaps with the pixel circuit connected to the second electrode of the at least one light-emitting element in the orthogonal projection of the substrate.

[0019] In some exemplary embodiments, the display substrate further includes a plurality of third transition electrodes. The first transition electrode is connected to the second transition electrode via the third transition electrodes, and the third transition electrodes and the first power line are in the same layer.

[0020] In some exemplary embodiments, in a direction perpendicular to the display substrate, the display substrate includes: a first conductive layer, a semiconductor layer, a second conductive layer, a third conductive layer, a fourth conductive layer, and a fifth conductive layer sequentially disposed on the substrate. The plurality of first transition electrodes are located on the fourth conductive layer, and the plurality of third transition electrodes and the first power line are located on the fifth conductive layer.

[0021] In some exemplary embodiments, at least one pixel circuit in the plurality of pixel circuits includes: a driving transistor, a compensation transistor, a first capacitor, and a second capacitor; a first electrode of the first capacitor is connected to the gate of the driving transistor, a second electrode of the first capacitor is connected to the second electrode of the compensation transistor, a first electrode of the compensation transistor is connected to the first electrode of the driving transistor and the first electrode of the second capacitor, and a second electrode of the second capacitor is connected to a second power line. The second electrode of the first capacitor includes: a first sub-electrode and a second sub-electrode connected to each other, the first sub-electrode of the first capacitor being located on the side of the second sub-electrode closer to the substrate, and the second electrode of the first capacitor being located on the side of the first sub-electrode away from the substrate and on the side of the second sub-electrode closer to the substrate. The first electrode of the second capacitor is located on the side of the second electrode of the second capacitor closer to the substrate, and the first electrode of the second capacitor and the second sub-electrode of the first capacitor are of the same layer structure.

[0022] In some exemplary embodiments, the active layer of the driving transistor is projected in an L-shape onto the substrate.

[0023] On the other hand, this embodiment provides a display device including the display substrate as described above.

[0024] On the other hand, this embodiment provides a display substrate, including: a substrate, a plurality of pixel circuits and a plurality of light-emitting elements disposed on the substrate. The substrate includes a display area and a peripheral area surrounding the display area. The plurality of pixel circuits and the plurality of light-emitting elements are located in the display area. The light-emitting elements include: a first electrode, a light-emitting functional layer and a second electrode disposed sequentially along a direction away from the substrate; the first electrode is connected to a first power line, and the second electrode is connected to the pixel circuit. At least one pixel circuit includes: a driving transistor, a compensation transistor, a first capacitor and a second capacitor; the first electrode of the first capacitor is connected to the gate of the driving transistor, the second electrode of the first capacitor is connected to the second electrode of the compensation transistor, the first electrode of the compensation transistor is connected to the first electrode of the driving transistor and the first electrode of the second capacitor, and the second electrode of the second capacitor is connected to a second power line. The second electrode of the first capacitor includes: a first sub-electrode and a second sub-electrode connected to each other, the first sub-electrode of the first capacitor is located on the side of the second sub-electrode closer to the substrate, and the second electrode of the first capacitor is located on the side of the first sub-electrode away from the substrate and on the side of the second sub-electrode closer to the substrate. The first electrode of the second capacitor is located on the side of the second electrode of the second capacitor closer to the substrate, and the first electrode of the second capacitor and the second sub-electrode of the first capacitor are of the same layer structure.

[0025] In some exemplary embodiments, the active layer of the driving transistor is projected in an L-shape onto the substrate.

[0026] In some exemplary embodiments, the at least one pixel circuit further includes: a data writing transistor, the gate of which is connected to a first scan line, a first electrode of which is connected to a data line, and a second electrode of which is connected to the second electrode of the compensation transistor and the second electrode of the first capacitor. The active layer of the compensation transistor and the active layer of the data writing transistor are integral structures and are located on the same side of the first capacitor and the driving transistor along the second direction.

[0027] In some exemplary embodiments, the at least one pixel circuit further includes: a first reset transistor, a second reset transistor, and a third reset transistor. The gate of the first reset transistor is connected to a first reset control line, the first terminal of the first reset transistor is connected to a first initial signal line, and the second terminal of the first reset transistor is connected to the second terminal of the driving transistor. The gate of the second reset transistor is connected to a second reset control line, the first terminal of the second reset transistor is connected to a second initial signal line, and the second terminal of the second reset transistor is connected to the first terminal of the driving transistor. The gate of the third reset transistor is connected to a third reset control line, the first terminal of the third reset transistor is connected to a reference signal line, and the second terminal of the third reset transistor is connected to the gate of the driving transistor. The first reset transistor and the third reset transistor are located on the same side of the driving transistor along a second direction, and the second reset transistor is located on the other side of the driving transistor along the second direction. The first reset control line, the second reset control line, and the third reset control line are in the same layer, and the first initial signal line, the second initial signal line, and the reference signal line are in the same layer.

[0028] In some exemplary embodiments, the at least one pixel circuit further includes: a fourth reset transistor; the gate of the fourth reset transistor is connected to a fourth reset control line, the first electrode of the fourth reset transistor is connected to a third initial signal line, and the second electrode of the fourth reset transistor is connected to the second electrode of the light-emitting element. Multiple pixel circuits arranged along a first direction constitute a row of pixel circuits, and the gate of the second reset transistor in one row of pixel circuits and the gate of the fourth reset transistor in another row of pixel circuits are integrally formed.

[0029] In some exemplary embodiments, the at least one pixel circuit further includes: a first light-emitting control transistor and a second light-emitting control transistor. The gate of the first light-emitting control transistor is connected to a light-emitting control line, a first electrode of the first light-emitting control transistor is connected to a second electrode of the driving transistor, and the second electrode of the first light-emitting control transistor is connected to a second electrode of the light-emitting element. The gate of the second light-emitting control transistor is connected to the light-emitting control line, a first electrode of the second light-emitting control transistor is connected to a second power supply line, and the second electrode of the second light-emitting control transistor is connected to a first electrode of the driving transistor. The first light-emitting control transistor and the second light-emitting control transistor of the at least one pixel circuit are aligned along a first direction; the active layer of the first light-emitting control transistor and the active layer of the first reset control transistor are integrally formed.

[0030] In some exemplary embodiments, in a direction perpendicular to the display substrate, the display substrate includes: a first conductive layer, a semiconductor layer, a second conductive layer, a third conductive layer, a fourth conductive layer, and a fifth conductive layer sequentially disposed on the substrate. The first conductive layer includes: the bottom gate of at least one transistor of the at least one pixel circuit; the semiconductor layer includes: the active layer of at least one transistor of the at least one pixel circuit; the second conductive layer includes: the gate of at least one transistor of the at least one pixel circuit; the second power line is located on the fifth conductive layer; the first sub-electrode of the first capacitor is located on the first conductive layer, the second sub-electrode of the first capacitor is located on the third conductive layer, and the first electrode of the first capacitor is located on the second conductive layer; the first electrode of the second capacitor is located on the third conductive layer, and the second electrode of the second capacitor is located on the fifth conductive layer.

[0031] In some exemplary embodiments, the material of the semiconductor layer includes an oxide semiconductor material.

[0032] After reading and understanding the accompanying diagrams and detailed descriptions, the other aspects can be understood.

[0033] Overview of the attached figures

[0034] The accompanying drawings are used to provide an understanding of the technical solutions of this application and constitute a part of the specification. They are used together with the embodiments of this application to explain the technical solutions of this application and do not constitute a limitation on the technical solutions of this application.

[0035] Figure 1 is a schematic diagram of a display substrate according to at least one embodiment of the present disclosure;

[0036] Figure 2 is a schematic diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0037] Figure 3 is an example of the operating timing diagram of the pixel circuit shown in Figure 2;

[0038] Figure 4 is a schematic diagram showing the connection between the pixel circuit and the light-emitting element in at least one embodiment of the present disclosure;

[0039] Figure 5 is a partial schematic diagram of a display substrate after the formation of the first conductive layer in at least one embodiment of the present disclosure;

[0040] Figure 6A is a partial schematic diagram of a display substrate after a semiconductor layer has been formed in at least one embodiment of the present disclosure;

[0041] Figure 6B is a schematic diagram of the semiconductor layer in Figure 6A;

[0042] Figure 7A is a partial schematic diagram of a display substrate after the formation of the second conductive layer in at least one embodiment of the present disclosure;

[0043] Figure 7B is a schematic diagram of the second conductive layer in Figure 7A;

[0044] Figure 8 is a partial schematic diagram of the display substrate after the formation of the third insulating layer in at least one embodiment of the present disclosure;

[0045] Figure 9A is a partial schematic diagram of a display substrate after the formation of the third conductive layer in at least one embodiment of the present disclosure;

[0046] Figure 9B is a schematic diagram of the third conductive layer in Figure 9A;

[0047] Figure 10 is a partial schematic diagram of the display substrate after the fourth insulating layer is formed in at least one embodiment of the present disclosure;

[0048] Figure 11A is a partial schematic diagram of a display substrate after the fourth conductive layer has been formed in at least one embodiment of the present disclosure;

[0049] Figure 11B is a schematic diagram of the fourth conductive layer in Figure 11A;

[0050] Figure 12 is a partial schematic diagram of the display substrate after the fifth insulating layer is formed in at least one embodiment of the present disclosure;

[0051] Figure 13A is a partial schematic diagram of a display substrate after the fifth conductive layer has been formed in at least one embodiment of the present disclosure;

[0052] Figure 13B is a schematic diagram of the fifth conductive layer in Figure 13A;

[0053] Figure 14 is a partial schematic diagram of the fourth conductive layer according to at least one embodiment of the present disclosure;

[0054] Figure 15 is a partial schematic diagram of the fourth and fifth conductive layers of at least one embodiment of the present disclosure;

[0055] Figure 16 is a partial schematic diagram of the fifth conductive layer according to at least one embodiment of the present disclosure;

[0056] Figure 17 is a partial schematic diagram of the display substrate after the formation of the sixth insulating layer in at least one embodiment of the present disclosure;

[0057] Figure 18 is a schematic diagram of the arrangement of multiple light-emitting elements according to at least one embodiment of the present disclosure;

[0058] Figure 19 is a partial schematic diagram of a display substrate after the anode layer has been formed in at least one embodiment of the present disclosure;

[0059] Figure 20 is a schematic diagram of the anode layer in Figure 19;

[0060] Figure 21 is a partial schematic diagram of the display substrate after the pixel definition layer is formed in at least one embodiment of the present disclosure;

[0061] Figure 22A is a schematic diagram of a display substrate after forming an isolation structure in at least one embodiment of the present disclosure;

[0062] Figure 22B is a plan view of the isolation structure in Figure 22A;

[0063] Figure 22C is a partial cross-sectional view along the PP' direction in Figure 22A;

[0064] Figure 22D is a partial cross-sectional view along the QQ' direction in Figure 22A;

[0065] Figure 23 is a schematic diagram of a display substrate after the cathode layer has been formed in at least one embodiment of the present disclosure;

[0066] Figure 24 is a magnified view of a portion of region O1 in Figure 23;

[0067] Figure 25A is a partial cross-sectional view of the display substrate along the PP' direction after the auxiliary conductive layer is formed in at least one embodiment of the present disclosure;

[0068] Figure 25B is a partial cross-sectional view of the display substrate along the QQ' direction after the auxiliary conductive layer is formed in at least one embodiment of the present disclosure.

[0069] Figure 26A is another partial cross-sectional view of the display substrate along the PP' direction after the auxiliary conductive layer has been formed in at least one embodiment of the present disclosure.

[0070] Figure 26B is another partial cross-sectional view of the display substrate along the QQ' direction after the formation of the auxiliary conductive layer in at least one embodiment of the present disclosure.

[0071] Figure 27 is another partial cross-sectional view of the display substrate along the QQ' direction after the formation of the auxiliary conductive layer in at least one embodiment of the present disclosure;

[0072] Figure 28 is another partial cross-sectional view of the display substrate along the QQ' direction after the formation of the auxiliary conductive layer in at least one embodiment of the present disclosure;

[0073] Figure 29 is a schematic diagram of a display device according to at least one embodiment of the present disclosure.

[0074] Detailed Explanation

[0075] The embodiments of this disclosure will now be described in detail with reference to the accompanying drawings. The implementation can be carried out in many different forms. Those skilled in the art will readily understand that the methods and content can be transformed into other forms without departing from the spirit and scope of this disclosure. Therefore, this disclosure should not be construed as limited to the content described in the following embodiments. Unless otherwise specified, the embodiments and features in the embodiments of this disclosure can be arbitrarily combined with each other.

[0076] In the accompanying drawings, the size of one or more constituent elements, the thickness of layers, or areas are sometimes exaggerated for clarity. Therefore, this disclosure is not necessarily limited to these dimensions, and the shape and size of one or more parts in the drawings do not reflect true proportions. Furthermore, the drawings schematically illustrate ideal examples, and this disclosure is not limited to the shapes or values ​​shown in the drawings.

[0077] The ordinal numbers such as "first," "second," and "third" used in this specification are used to avoid confusion among the constituent elements, not to limit the quantity. The term "multiple" in this disclosure refers to two or more quantities.

[0078] In this specification, for convenience, terms such as "middle," "upper," "lower," "front," "rear," "vertical," "horizontal," "top," "bottom," "inner," and "outer" are used to indicate orientation or positional relationships in conjunction with the accompanying drawings. This is solely for the purpose of facilitating the description and simplification, and does not imply that the device or component referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, it should not be construed as a limitation of this disclosure. The positional relationships of the constituent elements may be appropriately varied depending on the orientation of the constituent elements being described. Therefore, the use of terms not limited to those described in the specification may be appropriately replaced as needed.

[0079] In this specification, unless otherwise expressly specified and limited, the terms "installation," "connection," and "joining" should be interpreted broadly. For example, they may refer to a fixed connection, a detachable connection, or an integral connection; a mechanical connection or joint; a direct connection, an indirect connection via an intermediate component, or a connection within two components. Those skilled in the art will understand the meaning of these terms in this disclosure as appropriate.

[0080] In this specification, "connection" can include "electrical connection." "Electrical connection" includes situations where components are connected together by elements that have some electrical function. There are no particular limitations on the "elements that have some electrical function," as long as they enable the transmission of electrical signals between the connected components. Examples of "elements that have some electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other multifunctional elements.

[0081] In this specification, a transistor is a device that includes at least three terminals: a gate, a drain, and a source. A transistor has a channel region between its drain (drain terminal, drain region, or drain electrode) and its source (source terminal, source region, or source electrode), and current can flow through the drain, the channel region, and the source. In this specification, the channel region refers to the region through which current primarily flows.

[0082] In this specification, the first terminal can be the drain and the second terminal can be the source, or vice versa. When using transistors with opposite polarities or when the current direction changes during circuit operation, the functions of the "source" and "drain" are sometimes interchanged. Therefore, in this specification, the "source" and "drain" can be interchanged. Additionally, the gate can also be called the control terminal.

[0083] In this specification, "parallel" refers to the state where the angle formed by two straight lines is greater than or equal to -10° and less than 10°, and therefore also includes the state where the angle is greater than or equal to -5° and less than 5°. Similarly, "perpendicular" refers to the state where the angle formed by two straight lines is greater than or equal to 80° and less than 100°, and therefore also includes the state where the angle is greater than or equal to 85° and less than 95°.

[0084] In this specification, circles, ellipses, triangles, rectangles, trapezoids, pentagons, or hexagons are not strictly defined. They can be approximate circles, ellipses, triangles, rectangles, trapezoids, pentagons, or hexagons. Small deformations due to tolerances are possible, such as chamfers, curved edges, and other variations.

[0085] In this disclosure, "about" and "approximately" refer to situations where there are no strict limits and the process and measurement errors are allowed. In this disclosure, "same" can include cases where index values ​​differ by no more than 10%.

[0086] In this disclosure, "A extends along direction B" means that A may include a main part and a secondary part connected to the main part. The main part is a line, line segment, or strip-shaped solid. The main part extends along direction B, and the length of the main part extending along direction B is greater than the length of the secondary part extending along other directions. In this disclosure, "A extends along direction B" refers to "the main part of A extends along direction B".

[0087] In this disclosure, the conduction level signal includes the level signal that turns on the transistor. For example, the conduction level signal that turns on a P-type transistor is a low-level signal, and the conduction level signal that turns on an N-type transistor is a high-level signal.

[0088] In some implementations, the threshold voltage differences between different pixel circuits are significant, making display control difficult. This leads to variations in the driving current, which can easily cause uneven brightness on the display panel and affect image quality. Furthermore, during the patterning process of the cathode layer, the partition structure can easily become suspended, leading to collapse.

[0089] This embodiment provides a display substrate, including: a substrate, a plurality of pixel circuits disposed on the substrate, a plurality of light-emitting elements, and an isolation structure. The substrate includes a display area and a peripheral area surrounding the display area. The plurality of pixel circuits and the plurality of light-emitting elements are located in the display area. At least one of the plurality of light-emitting elements includes: a first electrode, a light-emitting functional layer, and a second electrode sequentially disposed along a direction away from the substrate. The first electrode of the at least one light-emitting element is connected to a first power line, and the second electrode of the at least one light-emitting element is connected to at least one pixel circuit among the plurality of pixel circuits. The isolation structure is located on the side of the first electrode of the at least one light-emitting element away from the substrate. The isolation structure has a plurality of grids, each grid surrounding the light-emitting area of ​​the at least one light-emitting element. The isolation structure is configured to isolate the second electrodes of the light-emitting elements in adjacent grids.

[0090] The display substrate provided in this embodiment can achieve patterning of the film layer where the second electrode is located by setting an isolation structure to isolate the second electrodes of the light-emitting elements in adjacent grids, and can also achieve separate driving of multiple light-emitting elements by multiple pixel circuits.

[0091] In some exemplary embodiments, the isolation structure may include a first isolation layer and a second isolation layer, wherein the second isolation layer may be located on the side of the first isolation layer away from the substrate. The hardness of the material of the second isolation layer may be greater than the hardness of the material of the first isolation layer. In some examples, the material of the first isolation layer may include an organic material; the material of the second isolation layer may include at least one of the following: inorganic materials, chemical mechanical polishing (CMP) materials, and metallic materials. The arrangement in this example allows the isolation structure to isolate the second electrodes of the light-emitting elements in adjacent grids and helps to ensure the stability of the isolation structure.

[0092] In some exemplary embodiments, the first isolation layer may include an isolation main portion and an isolation extension portion. The isolation extension portion may be located on the side of the isolation main portion away from the substrate, and the isolation extension portion may protrude from the sidewall of the isolation main portion in a direction parallel to the substrate. The arrangement of the first isolation layer in this example can ensure the isolation of the second electrodes of the light-emitting elements in adjacent grids.

[0093] In some exemplary embodiments, the orthographic projection of the surface of the first insulating layer away from the substrate onto the substrate may include the orthographic projection of the surface of the first insulating layer near the substrate onto the substrate. The first insulating layer may include a plurality of cross-sectional layers parallel to the plane of the substrate along a direction away from the substrate. The area of ​​the plurality of cross-sectional layers may gradually decrease and then gradually increase along the direction away from the substrate, or it may gradually increase along the direction away from the substrate. In some examples, the cross-section of the first insulating layer may be trapezoidal or approximately mushroom-shaped in a direction perpendicular to the substrate and perpendicular to the extension direction of the first insulating layer. This example is advantageous for patterning the second electrode of the light-emitting element.

[0094] In some exemplary embodiments, the display substrate may include a plurality of first transition electrodes. A second electrode of at least one light-emitting element can be connected to a pixel circuit via the first transition electrode; the first transition electrode may be located on the side of the second electrode closer to the substrate. The first transition electrode may include a first end connected to the second electrode of the light-emitting element and a second end connected to the pixel circuit. The first ends of the plurality of first transition electrodes may be arranged in a concentrated manner. The arrangement in this example ensures that the second electrodes of different light-emitting elements are connected to their corresponding pixel circuits, enabling multiple pixel circuits to drive multiple light-emitting elements separately.

[0095] In some exemplary embodiments, the display substrate may further include a plurality of second transition electrodes. A second electrode of at least one light-emitting element can be connected to a first transition electrode via the second transition electrodes. The second transition electrodes may be located on the side of the first transition electrode away from the substrate and on the side of the second electrode closer to the substrate. For example, the plurality of second transition electrodes and the first electrode of at least one light-emitting element may be in the same layer.

[0096] In some exemplary embodiments, the second electrode of at least one light-emitting element can be connected to a second transition electrode via a lap electrode. The lap electrode can be located on the side of the second electrode away from the substrate, and the lap electrode can be in direct contact with the second electrode and the second transition electrode. In this example, the lap electrode enables a large-area overlap between the second electrode of the light-emitting element and the second transition electrode, thereby ensuring the electrical connection between the second electrode of the light-emitting element and the pixel circuit.

[0097] In some exemplary embodiments, at least one pixel circuit in a plurality of pixel circuits may include: a driving transistor, a compensation transistor, a first capacitor, and a second capacitor. The first electrode of the first capacitor is connected to the gate of the driving transistor, the second electrode of the first capacitor is connected to the second electrode of the compensation transistor, the first electrode of the compensation transistor is connected to the first electrode of the driving transistor and the first electrode of the second capacitor, and the second electrode of the second capacitor is connected to a second power line. The second electrode of the first capacitor may include: a first sub-electrode and a second sub-electrode connected to each other, the first sub-electrode of the first capacitor being located on the side of the second sub-electrode closer to the substrate, and the second electrode of the first capacitor being located on the side of the first sub-electrode farther from the substrate and also on the side of the second sub-electrode closer to the substrate. The first electrode of the second capacitor may be located on the side of the second electrode of the second capacitor closer to the substrate, and the first electrode of the second capacitor and the second sub-electrode of the first capacitor may be of the same layer structure. The capacitor arrangement of the pixel circuit in this example is beneficial for ensuring capacitor performance and can save capacitor space.

[0098] The following examples illustrate the solution of this embodiment.

[0099] Figure 1 is a schematic diagram of a display substrate according to at least one embodiment of the present disclosure. In some examples, as shown in Figure 1, the display substrate may include a display area AA and a peripheral area BB surrounding the display area AA. For example, the peripheral area BB may include a lower border area and a upper border area located on both sides of the display area AA along a second direction D2, and a left border area and a right border area located on both sides of the display area AA along a first direction D1. The first direction D1 and the second direction D2 may intersect; for example, the first direction D1 may be perpendicular to the second direction D2.

[0100] In some examples, the display area AA can be rectangular. However, this embodiment is not limited to this. For example, the display area AA can be other shapes such as circular or elliptical. In some examples, the display substrate can be a flexible substrate, and thus the display substrate can be deformable, such as rolled, bent, folded, or rolled up.

[0101] In some examples, the display area AA can be a flat region comprising multiple sub-pixels forming a pixel array. These sub-pixels can be configured to display moving or still images. A sub-pixel can include a pixel circuit and a light-emitting element electrically connected to the pixel circuit. The pixel circuit can include multiple transistors and at least one capacitor. For example, the pixel circuit can be a 3T1C, 4T1C, 5T1C, 5T2C, 6T1C, 7T1C, 8T1C, 8T2C, or 9T2C structure. In these circuit structures, T refers to a thin-film transistor, C refers to a capacitor, the number before T represents the number of thin-film transistors in the circuit, and the number before C represents the number of capacitors in the circuit. In some examples, the multiple transistors in the pixel circuit can be P-type transistors or N-type transistors. Using the same type of transistors in the pixel circuit simplifies the manufacturing process, reduces the manufacturing difficulty of the display panel, and improves product yield. In other examples, the multiple transistors in the pixel circuit can include both P-type and N-type transistors.

[0102] Figure 2 is a schematic diagram of a pixel circuit according to at least one embodiment of the present disclosure. In some examples, as shown in Figure 2, the pixel circuit of this example can be a 9T2C structure, which may include: a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, an eighth transistor T8, a ninth transistor T9, a first capacitor C1, and a second capacitor C2.

[0103] In some examples, the first transistor T1 through the ninth transistor T9 of the pixel circuit can be of the same type. All nine transistors can be N-type transistors, and oxide thin-film transistors (OSBs) can be used. The active layer of an OSB is made of oxide semiconductor. OSBs have advantages such as low leakage current.

[0104] In some examples, the first transistor T1 can also be called the first reset transistor, the second transistor T2 can also be called the compensation transistor, the third transistor T3 can also be called the driving transistor, the fourth transistor T4 can also be called the data writing transistor, the fifth transistor T5 can also be called the first light-emitting control transistor, the sixth transistor T6 can also be called the second light-emitting control transistor, the seventh transistor T7 can also be called the second reset transistor, the eighth transistor T8 can also be called the third reset transistor, and the ninth transistor T9 can also be called the fourth reset transistor.

[0105] In some examples, the pixel circuit can be connected to the first scan line GL1, the second scan line GL2, the first reset control line RST1, the second reset control line RST2, the third reset control line RST3, the fourth reset control line RST4, the light emission control line EML, the first initial signal line INIT1, the second initial signal line INIT2, the third initial signal line INIT3, the reference signal line REF, and the second power supply line VSS. The light-emitting element EL can be connected to the pixel circuit and the first power supply line VDD. Specifically, the first electrode of the light-emitting element EL can be connected to the first power supply line VDD, and the second electrode of the light-emitting element EL can be connected to the fifth node N5 of the pixel circuit.

[0106] In some examples, the first scan line GL1 can be configured to provide a first scan signal to the pixel circuit. The second scan line GL2 can be configured to provide a second scan signal to the pixel circuit. The emission control line EML can be configured to provide an emission control signal to the pixel circuit. The first reset control line RST1 can be configured to provide a first reset control signal to the pixel circuit. The second reset control line RST2 can be configured to provide a second reset control signal to the pixel circuit. The third reset control line RST3 can be configured to provide a third reset control signal to the pixel circuit. The fourth reset control line RST4 can be configured to provide a fourth reset control signal to the pixel circuit. For example, the fourth reset control line RST4 connected to one row of pixel circuits can be connected to the second reset control line RST2 connected to another row (e.g., the previous row) of pixel circuits. In other words, the fourth reset control signal received by one row of pixel circuits can be the same as the second reset control signal received by the previous row of pixel circuits.

[0107] In some examples, the first power line VDD can be configured to provide a constant first power signal to the light-emitting element EL, and the second power line VSS can be configured to provide a constant second power signal to the pixel circuit. The first power signal can be greater than the second power signal. The first initial signal line INIT1 can be configured to provide a first initial signal to the pixel circuit, the second initial signal line INIT2 can be configured to provide a second initial signal to the pixel circuit, and the third initial signal line INIT3 can be configured to provide a third initial signal to the pixel circuit. The first, second, and third initial signals can be different. The reference signal line REF can be configured to provide a reference signal to the pixel circuit. The reference signal can be different from the first, second, and third initial signals.

[0108] In some examples, the gate of the third transistor T3 is connected to the first node N1, the first terminal of the third transistor T3 is connected to the second node N2, and the second terminal of the third transistor T3 is connected to the third node N3. The third transistor T3 can determine the magnitude of the drive signal between the first power line VDD and the second power line VSS based on the voltage difference between its gate and the first terminal.

[0109] In some examples, the gate of the first transistor T1 is connected to the first reset control line RST1, the first terminal of the first transistor T1 is connected to the first initial signal line INIT1, and the second terminal of the first transistor T1 is connected to the third node N3. When a conduction level signal is applied to the first reset control line RST1, the first transistor T1 can transmit the first initial signal provided by the first initial signal line INIT1 to the third node N3 to initialize the third node N3.

[0110] In some examples, the gate of the second transistor T2 is connected to the second scan line GL2, the first terminal of the second transistor T2 is connected to the second node N2, and the second terminal of the second transistor T2 is connected to the fourth node N4. When a conduction level signal is applied to the second scan line GL2, the second transistor T2 can turn on the second node N2 and the fourth node N4 to write the threshold voltage of the third transistor T3 into the fourth node N4.

[0111] In some examples, the gate of the fourth transistor T4 is connected to the first scan line GL1, the first terminal of the fourth transistor T4 is connected to the data line DL, and the second terminal of the fourth transistor T4 is connected to the fourth node N4. When a conduction level signal is applied to the first scan line GL1, the fourth transistor T4 can transmit the data signal provided by the data line DL to the fourth node N4.

[0112] In some examples, the gate of the fifth transistor T5 is connected to the light-emitting control line EML, the first terminal of the fifth transistor T5 is connected to the third node N3, and the second terminal of the fifth transistor T5 is connected to the fifth node N5. The gate of the sixth transistor T6 is connected to the light-emitting control line EML, the first terminal of the sixth transistor T6 is connected to the second power supply line VSS, and the second terminal of the sixth transistor T6 is connected to the second node N2. When a conduction level signal is applied to the light-emitting control line EML, the fifth transistor T5 can conduct the third node N3 and the fifth node N5, and the sixth transistor T6 can conduct the second node N2 and the second power supply line VSS. Thus, when the third transistor T3 is conducted, a transmission path for the driving signal can be formed between the first power supply line VDD and the second power supply line VSS, causing the light-emitting element EL to emit light.

[0113] In some examples, the gate of the seventh transistor T7 is connected to the second reset control line RST2, the first terminal of the seventh transistor T7 is connected to the second initial signal line INIT2, and the second terminal of the seventh transistor T7 is connected to the second node N2. When a conduction level signal is applied to the second reset control line RST2, the seventh transistor T7 can transmit the second initial signal provided by the second initial signal line INIT2 to the second node N2 to initialize the second node N2.

[0114] In some examples, the gate of the eighth transistor T8 is connected to the third reset control line RST3, the first terminal of the eighth transistor T8 is connected to the reference signal line REF, and the second terminal of the eighth transistor T8 is connected to the first node N1. When a conduction level signal is applied to the third reset control line RST3, the eighth transistor T8 can transmit the reference signal provided by the reference signal line REF to the first node N1 to initialize the first node N1.

[0115] In some examples, the gate of the ninth transistor T9 is connected to the fourth reset control line RST4, the first terminal of the ninth transistor T9 is connected to the third initial signal line INIT3, and the second terminal of the ninth transistor T9 is connected to the fifth node N5. When a conduction level signal is applied to the fourth reset control line RST4, the ninth transistor T9 can transmit the third initial signal provided by the third initial signal line INIT3 to the fifth node N5, resetting the fifth node N5 so that the voltage of the fifth node N5 is less than the voltage of the first electrode of the light-emitting element EL. This ensures that the voltage of the first electrode of the light-emitting element EL is greater than the voltage of the second electrode, thereby supporting the normal light emission of the light-emitting element EL.

[0116] In some examples, the first electrode of the first capacitor C1 can be connected to the first node N1, and the second electrode of the first capacitor C1 can be connected to the fourth node N4. The first electrode of the second capacitor C2 can be connected to the second node N2, and the second electrode of the second capacitor C2 can be connected to the second power line VSS.

[0117] In some examples, the first node N1 can be the connection point of the third transistor T3, the eighth transistor T8, and the first capacitor C1. The second node N2 can be the connection point of the third transistor T3, the second transistor T2, the seventh transistor T7, the sixth transistor T6, and the second capacitor C2. The third node N3 can be the connection point of the first transistor T1, the third transistor T3, and the fifth transistor T5. The fourth node N4 can be the connection point of the second transistor T2, the fourth transistor T4, and the first capacitor C1. The fifth node N5 can be the connection point of the fifth transistor T5, the ninth transistor T9, and the light-emitting element EL.

[0118] In this example, nodes N1, N2, N3, N4, and N5 do not represent actual components, but rather the junctions of related electrical connections in the circuit diagram. In other words, these nodes are equivalent to the junctions of related electrical connections in the circuit diagram.

[0119] Figure 3 is an example of the timing diagram of the pixel circuit shown in Figure 2. The operation of the pixel circuit shown in Figure 2 will be explained below. The explanation will take the example where all the transistors in the pixel circuit shown in Figure 2 are N-type transistors.

[0120] In some examples, the operation of a pixel circuit may include the following stages.

[0121] In the first reset phase S1, the fourth reset control line RST4 can provide a high-level signal, the ninth transistor T9 turns on, and the third initial signal provided by the third initial signal line INIT3 is written into the fifth node N5 to reset the second electrode of the light-emitting element EL.

[0122] In the second reset phase S2, the light emission control line EML, the fourth reset control line RST4, the first reset control line RST1, and the first scan line GL1 all provide low-level signals, while the second scan line GL2, the second reset control line RST2, and the third reset control line RST3 all provide high-level signals. When the second scan line GL2 provides a high-level signal, the second transistor T2 turns on, conducting the second node N2 and the fourth node N4. When the second reset control line RST2 provides a high-level signal, the seventh transistor T7 turns on, writing the second initial signal provided by the second initial signal line INIT2 into the second node N2, and then writing the second initial signal into the fourth node N4 through the conducting second transistor T2. When the third reset control line RST3 provides a high-level signal, the eighth transistor T8 turns on, writing the reference signal provided by the reference signal line REF into the first node N1. The potential of the first node N1 is the reference voltage Vref of the reference signal. When the first scan line GL1 provides a low-level signal, the fourth transistor T4 turns off. When the first reset control line RST1 provides a low-level signal, the first transistor T1 turns off. The fourth reset control line RST4 provides a low-level signal, turning off the ninth transistor T9. The light emission control line EML provides a low-level signal, turning off both the fifth transistor T5 and the sixth transistor T6.

[0123] During compensation phase S3, the light emission control line EML, the fourth reset control line RST4, the second reset control line RST2, and the first scan line GL1 all provide low-level signals, while the second scan line GL2, the first reset control line RST1, and the third reset control line RST3 all provide high-level signals. With the third reset control line RST3 providing a high-level signal, the eighth transistor T8 remains continuously on, and the reference signal provided by the reference signal line REF is continuously written to the first node N1. The potential of the first node N1 is maintained at the reference voltage Vref. With the first reset control line RST1 providing a high-level signal, the first transistor T1 turns on, writing the first initial signal provided by the first initial signal line INT1 to the third node N3. Since the third transistor T3 is on, the voltage at the third node N3 can be transferred to the second node N2 to compensate and charge it. As the potential of the second node N2 gradually increases, when the potential difference between the first node N1 and the second node N2 equals the threshold voltage Vth of the third transistor T3 (i.e., the voltage difference Vgs between the gate and the first electrode of the third transistor T3 = Vth), the compensation process ends. At this time, the voltage difference between the gate and the first electrode of the third transistor T3 is Vgs = Vth = Vref - Vn2, and the potential of the second node N2 is Vn2 = Vref - Vth. The second scan line GL2 provides a high-level signal, the second transistor T2 remains in the on state, and the second node N2 and the fourth node N4 can be turned on. The potential of the fourth node N4 is the same as the potential of the second node N2, which is Vref - Vth. Since the voltage across the first capacitor C1 is the voltage between the gate and the first electrode of the third transistor T3, at the end of the compensation phase, the voltage difference across the first capacitor C1 is the threshold voltage Vth of the third transistor T3.

[0124] During compensation phase S3, the first scan line GL1 provides a low-level signal, and the fourth transistor T4 is turned off. The second reset control line RST2 provides a low-level signal, and the seventh transistor T7 is turned off. The fourth reset control line RST4 provides a low-level signal, and the ninth transistor T9 is turned off. The light emission control line EML provides a low-level signal, and both the fifth transistor T5 and the sixth transistor T6 are turned off.

[0125] During the write phase S4, the light emission control line EML, the fourth reset control line RST4, the first reset control line RST1, the second reset control line RST2, and the third reset control line RST3 all provide low-level signals, while the first scan line GL1 and the second scan line GL2 both provide high-level signals. With the first scan line GL1 providing a high-level signal, the fourth transistor T4 turns on, writing the data signal provided by the data line DL into the fourth node N4. With the second scan line GL2 providing a high-level signal, the second transistor T2 remains on, and the second node N2 and the fourth node N4 are turned on. The threshold voltage Vth and the data voltage Vdata can be coupled to the first node N1 through the first capacitor C1, making the potential of the first node N1 Vdata + Vth.

[0126] During the light-emitting phase S5, the first scan line GL1, the second scan line GL2, the first reset control line RST1, the second reset control line RST2, the third reset control line RST3, and the fourth reset control line RST4 all provide low-level signals, while the light-emitting control line EML provides a high-level signal. The second scan line GL2 provides a low-level signal, and the second transistor T2 is turned off. During the light-emitting phase S5, the resistance of the light-emitting element EL changes with increasing temperature. By setting the second transistor T2 to the off state, the potential change of the first node N1 can be avoided, and the change in the resistance of the light-emitting element EL can be prevented from affecting the gate potential of the third transistor T3. This ensures that the driving current of the light-emitting element EL remains stable during the light-emitting phase, thereby ensuring uniform brightness of the display substrate and improving image quality. Furthermore, by controlling the on and off states of the second transistor T2, the influence of the gate potential of the third transistor T3 during low-frequency display startup can be prevented.

[0127] During the light-emitting stage S5, the light-emitting control line EML provides a high-level signal, and both the fifth transistor T5 and the sixth transistor T6 are turned on. With the sixth transistor T6 on, the first electrode voltage of the third transistor T3 (i.e., the potential of the second node N2) is equal to the voltage Vss of the second power supply signal provided by the second power supply line. The gate voltage of the third transistor T3 (i.e., the potential of the first node N1) is Vdata + Vth. The gate voltage of the third transistor T3 is greater than the first electrode voltage, and the voltage difference between the gate and the first electrode of the third transistor T3 is Vgs = Vdata + Vth - Vss. The third transistor T3 is turned on, forming a current path from the first power supply line VDD, the light-emitting element EL, the fifth transistor T5, the third transistor T3, the sixth transistor T6, to the second power supply line VSS. The magnitude of the driving current flowing through the third transistor T3 can be determined based on the data voltage Vdata and the second power supply voltage Vss, allowing the light-emitting element EL to generate light with a predetermined brightness in response to the magnitude of this driving current. The driving current of the light-emitting element EL can be: Ids = 0.5 × K(Vgs - Vth). 2 = 0.5 × K(Vdata + Vth - Vss - Vth) 2 = 0.5 × K(Vdata - Vss) 2 .

[0128] Where K is the current coefficient of the third transistor T3; Vgs is the voltage difference between the gate and the first terminal of the third transistor T3; Vth is the threshold voltage of the third transistor T3; Vdata is the data voltage; Vref is the reference voltage of the reference signal; and Vss is the voltage of the second power supply signal.

[0129] The pixel circuit of this embodiment can eliminate the influence of the threshold voltage of the driving transistor (i.e., the third transistor T3) on the driving signal, thereby ensuring uniform display brightness and improving the display effect; moreover, it can help improve the compensation effect of the threshold voltage of the driving transistor, thereby helping to improve display performance.

[0130] In this example, the data voltage written by the data line DL is performed before the high-level signal of the second scan line GL2 ends. In other examples, the data voltage can be written after the high-level signal of the second scan line GL2 ends. This embodiment is not limited to this.

[0131] In the pixel circuit of this example, the first node N1, connected to the gate of the third transistor T3, is connected to the eighth transistor T8 and the second transistor T2. The second transistor T2 is connected to the first node N1 through the first capacitor C1. Thus, when the voltage difference between the gate and the first electrode of the third transistor T3 reaches the threshold voltage of the third transistor T3, the voltage across the first capacitor C1 is the threshold voltage of the third transistor T3. Therefore, after the fourth transistor T4 writes the data voltage provided by the data line DL to the fourth node N4, the voltage of the first node N1 is the sum of the threshold voltage Vth and the data voltage Vdata. Subsequently, during the light-emitting stage, after the second node N2 and the third node N3 are turned on, the driving current flowing through the light-emitting element EL is independent of the threshold voltage Vth of the third transistor T3.

[0132] In this example pixel circuit, by setting a second capacitor C2, the first capacitor C1 and the second node N2 can be made independent during the low-frequency display stage, thus meeting the low-frequency display requirements and effectively isolating the potential changes of the second node N2 from the influence of the first node N1. By setting a seventh transistor T7, the reset function of the second node N2 can be implemented. The use of the second capacitor C2 helps stabilize the potential of the second node N2.

[0133] Figure 4 is a schematic diagram of the connection between the pixel circuit and the light-emitting element according to at least one embodiment of the present disclosure. In some examples, as shown in Figure 4, the light-emitting element EL may include: a first electrode, a light-emitting functional layer, and a second electrode. The first electrode of the light-emitting element EL may be connected to a first power line, and the second electrode may be connected to the pixel circuit. The first electrode of the light-emitting element may be an anode, and the second electrode of the light-emitting element may be a cathode. The light-emitting functional layer may include: a hole injection layer (HIL), a hole transport layer (HTL), an emitting layer (EML), an electron transport layer (ETL), and an electron injection layer (EIL) arranged sequentially. Under the voltage drive of the first electrode and the second electrode, the light-emitting functional layer can emit light at the required grayscale using the light-emitting characteristics of the organic material. In other examples, the light-emitting functional layer may also include at least one of the following: a hole blocking layer (HBL) and an electron blocking layer (EBL). This embodiment is not limited in this respect.

[0134] In some examples, the light-emitting layers of light-emitting elements of different colors can be different. For example, a red light-emitting element may include a red light-emitting layer, a green light-emitting element may include a green light-emitting layer, and a blue light-emitting element may include a blue light-emitting layer. For example, any one or more of the hole injection layer, hole transport layer, electron injection layer, and electron transport layer can be fabricated in a single process (single vapor deposition process or single inkjet printing process). The light-emitting layer can be formed by vapor deposition using a fine metal mask (FMM) or an open mask, or by inkjet printing.

[0135] The structure of a display substrate is illustrated below using an example of its fabrication process. The "patterning process" described in this disclosure includes, for metallic, inorganic, or transparent conductive materials, processes such as photoresist coating, mask exposure, development, etching, and photoresist stripping; for organic materials, it includes processes such as organic material coating, mask exposure, and development. Deposition can be performed using any one or more of sputtering, evaporation, and chemical vapor deposition; coating can be performed using any one or more of spraying, spin coating, and inkjet printing; etching can be performed using any one or more of dry etching and wet etching. This disclosure does not limit the methods used. A "thin film" refers to a thin film made of a certain material on a substrate using deposition, coating, or other processes. If the "thin film" does not require a patterning process during the entire fabrication process, it can also be called a "layer." If the "thin film" requires a patterning process during the entire fabrication process, it is called a "thin film" before the patterning process and a "layer" after the patterning process.

[0136] The terms "A and B are arranged in the same layer" or "A and B are of the same layer structure" in this disclosure mean that A and B are formed simultaneously through the same patterning process, or that the surfaces of A and B closest to the substrate are at substantially the same distance from the substrate, or that the surfaces of A and B closest to the substrate are in direct contact with the same film layer. "The orthographic projection of B is within the range of the orthographic projection of A" means that the boundary of the orthographic projection of B falls within the boundary range of the orthographic projection of A, or that the boundary of the orthographic projection of A overlaps with the boundary of the orthographic projection of B. "The orthographic projection of A includes the orthographic projection of B" means that the boundary of the orthographic projection of B falls within the boundary range of the orthographic projection of A. The term "shape of A" in this disclosure refers to the shape of the orthographic projection of A onto the substrate.

[0137] The following diagrams illustrate a pixel circuit with one row (e.g., row i) and three columns (e.g., columns j, j+1, and j+2) in Figures 5 to 13B, and a pixel circuit with two rows (e.g., rows i and i+1) and six columns (e.g., columns j to j+5) in Figures 14 to 19. Each row of pixel circuits includes multiple pixel circuits arranged sequentially along a first direction D1, and each column of pixel circuits includes multiple pixel circuits arranged sequentially along a second direction D2. The first direction D1 intersects the second direction D2; for example, the first direction D1 can be perpendicular to the second direction D2. The circuit diagram of the pixel circuit in this example is shown in Figure 2.

[0138] In some examples, the fabrication process of the display substrate may include the following operations.

[0139] (1) Providing a substrate. In some examples, the substrate can be a rigid substrate or a flexible substrate. For example, a rigid substrate can be, but is not limited to, one or more of glass and quartz; a flexible substrate can be, but is not limited to, one or more of polyethylene terephthalate, polyethylene terephthalate, polyetheretherketone, polystyrene, polycarbonate, polyarylate, polyarylate, polyimide, polyvinyl chloride, polyethylene, and textile fibers. In some examples, the flexible substrate may include a first flexible material layer, a first inorganic material layer, a second flexible material layer, and a second inorganic material layer stacked together. The materials of the first flexible material layer and the second flexible material layer may be polyimide (PI), polyethylene terephthalate (PET), or a surface-treated polymer film, etc. The materials of the first inorganic material layer and the second inorganic material layer may be silicon nitride (SiNx, x>0) or silicon oxide (SiOy, y>0), etc., to improve the substrate's resistance to water and oxygen.

[0140] (2) Forming a first conductive layer. In some examples, a first conductive thin film is deposited on the substrate on which the aforementioned pattern is formed, and the first conductive thin film is patterned by a patterning process to form a first conductive layer disposed on the substrate. For example, the first conductive layer may also be referred to as a first gate metal layer.

[0141] Figure 5 is a partial schematic diagram of a display substrate after the formation of the first conductive layer in at least one embodiment of the present disclosure. In some examples, as shown in Figure 5, the first conductive layer of the display substrate may include: the first sub-electrode C1-2a of the second electrode of the first capacitor of the multiple pixel circuits and the bottom gate T22 of the second transistor, as well as multiple auxiliary traces (e.g., including the first auxiliary trace 11 to the sixth auxiliary trace 16).

[0142] In some examples, the first auxiliary traces 11 to the sixth auxiliary traces 16 can be arranged sequentially along the second direction D2 and all extend along the first direction D1. The orthographic projection of the first sub-electrode C1-2a of the second electrode of the first capacitor of a row (e.g., the i-th row) pixel circuit onto the substrate can be located between the orthographic projections of the third auxiliary trace 13 and the fourth auxiliary trace 14 onto the substrate.

[0143] In some examples, the orthographic projection of the first auxiliary trace 11 to the sixth auxiliary trace 16 onto the substrate can be a straight line extending along the first direction D1. The fourth auxiliary trace 14 and the bottom gate T22 of the second transistor in the same row (e.g., the i-th row) of the pixel circuit can be an integral structure. The bottom gate T22 of the second transistor can be connected to the side of the fourth auxiliary trace 14 away from the first sub-electrode C1-2a of the second electrode of the first capacitor. The orthographic projection of the side of the fifth auxiliary trace 15 facing the fourth auxiliary trace 14 onto the substrate can be a broken line.

[0144] (3) Forming a semiconductor layer. In some examples, a first insulating film and a semiconductor film are deposited on the substrate on which the aforementioned pattern is formed, and the semiconductor film is patterned by a patterning process to form a first insulating layer and a semiconductor layer disposed on the substrate. In some examples, the material of the semiconductor layer may be an oxide semiconductor material, such as indium gallium zinc oxide (IGZO).

[0145] Figure 6A is a partial schematic diagram of a display substrate after the semiconductor layer has been formed in at least one embodiment of the present disclosure. Figure 6B is a schematic diagram of the semiconductor layer in Figure 6A. In some examples, as shown in Figures 6A and 6B, the semiconductor layer of the display substrate may include: an active layer of transistors for a plurality of pixel circuits (e.g., including an active layer T10 of the first transistor, an active layer T20 of the second transistor, an active layer T30 of the third transistor, an active layer T40 of the fourth transistor, an active layer T50 of the fifth transistor, an active layer T60 of the sixth transistor, an active layer T70 of the seventh transistor, an active layer T80 of the eighth transistor, and an active layer T90 of the ninth transistor of the next row of pixel circuits).

[0146] In some examples, the active layer of each transistor may include a first region, a second region, and a channel region located between the first and second regions. The semiconductor layer material may, for example, include polysilicon. The channel region may be undoped and possess semiconductor properties. The first and second regions may be doped regions on either side of the channel region and are doped with impurities, thus possessing conductivity. The impurities may vary depending on the type of transistor. In some examples, the doped regions of the active layer may be interpreted as the source or drain electrodes of the transistor. The portion of the active layer between transistors may be interpreted as doped wiring that can be used to electrically connect the transistors. This embodiment is not limited in this respect.

[0147] In some examples, the active layers T10 of the first transistor, T50 of the fifth transistor, T60 of the sixth transistor, and T80 of the eighth transistor of the same pixel circuit can be located on the same side of the active layer T30 of the third transistor along the second direction D2, and the active layers T20 of the second transistor, T40 of the fourth transistor, and T70 of the seventh transistor can be located on the other side of the active layer T30 of the third transistor along the second direction D2.

[0148] In some examples, the orthographic projection of the active layer T10 of the first transistor onto the substrate can be a strip extending along the second direction D2, and the orthographic projection of the active layer T50 of the fifth transistor onto the substrate can also be a strip extending along the second direction D2. The active layers T10 and T50 of the first and fifth transistors in the same pixel circuit can be an integral structure. The second region of the active layer T10 of the first transistor and the first region of the active layer T50 of the fifth transistor can be connected, and the first region of the active layer T10 of the first transistor and the second region of the active layer T50 of the fifth transistor can be set independently.

[0149] In some examples, the orthographic projection of the active layer T60 of the sixth transistor onto the substrate can be a strip extending along the second direction D2. The active layer T60 of the sixth transistor and the active layer T50 of the fifth transistor can be aligned along the first direction D1. The first region and the second region of the active layer T60 of the sixth transistor can be independently disposed on both sides of the channel region of the active layer T60 along the second direction D2.

[0150] In some examples, the orthographic projection of the active layer T20 of the second transistor onto the substrate can be a strip extending along the first direction D1, and the orthographic projection of the active layer T40 of the fourth transistor onto the substrate can be a strip extending along the second direction D2. The active layers T20 and T40 of the second and fourth transistors in the same pixel circuit can be a single structure, and the orthographic projection of this single structure onto the substrate can be L-shaped, such as an L-shape rotated 90 degrees clockwise. The second region of the active layer T20 of the second transistor and the second region of the active layer T40 of the fourth transistor can be connected, while the first regions of the active layers T20 and T40 of the fourth transistor can be independently configured.

[0151] In some examples, the orthographic projection of the active layer T30 of the third transistor onto the substrate can be L-shaped, such as an L-shape rotated 90 degrees counterclockwise. The first region and the second region of the active layer T30 of the third transistor can be independently disposed on both sides of the channel region of the active layer T30. The orthographic projection of the active layer T30 of the third transistor onto the substrate can be along the first direction D1, located on one side of the orthographic projection of the first sub-electrode C1-2a of the second electrode of the first capacitor onto the substrate.

[0152] In some examples, the orthogonal projection of the active layer T80 of the eighth transistor onto the substrate can be a strip extending along the second direction D2. The active layer T80 of the eighth transistor can be located on the side of the active layer T10 of the first transistor near the active layer T30 of the third transistor in the first direction D1. The first region and the second region of the active layer T80 of the eighth transistor can be independently disposed on both sides of the channel region of the active layer T80 along the second direction D2.

[0153] In some examples, the orthogonal projection of the active layer T70 of the seventh transistor onto the substrate can be a strip extending along the second direction D2. The active layer T70 of the seventh transistor can be located on the side of the active layer T20 of the second transistor away from the active layer T30 of the third transistor along the second direction D2. The first region and the second region of the active layer T70 of the seventh transistor can be independently disposed on both sides of the channel region of the active layer T70 along the second direction D2.

[0154] In some examples, the orthographic projection of the active layer T90 of the ninth transistor onto the substrate can be a strip extending along the second direction D2. The active layer T70 of the seventh transistor in the current row of pixel circuits can be aligned and spaced apart from the active layer T90 of the ninth transistor in the next row of pixel circuits along the first direction D1. The first and second regions of the active layer T90 of the ninth transistor can be independently disposed on both sides of the channel region of the active layer T90 along the second direction D2.

[0155] In some examples, the overlap between the first auxiliary trace 11 and the active layer T50 of the fifth transistor can serve as the bottom gate of the fifth transistor, and the overlap between the first auxiliary trace 11 and the active layer T60 of the sixth transistor can serve as the bottom gate of the sixth transistor. The bottom gates of the fifth and sixth transistors in the same row of pixel circuits can be connected to the same first auxiliary trace 11.

[0156] In some examples, the overlap between the second auxiliary trace 12 and the active layer T10 of the first transistor can serve as the bottom gate of the first transistor. The bottom gate of the first transistor in the same row of pixel circuits can be connected to the same second auxiliary trace 12.

[0157] In some examples, the overlap between the third auxiliary trace 13 and the active layer T80 of the eighth transistor can serve as the bottom gate of the eighth transistor. The bottom gate of the eighth transistor in the same row of pixel circuits can be connected to the same third auxiliary trace 13.

[0158] In some examples, the bottom gate T22 of the second transistor in the same row of pixel circuits can be connected to the same fourth auxiliary trace 14, for example, as a single integrated structure. The bottom gate of the fourth transistor in the same row of pixel circuits can be connected to the same fifth auxiliary trace 15. The overlap between the fifth auxiliary trace 15 and the active layer T40 of the fourth transistor can serve as the bottom gate of the fourth transistor.

[0159] In some examples, the bottom gate of the seventh transistor in the same row of pixel circuits and the bottom gate of the ninth transistor in the next row of pixel circuits can be connected to the same sixth auxiliary trace 16. The overlapping portion of the sixth auxiliary trace 16 with the active layer T70 of the seventh transistor in the same row of pixel circuits can serve as the bottom gate of the seventh transistor, and the overlapping portion of the sixth auxiliary trace 16 with the active layer T90 of the ninth transistor in the next row of pixel circuits can serve as the bottom gate of the ninth transistor.

[0160] (4) Forming a second conductive layer. In some examples, a second insulating film and a second conductive film are sequentially deposited on the substrate on which the aforementioned structure is formed. The second conductive film is patterned using a patterning process to form a second insulating layer and a second conductive layer disposed on the second insulating layer. For example, the second conductive layer may also be referred to as a second gate metal layer.

[0161] Figure 7A is a partial schematic diagram of a display substrate after the formation of the second conductive layer in at least one embodiment of the present disclosure. Figure 7B is a schematic diagram of the second conductive layer in Figure 7A. In some examples, as shown in Figures 7A and 7B, the second conductive layer of the display substrate may include: the first electrode C1-1 of the first capacitor of a plurality of pixel circuits and the gates of a plurality of transistors (e.g., including the gate T21 of the second transistor T2 and the gate T31 of the third transistor T3), and a plurality of signal lines (e.g., including the light emission control line EML, the first reset control line RST1, the second reset control line RST2, the third reset control line RST3, the first scan line GL1 and the second scan line GL2).

[0162] In some examples, the light emission control line EML, the first reset control line RST1, the third reset control line RST3, the second scan line GL2, the first scan line GL1, and the second reset control line RST2 can be arranged along the second direction D2 and all extend along the first direction D1. The light emission control line EML, the first reset control line RST1, and the third reset control line RST3 can be located on one side of the third transistor T3 along the second direction D2, and the second scan line GL2, the first scan line GL1, and the second reset control line RST2 can be located on the other side of the third transistor T3 along the second direction D2.

[0163] In some examples, the orthographic projection of the light-emitting control line EML onto the substrate can be a straight line extending along the first direction D1. The orthographic projection of the light-emitting control line EML onto the substrate can be located within the orthographic projection range of the first auxiliary trace 11 onto the substrate. The overlapping portion of the light-emitting control line EML with the active layer T50 of the fifth transistor T5 can serve as the gate of the fifth transistor T5, and the overlapping portion of the light-emitting control line EML with the active layer T60 of the sixth transistor T6 can serve as the gate of the sixth transistor T6. The gates of the fifth transistor T5 and the sixth transistor T6 in the same row of pixel circuits can be connected to the same light-emitting control line EML.

[0164] In some examples, the orthographic projection of the first reset control line RST1 onto the substrate can be a straight line extending along the first direction D1. The orthographic projection of the first reset control line RST1 onto the substrate can be located within the orthographic projection range of the second auxiliary trace 12 onto the substrate. The overlapping portion of the first reset control line RST1 with the active layer T10 of the first transistor T1 can serve as the gate of the first transistor T1. The gates of the first transistors T1 in the same row of pixel circuits can be connected to the same first reset control line RST1.

[0165] In some examples, the orthographic projection of the third reset control line RST3 onto the substrate can be approximately a straight line extending along the first direction D1. The orthographic projection of the third reset control line RST3 onto the substrate can be within the orthographic projection range of the third auxiliary trace 13 onto the substrate. The overlap between the third reset control line RST3 and the active layer T80 of the eighth transistor T8 can serve as the gate of the eighth transistor T8. The gate of the eighth transistor T8 in the same row of pixel circuits can be connected to the same third reset control line RST3.

[0166] In some examples, the orthographic projection of the second scan line GL2 onto the substrate can be a straight line extending along the first direction D1. The orthographic projection of the second scan line GL2 onto the substrate can be located within the orthographic projection range of the fourth auxiliary trace 14 onto the substrate. The second scan line GL2 can be connected to the gate T21 of the second transistor T2 in the same row of pixel circuits, for example, as a single integrated structure. The orthographic projection of the gate T21 of the second transistor T2 onto the substrate can be a strip extending along the second direction D2. The orthographic projection of the gate T21 of the second transistor T2 onto the substrate can be located within the orthographic projection range of the bottom gate T22 of the second transistor T2 onto the substrate.

[0167] In some examples, the orthographic projection of the first scan line GL1 onto the substrate can be approximately a strip extending along the first direction D1. The orthographic projection of the first scan line GL1 onto the substrate can at least partially overlap with the orthographic projection of the fifth auxiliary trace 15 onto the substrate. For example, the orthographic projection of the first scan line GL1 onto the substrate can be located within the orthographic projection range of the fifth auxiliary trace 15 onto the substrate. The overlapping portion of the first scan line GL1 with the active layer T40 of the fourth transistor T4 can serve as the gate of the fourth transistor T4. The gate of the fourth transistor T4 in the same row of pixel circuits can be connected to the same first scan line GL1.

[0168] In some examples, the orthographic projection of the second reset control line RST2 onto the substrate can be a straight line extending along the first direction D1. The orthographic projection of the second reset control line RST2 onto the substrate can be within the orthographic projection range of the sixth auxiliary trace 16 onto the substrate. The overlapping portion of the second reset control line with the active layer T70 of the seventh transistor T7 of the current row pixel circuit can serve as the gate of the seventh transistor T7, and the overlapping portion of the second reset control line RST2 with the active layer T90 of the ninth transistor T9 of the next row pixel circuit can serve as the gate of the ninth transistor T9. The gate of the seventh transistor T7 of the current row pixel circuit and the gate of the ninth transistor T9 of the next row pixel circuit can be connected to the same second reset control line RST2. In this example, the fourth reset control line connected to the current row pixel circuit can be the second reset control line connected to the previous row pixel circuit.

[0169] In some examples, the first electrode C1-1 of the first capacitor in the pixel circuit and the gate T31 of the third transistor T3 can be an integral structure. The orthographic projection of the first electrode C1-1 of the first capacitor onto the substrate can be approximately rectangular, and the orthographic projection of the gate T31 of the third transistor T3 onto the substrate can also be approximately rectangular. The first electrode C1-1 of the first capacitor and the gate T31 of the third transistor can be arranged along a first direction D1, and can be misaligned along a second direction D2. The orthographic projection of the first electrode C1-1 of the first capacitor onto the substrate and the orthographic projection of the first sub-electrode C1-2a of the second electrode onto the substrate can partially overlap.

[0170] (5) Forming a third insulating layer. In some examples, a third insulating film is deposited on the substrate on which the aforementioned structure is formed, and the third insulating film is patterned by a patterning process to form a third insulating layer. In some examples, the third insulating layer may also be referred to as an interlayer insulating layer.

[0171] Figure 8 is a partial schematic diagram of a display substrate after the formation of a third insulating layer in at least one embodiment of this disclosure. In some examples, as shown in Figure 8, the third insulating layer of the display substrate may have multiple vias, for example, it may include a first via V1 to an eighteenth via V18. The third and second insulating layers within the first via V1 to the sixteenth via V16 may be removed, exposing a portion of the surface of the semiconductor layer. The third insulating layer within the seventeenth via V17 may be removed, exposing a portion of the surface of the second conductive layer. The third, second, and first insulating layers within the eighteenth via V18 may be removed, exposing a portion of the surface of the first conductive layer.

[0172] (6) Forming a third conductive layer. In some examples, a third conductive film is deposited on the substrate on which the aforementioned structure is formed, and the third conductive film is patterned by a patterning process to form a third conductive layer disposed on the third insulating layer. In some examples, the third conductive layer may also be referred to as a first source / drain metal layer.

[0173] Figure 9A is a partial schematic diagram of a display substrate after the formation of the third conductive layer in at least one embodiment of the present disclosure. Figure 9B is a schematic diagram of the third conductive layer in Figure 9A. In some examples, as shown in Figures 9A and 9B, the third conductive layer of the display substrate may include: a second sub-electrode C1-2b of the second electrode of the first capacitor C1 of a plurality of pixel circuits and a first electrode C2-1 of the second capacitor, a plurality of connecting electrodes (e.g., including the first connecting electrode 201 to the twelfth connecting electrode 212), and a plurality of signal lines (e.g., including the first initial signal line INIT1, the second initial signal line INT2, the third initial signal line INIT3, and the reference signal line REF).

[0174] In some examples, the first initial signal line INIT1, the reference signal line REF, the third initial signal line INIT3, and the second initial signal line INT2 can be arranged along the second direction D2 and all extend along the first direction D1. The first initial signal line INIT1 and the reference signal line REF can be located on one side of the third transistor T3 along the second direction D2, and the third initial signal line INIT3 and the second initial signal line INT2 can be located on the other side of the third transistor T3 along the second direction D2.

[0175] In some examples, the orthographic projection of the first initial signal line INIT1 onto the substrate can be a broken line extending along the first direction D1. The orthographic projection of the first initial signal line INIT1 onto the substrate can be located on the side of the reference signal line REF onto the substrate away from the third transistor T3. The orthographic projection of the first initial signal line INIT1 onto the substrate can be located between the orthographic projections of the first reset control line RST1 and the third reset control line RST3 onto the substrate, and overlap with a portion of the orthographic projection of the first reset control line RST1 onto the substrate. The first initial signal line INIT1 can be connected to the first region of the active layer T10 of the first transistor T1 through the third via V3.

[0176] In some examples, the orthographic projection of the reference signal line REF onto the substrate can be a straight line extending along the first direction D1. The orthographic projection of the reference signal line REF onto the substrate can overlap with the orthographic projection of the third reset control line RST3 onto the substrate. The reference signal line REF is connected to multiple tenth connection electrodes 210, which can be, for example, a single integrated structure. Multiple tenth connection electrodes 210 connected to a row of pixel circuits are connected to the side of the reference signal line REF facing the first initial signal line INIT1. The orthographic projection of the tenth connection electrode 210 onto the substrate can be a strip extending along the second direction D2. The tenth connection electrode 210 can be connected to the first region of the active layer T80 of the eighth transistor T8 through the sixth via V6. The tenth connection electrode 210 can serve as the first electrode of the eighth transistor T8.

[0177] In some examples, the orthographic projection of the third initial signal line INIT3 onto the substrate can be a straight line extending along the first direction D1. The orthographic projection of the third initial signal line INIT3 onto the substrate can at least partially overlap with the orthographic projection of the first scan line GL1 onto the substrate. For example, the orthographic projection of the third initial signal line INIT3 onto the substrate can be located within the orthographic projection range of the first scan line GL1 onto the substrate. The third initial signal line INIT3 is connected to a plurality of ninth connection electrodes 209, for example, as a single integrated structure. The plurality of ninth connection electrodes 209 connected to a row of pixel circuits can be connected to the side of the third initial signal line INIT3 facing the second initial signal line INIT2. The orthographic projection of the ninth connection electrode 209 onto the substrate can be a strip extending along the second direction D2. The ninth connection electrode 209 can be connected to the first region of the active layer T90 of the ninth transistor T9 of the next row of pixel circuits through the fifteenth via V15. The ninth connection electrode 209 can serve as the first electrode of the ninth transistor T9.

[0178] In some examples, the orthographic projection of the second initial signal line INIT2 onto the substrate can be a straight line extending along the first direction D1. The orthographic projection of the second initial signal line INIT2 onto the substrate can at least partially overlap with the orthographic projection of the second reset control line RST2 onto the substrate. For example, the orthographic projection of the second initial signal line INIT2 onto the substrate can be located within the orthographic projection range of the second reset control line RST2 onto the substrate. The second initial signal line INIT2 is connected to a plurality of seventh connection electrodes 207, which can be, for example, a single integrated structure. The plurality of seventh connection electrodes 207 connected to a row of pixel circuits can be connected to the side of the second initial signal line INIT2 away from the third initial signal line INIT3. The orthographic projection of the seventh connection electrode 207 onto the substrate can be a strip extending along the second direction D2. The seventh connection electrode 207 can be connected to the first region of the active layer T70 of the seventh transistor T7 through the fourteenth via V14. The seventh connection electrode 207 can serve as the first electrode of the seventh transistor T7.

[0179] This example demonstrates how overlapping signal lines on the third conductive layer and the second conductive layer can help save space occupied by the wiring.

[0180] In some examples, the orthographic projection of the second sub-electrode C1-2b of the second electrode of the first capacitor C1 onto the substrate can be approximately L-shaped, for example, it can be an L-shaped structure arranged symmetrically about the first direction D1. The orthographic projection of the second sub-electrode C1-2b of the first capacitor C1 onto the substrate can overlap with the orthographic projections of the first electrode C1-1 and the first sub-electrode C1-2a of the first capacitor C1 onto the substrate. The second sub-electrode C1-2b of the first capacitor C1 can be connected to the first sub-electrode C1-2a through the eighteenth via V18, and can also be connected to the second region of the active layer T20 of the second transistor T2 and the second region of the active layer T40 of the fourth transistor T4 through the eleventh via V11.

[0181] In some examples, the orthographic projection of the first electrode C2-1 of the second capacitor onto the substrate can be approximately L-shaped, such as a mirror-reversed L-shape. The first electrode C2-1 of the second capacitor can be connected to the first region of the active layer T30 of the third transistor T3 through the eighth via V8, and can also be connected to the first region of the active layer T20 of the second transistor T2 through the tenth via V10.

[0182] In some examples, the orthographic projection of the first connection electrode 201 onto the substrate can be approximately rectangular. The first connection electrode 201 can be connected to the second region of the active layer T20 of the first transistor T1 and the first region of the active layer T50 of the fifth transistor T5 through the second via V2. The first connection electrode 201 can simultaneously serve as the second electrode of the first transistor T1 and the first electrode of the fifth transistor T5.

[0183] In some examples, the orthographic projection of the second connection electrode 202 onto the substrate can be approximately rectangular. The second connection electrode 202 can be connected to the second region of the active layer T30 of the third transistor T3 via the ninth via V9. The second connection electrode 202 can serve as the second electrode of the third transistor T3.

[0184] In some examples, the orthographic projection of the third connection electrode 203 onto the substrate can be approximately rectangular. The third connection electrode 203 can be connected to the first region of the active layer T40 of the fourth transistor T4 through the twelfth via V12. The third connection electrode 203 can serve as the first electrode of the fourth transistor T4.

[0185] In some examples, the orthographic projection of the fourth connection electrode 204 onto the substrate can be approximately T-shaped. The fourth connection electrode 204 can be connected to the second region of the active layer T50 of the fifth transistor T5 via the first via V1. The fourth connection electrode 204 can also be connected to the second region of the active layer of the ninth transistor in the previous row of pixel circuits. The fourth connection electrode 204 can serve as the fifth node N5 of the pixel circuit.

[0186] In some examples, the orthographic projection of the fifth connection electrode 205 onto the substrate can be approximately rectangular. The fifth connection electrode 205 can be connected to the first region of the active layer T60 of the sixth transistor T6 via the fourth via V4. The fifth connection electrode 205 can serve as the first electrode of the sixth transistor T6.

[0187] In some examples, the orthographic projection of the sixth connection electrode 206 onto the substrate can be approximately rectangular. The sixth connection electrode 206 can be connected to the second region of the active layer T60 of the sixth transistor T6 through the fifth via V5. The sixth connection electrode 206 can serve as the second electrode of the sixth transistor T6.

[0188] In some examples, the orthographic projection of the eighth connection electrode 208 onto the substrate can be approximately rectangular. The eighth connection electrode 208 can be connected to the first region of the active layer T70 of the seventh transistor T7 via the thirteenth via V13. The eighth connection electrode 208 can serve as the second electrode of the seventh transistor T7.

[0189] In some examples, the orthographic projection of the eleventh connection electrode 211 onto the substrate can be approximately rectangular. The eleventh connection electrode 211 can be connected to the second region of the active layer T80 of the eighth transistor T8 through the seventh via V7, and can also be connected to the gate T31 of the third transistor T3 through the seventeenth via V17. Since the first electrode C1-1 of the first capacitor C1 and the gate T31 of the third transistor T3 are integrally structured, the eleventh connection electrode 211 can serve as the first node N1, realizing the electrical connection between the second electrode of the eighth transistor T8, the gate T31 of the third transistor T3, and the first electrode C1-1 of the first capacitor C1.

[0190] In some examples, the orthographic projection of the twelfth connection electrode 212 onto the substrate can be approximately rectangular. The twelfth connection electrode 212 can be connected to the second region of the active layer T90 of the ninth transistor T9 in the next row of pixel circuits via the sixteenth via V16. The twelfth connection electrode 212 can serve as the second electrode of the ninth transistor T9. The fourth connection electrode 204 connected to the pixel circuit in this row can be integrated with the twelfth connection electrode 212 connected to the pixel circuit in the previous row, serving as the fifth node N5 of the pixel circuit.

[0191] In some examples, the fifth transistor T5 and the sixth transistor T6 of the same pixel circuit can be aligned along the first direction D1. The first transistor T1 and the fifth transistor T5 can be aligned along the second direction D2. The eighth transistor T8 can be located on the side of the first transistor T1 closer to the sixth transistor T6. The third transistor T3 and the first capacitor C1 can be arranged adjacent to each other along the first direction D1. The second transistor T2 and the fourth transistor T4 can be located on the side of the third transistor T3 away from the eighth transistor T8. The fourth transistor T4 can be located on the side of the second transistor T2 away from the third transistor T3. The seventh transistor T7 and the ninth transistor T9 of the next row of pixel circuits can be aligned along the first direction D1, and can be located on the side of the second transistor T2 away from the third transistor T3 along the second direction D2.

[0192] In this example, the second electrode of the first capacitor C1 in the pixel circuit includes a first sub-electrode C1-2a located in the first conductive layer and a second sub-electrode C1-2b located in the third conductive layer. The first electrode C1-1 of the first capacitor C1 is located in the second conductive layer and sandwiched between the first sub-electrode C1-2a and the second sub-electrode C1-2b. The structure of the three plates of the first capacitor C1 in this example can help improve the performance of the first capacitor C1 and save the space occupied by the first capacitor C1.

[0193] (7) Forming a fourth insulating layer. In some examples, a fourth insulating film is coated on the substrate on which the aforementioned structure is formed, and the fourth insulating film is patterned by a patterning process to form a fourth insulating layer. In some examples, the fourth insulating layer may also be referred to as a first planarization layer.

[0194] Figure 10 is a partial schematic diagram of a display substrate after the formation of the fourth insulating layer in at least one embodiment of the present disclosure. In some examples, as shown in Figure 10, the fourth insulating layer of the display substrate may have multiple vias, such as vias V21 to V28. The fourth insulating layer within vias V21 to V28 may be removed, exposing a portion of the surface of the third conductive layer.

[0195] (8) Forming a fourth conductive layer. In some examples, a fourth conductive thin film is deposited on the substrate on which the aforementioned structure is formed, and the fourth conductive thin film is patterned by a patterning process to form a fourth conductive layer disposed on the fourth insulating layer. In some examples, the fourth conductive layer may also be referred to as a second source / drain metal layer.

[0196] Figure 11A is a partial schematic diagram of the display substrate after the fourth conductive layer is formed in at least one embodiment of the present disclosure. Figure 11B is a schematic diagram of the fourth conductive layer in Figure 11A. Figure 14 is a partial schematic diagram of the fourth conductive layer in at least one embodiment of the present disclosure. Figure 14 illustrates the fourth conductive layer corresponding to two rows (row i and row i+1) and six columns (columns j to j+5) of pixel circuits as an example.

[0197] In some examples, as shown in Figures 11A, 11B and 14, the fourth conductive layer of the display substrate may include: a plurality of connecting electrodes (e.g., including the fifteenth connecting electrode 215 to the eighteenth connecting electrode 218) and a plurality of first transition electrodes (e.g., including the first transition electrodes 301a, 301b, 301c, 301d, 301e, 301f, 301g).

[0198] In some examples, the orthographic projection of the fifteenth connecting electrode 215 onto the substrate can be a strip extending along the second direction D2. The fifteenth connecting electrode 215 can be connected to the first connecting electrode 201 through the twenty-third via V23, and can also be connected to the second connecting electrode 202 through the twenty-first via V21. The fifteenth connecting electrode 215 can serve as a third node N3, realizing the electrical connection between the second terminal of the first transistor T1, the first terminal of the fifth transistor T5, and the second terminal of the third transistor T3.

[0199] In some examples, the orthographic projection of the sixteenth connecting electrode 216 onto the substrate can be a strip extending along the second direction D2. The sixteenth connecting electrode 216 can be connected to the sixth connecting electrode 206 via the twenty-seventh via V27, to the first electrode C2-1 of the second capacitor via the twenty-second via V22, and to the eighth connecting electrode 208 via the twenty-fifth via V25. The sixteenth connecting electrode 216 can serve as the second node N2, enabling electrical connections between the first electrode of the third transistor T3, the second electrode of the seventh transistor T7, the second electrode of the sixth transistor T6, the first electrode of the second transistor T2, and the first electrode C2-1 of the second capacitor C2.

[0200] In some examples, the orthographic projection of the seventeenth connection electrode 217 onto the substrate can be approximately rectangular. The seventeenth connection electrode 217 can be connected to the third connection electrode 203 via the twenty-fourth via V24, thereby achieving an electrical connection with the first electrode of the fourth transistor T4.

[0201] In some examples, the orthographic projection of the eighteenth connecting electrode 218 onto the substrate can be approximately rectangular. The eighteenth connecting electrode 218 can be connected to the fifth connecting electrode 205 via the twenty-sixth via V26, thereby achieving an electrical connection with the first electrode of the sixth transistor T6.

[0202] In some examples, a first adapter electrode can be connected to a fifth node of a pixel circuit. For example, the first adapter electrode 301a can be projected onto the substrate in a generally bent strip shape extending along a first direction D1. The first adapter electrode 301a can be connected to the fourth connection electrode 204 connected to the pixel circuit in the i-th row and j-th column via the twenty-eighth via V28, thereby achieving electrical connection to the fifth node of the pixel circuit in the i-th row and j-th column. The first adapter electrode 301b can be projected onto the substrate in a straight strip shape extending along a second direction D2. The first adapter electrode 301b can be connected to the fourth connection electrode connected to the pixel circuit in the i-th row and (j+1)-th column, thereby achieving electrical connection to the fifth node of the pixel circuit in the i-th row and (j+1)-th column. The first adapter electrode 301c can be projected onto the substrate in a bent strip shape extending along a second direction D2. The first adapter electrode 301c can be connected to the fourth connection electrode connected to the pixel circuit in the i-th row and (j+2)-th column, thereby achieving electrical connection to the fifth node of the pixel circuit in the i-th row and (j+2)-th column. The orthographic projection of the first adapter electrode 301d onto the substrate can be approximately L-shaped. The first adapter electrode 301d can be electrically connected to the fifth node of the pixel circuit in the i-th row and j+3-th column. The orthographic projection of the first adapter electrode 301e onto the substrate can be approximately rectangular. The first adapter electrode 301e can be electrically connected to the fifth node of the pixel circuit in the (i+1)-th row and j+1-th column. The orthographic projection of the first adapter electrode 301f onto the substrate can be approximately a strip extending along the first direction D1. The first adapter electrode 301f can be electrically connected to the fifth node of the pixel circuit in the (i+1)-th row and j+2-th column. The orthographic projection of the first adapter electrode 301g onto the substrate can be approximately L-shaped, such as an L-shape rotated 90 degrees counterclockwise. The first adapter electrode 301g can be electrically connected to the fifth node of the pixel circuit in the (i+1)-th row and j+3-th column.

[0203] In some examples, the first transition electrodes 301b, 301c, and 301d adjacent along the first direction D1 can serve as a first group of first transition electrodes, and the first transition electrodes 301e, 301f, and 301g adjacent along the first direction D1 can serve as a second group of first transition electrodes. The first group of first transition electrodes and the second group of first transition electrodes can be arranged at intervals along the first direction D1 and the second direction D2 to achieve electrical connection corresponding to the fifth node of the multiple pixel circuits arranged in the array.

[0204] In some examples, the first transition electrode may include: a first end connected to the light-emitting element, and a second end connected to the fifth node of the pixel circuit. Specifically, the first transition electrode 301b may include: a first end 301b-1 and a second end 301b-2 connected to the fifth node of the pixel circuit in the i-th row and j+1-th column; the first transition electrode 301c may include: a first end 301c-1 and a second end 301c-2 connected to the fifth node of the pixel circuit in the i-th row and j+2-th column; the first transition electrode 301d may include: a first end 301d-1 and a second end 301d-2 connected to the fifth node of the pixel circuit in the i-th row and j+3-th column; A first adapter electrode 301e may include: a first end 301e-1 and a second end 301e-2 connected to the fifth node of the pixel circuit in the (i+1)th row and (j+1)th column; a first adapter electrode 301f may include: a first end 301f-1 and a second end 301f-2 connected to the fifth node of the pixel circuit in the (i+1)th row and (j+2)th column; a first adapter electrode 301g may include: a first end 301g-1 and a second end 301g-2 connected to the fifth node of the pixel circuit in the (i+1)th row and (j+3)th column.

[0205] In some examples, the first ends of multiple (e.g., six) first transition electrodes can be arranged in a group. For example, the first ends 301b-1 of first transition electrodes 301b, 301c-1 of first transition electrodes 301c, 301d-1 of first transition electrodes 301d, 301e-1 of first transition electrodes 301e, 301f-1 of first transition electrodes 301f, and 301g-1 of first transition electrodes 301g can be located between the pixel circuits in the i-th and i+1-th rows, for example, arranged in a two-row, three-column array. The first ends 301b-1 of first transition electrodes 301b, 301c-1 of first transition electrodes 301c, and 301d-1 of first transition electrodes 301d can be aligned in a row along the first direction D1. The first end 301e-1 of the first transfer electrode 301e, the first end 301f-1 of the first transfer electrode 301f, and the first end 301g-1 of the first transfer electrode 301g can be arranged in a row along the first direction D1.

[0206] In some examples, the first end 301b-1 of the first transition electrode 301b and the first end 301e-1 of the first transition electrode 301e can be aligned and arranged in a row along the second direction D2; the first end 301c-1 of the first transition electrode 301c and the first end 301f-1 of the first transition electrode 301f can be aligned and arranged in a row along the second direction D2; the first end 301d-1 of the first transition electrode 301d and the first end 301g-1 of the first transition electrode 301g can be aligned and arranged in a row along the second direction D2.

[0207] This example facilitates the electrical connection between the pixel circuit and the second electrode of the light-emitting element by centrally arranging the first ends of multiple first adapter electrodes connected to the light-emitting element.

[0208] (9) Forming a fifth insulating layer. In some examples, a fifth insulating film is coated on the substrate on which the aforementioned structure is formed, and the fifth insulating film is patterned by a patterning process to form a fifth insulating layer. In some examples, the fifth insulating layer may also be referred to as a second planarization layer.

[0209] Figure 12 is a partial schematic diagram of a display substrate after the formation of the fifth insulating layer in at least one embodiment of the present disclosure. In some examples, as shown in Figure 12, the fifth insulating layer of the display substrate may have multiple vias, such as vias V31 to V34. The fifth insulating layer within vias V31 to V34 may be removed, exposing a portion of the surface of the fourth conductive layer.

[0210] (10) Forming a fifth conductive layer. In some examples, a fifth conductive thin film is deposited on the substrate on which the aforementioned structure is formed, and the fifth conductive thin film is patterned by a patterning process to form a fifth conductive layer disposed on the fifth insulating layer. In some examples, the fifth conductive layer may also be referred to as a third source / drain metal layer.

[0211] Figure 13A is a partial schematic diagram of the display substrate after the formation of the fifth conductive layer in at least one embodiment of the present disclosure. Figure 13B is a schematic diagram of the fifth conductive layer in Figure 13A. Figure 15 is a partial schematic diagram of the fourth and fifth conductive layers in at least one embodiment of the present disclosure. Figure 16 is a partial schematic diagram of the fifth conductive layer in at least one embodiment of the present disclosure. Figures 15 and 16 illustrate the conductive layer corresponding to two rows (row i and row i+1) and six columns (columns j to j+5) of pixel circuits as an example.

[0212] In some examples, as shown in Figures 13A, 13B, 15, and 16, the fifth conductive layer of the display substrate may include: the second electrode C2-2 of the second capacitor C2 of multiple pixel circuits, multiple first power lines (e.g., first power lines VDD(j), VDD(j+1), VDD(j+2), VDD(j+3), VDD(j+4), VDD(j+5)), multiple second power lines (e.g., second power lines VSS(j), VSS(j+1), VSS(j+2), VSS(j+3), VSS(j+4), VSS(j+5)), multiple data lines (e.g., data lines DL(j), DL(j+1), DL(j+2), DL(j+3), DL(j+4), DL(j+5)), and multiple third transition electrodes (e.g., including third transition electrodes 303b, 303c, 303d, 303e, 303f, 303g).

[0213] In some examples, multiple data lines, multiple first power lines, and multiple second power lines may all extend along the second direction D2. In the first direction D1, the first power lines may be located between the data lines and the second power lines. For example, the first power line VDD(j) may be located between the data line DL(j) and the second power line VSS(j).

[0214] In some examples, a data line can provide a data signal to the fourth transistor of a column of pixel circuits. For example, the data line DL(j) can be connected to the seventeenth connection electrode 217 through the thirty-second via V32, thereby achieving an electrical connection to the first electrode of the fourth transistor T4 of the i-th row and j-th column pixel circuit.

[0215] In some examples, a second power line can provide a second power signal to the sixth transistor of a column of pixel circuits. For example, the second power line VSS(j) can be connected to the eighteenth connection electrode 218 through the thirty-first via V31, thereby achieving a first electrode connection to the sixth transistor T6 of the i-th row and j-th column pixel circuit.

[0216] In some examples, a second power line can be connected to the second electrode of the second capacitor of a column of pixel circuits. For example, the second power line VSS(j) can be connected to the second electrode C2-2 of the second capacitor of the i-th row and j-th column pixel circuit, and can be a single, integrated structure. The orthographic projection of the second electrode C2-2 onto the substrate can be approximately rectangular. The orthographic projection of the second electrode C2-2 onto the substrate of the second capacitor C2 can at least partially overlap with the orthographic projection of the first electrode C2-1 onto the substrate of the second capacitor C2. For example, the orthographic projection of the second electrode C2-2 onto the substrate of the second capacitor C2 can cover the orthographic projection of the first electrode C2-1 onto the substrate of the second capacitor C2.

[0217] In some examples, multiple third transition electrodes can be arranged in a cluster. For instance, six third transition electrodes 303b, 303c, 303d, 303e, 303f, and 303g can be arranged clustered between the pixel circuits in the i-th and i+1-th rows, such as in a two-row, three-column array. Third transition electrodes 303b, 303c, and 303d can be aligned in a row along the first direction D1, and third transition electrodes 303e, 303f, and 303g can also be arranged in a row along the first direction D1. The third transition electrodes 303b and 303e can be aligned in a row along the second direction D2 and located between the first power line VDD(j+1) and the second power line VSS(j+1); the third transition electrodes 303c and 303f can be aligned in a row along the second direction D2 and located between the data line DL(j+2) and the first power line VDD(j+2); the third transition electrodes 303d and 303g can be aligned in a row along the second direction D2 and located between the first power line VDD(j+2) and the second power line VSS(j+2).

[0218] In some examples, the third adapter electrode can be electrically connected to the first end of the first adapter electrode located in the fourth conductive layer through a via in the fifth insulating layer. For example, the third adapter electrode 303b can be electrically connected to the first end 301b-1 of the first adapter electrode 301b through the thirty-third via V33, and the third adapter electrode 303c can be electrically connected to the first end 301c-1 of the first adapter electrode 301c through the thirty-fourth via V34. The third adapter electrode 303d can be connected to the first end 301d-1 of the first adapter electrode 301d; the third adapter electrode 303e can be connected to the first end 301e-1 of the first adapter electrode 301e; the third adapter electrode 303f can be connected to the first end 301f-1 of the first adapter electrode 301f; and the third adapter electrode 303g can be connected to the first end 301g-1 of the first adapter electrode 301g.

[0219] (11) Forming a sixth insulating layer. In some examples, a sixth insulating film is coated on the substrate on which the aforementioned structure is formed, and the sixth insulating film is patterned by a patterning process to form a sixth insulating layer. In some examples, the sixth insulating layer may also be referred to as a third planarization layer.

[0220] Figure 17 is a partial schematic diagram of a display substrate after the formation of the sixth insulating layer in at least one embodiment of this disclosure. Figure 17 illustrates the fifth conductive layer and the sixth insulating layer as examples. In some examples, as shown in Figure 17, the sixth insulating layer of the display substrate may have multiple vias, for example, it may include: vias V41 to V48 (forty-first via V41 to forty-eighth via V48). The sixth insulating layer within vias V41 to V48 may be removed, exposing a portion of the surface of the fifth conductive layer.

[0221] At this point, the circuit structure layer of the display substrate is complete. The circuit structure layer in this example may include: a first conductive layer, a first insulating layer, a semiconductor layer, a second insulating layer, a second conductive layer, a third insulating layer, a third conductive layer, a fourth insulating layer, a fourth conductive layer, a fifth insulating layer, a fifth conductive layer, and a sixth insulating layer, sequentially disposed on the substrate.

[0222] In some examples, the first, second, third, fourth, and fifth conductive layers can be made of metallic materials, such as any one or more of silver (Ag), copper (Cu), aluminum (Al), and molybdenum (Mo), or alloys of the above metals, such as aluminum-neodymium alloy (AlNd) or molybdenum-niobium alloy (MoNb). These can be single-layer structures or multi-layer composite structures, such as Mo / Cu / Mo. The first, second, and third insulating layers can be made of any one or more of silicon oxide (SiOx, x>0), silicon nitride (SiNy, y>0), and silicon oxynitride (SiON). These can be single-layer, multi-layer, or composite layers. The fourth, fifth, and sixth insulating layers can be made of organic materials such as polyimide, acrylic, or polyethylene terephthalate. However, this embodiment is not limited in this regard.

[0223] Figure 18 is a schematic diagram illustrating the arrangement of multiple light-emitting elements according to at least one embodiment of the present disclosure. In some examples, as shown in Figure 18, the display substrate may further include a light-emitting structure layer located on the side of the circuit structure layer away from the substrate, and the light-emitting structure layer may include multiple light-emitting elements. The multiple light-emitting elements may include multiple groups of light-emitting elements. A group of light-emitting elements may include: a first light-emitting element emitting a first color light, a second light-emitting element emitting a second color light, and a third light-emitting element emitting a third color light. For example, the first color light may be red light, the second color light may be green light, and the third color light may be blue light.

[0224] In some examples, the multiple light-emitting element groups of the display substrate may include: multiple first-arranged light-emitting element groups ELA and multiple second-arranged light-emitting element groups ELB. For example, the first-arranged light-emitting element group ELA may include: a first light-emitting element ELA-1, a second light-emitting element ELA-2, and a third light-emitting element ELA-3. The first light-emitting element ELA-1 and the second light-emitting element ELA-2 may be located on the same side of the third light-emitting element ELA-3 along a first direction D1, and the first light-emitting element ELA-1 and the second light-emitting element ELA-2 may be aligned along a second direction D2. The second-arranged light-emitting element group ELB may include: a first light-emitting element ELB-1, a second light-emitting element ELB-2, and a third light-emitting element ELB-3. The first light-emitting element ELB-1 and the second light-emitting element ELB-2 may be located on the same side of the third light-emitting element ELB-3 along a first direction D1, and the arrangement order of the first light-emitting element ELB-1 and the second light-emitting element ELB-2 along the second direction D2 may be the reverse of the arrangement order of the first light-emitting element ELA-1 and the second light-emitting element ELA-2 along the second direction D2. In this example, the adjacent first row of light-emitting element group ELA and the second row of light-emitting element group ELB can be mirror images of each other about the midline between them.

[0225] In some examples, multiple first-row light-emitting element groups ELA and multiple second-row light-emitting element groups ELB can be arranged in an array, for example, they can be arranged at intervals along a first direction D1 and at intervals along a second direction D2. The multiple first-row light-emitting elements and the multiple second-row light-emitting elements can be aligned along the second direction D2, and the multiple third-row light-emitting elements can also be aligned along the second direction D2.

[0226] The following example illustrates the fabrication process of the light-emitting structure layer of a display substrate.

[0227] (12) Forming an anode layer. In some examples, an anode thin film is deposited on the substrate on which the aforementioned structure is formed, and the anode thin film is patterned by a patterning process to form an anode layer disposed on the sixth insulating layer.

[0228] Figure 19 is a partial schematic diagram of a display substrate after the anode layer has been formed in at least one embodiment of the present disclosure. Figure 19 illustrates the fifth conductive layer and the anode layer as an example. Figure 20 is a schematic diagram of the anode layer in Figure 19. In some examples, as shown in Figures 18 and 19, the anode layer of the display substrate may include: anodes of multiple light-emitting elements (e.g., anodes ELA-11 of the first light-emitting element ELA-1, ELA-21 of the second light-emitting element ELA-2, ELA-31 of the third light-emitting element ELA-3, ELB-11 of the first light-emitting element ELB-1, ELB-21 of the second light-emitting element ELB-2, and ELB-31 of the third light-emitting element ELB-3), and multiple second transition electrodes (e.g., second transition electrodes 302b, 302c, 302d, 302e, 302f, 302g).

[0229] In some examples, the orthographic projection of the anodes of multiple light-emitting elements onto the substrate can be approximately rectangular. Taking the first row of light-emitting element group ELA as an example, the orthographic projection area of ​​the anode ELA-11 of the first light-emitting element ELA-1 onto the substrate can be smaller than the orthographic projection area of ​​the anode ELA-21 of the first light-emitting element ELA-2 onto the substrate, and the orthographic projection area of ​​the anode ELA-21 of the first light-emitting element ELA-2 onto the substrate can be smaller than the orthographic projection area of ​​the anode ELA-31 of the first light-emitting element ELA-3 onto the substrate.

[0230] In some examples, the anode of the light-emitting element can be connected to the first power line. The anodes of the second light-emitting element ELA-2 in the first row of light-emitting element group ELA and the first light-emitting element ELB-1 in the second row of light-emitting element group ELB, both located in the same column, can be connected to the same first power line. Similarly, the anodes of the third light-emitting element ELA-3 in the first row of light-emitting element group ELA and the third light-emitting element ELB-3 in the second row of light-emitting element group ELB, both located in the same column, can be connected to the same first power line. For example, the anode ELA-21 of the second light-emitting element ELA-2 can be connected to the first power line VDD(j) through the forty-first via V41, and the anode ELB-11 of the first light-emitting element ELB-1 can be connected to the first power line VDD(j) through the forty-second via V42. The anode ELA-11 of the first light-emitting element ELA-1 can be connected to the first power line VDD(j+1) through via V43 (forty-three). The anode ELB-21 of the second light-emitting element ELB-2 can be connected to the first power line VDD(j+1) through via V44 (forty-fourth). The anode ELA-31 of the third light-emitting element ELA-3 can be connected to the first power line VDD(j+2) through via V45 (forty-fifth). The anode ELB-31 of the third light-emitting element ELB-3 can be connected to the first power line VDD(j+2) through via V46 (forty-sixth). In some other examples, the anodes of the first light-emitting elements in the same column can be connected to the same first power line, and the anodes of the second light-emitting elements in the same column can be connected to the same first power line.

[0231] In other examples, the number of first power lines on the display substrate can be reduced, thereby increasing the spacing between adjacent traces on the fifth conductive layer. For example, multiple first light-emitting elements and multiple second light-emitting elements aligned along the second direction D2 can be connected to the same first power line. For instance, in Figure 19, the first power lines VDD(j+1) and VDD(j+4) can be omitted, and the anodes ELA-11 of the first light-emitting element ELA-1, ELA-21 of the second light-emitting element ELA-2, ELB-1 of the first light-emitting element ELB-1, and ELB-21 of the second light-emitting element ELB-2 can all be connected to the first power line VDD(j). Furthermore, the anodes of multiple light-emitting elements in the same light-emitting element group can be connected to the same first power line. For example, in Figure 19, the first power lines VDD(j), VDD(j+2), VDD(j+3), and VDD(j+5) can be omitted, and the anodes ELA-11 of the first light-emitting element ELA-1, ELA-21 of the second light-emitting element ELA-2, and ELA-31 of the third light-emitting element ELA-3 can all be connected to the first power line VDD(j+1). This embodiment is not limited in this respect.

[0232] In some examples, multiple second transition electrodes can be arranged together as a group of second transition electrodes, which can be located between two adjacent light-emitting element groups along the second direction D2. For example, six second transition electrodes 302b, 302c, 302d, 302e, 302f, and 302g can be a group of second transition electrodes, and the orthographic projection of this group of second transition electrodes onto the substrate can be located between the orthographic projections of the anode of the third light-emitting element ELA-31 of the first light-emitting element group ELA and the anode of the third light-emitting element ELB-31 of the second light-emitting element group ELB adjacent along the second direction D2 onto the substrate.

[0233] In some examples, the orthographic projection of each second adapter electrode onto the substrate can be approximately rectangular. Multiple second adapter electrodes can be electrically connected to multiple third adapter electrodes one-to-one vias formed in the sixth insulating layer. For example, second adapter electrode 302b can be electrically connected to third adapter electrode 303b via the forty-seventh via V47; second adapter electrode 302e can be electrically connected to third adapter electrode 303e via the forty-eighth via V48; second adapter electrode 302c can be electrically connected to third adapter electrode 303c; second adapter electrode 302f can be electrically connected to third adapter electrode 303f; second adapter electrode 302d can be electrically connected to third adapter electrode 303d; and second adapter electrode 302g can be electrically connected to third adapter electrode 303g.

[0234] In some examples, multiple second transition electrodes within a group of second transition electrodes can be arranged in an array. For example, six second transition electrodes 302b, 302c, 302d, 302e, 302f, and 302g can be arranged in a two-row, three-column array. Specifically, second transition electrodes 302b, 302c, and 302d can be aligned along the first direction D1 in one row, second transition electrodes 302e, 302f, and 302g can be aligned along the first direction D1 in one row, second transition electrodes 302b and 302e can be aligned along the second direction D2 in one column, second transition electrodes 302c and 302f can be aligned along the second direction D2 in one column, and second transition electrodes 302d and 302g can be aligned along the second direction D2 in one column.

[0235] (13) Forming a pixel definition layer. In some examples, a pixel definition film is coated on the substrate on which the aforementioned structure is formed, and the pixel definition film is patterned by a patterning process to form a pixel definition layer disposed on the anode layer. For example, the pixel definition film can be made of organic materials such as polyimide, acrylic, or polyethylene terephthalate.

[0236] Figure 21 is a partial schematic diagram of a display substrate after the pixel definition layer has been formed in at least one embodiment of this disclosure. Figure 21 illustrates the pixel definition layer, the anode layer, the fifth conductive layer, and the fourth conductive layer. In some examples, as shown in Figure 21, the pixel definition layer of the display substrate may have multiple pixel openings (e.g., including pixel openings OPA1, OPA2, OPA3, OPB1, OPB2, OPB3) and multiple transition openings K1. The pixel definition films within the multiple pixel openings and the multiple transition openings K1 can be removed, exposing a portion of the surface of the anode layer.

[0237] In some examples, the orthographic projection of the transition opening K1 onto the substrate can be approximately rectangular. The transition opening K1 can expose the surfaces of multiple second transition electrodes. For example, the orthographic projection of one transition opening K1 onto the substrate can cover the orthographic projections of six second transition electrodes onto the substrate. In this example, removing the pixel definition layer on the side of a set of second transition electrodes away from the substrate facilitates subsequent electrode bonding to achieve electrical connection between the second transition electrodes and the second electrodes of the light-emitting element.

[0238] In some examples, the orthographic projection of multiple pixel openings onto the substrate can be approximately rectangular. Pixel openings can expose a portion of the anode surface of the light-emitting element. For example, pixel opening OPA1 can expose a portion of the anode surface ELA-11 of the first light-emitting element ELA-1, pixel opening OPA2 can expose a portion of the anode surface ELA-21 of the second light-emitting element ELA-2, and pixel opening OPA3 can expose a portion of the anode surface ELA-31 of the third light-emitting element ELA-3; pixel opening OPB1 can expose a portion of the anode surface ELB-11 of the first light-emitting element ELB-1; pixel opening OPB2 can expose a portion of the anode surface ELB-21 of the second light-emitting element ELB-2; and pixel opening OPB3 can expose a portion of the anode surface ELB-31 of the third light-emitting element ELB-3.

[0239] In some examples, the projected areas of pixel apertures OPA1 and OPB1 on the substrate can be approximately the same, the projected areas of pixel apertures OPA2 and OPB2 on the substrate can be approximately the same, and the projected areas of pixel apertures OPA3 and OPB3 on the substrate can be approximately the same. The projected area of ​​pixel aperture OPA1 on the substrate can be smaller than the projected area of ​​pixel aperture OPA2 on the substrate, and the projected area of ​​pixel aperture OPA2 on the substrate can be smaller than the projected area of ​​pixel aperture OPA3 on the substrate.

[0240] In some examples, the light-emitting area of ​​a light-emitting element can be the portion of a pixel opening located in the pixel definition layer. For example, the light-emitting area of ​​the first light-emitting element ELA-1 corresponds to pixel opening OPA1, the light-emitting area of ​​the second light-emitting element ELA-2 corresponds to pixel opening OPA2, and the light-emitting area of ​​the third light-emitting element ELA-3 corresponds to pixel opening OPA3. The light-emitting areas of the first light-emitting element ELA-1, the second light-emitting element ELA-2, and the third light-emitting element ELA-3 can all be approximately rectangular. The maximum length of the light-emitting area of ​​the first light-emitting element ELA-1 along the first direction D1 can be greater than the maximum length along the second direction D2; the maximum length of the light-emitting area of ​​the second light-emitting element ELA-2 along the first direction D1 can be less than the maximum length along the second direction D2; and the maximum length of the light-emitting area of ​​the third light-emitting element ELA-3 along the first direction D1 can be less than the maximum length along the second direction D2.

[0241] In some examples, the area of ​​the light-emitting region of the first light-emitting element ELA-1 may be smaller than the area of ​​the light-emitting region of the second light-emitting element ELA-2, and the area of ​​the light-emitting region of the second light-emitting element ELA-2 may be smaller than the area of ​​the light-emitting region of the third light-emitting element ELA-3.

[0242] (14) Forming an isolation structure. In some examples, an isolation structure 51 is formed on the substrate on which the aforementioned structure is formed. FIG22A is a schematic diagram of a display substrate after the isolation structure is formed in at least one embodiment of the present disclosure. FIG22A mainly illustrates the anode layer, pixel definition layer and isolation structure as examples. FIG22B is a plan view of the isolation structure in FIG22A. FIG22C is a partial cross-sectional view along the PP' direction in FIG22A. FIG22D is a partial cross-sectional view along the QQ' direction in FIG22A. FIG22C shows the sixth insulating layer 106 and the pixel definition layer 107, as well as the film layer of the pixel definition layer 107 away from the substrate; FIG22D shows the fifth insulating layer 105, as well as the film layer of the fifth insulating layer 105 away from the substrate.

[0243] In some examples, as shown in Figures 22A to 22D, the isolation structure 51 of the display substrate can be a mesh structure, having multiple meshes 510. The meshes 510 can surround the light-emitting area of ​​a light-emitting element, configured to isolate the second electrodes of light-emitting elements within adjacent meshes. In other examples, the meshes 510 can surround the light-emitting areas of one or more light-emitting elements emitting the same color light, and the light-emitting elements surrounded by the meshes 510 can be connected to the same pixel circuit.

[0244] In some examples, the isolation structure 51 may include a plurality of first isolation strips extending along a first direction D1 and a plurality of second isolation strips extending along a second direction D2, the plurality of first isolation strips and the plurality of second isolation strips being connected around to form a plurality of grids 510.

[0245] In some examples, as shown in Figures 22C and 22D, the isolation structure 51 may include a first isolation layer 511 and a second isolation layer 512. The second isolation layer 512 may be located on the side of the first isolation layer 511 away from the substrate. For example, the material of the first isolation layer 511 may include an organic material, and the material of the second isolation layer 512 may include a chemical mechanical polishing (CMP) material. The first isolation layer 511 may be in the same layer as the isolation pillar. For example, during the fabrication of the isolation structure 51, an organic material may be coated on the substrate on which the aforementioned structure is formed, and a CMP material may be deposited. Subsequently, a patterning process (e.g., etching) may be performed on the CMP material and the organic material to form the morphology of the isolation structure 51.

[0246] In some examples, as shown in Figures 22C and 22D, the first isolation layer 511 may include an isolation main body 5111 and an isolation extension 5112. The isolation extension 5112 may be located on the side of the isolation main body 5111 away from the substrate, and the isolation extension 5112 may protrude from the sidewall of the isolation main body 5111 in a direction parallel to the substrate. The orthographic projection of the surface of the isolation main body 5111 near the substrate onto the substrate may cover the orthographic projection of the surface away from the substrate onto the substrate. For example, the cross-sectional shape of the isolation main body 5111 along the extension direction perpendicular to the substrate and perpendicular to the first isolation layer 511 may be approximately trapezoidal. The orthographic projection of the surface of the isolation extension 5112 away from the substrate onto the substrate may cover the orthographic projection of the surface near the substrate onto the substrate. For example, the area of ​​multiple cross-sectional layers of the isolation extension 5112 parallel to the plane of the substrate along the direction away from the substrate may gradually increase and remain constant, or gradually increase. For example, the sidewall of the isolation extension 5112 protruding from the isolation main body 5111 may be an arc-shaped sidewall. The cross-sectional shape of the first isolation layer 511 along the extension direction perpendicular to the substrate and perpendicular to the first isolation layer 511 can be approximately mushroom-shaped.

[0247] In some examples, the orthographic projection of the grid 510 of the isolation structure 51 onto the substrate may overlap with the orthographic projection of the second transfer electrode onto the substrate. As shown in FIG22D, the isolation structure 51 may separate the second transfer electrodes 302f and 302e, and also separate the second transfer electrodes 302f and 302g.

[0248] (15) Forming a light-emitting functional layer and a cathode layer. In some examples, a light-emitting functional layer is formed within the aforementioned pixel opening, and the light-emitting functional layer is in contact with the anode layer exposed by the pixel opening. Subsequently, a cathode film is deposited, and the cathode film is patterned using the isolation structure 51 to form a cathode layer. The cathode layer may include the cathodes of multiple light-emitting elements.

[0249] In some examples, after forming the cathode layer, an auxiliary conductive film can be deposited on the substrate where the aforementioned structure is formed, and the auxiliary conductive film can be patterned using the isolation structure 51 to form an auxiliary conductive layer. In some examples, the material of the auxiliary conductive film may include metallic materials, such as magnesium (Mg) and silver (Ag).

[0250] Figure 23 is a schematic diagram of a display substrate after forming a cathode layer in at least one embodiment of the present disclosure. Figure 24 is a partially enlarged schematic diagram of region O1 in Figure 23. The cathode layer is not shown in Figure 24. Figure 25A is a partial cross-sectional schematic diagram of the display substrate after forming an auxiliary conductive layer in at least one embodiment of the present disclosure along the PP' direction; Figure 25B is a partial cross-sectional schematic diagram of the display substrate after forming an auxiliary conductive layer in at least one embodiment of the present disclosure along the QQ' direction.

[0251] In some examples, as shown in Figures 23 to 25B, the light-emitting functional layers of light-emitting elements within adjacent grids 510 can be separated by the isolation structure 51. For example, the light-emitting functional layer ELA-22 of the second light-emitting element ELA-2 and the light-emitting functional layer ELA-32 of the adjacent third light-emitting element ELA-3 can be separated by the isolation structure 51. The cathodes of light-emitting elements within adjacent grids 510 can be separated by the isolation structure 51. For example, the cathode ELA-23 of the second light-emitting element ELA-2 and the cathode ELA-33 of the adjacent third light-emitting element ELA-3 can be separated by the isolation structure 51.

[0252] In some examples, the cathode of a light-emitting element can be connected to a second transition electrode surrounded by the same grid 510 to achieve an electrical connection with the pixel circuitry. For example, the cathode of the first light-emitting element ELA-1 can be connected to the second transition electrode 302b, the cathode of the third light-emitting element ELA-3 can be connected to the second transition electrode 302c, the cathode of the first light-emitting element ELB-1 can be connected to the second transition electrode 302e, and the cathode of the second light-emitting element ELB-3 can be connected to the second transition electrode 302f. The second transition electrode 302d can be connected to the cathode of a second light-emitting element in another second arrangement of light-emitting elements, and the second transition electrode 302g can be connected to the cathode of a second light-emitting element in another first arrangement of light-emitting elements.

[0253] In some examples, the first power line to which the anode of at least one light-emitting element is connected and the pixel circuit to which the cathode of the light-emitting element is connected may overlap on the substrate in their orthogonal projections. For example, the anode of the first light-emitting element ELA-1 is connected to the first power line VDD(j+1), and the cathode of the first light-emitting element ELA-1 is connected to the fifth node of the pixel circuit in the i-th row and j+1-th column. The anode of the third light-emitting element ELA-3 is connected to the first power line VDD(j+2), and the cathode of the third light-emitting element ELA-3 is connected to the fifth node of the pixel circuit in the i-th row and j+2-th column.

[0254] In some examples, as shown in Figures 23, 25A, and 25B, the auxiliary conductive layer of the display substrate may include a plurality of lap electrodes 305 and a plurality of auxiliary electrodes 36. The lap electrodes 305 may be located in region O1, which is a region where a set of second transition electrodes is disposed. Within region O1, the lap electrodes 305 may be in direct contact with the cathode of the light-emitting element (e.g., the cathode ELB-23 of the second light-emitting element ELB-2) and the second transition electrode (e.g., the second transition electrode 302f). Within region O1, the cathode of the light-emitting element and the second transition electrode located in the anode layer are separated by a non-functional layer 35. The non-functional layer 35 is a co-layer structure with the light-emitting functional layer and is not used to form the light-emitting element. The lap electrode 305 and the surface of the cathode ELB-23 of the second light-emitting element ELB-2 away from the substrate, as well as the second transfer electrode 302f, are not in direct contact with the surface of the cathode ELB-23 of the second light-emitting element ELB-2, thereby realizing the electrical connection between the cathode ELB-23 of the second light-emitting element ELB-2 and the second transfer electrode 302f.

[0255] In some examples, the orthographic projection of the auxiliary electrode 36 onto the substrate may at least partially overlap with the orthographic projection of the cathode of the light-emitting element onto the substrate. For example, the auxiliary electrode 36 and the overlapping electrode 305 located in the same grid 510 of the isolation structure 51 may be an integral structure, the orthographic projection of which onto the substrate may cover the orthographic projection of the cathode of the light-emitting element onto the substrate within the grid 510.

[0256] In this example, after the cathode film is deposited, the cathodes of the light-emitting elements located in adjacent grids are isolated by the isolation structure 51. By setting an auxiliary conductive layer to form multiple overlapping electrodes 305, the electrical connection between the cathode of the light-emitting element and the second transfer electrode can be guaranteed.

[0257] In this example, the cathode of the light-emitting element can be connected to the fifth node of the corresponding pixel circuit in sequence through the overlapping electrode, the second transition electrode, the third transition electrode, and the first transition electrode.

[0258] In some examples, the second isolation layer 512 of the isolation structure 51 is made of CMP material, which can prevent the auxiliary conductive layer from being deposited on the surface of the isolation structure 51 away from the substrate.

[0259] In some examples, after fabricating the light-emitting structure layer, an encapsulation structure layer can be formed on the cathode layer. In some examples, the encapsulation structure layer may include a first encapsulation layer, a second encapsulation layer, and a third encapsulation layer stacked together. The first and third encapsulation layers may be made of inorganic materials, while the second encapsulation layer may be made of organic materials. The second encapsulation layer may be disposed between the first and third encapsulation layers, forming an inorganic / organic / inorganic material stacked structure, which can ensure that external moisture cannot enter the light-emitting structure layer. In some possible implementations, the display substrate may also include other film layers, such as a touch structure layer, a color filter layer, etc., which are not limited in this embodiment.

[0260] The structure and fabrication process of the display substrate in this embodiment are merely illustrative. In some exemplary embodiments, the corresponding structure and patterning processes can be modified and added or reduced according to actual needs. The fabrication process of this exemplary embodiment can be implemented using currently mature fabrication equipment, is well compatible with existing fabrication processes, is simple to implement, easy to carry out, has high production efficiency, low production cost, and high yield.

[0261] The display substrate provided in this embodiment, by setting overlapping electrodes and multiple transition electrodes (e.g., including a second transition electrode, a third transition electrode, and a first transition electrode), can realize the connection between the cathode of the light-emitting element and the pixel circuit, thus meeting the driving requirements of the light-emitting element. Moreover, the isolation structure set in this example has better stability and reliability, which is beneficial for realizing the patterning of the cathode layer.

[0262] Figure 26A is another partial cross-sectional view of the display substrate after the auxiliary conductive layer is formed in at least one embodiment of the present disclosure along the PP' direction; Figure 26B is another partial cross-sectional view of the display substrate after the auxiliary conductive layer is formed in at least one embodiment of the present disclosure along the QQ' direction.

[0263] In some examples, as shown in Figures 26A and 26B, the isolation structure 51 may include a first isolation layer 511 and a second isolation layer 512. The material of the first isolation layer 511 may include an organic material, and the material of the second isolation layer 512 may include an inorganic material. For example, in the fabrication process of the isolation structure 51, an organic material may be coated on the substrate on which the aforementioned structure is formed, and an inorganic material (e.g., including silicon nitride) may be deposited. Subsequently, the inorganic material may be dry-etched, and then the organic material may be etched by development to form the morphology of the isolation structure 51.

[0264] In some examples, the auxiliary conductive layer may include: a lap electrode 305, an auxiliary electrode 36, and a deactivated auxiliary electrode 37 located on the side of the isolation structure 51 away from the substrate. The lap electrode 305 is in direct contact with the cathode of the light-emitting element and the corresponding second transfer electrode, and the auxiliary electrode 36 is in direct contact with the cathode of the corresponding light-emitting element. The deactivated auxiliary electrode 37 is auxiliary conductive material remaining on the side of the isolation structure 51 away from the substrate. The remaining structure of the display substrate in this example can be referred to the description of the foregoing embodiments, and therefore will not be repeated here.

[0265] Figure 27 is another partial cross-sectional view of the display substrate along the QQ' direction after the auxiliary conductive layer has been formed in at least one embodiment of this disclosure. In some examples, as shown in Figure 27, the isolation structure 51 may include a first isolation layer 511 and a second isolation layer 512. The material of the first isolation layer 511 may include an organic material, and the material of the second isolation layer 512 may include a metallic material. For example, in the fabrication process of the isolation structure 51, an organic material may be coated on the substrate on which the aforementioned structure is formed, and a metallic material may be deposited. Subsequently, the metallic material may be dry-etched, and then the organic material may be etched by development to form the morphology of the isolation structure 51. The remaining structure of the display substrate of this example can be referred to the description of the foregoing embodiments, and therefore will not be repeated here.

[0266] Figure 28 is another partial cross-sectional view of the display substrate along the QQ' direction after the auxiliary conductive layer has been formed in at least one embodiment of this disclosure. In some examples, as shown in Figure 28, the isolation structure 51 may include a first isolation layer 511 and a second isolation layer 512. The orthographic projection of the surface of the first isolation layer 511 away from the substrate onto the substrate may cover the orthographic projection of the surface of the first isolation layer 511 close to the substrate onto the substrate. The cross-sectional shape of the first isolation layer 511 along the extension direction perpendicular to the substrate and perpendicular to the first isolation layer 511 may be approximately inverted trapezoidal.

[0267] In some examples, the material of the first isolation layer 511 may include an organic material, and the material of the second isolation layer 512 may include a CMP material. For example, during the fabrication of the isolation structure 51, an organic material may be coated on the substrate on which the aforementioned structure is formed, and a CMP material may be deposited. Subsequently, the CMP material may be etched, and then the organic material may be etched by development to form the morphology of the isolation structure 51. The remaining structure of the display substrate in this example can be referred to the description of the foregoing embodiments, and therefore will not be repeated here.

[0268] This embodiment also provides a display substrate, including: a substrate, a plurality of pixel circuits and a plurality of light-emitting elements disposed on the substrate. The light-emitting elements include: a first electrode, a light-emitting functional layer, and a second electrode sequentially disposed along a direction away from the substrate; the first electrode is connected to a first power line, and the second electrode is connected to the pixel circuits. At least one pixel circuit includes: a driving transistor, a compensation transistor, a first capacitor, and a second capacitor; the first electrode of the first capacitor is connected to the gate of the driving transistor, the second electrode of the first capacitor is connected to the second electrode of the compensation transistor, the first electrode of the compensation transistor is connected to the first electrode of the driving transistor and the first electrode of the second capacitor, and the second electrode of the second capacitor is connected to a second power line. The second electrode of the first capacitor includes: a first sub-electrode and a second sub-electrode connected to each other; the first sub-electrode of the first capacitor is located on the side of the second sub-electrode closer to the substrate, and the second electrode of the first capacitor is located on the side of the first sub-electrode away from the substrate and on the side of the second sub-electrode closer to the substrate. The first electrode of the second capacitor is located on the side of the second electrode of the second capacitor closer to the substrate, and the first electrode of the second capacitor and the second sub-electrode of the first capacitor are of the same layer structure.

[0269] In some exemplary embodiments, the active layer of the driving transistor is projected in an L-shape onto the substrate.

[0270] In some exemplary embodiments, the at least one pixel circuit further includes: a data writing transistor, the gate of which is connected to a first scan line, a first electrode of which is connected to a data line, and a second electrode of which is connected to the second electrode of the compensation transistor and the second electrode of the first capacitor. The active layer of the compensation transistor and the active layer of the data writing transistor are integral structures and are located on the same side of the first capacitor and the driving transistor along the second direction.

[0271] In some exemplary embodiments, the at least one pixel circuit further includes: a first reset transistor, a second reset transistor, and a third reset transistor. The gate of the first reset transistor is connected to a first reset control line, the first terminal of the first reset transistor is connected to a first initial signal line, and the second terminal of the first reset transistor is connected to the second terminal of the driving transistor. The gate of the second reset transistor is connected to a second reset control line, the first terminal of the second reset transistor is connected to a second initial signal line, and the second terminal of the second reset transistor is connected to the first terminal of the driving transistor. The gate of the third reset transistor is connected to a third reset control line, the first terminal of the third reset transistor is connected to a reference signal line, and the second terminal of the third reset transistor is connected to the gate of the driving transistor. The first reset transistor and the third reset transistor are located on the same side of the driving transistor along a second direction, and the second reset transistor is located on the other side of the driving transistor along the second direction. The first reset control line, the second reset control line, and the third reset control line are in the same layer, and the first initial signal line, the second initial signal line, and the reference signal line are in the same layer.

[0272] In some exemplary embodiments, the at least one pixel circuit further includes: a fourth reset transistor; the gate of the fourth reset transistor is connected to a fourth reset control line, the first electrode of the fourth reset transistor is connected to a third initial signal line, and the second electrode of the fourth reset transistor is connected to the second electrode of the light-emitting element. Multiple pixel circuits arranged along a first direction constitute a row of pixel circuits, and the gate of the second reset transistor in one row of pixel circuits and the gate of the fourth reset transistor in another row of pixel circuits are integrally formed.

[0273] In some exemplary embodiments, the at least one pixel circuit further includes: a first light-emitting control transistor and a second light-emitting control transistor. The gate of the first light-emitting control transistor is connected to a light-emitting control line, a first electrode of the first light-emitting control transistor is connected to a second electrode of the driving transistor, and the second electrode of the first light-emitting control transistor is connected to a second electrode of the light-emitting element. The gate of the second light-emitting control transistor is connected to the light-emitting control line, a first electrode of the second light-emitting control transistor is connected to a second power supply line, and the second electrode of the second light-emitting control transistor is connected to a first electrode of the driving transistor. The first light-emitting control transistor and the second light-emitting control transistor of the at least one pixel circuit are aligned along a first direction; the active layer of the first light-emitting control transistor and the active layer of the first reset control transistor are integrally formed.

[0274] In some exemplary embodiments, in a direction perpendicular to the display substrate, the display substrate includes: a first conductive layer, a semiconductor layer, a second conductive layer, a third conductive layer, a fourth conductive layer, and a fifth conductive layer sequentially disposed on the substrate. The first conductive layer includes: the bottom gate of at least one transistor of the at least one pixel circuit; the semiconductor layer includes: the active layer of at least one transistor of the at least one pixel circuit; the second conductive layer includes: the gate of at least one transistor of the at least one pixel circuit; the second power line is located on the fifth conductive layer; the first sub-electrode of the first capacitor is located on the first conductive layer, the second sub-electrode of the first capacitor is located on the third conductive layer, and the first electrode of the first capacitor is located on the second conductive layer; the first electrode of the second capacitor is located on the third conductive layer, and the second electrode of the second capacitor is located on the fifth conductive layer.

[0275] In some exemplary embodiments, the material of the semiconductor layer includes an oxide semiconductor material.

[0276] The structure of the display substrate in this example can be referred to the description of the foregoing embodiments, and therefore will not be repeated here.

[0277] Figure 29 is a schematic diagram of a display device according to at least one embodiment of the present disclosure. As shown in Figure 29, this embodiment provides a display device 91, including a display substrate 910. In some examples, the display substrate 910 can be a flexible OLED display substrate, a QLED display substrate, a Micro-LED display substrate, or a Mini-LED display substrate. The display device 91 can be a product with image (including static images or dynamic images, wherein the dynamic image can be video) display function. For example, the display device can be any of the following products: monitor, television, billboard, digital photo frame, laser printer with display function, telephone, mobile phone, drawing screen, personal digital assistant (PDA), digital camera, portable camcorder, viewfinder, navigator, vehicle, large-area wall, information query equipment (such as business query equipment of e-government, bank, hospital, power and other departments), monitor, etc. Furthermore, the display device can also be any of the following products: microdisplay, VR device or AR device including microdisplay, etc.

[0278] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of this application. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in a suitable manner in any one or more embodiments or examples. Moreover, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described in this specification, as well as the features of different embodiments or examples.

[0279] Although embodiments of this application have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting this application. Those skilled in the art can make changes, modifications, substitutions and variations to the above embodiments within the scope of this application.

Claims

1. A display substrate, comprising: The substrate includes a display area and a peripheral area surrounding the display area; Multiple pixel circuits and multiple light-emitting elements are disposed on the substrate and located in the display area; At least one of the plurality of light-emitting elements includes: a first electrode, a light-emitting functional layer, and a second electrode arranged sequentially along a direction away from the substrate; the first electrode of the at least one light-emitting element is connected to a first power line, and the second electrode of the at least one light-emitting element is connected to at least one pixel circuit among the plurality of pixel circuits; An isolation structure is located on the side of the first electrode of the at least one light-emitting element away from the substrate. The isolation structure has a plurality of grids, each grid surrounding the light-emitting area of ​​the at least one light-emitting element. The isolation structure is configured to isolate the second electrodes of the light-emitting elements located in adjacent grids.

2. The display substrate according to claim 1, wherein, The isolation structure includes: a first isolation layer and a second isolation layer, wherein the second isolation layer is located on the side of the first isolation layer away from the substrate, and the hardness of the material of the second isolation layer is greater than the hardness of the material of the first isolation layer.

3. The display substrate according to claim 2, wherein, The material of the first isolation layer includes organic materials; the material of the second isolation layer includes at least one of the following: inorganic materials, chemical mechanical polishing materials, and metallic materials.

4. The display substrate according to claim 2, wherein, The first isolation layer includes an isolation main body and an isolation extension, wherein the isolation extension is located on the side of the isolation main body away from the substrate, and the isolation extension protrudes from the sidewall of the isolation main body in a direction parallel to the substrate.

5. The display substrate according to claim 2, wherein, The orthographic projection of the surface of the first isolation layer away from the substrate onto the substrate includes the orthographic projection of the surface of the first isolation layer near the substrate onto the substrate. The first isolation layer includes: a plurality of cross-sectional layers parallel to the plane of the substrate along a direction away from the substrate; the area of ​​the plurality of cross-sectional layers gradually decreases and then gradually increases along the direction away from the substrate, or gradually increases along the direction away from the substrate.

6. The display substrate according to any one of claims 1 to 5, further comprising: Multiple first transfer electrodes; The second electrode of at least one light-emitting element is connected to the pixel circuit through the first adapter electrode; The first adapter electrode is located on the side of the second electrode closer to the substrate; The first adapter electrode includes: a first end connected to the second electrode, and a second end connected to the pixel circuit; The first ends of multiple first adapter electrodes are arranged in a concentrated manner.

7. The display substrate according to claim 6, further comprising: Multiple second transfer electrodes; The second electrode of the at least one light-emitting element is connected to the first transfer electrode via the second transfer electrode, wherein the second transfer electrode is located on the side of the first transfer electrode away from the substrate and on the side of the second electrode close to the substrate.

8. The display substrate according to claim 7, wherein, The plurality of second transfer electrodes and the first electrode of the at least one light-emitting element are in the same layer structure.

9. The display substrate according to claim 8, wherein, The second electrode of the at least one light-emitting element is connected to the second transfer electrode via a lap electrode, the lap electrode being located on the side of the second electrode away from the substrate; The lap electrode is in direct contact with the second electrode and the second transfer electrode.

10. The display substrate according to claim 7, wherein, The plurality of light-emitting elements includes: a plurality of light-emitting element groups; At least one of the plurality of light-emitting element groups includes: a first light-emitting element emitting a first color light, a second light-emitting element emitting a second color light, and a third light-emitting element emitting a third color light, wherein the first light-emitting element and the second light-emitting element are located on the same side of the third light-emitting element along a first direction, and the first light-emitting element and the second light-emitting element are aligned along a second direction, wherein the first direction and the second direction intersect. A set of second transition electrodes includes: a plurality of second transition electrodes that are connected one-to-one with the first ends of a plurality of first transition electrodes arranged in a central manner; the set of second transition electrodes is located between two adjacent light-emitting element groups along the second direction.

11. The display substrate according to claim 10, wherein, The plurality of light-emitting element groups include: a plurality of first arrangement light-emitting element groups and a plurality of second arrangement light-emitting element groups, wherein the arrangement order of the first light-emitting element and the second light-emitting element in the first arrangement light-emitting element group along the second direction is opposite to the arrangement order of the first light-emitting element and the second light-emitting element in the second arrangement light-emitting element group along the second direction; The plurality of first-arranged light-emitting element groups and the plurality of second-arranged light-emitting element groups are arranged at intervals along the first direction and at intervals along the second direction; The set of second transition electrodes is located between the third light-emitting element of the first row of light-emitting elements and the third light-emitting element of the second row of light-emitting elements, which are adjacent to each other along the second direction.

12. The display substrate according to claim 11, wherein, The set of second transition electrodes includes six second transition electrodes arranged in an array along the first direction and the second direction.

13. The display substrate according to claim 7, wherein, The first power line is located on the side of the conductive layer containing the plurality of first transition electrodes that is away from the substrate, and on the side of the conductive layer containing the plurality of second transition electrodes that is close to the substrate.

14. The display substrate according to claim 13, wherein, The first power line connected to the first electrode of at least one of the plurality of light-emitting elements overlaps with the pixel circuit connected to the second electrode of the at least one light-emitting element in the orthogonal projection of the substrate.

15. The display substrate according to claim 13, further comprising: Multiple third-level transfer electrodes; The first adapter electrode is connected to the second adapter electrode through the third adapter electrode, and the third adapter electrode and the first power line are in the same layer.

16. The display substrate according to claim 15, wherein, In a direction perpendicular to the display substrate, the display substrate includes: a first conductive layer, a semiconductor layer, a second conductive layer, a third conductive layer, a fourth conductive layer, and a fifth conductive layer sequentially disposed on the substrate; The plurality of first transition electrodes are located in the fourth conductive layer, and the plurality of third transition electrodes and the first power line are located in the fifth conductive layer.

17. The display substrate according to claim 1, wherein, At least one pixel circuit in the plurality of pixel circuits includes: a driving transistor, a compensation transistor, a first capacitor, and a second capacitor; the first electrode of the first capacitor is connected to the gate of the driving transistor, the second electrode of the first capacitor is connected to the second electrode of the compensation transistor, the first electrode of the compensation transistor is connected to the first electrode of the driving transistor and the first electrode of the second capacitor, and the second electrode of the second capacitor is connected to a second power supply line. The second electrode of the first capacitor includes: a first sub-electrode and a second sub-electrode connected to each other, wherein the first sub-electrode of the first capacitor is located on the side of the second sub-electrode closer to the substrate, and the second electrode of the first capacitor is located on the side of the first sub-electrode away from the substrate and on the side of the second sub-electrode closer to the substrate; The first electrode of the second capacitor is located on the side of the second electrode of the second capacitor that is close to the substrate, and the first electrode of the second capacitor and the second sub-electrode of the first capacitor are in the same layer.

18. The display substrate according to claim 17, wherein, The active layer of the driving transistor has an L-shaped orthographic projection onto the substrate.

19. A display device comprising a display substrate as claimed in any one of claims 1 to 18.

20. A display substrate, comprising: The substrate includes a display area and a peripheral area surrounding the display area; Multiple pixel circuits and multiple light-emitting elements are disposed on the substrate and located in the display area; At least one of the plurality of light-emitting elements includes: a first electrode, a light-emitting functional layer, and a second electrode arranged sequentially along a direction away from the substrate; the first electrode is connected to a first power line, and the second electrode is connected to at least one pixel circuit among the plurality of pixel circuits. The at least one pixel circuit includes: a driving transistor, a compensation transistor, a first capacitor, and a second capacitor; the first electrode of the first capacitor is connected to the gate of the driving transistor, the second electrode of the first capacitor is connected to the second electrode of the compensation transistor, the first electrode of the compensation transistor is connected to the first electrode of the driving transistor and the first electrode of the second capacitor, and the second electrode of the second capacitor is connected to a second power line. The second electrode of the first capacitor includes: a first sub-electrode and a second sub-electrode connected to each other, wherein the first sub-electrode of the first capacitor is located on the side of the second sub-electrode closer to the substrate, and the second electrode of the first capacitor is located on the side of the first sub-electrode away from the substrate and on the side of the second sub-electrode closer to the substrate; The first electrode of the second capacitor is located on the side of the second electrode of the second capacitor that is close to the substrate, and the first electrode of the second capacitor and the second sub-electrode of the first capacitor are in the same layer.

21. The display substrate according to claim 20, wherein, The active layer of the driving transistor has an L-shaped orthographic projection onto the substrate.

22. The display substrate according to claim 20, wherein, The at least one pixel circuit further includes: a data writing transistor, the gate of which is connected to a first scan line, the first electrode of which is connected to a data line, and the second electrode of which is connected to the second electrode of the compensation transistor and the second electrode of the first capacitor; The active layer of the compensation transistor and the active layer of the data writing transistor are an integral structure and are located on the same side of the first capacitor and the driving transistor along the second direction.

23. The display substrate according to claim 20, wherein, The at least one pixel circuit further includes: a first reset transistor, a second reset transistor, and a third reset transistor; The gate of the first reset transistor is connected to the first reset control line, the first terminal of the first reset transistor is connected to the first initial signal line, and the second terminal of the first reset transistor is connected to the second terminal of the driving transistor. The gate of the second reset transistor is connected to the second reset control line, the first terminal of the second reset transistor is connected to the second initial signal line, and the second terminal of the second reset transistor is connected to the first terminal of the driving transistor. The gate of the third reset transistor is connected to the third reset control line, the first terminal of the third reset transistor is connected to the reference signal line, and the second terminal of the third reset transistor is connected to the gate of the driving transistor. The first reset transistor and the third reset transistor are located on the same side of the driving transistor along the second direction, and the second reset transistor is located on the other side of the driving transistor along the second direction; The first reset control line, the second reset control line, and the third reset control line are in the same layer, as are the first initial signal line, the second initial signal line, and the reference signal line.

24. The display substrate according to claim 23, wherein, The at least one pixel circuit further includes: a fourth reset transistor; the gate of the fourth reset transistor is connected to a fourth reset control line, the first electrode of the fourth reset transistor is connected to a third initial signal line, and the second electrode of the fourth reset transistor is connected to the second electrode of the light-emitting element; Multiple pixel circuits arranged along the first direction form a row of pixel circuits. The gate of the second reset transistor of the row of pixel circuits and the gate of the fourth reset transistor of the other row of pixel circuits are integrated into one structure.

25. The display substrate according to claim 23, wherein, The at least one pixel circuit further includes: a first light-emitting control transistor and a second light-emitting control transistor; The gate of the first light-emitting control transistor is connected to the light-emitting control line, the first electrode of the first light-emitting control transistor is connected to the second electrode of the driving transistor, and the second electrode of the first light-emitting control transistor is connected to the second electrode of the light-emitting element. The gate of the second light-emitting control transistor is connected to the light-emitting control line, the first terminal of the second light-emitting control transistor is connected to the second power supply line, and the second terminal of the second light-emitting control transistor is connected to the first terminal of the driving transistor. The first light-emitting control transistor and the second light-emitting control transistor of the at least one pixel circuit are aligned and arranged along a first direction; the active layer of the first light-emitting control transistor and the active layer of the first reset control transistor are integral structures.

26. The display substrate according to claim 20, wherein, In a direction perpendicular to the display substrate, the display substrate includes: a first conductive layer, a semiconductor layer, a second conductive layer, a third conductive layer, a fourth conductive layer, and a fifth conductive layer sequentially disposed on the substrate; Wherein, the first conductive layer includes: the bottom gate of at least one transistor of the at least one pixel circuit; The semiconductor layer includes: an active layer of at least one transistor of the at least one pixel circuit; The second conductive layer includes: the gate of at least one transistor of the at least one pixel circuit; The second power line is located in the fifth conductive layer; The first sub-electrode of the first capacitor is located in the first conductive layer, the second sub-electrode of the first capacitor is located in the third conductive layer, and the first electrode of the first capacitor is located in the second conductive layer. The first electrode of the second capacitor is located in the third conductive layer, and the second electrode of the second capacitor is located in the fifth conductive layer.

27. The display substrate according to claim 26, wherein, The semiconductor layer is made of oxide semiconductor material.

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