Display panel, display screen, and display device

Abstract

The present application relates to the technical field of display, and relates to a display panel, a display screen, and a display device. The display panel comprises a plurality of pixel circuit columns, a plurality of first data lines, and a plurality of second data lines. Each pixel circuit column is provided with one first data line and one second data line. Each pixel circuit column comprises a plurality of first pixel circuits and a plurality of second pixel circuits. In a same pixel circuit column, each first pixel circuit is connected to the first data line, each second pixel circuit is connected to the second data line, layout structures of each first pixel circuit and the corresponding second pixel circuit are mirror-image structures of each other along the pixel circuit column direction, a first connection point between each first pixel circuit and the first data line is located at the edge of the first pixel circuit close to the first data line, and a second connection point between each second pixel circuit and the second data line is located at the edge of the second pixel circuit close to the second data line. By using the present application, the crosstalk between a data line and other signal lines can be reduced, thereby improving the display performance.

Description

Display panel, display screen and display device

[0001] Cross-reference to related applications

[0002] This application claims priority to Chinese Patent Application No. 202411804265.7, filed on December 09, 2024, entitled “Display Panel, Display Screen and Display Device”, the entire contents of which are incorporated herein by reference. Technical Field

[0003] This application relates to the field of display technology, and in particular to a display panel, display screen and display device. Background Technology

[0004] With the continuous development of display technology, the refresh rate of display panels is also constantly increasing. At high refresh rates, the line scanning time of the pixel circuit in the display panel is shortened, and the threshold compensation time of the pixel circuit is also shortened accordingly.

[0005] In existing designs, a dual-data-line driving method can be used to increase the threshold compensation time of pixel circuits. That is, the pixel circuits of adjacent rows in the same pixel column are connected to different data lines. However, with this setup, there is a problem of crosstalk between the data lines and other signal lines in the display panel. Summary of the Invention

[0006] This application provides a display panel, a display screen, and a display device that can reduce crosstalk between data lines and other signal lines within the display panel, thereby improving display performance.

[0007] In a first aspect, embodiments of this application provide a display panel, including multiple pixel circuit columns, multiple first data lines, and multiple second data lines, wherein each pixel circuit column is provided with one first data line and one second data line; wherein...

[0008] The pixel circuit column includes multiple first pixel circuits and multiple second pixel circuits. In the same pixel circuit column, each first pixel circuit is connected to the first data line, and each second pixel circuit is connected to the second data line. The layout structures of the first pixel circuits and the second pixel circuits are mirror images of each other along the direction of the pixel circuit column.

[0009] The first connection point between the first pixel circuit and the first data line is located at the edge of the first pixel circuit near the first data line, and the second connection point between the second pixel circuit and the second data line is located at the edge of the second pixel circuit near the second data line.

[0010] Secondly, embodiments of this application provide a display screen, including a cover plate and a display panel as described above, wherein the cover plate is located on the surface of the display panel in the light-emitting direction.

[0011] Thirdly, embodiments of this application provide a display device, which includes the display panel as described above.

[0012] The display panel, display screen, and display device provided in this application embodiment each have a first data line and a second data line in each pixel circuit column. In each pixel circuit column, each first pixel circuit is connected to the first data line, and each second pixel circuit is connected to the second data line. The layout structure of the first pixel circuit and the layout structure of the second pixel circuit are mirror images of each other along the direction of the pixel circuit column. In this case, the first connection point between the first pixel circuit and the first data line can be located at the edge of the first pixel circuit near the first data line, and the second connection point between the second pixel circuit and the second data line can be located at the edge of the second pixel circuit near the second data line. Thus, when the first data line and the second data line drive the same pixel circuit column, that is, when the dual data line (including the first data line and the second data line) driving method is used, the data line does not need to cross the pixel circuit area to connect with the pixel circuit. That is, there is no need for the data line and the pixel circuit to cross the line, which shortens the connection length between the data line and the pixel circuit, saves space, and is conducive to realizing a display panel with narrow bezels and high pixel density. It also reduces the coupling capacitance between the data line and other signal lines in the display panel, thereby improving the problem of crosstalk between the data line and other signal lines and improving the display effect of the display panel. In addition, in the same pixel circuit column, the layout structure of the first pixel circuit and the second pixel circuit is designed as a mirror structure, which avoids data lines crossing in the pixel circuit area, reduces the total capacitance of the data lines, improves the pixel charging rate, and allows the impedance of the fan-out traces of the display panel to be further increased and the line width to be further compressed, which is beneficial to the narrow bezel design of the display panel. Attached Figure Description

[0013] Figure 1 is a top view of a display panel provided in an embodiment of this application;

[0014] Figure 2 is a top view of a display panel structure;

[0015] Figure 3 is a top view of another display panel provided in an embodiment of this application;

[0016] Figure 4 is a schematic diagram of the layout structure of a display panel provided in an embodiment of this application;

[0017] Figure 5 is a schematic diagram of the layout structure of another display panel provided in an embodiment of this application;

[0018] Figure 6 is a top view of another display panel provided in an embodiment of this application;

[0019] Figure 7 is a top view of another display panel provided in an embodiment of this application;

[0020] Figure 8 is a timing diagram of a control signal provided in an embodiment of this application;

[0021] Figure 9 is a schematic diagram of the layout structure of another display panel provided in an embodiment of this application;

[0022] Figure 10 is a schematic diagram of the layout structure of another display panel provided in an embodiment of this application;

[0023] Figure 11 is a schematic diagram of the internal structure of a pixel circuit provided in an embodiment of this application;

[0024] Figure 12 is a schematic cross-sectional view of a display panel provided in an embodiment of this application;

[0025] Figure 13 is a schematic diagram of the layout structure of a semiconductor layer provided in an embodiment of this application;

[0026] Figure 14 is a schematic diagram of the layout structure of a first conductive layer provided in an embodiment of this application;

[0027] Figure 15 is a schematic diagram of the layout structure of a capacitor conductive layer provided in an embodiment of this application;

[0028] Figure 16 is a schematic diagram of the layout structure of a second conductive layer provided in an embodiment of this application;

[0029] Figure 17 is a schematic diagram of the layout structure of a third conductive layer provided in an embodiment of this application;

[0030] Figure 18 is a schematic diagram of the layout structure of another display panel provided in an embodiment of this application;

[0031] Figure 19 is a schematic diagram of another layout structure of the third conductive layer provided in an embodiment of this application;

[0032] Figure 20 is a schematic cross-sectional view of a display screen provided in an embodiment of this application;

[0033] Figure 21 is a top view of another display device provided in an embodiment of this application. Detailed Implementation

[0034] To facilitate understanding of this application, a more complete description will be provided below with reference to the accompanying drawings. Preferred embodiments of this application are shown in the drawings. However, this application can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided to provide a thorough and complete understanding of the disclosure of this application.

[0035] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein in the specification of this application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. The term "and / or" as used herein includes any and all combinations of one or more of the associated listed items.

[0036] When describing positional relationships, unless otherwise specified, when an element, such as a layer, film, or substrate, is referred to as being "on" another element, it may be directly on the other element or there may be intermediate elements present. Furthermore, when a layer is referred to as being "below" another layer, it may be directly below it or there may be one or more intermediate elements present. It is also understood that when a layer is referred to as being "between" two layers, it may be the only layer between the two layers, or there may be one or more intermediate elements present.

[0037] When using the terms “including,” “having,” and “comprising” as described herein, another component may be added unless explicitly qualifying terms such as “only,” “consisting of,” etc. are used. Unless otherwise stated, singular terms may include plural forms and should not be construed as having a quantity of one.

[0038] It should be understood that although the terms "first," "second," etc., may be used herein to describe various elements, these elements should not be limited by these terms. These terms are used only to distinguish one element from another. For example, without departing from the scope of this application, a first data line may be referred to as a second data line, and similarly, a second data line may be referred to as a first data line.

[0039] It should also be understood that, in interpreting an element, although not explicitly described, the element is interpreted as including a range of error, which should be within the acceptable deviation range of a particular value as determined by a person skilled in the art. For example, "approximately," "about," or "substantially" can mean within one or more standard deviations, without limitation herein.

[0040] Furthermore, in the instruction manual, the phrase "planar distribution diagram" refers to the diagram when the target part is viewed from above, and the phrase "cross-sectional diagram" refers to the diagram when the target part is viewed from the side as a cross-section taken by vertically cutting the target part.

[0041] Furthermore, the accompanying drawings are not drawn to a 1:1 scale, and the relative dimensions of the components are shown in the drawings only as examples and not necessarily to actual scale.

[0042] Figure 1 is a top view of a display panel according to an embodiment of this application. Referring to Figure 1, in one embodiment, the display panel includes an array of pixel circuits. Each pixel circuit column 10 is connected to two data lines 20. Each pixel circuit column 10 writes data signals through the two connected data lines 20, i.e., using a double data line (DDL) driving method. This reduces the transient effect caused by the switching of pixel circuits on the same data line 20, improving circuit stability. Simultaneously, it reduces the signal delay of the data lines 20, improves the charging efficiency of the pixel circuits, and helps achieve high-frequency display.

[0043] As described in the background section, display panels in related technologies employ a dual-data-line driving method, which leads to crosstalk between the data lines and other signal lines within the display panel. The inventors discovered that this problem arises because the layout structure of each pixel circuit in the display panel is specifically designed such that the connection points between each pixel circuit in the same pixel circuit column and the two data lines are all located on the same side of the pixel circuit. Therefore, for the two data lines located on opposite sides of the pixel circuit column, at least one data line needs to cross the pixel circuit area to connect to the pixel circuit; that is, a cross-line connection is required between the data line and the pixel circuit. Consequently, data lines with cross-line connections are easily coupled by other signal lines in the display panel, leading to crosstalk between the data lines and other signal lines, thus affecting the display performance of the display panel. For example, Figure 2 provides a top view of a display panel structure. As shown in Figure 2, due to the layout of the pixel circuit P, in each pixel circuit column P, the connection points CON between each pixel circuit P and the two data lines DL are all located on the left side of the pixel circuit P. Therefore, the data line DL located on the right side of the pixel circuit P column needs to be connected across the pixel circuit P in the row direction of the pixel circuit P. As a result, the data line DL located on the right side of the pixel circuit P column is prone to crosstalk with the signal lines extending along the row direction of the pixel circuit P in the display panel, thereby affecting the display performance of the display panel.

[0044] Based on the aforementioned technical problems, the inventors discovered that by designing the pixel circuit layout structure connecting different data lines in the same pixel circuit column as a mirror structure along the direction of the pixel circuit column, the connection point between the data line and the pixel circuit is located at the edge of the pixel circuit near the data line. This avoids cross-line connections between the data line and the pixel circuit, thereby reducing crosstalk between the data line and other signal lines in the display panel, and thus improving the display performance of the display panel. Based on this, the inventors further developed the technical solution of the embodiments of this application. Specifically, the display panel provided in this application embodiment includes multiple pixel circuit columns, multiple first data lines, and multiple second data lines. Each pixel circuit column has one first data line and one second data line. Each pixel circuit column includes multiple first pixel circuits and multiple second pixel circuits. In the same pixel circuit column, each first pixel circuit is connected to a first data line, and each second pixel circuit is connected to a second data line. The layout structures of the first pixel circuits and the second pixel circuits are mirror images of each other along the direction of the pixel circuit column. The first connection point between the first pixel circuit and the first data line is located at the edge of the first pixel circuit near the first data line, and the second connection point between the second pixel circuit and the second data line is located at the edge of the second pixel circuit near the second data line.

[0045] Because the layout structures of the first pixel circuit and the second pixel circuit in the same pixel circuit column are mirror images of each other along the column direction, the first connection point between the first pixel circuit and the first data line is located at the edge of the first pixel circuit near the first data line, and the second connection point between the second pixel circuit and the second data line is located at the edge of the second pixel circuit near the second data line. In other words, the connection points between each pixel circuit and the data line are close to their respective data lines. Therefore, there is no need for cross-line connections between the data lines and the pixel circuits. This reduces the coupling effect between the data lines and other signals, avoids crosstalk problems caused by cross-line connections, and ultimately improves the display performance of the display panel.

[0046] The above is the core idea of ​​this application. The technical solutions in the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of this application.

[0047] Figure 3 is a top view of a display panel according to an embodiment of this application; Figure 4 is a layout diagram of a display panel according to an embodiment of this application; and Figure 5 is a layout diagram of a display panel according to an embodiment of this application. Referring to Figures 3 to 5, in one embodiment, a display panel is provided, which includes multiple pixel circuit columns, multiple first data lines 21, and multiple second data lines 22.

[0048] The pixel circuit column has a first data line 21 and a second data line 22. The first data line 21 and the second data line 22 are used to provide data signals VData. The first data line 21 and the second data line 22 extend along the pixel circuit column direction Y and are arranged along the pixel circuit row direction X. Y and X intersect, for example, Y is perpendicular to X. Exemplarily, in the same pixel circuit column, the first data line 21 and the second data line 22 are located on opposite sides of the pixel circuit column. For example, as shown in Figures 3 to 5, in the same pixel circuit column, the first data line 21 is located on the left side of the pixel circuit column, and the second data line 22 is located on the right side. It should be noted that the above is only an illustrative example; the relative positions of the first data line 21 and the second data line 22 with respect to the pixel circuit column can also be other layout methods. For example, the first data line 21 may be located on the right side of the pixel circuit column, and the second data line 22 may be located on the left side. A suitable layout method can be selected according to the actual application scenario, and is not limited here.

[0049] The pixel circuit array includes multiple first pixel circuits 110 and multiple second pixel circuits 120. Within the same pixel circuit array, each first pixel circuit 110 is connected to a first data line 21, and each second pixel circuit 120 is connected to a second data line 22. That is, within the same pixel circuit, the pixel circuit connected to the first data line 21 is the first pixel circuit 110, and the pixel circuit connected to the second data line 22 is the second pixel circuit 120.

[0050] For example, in the same pixel circuit column, the first pixel circuit 110 and the second pixel circuit 120 are alternately arranged, that is, the first pixel circuit 110 and the second pixel circuit 120 are arranged alternately along the direction of the pixel circuit column. For example, in the same pixel circuit column, the pixel circuit located in the odd-numbered rows is the first pixel circuit 110 and is connected to the first data line 21, and the pixel circuit located in the even-numbered rows is the second pixel circuit 120 and is connected to the second data line 22; alternatively, the pixel circuit located in the odd-numbered rows is the second pixel circuit 120 and is connected to the second data line 22, and the pixel circuit located in the even-numbered rows is the first pixel circuit 110 and is connected to the first data line 21. It should be noted that, in the application, the first pixel circuit 110 and the second pixel circuit 120 in the same pixel circuit column may not be arranged alternately. For example, multiple first pixel circuits 110 are arranged adjacently and continuously, and multiple second pixel circuits 120 are arranged adjacently and continuously. Furthermore, the multiple consecutively arranged first pixel circuits 110 and the multiple consecutively arranged second pixel circuits 120 are arranged alternately along the direction of the pixel circuit column. The above are all exemplary descriptions. In the application, the appropriate layout method of the arrangement of the first pixel circuit 110 and the second pixel circuit 120 can be selected according to actual needs, and no limitation is made here.

[0051] The positions of the first pixel circuit 110 and the second pixel circuit 120 in different pixel circuit columns can be the same or different. For example, in each pixel circuit column, the pixel circuit located in the odd-numbered rows is the first pixel circuit 110 and connected to the first data line 21, and the pixel circuit located in the even-numbered rows is the second pixel circuit 120 and connected to the second data line 22. As another example, in two adjacent pixel circuit columns, in one column, the pixel circuit located in the odd-numbered rows is the first pixel circuit 110 and connected to the first data line 21, and the pixel circuit located in the even-numbered rows is the second pixel circuit 120 and connected to the second data line 22; in the other column, the pixel circuit located in the odd-numbered rows is the second pixel circuit 120 and connected to the second data line 22, and the pixel circuit located in the even-numbered rows is the first pixel circuit 110 and connected to the first data line 21. It should be noted that the above is only an illustrative example. The arrangement of pixel circuits in the pixel circuit column can also be a combination of the above methods. In application, the arrangement of pixel circuits in each pixel circuit column of the display panel can be selected according to the actual scenario, and no further restrictions are imposed here.

[0052] The layout structure of the first pixel circuit 110 and the layout structure of the second pixel circuit 120 are mirror images of each other along the pixel circuit column direction. That is, within the same pixel circuit row, the layout structures of the first pixel circuit 110 and the second pixel circuit 120 are symmetrically arranged along the pixel circuit column direction. Furthermore, within the same pixel circuit column, the layout structures of the first pixel circuit 110 and the second pixel circuit 120 are symmetrical along the pixel circuit column direction.

[0053] The connection point between the first pixel circuit 110 and the first data line 21 is designated as the first connection point 31, and the first connection point 31 is located on the edge of the first pixel circuit 110 near the first data line 21. The connection point between the second pixel circuit 120 and the second data line 22 is designated as the second connection point 32, and the second connection point 32 is located on the edge of the second pixel circuit 120 near the second data line 22. For example, as shown in Figures 3 to 5, the first connection point 31 is located on the left edge of the first pixel circuit 110 near the first data line 21, and the second connection point 32 is located on the right edge of the second pixel circuit 120 near the second data line 22. It should be noted that the above is only an illustrative example. In application, the specific positions of the first connection point 31 and the second connection point 32 can be determined based on factors such as the relative positional relationship between the first data line 21 and the second data line 22 and the pixel circuit column, and the arrangement of the pixel circuit column. No further limitations are imposed here.

[0054] The first connection point 31 is located at the edge of the first pixel circuit 110 near the first data line 21, and the second connection point 32 is located at the edge of the second pixel circuit 120 near the second data line 22. Therefore, there is no need for a cross-line connection between the first data line 21 and the first pixel circuit 110, and there is no need for a cross-line connection between the second data line 22 and the second pixel circuit 120. In other words, there is no need for a cross-line connection between the data line 20 and the corresponding pixel circuit. That is, the connection point of the data line 20 is located at the edge of the pixel circuit near the corresponding connected data line 20.

[0055] For example, the first connection point 31 and the second connection point 32 are mirror images of each other along the pixel circuit column direction. That is, the first connection point 31 and the second connection point 32 are symmetrical. Specifically, within the same pixel circuit column, the first connection point 31 and the second connection point 32 are symmetrical along the pixel circuit column direction. Furthermore, within the same pixel circuit row, the first connection point 31 and the second connection point 32 are symmetrically arranged along the pixel circuit column direction.

[0056] In the aforementioned display panel, each pixel circuit column is provided with a first data line 21 and a second data line 22. In each pixel circuit column, each first pixel circuit 110 is connected to the first data line 21, and each second pixel circuit 120 is connected to the second data line 22. The layout structure of the first pixel circuit 110 and the layout structure of the second pixel circuit 120 are mirror images of each other along the direction of the pixel circuit column. In this case, the first connection point 31 between the first pixel circuit 110 and the first data line 21 can be located at the edge of the first pixel circuit 110 near the first data line 21, and the second connection point 32 between the second pixel circuit 120 and the second data line 22 can be located at the edge of the first pixel circuit 110 near the first data line 21. The second pixel circuit 120 is located near the edge of the second data line 22. Therefore, when the first data line 21 and the second data line 22 drive the same pixel circuit array (i.e., using dual data lines 20 (including the first data line 21 and the second data line 22)), the data lines 20 do not need to cross the pixel circuit area to connect with the pixel circuit. This saves space, which is beneficial for high-pixel-density display panels. It also reduces coupling between the data lines 20 and other signal lines within the display panel, thus improving crosstalk between the data lines 20 and other signal lines and enhancing the display panel's performance. Furthermore, in the same pixel circuit array, the layout structure of the first pixel circuit 110 and the second pixel circuit 120 is designed as a mirror image, avoiding data lines 20 crossing the pixel circuit area. This reduces the total capacitance of the data lines 20, increases the pixel charging rate, and allows for further increases in the impedance of the fan-out traces on the display panel, while further compressing the line width, which is beneficial for narrow bezel designs.

[0057] Figure 6 is a top view of a display panel according to an embodiment of this application. Referring to Figure 6, in one embodiment, the display panel further includes a gating circuit 40. Exemplarily, the gating circuit 40 includes a multiplexer (Demux).

[0058] At least one pixel circuit column connects a first data line 21 and a second data line 22 to a data signal terminal Data_in via a gating circuit 40. The input terminal of the gating circuit 40 is connected to the data signal terminal Data_in, and multiple output terminals of the gating circuit 40 are respectively connected to the first data line 21 and the second data line 22 connected to at least one pixel circuit column.

[0059] Each gating circuit 40 is connected to at least one pixel circuit column, meaning each gating circuit 40 can connect to one or more pixel circuit columns. The pixel circuit columns connected to each gating circuit 40 are different, and the data signal terminals (Data_in) connected to each gating circuit 40 are also different. For example, if each gating circuit 40 is connected to one pixel circuit column, the first data line 21 and the second data line 22 of one pixel circuit column are connected to the data signal terminal (Data_in) via the gating circuit 40. The ratio of the number of data signal terminals (Data_in) connected to the gating circuit 40 to the number of data lines 20 is 1:2, which can be denoted as DDL+Demux1:2. As another example, if each gating circuit 40 is connected to two adjacent pixel circuit columns, the first data line 21 and the second data line 22 of the two pixel circuit columns are each connected to the data signal terminal (Data_in) via the gating circuit 40. The ratio of the number of data signal terminals (Data_in) connected to the gating circuit 40 to the number of data lines 20 is 1:4, which can be denoted as DDL+Demux1:4. In applications, the connection method between the gating circuit 40 and the first data line 21 and the second data line 22 connected to the pixel circuit column can be selected according to the actual scenario. The ratio of the number of data signal terminals Data_in connected to the gating circuit 40 to the number of data lines 20 is 1:n, where n is an even number greater than or equal to 2, i.e., DDL+Demux1:n, which is not limited here.

[0060] The data signal terminal Data_in is used to provide the data signal VData. The gating circuit 40 is used to time-division multiplex the data signal VData provided by the data signal terminal Data_in to the first data line 21 and the second data line 22 connected to the gating circuit 40. That is, the gating circuit 40 is used to time-division multiplex the paths between the data signal terminal Data_in and the first data line 21 and the second data line 22, respectively, so as to time-division multiplex the transmission of the data signal VData to the first data line 21 and the second data line 22.

[0061] It should be noted that the number of gating circuits 40 and the number of first data lines 21 and second data lines 22 connected to the gating circuits 40 can be determined according to the actual application scenario. For example, if the display panel includes N pixel circuit columns, and each gating circuit 40 is connected to the first data line 21 and second data line 22 of one pixel circuit column, i.e., n=2, then the number of gating circuits 40 is N. In application, other methods can also be used, such as when n=4, the number of gating circuits 40 is N / 2, etc., which will not be further limited here.

[0062] In the aforementioned display panel, at least one pixel circuit column is connected to the first data line 21 and the second data line 22 via a gating circuit 40, which is then connected to the data signal terminal Data_in. The gating circuit 40 transmits the data signal VData provided by the data signal terminal Data_in to the first data line 21 and the second data line 22 connected to the gating circuit 40 in a time-division manner. This allows multiple data lines 20 to share the same data signal terminal Data_in via the gating circuit 40, reducing the number of data signal terminals Data_in and contributing to the realization of a display panel with narrow bezels and high pixel density. Furthermore, it can reduce the transient effects caused by the switching of each row of pixel circuits on the same data line 20, thereby improving circuit stability. In addition, it can reduce the signal delay of the data line 20, thereby improving the charging efficiency of the pixel circuit and contributing to the realization of high-frequency display.

[0063] Figure 7 is a top view of a display panel according to an embodiment of this application. Referring to Figure 7, in one embodiment, the plurality of pixel circuit columns include a plurality of first pixel circuit columns 11 and a plurality of second pixel circuit columns 12. The first pixel circuit columns 11 and the second pixel circuit columns 12 are alternately arranged along the pixel circuit row direction; that is, the first pixel circuit columns 11 and the second pixel circuit columns 12 are arranged in turn along the pixel circuit row direction.

[0064] Four data lines 20 connected to the first pixel circuit column 11 and the second pixel circuit column 12 are connected to the data signal terminal Data_in via a gating circuit 40. The four data lines 20 refer to the first data line 21 and the second data line 22 connected to the first pixel circuit column 11, and the first data line 21 and the second data line 22 connected to the second pixel circuit column 12. The input terminal of the gating circuit 40 is connected to the data signal terminal Data_in, and the four output terminals of the gating circuit 40 are respectively connected to the first data line 21 and the second data line 22 connected to the first pixel circuit column 11, and the first data line 21 and the second data line 22 connected to the second pixel circuit column 12. The four data lines 20 connected to each gating circuit 40 are different; that is, the first pixel circuit column 11 and the second pixel circuit column 12 connected to each gating circuit 40 are different. For example, the first pixel circuit column 11 and the second pixel circuit column 12 connected to the same gating circuit 40 are adjacent in the pixel circuit row direction.

[0065] The gating circuit 40 is used to time-division multiplex the data signal VData provided by the data signal terminal Data_in to the four data lines 20 connected to the gating circuit 40. That is, the gating circuit 40 is used to time-division multiplex the paths between the first data line 21 and the second data line 22 of the first pixel circuit column 11 and the first data line 21 and the second data line 22 of the second pixel circuit column 12 and the data signal terminal Data_in, so as to time-division multiplex the data signal VData to the first data line 21 and the second data line 22 of the first pixel circuit column 11 and the first data line 21 and the second data line 22 of the second pixel circuit column 12.

[0066] In the aforementioned display panel, four data lines 20 connected to the first pixel circuit column 11 and the second pixel circuit column 12 are connected to the data signal terminal Data_in via a gating circuit 40. The gating circuit 40 transmits the data signal VData provided by the data signal terminal Data_in to the four data lines 20 connected to the gating circuit 40 in a time-division manner, realizing that the four data lines 20 share a single data signal terminal Data_in. Compared with the method of not reusing the data signal terminal Data_in and two data lines 20 sharing a single data signal terminal Data_in, the number of data signal terminals Data_in is significantly reduced, which helps to further realize a display panel with narrow bezels and high pixel density; furthermore, it can further reduce the jumping effect caused by the switching of each row of pixel circuits on the same data line 20, thereby further improving circuit stability; in addition, it can further reduce the signal delay of the data line 20, thereby further improving the charging efficiency of the pixel circuit and helping to realize high-frequency display.

[0067] Figure 8 is a timing diagram of a display panel provided in an embodiment of this application, and Figure 9 is a layout structure diagram of a display panel provided in an embodiment of this application. Referring to Figures 7 to 9, in one embodiment, the multiple first data lines 21 include multiple first A data lines 211 and multiple first B data lines 212. The multiple second data lines 22 include multiple second A data lines 221 and multiple second B data lines 222. The first A data lines 211 and second A data lines 221 are respectively connected to the same first pixel circuit column 11, and the first B data lines 212 and second B data lines 222 are respectively connected to the same second pixel circuit column 12. The selection circuit 40 includes a first switching unit 410, a second switching unit 420, a third switching unit 430, and a fourth switching unit 440.

[0068] For example, the number of first data lines 21 and second data lines 22 is the same, wherein the number of first A data lines 211 and first B data lines 212 is the same, and the number of second A data lines 221 and second B data lines 222 is the same. For instance, taking a display panel comprising N pixel circuit columns as an example, the display panel includes N / 4 gating circuits 40, N first data lines 21, and N second data lines 22. The N / 4 gating circuits 40 include N switching units, the N first data lines 21 include N / 2 first A data lines 211 and N / 2 first B data lines 212, and the N second data lines 22 include N / 2 second A data lines 221 and N / 2 second B data lines 222. The switching units are a collective term for the first switching unit 410, the second switching unit 420, the third switching unit 430, and the fourth switching unit 440.

[0069] For example, the first data line 211 and the second data line 222 are symmetrically arranged, and the second data line 221 and the first data line 212 are symmetrically arranged. That is, among the four data lines 20 connected by the same gating circuit 40, the first data line 211 and the first data line 212 are symmetrically arranged along the second central axis, and the second data line 221 and the first data line 212 are symmetrically arranged along the second central axis, wherein the second central axis is the central axis between the first pixel circuit column 11 and the second pixel circuit column 12 connected by the four data lines 20.

[0070] For example, the first data line 211, the second data line 221, the first data line 212, and the second data line 222 are alternately arranged along the pixel circuit row direction. For example, the first data line 211 and the second data line 221 are respectively located on both sides of the first pixel circuit column 11, and the first data line 212 and the second data line 222 are respectively located on both sides of the second pixel circuit column 12, and the second data line 221 and the first data line 212 are adjacent to each other.

[0071] It should be noted that the first A data line 211, the second A data line 221, the first B data line 212, and the second B data line 222 can also be arranged in other ways along the pixel circuit row direction. For example, the second A data line 221, the first A data line 211, the second B data line 222, and the first B data line 212 can be arranged alternately along the pixel circuit row direction; another example is that the first A data line 211, the second A data line 221, the second B data line 222, and the first B data line 212 can be arranged along the pixel circuit row direction; yet another example is that the second A data line 221, the first A data line 211, the first B data line 212, and the second B data line 222 can be arranged alternately along the pixel circuit row direction. In application, a suitable arrangement method can be selected according to the actual scenario, and no further restrictions are imposed here.

[0072] For example, each gating circuit 40 is connected to two adjacent first pixel circuit columns 11 and second pixel circuit columns 12. For example, among the four data lines 20 connected to the same gating circuit 40, the first pixel circuit 110 in the first pixel circuit column 11 is connected to the first A data line 211, the second pixel circuit 120 in the first pixel circuit column 11 is connected to the second A data line 221, the first pixel circuit 110 in the second pixel circuit column 12 is connected to the first B data line 212, and the second pixel circuit 120 in the second pixel circuit column 12 is connected to the second B data line 222.

[0073] For example, in the same first pixel circuit column 11, the connection point between the first pixel circuit 110 and the first data line 211 is called the first A connection point, and the first A connection point is located at the edge of the first pixel circuit 110 near the first data line 211; the connection point between the second pixel circuit 120 and the second data line 221 is called the second A connection point, and the second A connection point is located near the edge of the second pixel circuit 120 near the second data line 221. For example, the first A connection point and the second A connection point are mirror images of each other along the direction of the pixel circuit column.

[0074] For example, in the same second pixel circuit column 12, the connection point between the first pixel circuit 110 and the first B data line 212 is the first B connection point, and the first B connection point is located at the edge of the first pixel circuit 110 near the first B data line 212; the connection point between the second pixel circuit 120 and the second B data line 222 is the second B connection point, and the second B connection point is located at the edge of the second pixel circuit 120 near the second B data line 222. For example, the first B connection point and the second B connection point are mirror images of each other along the pixel circuit column direction.

[0075] For example, as shown in Figures 7 and 9, among the four data lines 20 connected by the same gating circuit 40, the first A data line 211, the second A data line 221, the first B data line 212, and the second B data line 222 are alternately arranged along the pixel circuit row direction. The first A data line 211 is located on the left side of the first pixel circuit column 11, and the first A data line 211 is connected to each first pixel circuit 110 in the first pixel circuit column 11. The first A connection point is located on the left edge of the first pixel circuit 110 near the first A data line 211. The second A data line 221 is located on the right side of the first pixel circuit column 11, and the second A data line 221 is connected to each second pixel circuit 11 in the first pixel circuit column 11. Circuit 120 is connected, and the second A connection point is located on the right edge of the second pixel circuit 120 near the second A data line 221; the first B data line 212 is located on the left side of the second pixel circuit column 12, and the first B data line 212 is connected to each of the first pixel circuits 110 in the second pixel circuit column 12, and the first B connection point is located on the left edge of the first pixel circuit 110 near the first B data line 212; the second B data line 222 is located on the right side of the second pixel circuit column 12, and the second B data line 222 is connected to each of the second pixel circuits 120 in the second pixel circuit column 12, and the second B connection point is located on the right edge of the second pixel circuit 120 near the second B data line 222.

[0076] The first terminals of the first switch unit 410, the second switch unit 420, the third switch unit 430, and the fourth switch unit 440 are respectively connected to the data signal terminal Data_in. The control terminals of the first switch unit 410, the second switch unit 420, the third switch unit 430, and the fourth switch unit 440 are used to receive different control signals. The enable pulses of the control signals received by the control terminals of the first switch unit 410, the second switch unit 420, the third switch unit 430, and the fourth switch unit 440 do not overlap. That is, the time periods during which the first switch unit 410, the second switch unit 420, the third switch unit 430, and the fourth switch unit 440 are in the on state do not overlap.

[0077] The second terminal of the first switching unit 410 is connected to the first data line 211. The first switching unit 410 is used to select and connect the data signal terminal Data_in and the first data line 211 under the control of the control signal received at the control terminal of the first switching unit 410; the first switching unit 410 is used to turn on in response to the enable pulse of the control signal received at the control terminal of the first switching unit 410, so as to transmit the data signal VData provided by the data signal terminal Data_in to the first data line 211.

[0078] The second terminal of the second switching unit 420 is connected to the second data line 221. The second switching unit 420 is used to select and connect the data signal terminal Data_in and the second data line 221 under the control of the control signal received at the control terminal of the second switching unit 420; the second switching unit 420 is used to turn on in response to the enable pulse of the control signal received at the control terminal of the second switching unit 420, so as to transmit the data signal VData provided by the data signal terminal Data_in to the second data line 221.

[0079] The second terminal of the third switching unit 430 is connected to the first B data line 212. The third switching unit 430 is used to select and connect the data signal terminal Data_in and the first B data line 212 under the control of the control signal received at the control terminal of the third switching unit 430; the third switching unit 430 is used to conduct in response to the enable pulse of the control signal received at the control terminal of the third switching unit 430, so as to transmit the data signal VData provided by the data signal terminal Data_in to the first B data line 212.

[0080] The second terminal of the fourth switching unit 440 is connected to the second B data line 222. The fourth switching unit 440 is used to select and connect the data signal terminal Data_in and the second B data line 222 under the control of a control signal received at its control terminal; the fourth switching unit 440 is also used to conduct in response to an enable pulse of the control signal received at its control terminal, so as to transmit the data signal VData provided by the data signal terminal Data_in to the second B data line 222.

[0081] For example, the display panel further includes four control lines 50, which are respectively connected to the first switch unit 410, the second switch unit 420, the third switch unit 430, and the fourth switch unit 440. Each of the four control lines 50 is used to provide a different control signal. For example, the four control lines 50 include a first control line 51, a second control line 52, a third control line 53, and a fourth control line 54. Specifically, the first control line 51 is connected to the control terminal of the first switch unit 410 and is used to provide a first control signal MUX1; the second control line 52 is connected to the control terminal of the second switch unit 420 and is used to provide a second control signal MUX2; the third control line 53 is connected to the control terminal of the third switch unit 430 and is used to provide a third control signal MUX3; and the fourth control line 54 is connected to the control terminal of the fourth switch unit 440 and is used to provide a fourth control signal MUX4. The enable pulses of the first control signal MUX1, the second control signal MUX2, the third control signal MUX3, and the fourth control signal MUX4 do not overlap.

[0082] For example, the first switching unit 410 includes a first transistor, the first terminal of the first transistor is connected to the data signal terminal Data_in, the second terminal of the first transistor is connected to the first data line 211, and the gate of the first transistor is connected to the first control line 51. The first transistor is used to transmit the data signal VData provided by the data signal terminal Data_in to the first data line 211 in response to the enable pulse of the first control signal MUX1 provided by the first control line 51.

[0083] For example, the second switching unit 420 includes a second transistor, the second terminal of the second transistor is connected to the data signal terminal Data_in, the second terminal of the second transistor is connected to the second data line 221, and the gate of the second transistor is connected to the second control line 52. The second transistor is used to transmit the data signal VData provided by the data signal terminal Data_in to the second data line 221 in response to the enable pulse of the second control signal MUX2 provided by the second control line 52.

[0084] For example, the third switching unit 430 includes a third transistor, the third terminal of the third transistor is connected to the data signal terminal Data_in, the second terminal of the third transistor is connected to the first data line 212, and the gate of the third transistor is connected to the third control line 53. The third transistor is used to transmit the data signal VData provided by the data signal terminal Data_in to the first data line 212 in response to the enable pulse of the third control signal MUX3 provided by the third control line 53.

[0085] For example, the fourth switching unit 440 includes a fourth transistor, the fourth terminal of the fourth transistor is connected to the data signal terminal Data_in, the second terminal of the fourth transistor is connected to the second data line 222, and the gate of the fourth transistor is connected to the fourth control line 54. The fourth transistor is used to transmit the data signal VData provided by the data signal terminal Data_in to the second data line 222 in response to the enable pulse of the fourth control signal MUX4 provided by the fourth control line 54.

[0086] For example, the number of the first transistor, the second transistor, the third transistor, and the fourth transistor can be one or more, their conductivity type can be P-type transistor or N-type transistor, and their process type can be MOS (Metal-Oxide-Semiconductor) transistor or TFT (Thin Film Transistor). The specific number and type of each transistor can be selected according to the actual scenario, and no further restrictions are imposed here.

[0087] It should be noted that the above description takes the gating circuit 40 connected to four data lines 20 as an example. In application, the number of switching units in the gating circuit 40 can be set according to the number of data lines 20 connected to the gating circuit 40, and the switching unit can be one or more switching devices (such as transistors), without further limitation here.

[0088] The aforementioned display panel includes four switching units in each selection circuit 40: a first switching unit 410, a second switching unit 420, a third switching unit 430, and a fourth switching unit 440. These four switching units connect the data signal terminal Data_in to four data lines 20: the first A data line 211 and the second A data line 221 connected to the first pixel circuit column 11, and the first B data line 212 and the second B data line 222 connected to the second pixel circuit column 12. This allows the four data lines 20 to share a single data signal terminal Data_in, reducing the number of Data_in terminals and providing technical support for charging the pixel circuits using dual data lines 20. This improves the charging efficiency of the pixel circuits, enhancing the display performance of the display panel and facilitating high-frequency displays. Furthermore, the absence of cross-wire connections between the data lines 20 and the pixel circuits saves space, which is beneficial for high-pixel-density display panels. It also reduces crosstalk between the data lines 20 and other signal lines, improving the display effect of the panel. In addition, the total capacitance of the data line 20 has been reduced, which has improved the pixel charging rate. This allows the impedance of the fan-out traces to be further increased and the line width to be further compressed, which is beneficial for the narrow bezel design of the display panel.

[0089] Referring to Figure 7, in one embodiment, in the first pixel circuit column 11, the first pixel circuit 110 drives the first color pixel, and the second pixel circuit 120 drives the second color pixel. In the second pixel circuit column 12, the first pixel circuit 110 and the second pixel circuit 120 drive the third color pixel, respectively. The first color, the second color, and the third color are all different. Thus, by driving the pixels to emit different colors of light through the first pixel circuit 110, the second pixel circuit 120, and the third pixel circuit, the display panel can perform color display to meet display requirements.

[0090] Referring to Figure 7, in one embodiment, the first color pixel is a red pixel, the second color pixel is a blue pixel, and the third color pixel is a green pixel. In another embodiment, the first color pixel is a blue pixel, the second color pixel is a red pixel, and the third color pixel is a green pixel. That is, in the first pixel circuit array 11, one of the first pixel circuit 110 and the second pixel circuit 120 drives the red pixel, and the other drives the blue pixel. In the second pixel circuit array 12, the first pixel circuit 110 and the second pixel circuit 120 drive the green pixel. Thus, by driving the pixels to emit three colors of light (red, green, and blue) through the first pixel circuit 110, the second pixel circuit 120, and the third pixel circuit, the display panel can perform color display, satisfying the display requirements of multiple colors.

[0091] For example, in the four pixel circuit columns connected by two adjacent gating circuits 40 (e.g., the first gating circuit 41 and the second gating circuit 42), the first pixel circuit column 11 and the second pixel circuit column 12 are connected by the first gating circuit 41, and the first pixel circuit 110 and the second pixel circuit 120 are connected by the second gating circuit 42, arranged sequentially along the pixel circuit row direction; in the first pixel circuit column 11 connected by the first gating circuit 41, the pixel circuits in the odd-numbered rows are the first pixel circuits 110 and drive the red pixels, and are connected to the first A data line 211; the pixel circuits in the even-numbered rows are the second pixel circuits 120 and drive the blue pixels, and are connected to the second A data line 221; in the second pixel circuit column 12 connected by the first gating circuit 41, each pixel circuit drives the green pixels; the pixel circuits in the odd-numbered rows are the second pixel circuits 120 and are connected to the second B data line 222; the pixel circuits in the even-numbered rows are the first pixel circuits 110 and are connected to the first B data line 212; the second gating circuit 4... In the first pixel circuit column 11 connected by 2, the pixel circuits in the odd-numbered rows are the second pixel circuits 120, which drive the blue pixels and are connected to the second A data line 221. The pixel circuits in the even-numbered rows are the first pixel circuits 110, which drive the red pixels and are connected to the first A data line 211. In the second pixel circuit column 12 connected by the second gating circuit 42, each pixel circuit drives the green pixels. The pixel circuits in the odd-numbered rows are the first pixel circuits 110 and are connected to the first B data line 212. The pixel circuits in the even-numbered rows are the second pixel circuits 120 and are connected to the second B data line 222. In the same row, the pixel circuits in the first pixel circuit column 11 connected by the first gating circuit 41 and the pixel circuits in the second pixel circuit column 12 connected by the second gating circuit 42 have the same layout structure. In the same row, the pixel circuits in the second pixel circuit column 12 connected by the first gating circuit 41 and the pixel circuits in the first pixel circuit column 11 connected by the second gating circuit 42 have the same layout structure.

[0092] It should be noted that the above description only illustrates the RGB arrangement of multiple pixels on the display panel. In other embodiments, the multiple pixels may be arranged in other ways. Furthermore, the shape of the light-emitting area of ​​a pixel includes, but is not limited to, the rectangle shown in Figure 7. In other embodiments, the shape of the light-emitting area of ​​a pixel may be designed according to actual needs, and this embodiment of the invention does not impose specific limitations on it.

[0093] Figure 10 is a schematic diagram of the layout structure of a display panel provided in an embodiment of this application. Referring to Figures 7 to 10, in one embodiment, in the first pixel circuit column 11 and the second pixel circuit column 12 connected by the same gating circuit 40, the layout structures of two adjacent pixel circuits located in the same row are mirrored along the direction of the pixel circuit column. That is, the first pixel circuit column 11 and the second pixel circuit column 12 connected by the same gating circuit 40 are symmetrical along a second central axis. The second central axis is the central axis of the first pixel circuit column 11 and the second pixel circuit column 12. For example, as shown in Figure 10, in the leftmost first pixel circuit column 1111 and the adjacent second pixel circuit column 1212, the layout structures of two adjacent pixel circuits located in the same row are symmetrical along the direction of the pixel circuit column; in the rightmost second pixel circuit column 1212 and the adjacent first pixel circuit column 1111, the layout structures of two adjacent pixel circuits located in the same row are symmetrical along the direction of the pixel circuit column.

[0094] In the first pixel circuit column 11 and the second pixel circuit column 12 connected by the same gating circuit 40, the connection points between each pixel circuit and the data line 20 in the first pixel circuit column 11 and the connection points between each pixel circuit and the data line 20 in the second pixel circuit column 12 are mirror images, or symmetrical along the second central axis. Specifically, the first A connection point is symmetrical to the second B connection point, and the second A connection point is symmetrical to the first B connection point. Among them, the first A connection point is the connection point between the first pixel circuit 110 and the first A data line 211 in the first pixel circuit column 11, the second A connection point is the connection point between the second pixel circuit 120 and the second A data line 221 in the first pixel circuit column 11, the first B connection point is the connection point between the first pixel circuit 110 and the first B data line 212 in the second pixel circuit column 12, and the second B connection point is the connection point between the second pixel circuit 120 and the second B data line 222 in the second pixel circuit column 12.

[0095] In the aforementioned display panel, the layout structures of adjacent pixel circuits in the same row of the first pixel circuit column 11 and the second pixel circuit column 12, connected by the same gate circuit 40, are mirrored along the direction of the pixel circuit column. This allows the connection points between each pixel circuit and the data line 20 to be located at the edge of the pixel circuit near the data line 20, thereby preventing the data line 20 from crossing the pixel circuit area to connect with the pixel circuit. This avoids cross-line connections between the data line 20 and the pixel circuit, saving space and benefiting high pixel density display panels. It also improves the problem of crosstalk between the data line 20 and other signal lines, enhancing the display effect of the display panel. In addition, reducing the total capacitance of the data line 20 increases the pixel charging rate, allowing for a further increase in the impedance of the fan-out traces on the display panel and a further compression of the line width, which is beneficial for narrow bezel designs of the display panel.

[0096] For ease of description, in this application embodiment, the first pixel circuit 110 and the second pixel circuit 120 are collectively referred to as pixel circuits, and the first data line 21 and the second data line 22 are collectively referred to as data line 20. Figure 11 is a schematic diagram of the internal structure of a pixel circuit provided in an embodiment of this application. Referring to Figure 11, in one embodiment, the pixel circuit of the pixel circuit column includes a driving transistor T0, a storage capacitor Cst, a data writing transistor T1, and a threshold compensation transistor T2.

[0097] The driving transistor T0 provides driving current to the light-emitting element D. The first terminal of the storage capacitor Cst receives the first power supply signal pvdd. The second terminal of the storage capacitor Cst is connected to the gate of the driving transistor T0.

[0098] The first terminal of the data writing transistor T1 is connected to the data line 20, and the second terminal of the data writing transistor T1 is connected to the first terminal of the driving transistor T0. The gate of the data writing transistor T1 is used to receive the first scan signal Scan1. Under the control of the first scan signal Scan1, the data writing transistor T1 writes the data signal VData provided by the data line 20 to the first terminal of the driving transistor T0.

[0099] The first terminal of the threshold compensation transistor T2 is connected to the gate of the driving transistor T0 and the second terminal of the storage capacitor Cst, respectively. The second terminal of the threshold compensation transistor T2 is connected to the second terminal of the driving transistor T0, respectively. The gate of the threshold compensation transistor T2 is used to receive the first scan signal Scan1. Under the control of the first scan signal Scan1, the threshold compensation transistor T2 is used to compensate the threshold voltage of the driving transistor T0 to the gate of the driving transistor T0. For example, there can be one or more threshold compensation transistors T2, which is not limited here.

[0100] For example, the first terminal of the data writing transistor T1 in the first pixel circuit 110 is connected to the first data line 21, and the first terminal of the data writing transistor in the second pixel circuit 120 is connected to the second data line 22. For example, taking the gating circuit 40 connected to the four data lines 20 of the two pixel circuit columns respectively, in the first pixel circuit column 11, the first terminal of the data writing transistor T1 in the first pixel circuit 110 is connected to the first A data line 211, and the first terminal of the data writing transistor T1 in the second pixel circuit 120 is connected to the second A data line 221; in the second pixel circuit column 12, the first terminal of the data writing transistor in the first pixel circuit 110 is connected to the first B data line 212, and the first terminal of the data writing transistor T1 in the second pixel circuit 120 is connected to the second B data line 222.

[0101] In the aforementioned display panel, the pixel circuit provides driving current to the light-emitting element D via a driving transistor T0 to drive the light-emitting element D to emit light. A data writing transistor T1 writes the data signal VData provided by the data line 20 to the first terminal of the driving transistor T0. A storage capacitor Cst stores the gate potential of the driving transistor T0 to maintain the light-emitting element D's illumination. A threshold compensation transistor T2 performs threshold compensation on the gate potential of the driving transistor T0 to adjust its threshold voltage. This achieves the driving of the light-emitting element D by the pixel circuit, thereby realizing the display function of the display panel. Furthermore, the use of a first data line 21 and a second data line 22 (i.e., dual data lines 20) to provide the data signal VData in the same pixel circuit column improves the charging efficiency of the pixel circuit, contributing to further enhancement of display performance.

[0102] Figure 12 is a cross-sectional structural diagram of a display panel provided in an embodiment of this application; Figure 13 is a layout structural diagram of a semiconductor layer Poly provided in an embodiment of this application; Figure 14 is a layout structural diagram of a first conductive layer M1 provided in an embodiment of this application; Figure 15 is a layout structural diagram of a capacitor conductive layer MC provided in an embodiment of this application; Figure 16 is a layout structural diagram of a second conductive layer M2 provided in an embodiment of this application; Figure 17 is a layout structural diagram of a third conductive layer M3 provided in an embodiment of this application; and Figure 18 is a layout structural diagram of a display panel provided in an embodiment of this application. Figure 18 is a schematic diagram showing the sequentially stacked layers of Figures 13 to 17.

[0103] Referring to Figures 12 to 18, in one embodiment, the display panel includes a substrate Sub and a semiconductor layer Poly, a first conductive layer M1, a capacitive conductive layer MC, a second conductive layer M2, and a third conductive layer M3, which are sequentially located away from the substrate Sub.

[0104] The pixel circuit includes an active layer. The active layer of the pixel circuit is located on the semiconductor layer Poly. The gate of the driving transistor T0, the gate of the data writing transistor T1, the gate of the threshold compensation transistor T2, and the second terminal of the storage capacitor Cst are respectively located on the first conductive layer M1. The first terminal of the storage capacitor Cst is located on the capacitor conductive layer MC. The first data line 21 and the second data line 22 are respectively located on the third conductive layer M3.

[0105] The active layer of the pixel circuit includes the active layer of driving transistor T0, the active layer of data writing transistor T1, and the active layer of threshold compensation transistor T2. The first and second terminals of driving transistor T0 are connected to its active layer. The first and second terminals of data writing transistor T1 are connected to its active layer. The first and second terminals of threshold compensation transistor T2 are connected to its active layer.

[0106] In the same pixel circuit column, the active layer of the first pixel circuit 110 and the active layer of the second pixel circuit 120 are mirror images of each other along the direction of the pixel circuit column; that is, the active layers of the first pixel circuit 110 and the active layers of the second pixel circuit 120 are symmetrical along the direction of the pixel circuit column.

[0107] For example, as shown in Figure 13, in the first pixel circuit column 11 and the second pixel circuit column 12 connected to the gating circuit 40, the active layers of two adjacent pixel circuits in the same row are mirrored, or symmetrically arranged along the second central axis. For example, in the same row, the active layers of the pixel circuits in the first pixel circuit column 11 connected to the first gating circuit 41 and the pixel circuits in the second pixel circuit column 12 connected to the second gating circuit 42 are the same; in the same row, the active layers of the pixel circuits in the second pixel circuit column 12 connected to the first gating circuit 41 and the pixel circuits in the first pixel circuit column 11 connected to the second gating circuit 42 are the same.

[0108] The aforementioned display panel, by placing the active layer of the pixel circuit on the semiconductor layer Poly, and placing the gate of the driving transistor T0, the gate of the data writing transistor T1, the gate of the threshold compensation transistor T2, and the second end of the storage capacitor Cst on the first conductive layer M1, and placing the first end of the storage capacitor Cst on the capacitor conductive layer MC, and placing the first data line 21 and the second data line 22 on the third conductive layer M3, that is, by placing different structures on different film layers, it is beneficial to signal routing, reduces interference between signals, and can effectively utilize space, which helps to achieve a narrow bezel. Furthermore, by setting the active layers of the first pixel circuit 110 and the second pixel circuit 120 as mirror layers along the pixel circuit column direction, the first connection point 31 connecting the first pixel circuit 110 to the first data line 21 via the active layer can be located at the edge of the first pixel circuit 110 near the first data line 21, and the second connection point 32 connecting the second pixel circuit 120 to the second data line 22 via the active layer can be located at the edge of the second pixel circuit 120 near the second data line 22. This avoids the data line 20 crossing the pixel area to connect with the pixel circuit, thus preventing cross-line connections between the data line 20 and the pixel circuit, improving the crosstalk problem between the data line 20 and other signal lines, and thereby enhancing display performance. It also reduces the total capacitance of the data line 20, improves the charging efficiency of the pixel circuit, helps to further increase the impedance of the fan-out traces of the display panel, and further compresses the line width, which is beneficial for the narrow bezel design of the display panel.

[0109] Figure 19 is a schematic diagram of the layout structure of a data line 20 according to an embodiment of this application. Referring to Figure 19, in one embodiment, the first data line 21 includes a first data line body 2111 and a plurality of first data signal output nodes 2112. In the same first data line 21, each first data signal output node 2112 is connected to the first data line body 2111. The second data line 22 includes a connected second data line body 2211 and a plurality of second data signal output nodes 2212. In the same second data line 22, each second data signal output node 2212 is connected to the second data line body 2211.

[0110] For example, for any pixel circuit column, the number of the first data signal output node 2112 of the first data line 21 and the second data signal output node 2212 of the second data line 22 connected to it is the same, and the same as the number of pixel circuits in the pixel circuit column. It should be noted that the first data line body 2111 and the second data line body 2211 can be straight, the first data signal output node 2112 and the second data signal output node 2212 can be cylindrical, and each body and each node can also be any other suitable shape, without being limited in detail here.

[0111] The first data signal output node 2112 is connected to the first data signal input node VData in the first pixel circuit 110 via a first via. The first data signal input node VData is located in the active layer of the first pixel circuit 110, and is located near the edge of the active layer of the first pixel circuit 110 close to the first data line 21. The active layer of the first pixel circuit 110 is connected to the first electrode of the data writing transistor T1. Therefore, the first data line 21 is connected to the first electrode of the data writing transistor T1 in the first pixel circuit 110 through the first data signal VData node, the first via, the first data signal VData input node, and the active layer of the first pixel circuit 110. In this way, the connection between the first pixel circuit 110 and the first data line 21 is realized. The first connection point 31 between the first pixel circuit 110 and the first data line 21 can be understood as a connection structure composed of the first data signal output node 2112, the first via, and the first data signal VData input node.

[0112] The second data signal output node 2212 is connected to the second data signal VData input node in the second pixel circuit 120 via the second via. The second data signal VData input node is located in the active layer of the second pixel circuit 120, and is located near the edge of the active layer of the second pixel circuit 120 close to the second data line 22. The active layer of the second pixel circuit 120 is connected to the first electrode of the data writing transistor T1. Therefore, the second data line 22 is connected to the first electrode of the data writing transistor T1 in the second pixel circuit 120 through the second data signal VData node, the second via, the second data signal VData input node, and the active layer of the second pixel circuit 120, thus realizing the connection between the second pixel circuit 120 and the second data line 22. The second connection point 32 between the second pixel circuit 120 and the second data line 22 can be understood as a connection structure composed of the second data signal output node 2212, the second via, and the second data signal VData input node.

[0113] It is understood that the data line 20 and the active layer of the pixel circuit are located on different film layers. Therefore, in this embodiment, the data signal VData output node and the data signal VData input node are connected by vias, thereby realizing the connection between the data line 20 and the data writing transistor T1 in the pixel circuit. The number of first vias is the same as the number of correspondingly connected first pixel circuits 110, and the number of second vias is the same as the number of correspondingly connected second pixel circuits 120. The shapes of the first and second vias can be cylindrical or other suitable structures, and can be set according to the actual scenario; no further limitations are imposed here.

[0114] In the aforementioned display panel, the first data line 21 is connected to the first data signal output node 2112 via the first data line body 2111, and is connected to the first data signal VData input node in the first pixel circuit 110 via the first data signal output node 2112 and the active layer of the first pixel circuit 110 via the first data signal VData input node, thereby realizing the connection between the first data line 21 and the first pixel circuit 110.

[0115] Furthermore, since the first data signal VData input node is located on the active layer of the first pixel circuit 110 near the edge of the first data line 21, there is no need for a cross-line connection between the first data line 21 and the first pixel circuit 110, thus avoiding crosstalk between the first data line 21 and other signal lines and reducing the total capacitance of the first data line 21. Similarly, the second data line 22 is connected to the second data signal output node 2212 through the second data line body 2211, and is connected to the second data signal VData input node in the second pixel circuit 120 through the second data signal output node 2212 via the second via. It is also connected to the active layer of the second pixel circuit 120 through the second data signal VData input node, thereby realizing the connection between the second data line 22 and the second pixel circuit 120. Furthermore, since the input node of the second data signal VData is located on the active layer of the second pixel circuit 120 near the edge of the second data line 22, there is no need for a cross-line connection between the second data line 22 and the second pixel circuit 120. This avoids crosstalk between the second data line 22 and other signal lines, reduces the total capacitance of the second data line 22, thereby improving the problem of crosstalk between the data line 20 and other signal lines, enhancing the display effect, reducing the total capacitance of the data line 20, increasing the pixel charging rate, and allowing the impedance of the fan-out traces of the display panel to be further increased and the line width to be further compressed, which is beneficial for the narrow bezel design of the display panel.

[0116] Please continue to refer to Figure 19. In one embodiment, the first data signal output node 2112 is located on the side of the first data line body 2111 close to the target pixel circuit column, and the second data signal output node 2212 is located on the side of the second data line body 2211 close to the target pixel circuit column.

[0117] The target pixel circuit array is connected to the first data signal output node 2112 and the second data signal output node 2212, respectively. The target pixel circuit array can be any pixel circuit array in the display panel. This minimizes the connection length between the data line 20 and the pixel circuit, significantly reducing the possibility of crosstalk between the data line 20 and other signal lines, and decreasing the total capacitance of the data line 20. This is beneficial for display panel designs with narrow bezels, high-frequency displays, and high pixel density.

[0118] For example, the first data line 21 and the second data line 22 of the same pixel circuit column are located on opposite sides of the pixel circuit column, wherein each first data signal output node 2112 is located on the side of the first data line body 2111 closer to the pixel circuit column, and each second data signal output node 2212 is located on the side of the second data line body 2211 closer to the pixel circuit column. For example, as shown in FIG19, the first data line 21 connected to the same pixel circuit column is located on the left side of the pixel circuit column, and the second data line 22 is located on the right side of the pixel circuit column, wherein the first data signal output node 2112 is located on the right side of the first data line body 2111 closer to the pixel circuit column, and the second data signal output node 2212 is located on the left side of the second data line body 2211 closer to the pixel circuit column.

[0119] It should be noted that the above is only an illustrative example. In application, the relative positional relationship between the first data signal output node 2112 and the second data signal output node 2212 and the target pixel circuit column can be determined according to the layout of the pixel circuit column, the first data line 21 and the second data line 22 in the display panel, etc., and will not be limited in detail here.

[0120] Referring to Figure 19, in one embodiment, the first distance d1 between the first data line body 2111 and the first data signal output node 2112 is the same as, or similar to, the second distance d2 between the second data line body 2211 and the second data signal output node 2212. The first distance d1 and the second distance d2 are both less than the width of the pixel circuit in the pixel circuit row direction. It should be noted that due to factors such as manufacturing precision, the first distance d1 and the second distance d2 may differ during actual manufacturing. However, if the error between the first distance d1 and the second distance d2 is less than a set distance threshold, they can be considered the same. Referring to Figure 2, in a display panel of the related art, among two data lines 20 connected to the same pixel circuit column, the distance between the body of one data line 20 and the connected data signal VData output node is greater than the width of the pixel circuit in the pixel circuit row direction.

[0121] Based on the above comparison, it can be seen that the display panel provided in this application embodiment shortens the distance between the data signal VData output node and the main body of the data line 20, avoiding the connection between the main body of the data line 20 and the corresponding data signal VData output node across the pixel circuit. This avoids cross-line connections between the data line 20 and the pixel circuit, saving space and facilitating narrow bezel and high pixel density display panels. Furthermore, it reduces the coupling capacitance between the data line 20 and other signal lines within the display panel, improving the crosstalk problem between the data line 20 and other signal lines and enhancing the display panel's display effect. In addition, it reduces the total capacitance of the data line 20, increasing the pixel charging rate, allowing for a further increase in the impedance of the fan-out traces in the display panel and a further compression of the line width, which is beneficial for narrow bezel design of the display panel.

[0122] Please continue to refer to Figures 11 to 19. In one embodiment, the pixel circuit further includes a first initialization transistor T3, a second initialization transistor T4, a first light-emitting control transistor T5, and a second light-emitting control transistor T6.

[0123] The first terminal of the first initialization transistor T3 is used to receive the first initialization signal Vref1. The second terminal of the first initialization transistor T3 is connected to the gate of the driving transistor T0, the second terminal of the storage capacitor Cst, and the first terminal of the threshold compensation transistor T2. The gate of the first initialization transistor T3 is used to receive the second scan signal Scan2. Under the control of the second scan signal Scan2, the first initialization transistor T3 initializes the gate potential of the driving transistor T0 using the first initialization signal Vref1. The first and second terminals of the first initialization transistor T3 are connected to the active layer of the first initialization transistor T3, which is located in the semiconductor layer Poly. The gate of the first initialization transistor T3 is located in the first conductive layer M1. There can be one or more first initialization transistors T3; the specific number can be selected according to the actual scenario and is not limited here.

[0124] The first terminal of the second initialization transistor T4 is used to receive the second initialization signal Vref2. The second terminal of the second initialization transistor T4 is connected to the anode of the light-emitting element D. The gate of the second initialization transistor T4 is used to receive the first scan signal Scan1. Under the control of the first scan signal Scan1, the second initialization transistor T4 initializes the anode potential of the light-emitting element D using the second initialization signal Vref2. The first and second terminals of the second initialization transistor T4 are respectively connected to the active layer of the second initialization transistor T4, which is located in the semiconductor layer Poly, and the gate of the second initialization transistor T4 is located in the first conductive layer M1.

[0125] The first terminal of the first light-emitting control transistor T5 is used to receive the first power supply signal pvdd. The first terminal of the first light-emitting control transistor T5 is connected to the first terminal of the storage capacitor Cst. The second terminal of the first light-emitting control transistor T5 is connected to the first terminal of the driving transistor T0 and the first terminal of the data writing transistor T1, respectively. The gate of the first light-emitting control transistor T5 is used to receive the light-emitting control signal Emit. The first light-emitting control transistor T5 is used to control the light-emitting element D to emit light under the control of the light-emitting control signal Emit. The first and second terminals of the first light-emitting control transistor T5 are respectively connected to the active layer of the first light-emitting control transistor T5, which is located in the semiconductor layer Poly, and the gate of the first light-emitting control transistor T5 is located in the first conductive layer M1.

[0126] The first terminal of the second light-emitting control transistor T6 is connected to the second terminal of the driving transistor T0 and the second terminal of the threshold compensation transistor T2, respectively. The second terminal of the second light-emitting control transistor T6 is connected to the anode of the light-emitting element D and the second terminal of the second initialization transistor T4, respectively. The gate of the second light-emitting control transistor T6 is used to receive the light-emitting control signal Emit. The second light-emitting control transistor T6 is used to control the light-emitting element D to emit light under the control of the light-emitting control signal Emit. The first and second terminals of the second light-emitting control transistor T6 are connected to the active layer of the second light-emitting control transistor T6, which is located in the semiconductor layer Poly, and the gate of the second light-emitting control transistor T6 is located in the first conductive layer M1.

[0127] The cathode of the light-emitting element D is used to receive the second power supply signal pvss. The light-emitting element D emits light under the action of the driving current. The first power supply signal pvdd and the second power supply signal pvss are different.

[0128] Each transistor in the pixel circuit can be a low-temperature polycrystalline silicon (LTPS) thin-film transistor (Tx) or a low-temperature polycrystalline oxide (LTPO) thin-film transistor (Ty), specifically an indium gallium zinc oxide (IGZO) thin-film transistor. For example, in the pixel circuit shown in Figure 11, the threshold compensation transistor T2 and the first initialization transistor T3 can be LTPO thin-film transistors Ty, while the other transistors can be LTPS thin-film transistors Tx.

[0129] It should be noted that the pixel circuit provided above is a 7T1C structure. In applications, the pixel circuit can be other structure types, such as 8T1C, 9T1C, etc. The appropriate type can be selected according to the actual scenario, and no further restrictions are imposed here.

[0130] The display panel also includes a first power signal line PVDD, a first scan signal line S1, a second scan signal line S2, a first initialization signal line V1, a second initialization signal line V2, and an illumination control signal line EM.

[0131] The first power signal line PVDD is used to output the first power signal pvdd. The first power signal line PVDD is located in the second conductive layer M2. The first power signal line PVDD is connected to the first terminal of the storage capacitor Cst and the active layer of the first light-emitting control transistor T5. The active layer of the first light-emitting control transistor T5 is connected to its first electrode, thus the first power signal line PVDD is connected to the first electrode of the first light-emitting control transistor T5 through its active layer, providing the first power signal pvdd to the first electrode of the first light-emitting control transistor T5. For example, the first power signal line PVDD extends along the pixel circuit column direction and is arranged along the pixel circuit row direction.

[0132] The first scan signal line S1 is used to output the first scan signal Scan1. The first scan signal line S1 is located in the first conductive layer M1. The first scan signal line S1 is connected to the gate of the data writing transistor T1, the gate of the threshold compensation transistor T2, and the gate of the second initialization transistor T4, respectively, thereby providing the first scan signal Scan1 to the gates of the data writing transistor T1, the threshold compensation transistor T2, and the second initialization transistor T4. For example, the first scan signal line S1 is arranged along the column direction of the pixel circuit and extends along the row direction of the pixel circuit.

[0133] The second scan signal line S2 is used to output the second scan signal Scan2. The second scan signal line S2 is located in the first conductive layer M1. The second scan signal line S2 is connected to the gate of the first initialization transistor T3, thereby providing the second scan signal Scan2 to the gate of the first initialization transistor T3. For example, the second scan signal line S2 is arranged along the column direction of the pixel circuit and extends along the row direction of the pixel circuit.

[0134] The first initialization signal line V1 is used to output the first initialization signal Vref1. The first initialization signal line V1 is located in the capacitor conductive layer MC. The first initialization signal line V1 is connected to the active layer of the first initialization transistor T3, thereby connecting the first initialization signal line V1 to the first terminal of the first initialization transistor T3 through the active layer of the first initialization transistor T3, and thus providing the first initialization signal Vref1 to the first terminal of the first initialization transistor T3. For example, the first initialization signal line V1 is arranged along the pixel circuit column direction and extends along the pixel circuit row direction.

[0135] The second initialization signal line V2 is used to output the second initialization signal Vref2. The second initialization signal line V2 is located in the capacitor conductive layer MC. The second initialization signal line V2 is connected to the active layer of the second initialization transistor T4, thereby connecting the second initialization signal line V2 to the first terminal of the second initialization transistor T4 through the active layer of T4, and thus providing the second initialization signal Vref2 to the first terminal of T4. For example, the second initialization signal line V2 is arranged along the pixel circuit column direction and extends along the pixel circuit row direction.

[0136] The light emission control signal line EM is used to output the light emission control signal Emit. The light emission control signal line EM is located in the first conductive layer M1. The light emission control signal line EM is connected to the gate of the first light emission control transistor T5 and the gate of the second light emission control transistor T6, respectively. For example, the light emission control signal line EM is arranged along the column direction of the pixel circuit and extends along the row direction of the pixel circuit.

[0137] It should be noted that the above is only an illustrative example. In actual applications, the display panel can be configured with signal lines according to the signal requirements of the pixel circuit, and no limitations are imposed here.

[0138] The aforementioned display panel, by further configuring the pixel circuit with a first initialization transistor T3, a second initialization transistor T4, a first light-emitting control transistor T5, and a second light-emitting control transistor T6, and correspondingly configuring a first power signal line PVDD, a first scan signal line S1, a second scan signal line S2, a first initialization signal line V1, a second initialization signal line V2, and a light-emitting control signal line EM in the display panel, enables the display panel to drive the light-emitting element D to emit light through the pixel circuit of the 7T1C structure, providing technical support for the display function of the display panel. Compared with the pixel circuits of the 2T1C structure in related technologies, it improves the display performance.

[0139] Based on the same concept, this application also provides a display screen. Figure 20 is a cross-sectional structural diagram of the display screen 1000 provided in this application embodiment. As shown in Figure 20, the display screen 1000 includes a cover plate 1200 and a display panel 1100 as described in any of the above embodiments. The cover plate 1200 is located on the surface of the display panel 1100 in the light-emitting direction, that is, the cover plate 1200 is located on the side of the display panel 1100 that emits light. Therefore, the display screen 1000 also has the beneficial effects of the display panel 1100 in the above embodiments. The similarities can be understood by referring to the explanation of the display panel 1100 above, and will not be repeated below.

[0140] Based on the same concept, this application also provides a display device. Figure 21 is a top view of the display device provided in this application. As shown in Figure 21, the display device 10000 includes the display screen 1000 in any of the above embodiments. Exemplarily, as shown in Figure 21, the display device 10000 includes the display screen 1000, and the display screen 1000 includes a cover plate 1200 and a display panel 1100 in any of the above embodiments. Therefore, the display device 10000 also has the beneficial effects of the display panel 1100 in the above embodiments. The similarities can be understood by referring to the explanation of the display panel 1100 above, and will not be repeated below.

[0141] The display device provided in this application embodiment can be the mobile phone shown in FIG21, or any electronic product with display function, including but not limited to the following categories: television, laptop, desktop monitor, tablet computer, digital camera, smart bracelet, smart glasses, vehicle display, industrial control equipment, medical display screen, touch interactive terminal, etc. This application embodiment does not make any special limitation in this regard.

[0142] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0143] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the invention patent. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims.

Claims

1. A display panel, comprising: The system comprises multiple pixel circuit columns, multiple first data lines, and multiple second data lines, wherein each pixel circuit column has one first data line and one second data line; wherein, The pixel circuit column includes multiple first pixel circuits and multiple second pixel circuits. In the same pixel circuit column, each first pixel circuit is connected to the first data line, and each second pixel circuit is connected to the second data line. The layout structures of the first pixel circuits and the second pixel circuits are mirror images of each other along the direction of the pixel circuit column. The first connection point between the first pixel circuit and the first data line is located at the edge of the first pixel circuit near the first data line, and the second connection point between the second pixel circuit and the second data line is located at the edge of the second pixel circuit near the second data line.

2. The display panel according to claim 1, wherein, The display panel further includes a gating circuit, wherein the first data line and the second data line connected to at least one of the pixel circuit columns are connected to a data signal terminal via the gating circuit. The gating circuit is used to transmit the data signal provided by the data signal terminal to the first data line and the second data line connected to the gating circuit in a time-division manner.

3. The display panel according to claim 2, wherein, The plurality of pixel circuit columns include a plurality of first pixel circuit columns and a plurality of second pixel circuit columns, wherein the first pixel circuit columns and the second pixel circuit columns are alternately arranged; The four data lines connected to the first pixel circuit column and the second pixel circuit column are connected to the data signal terminal via the gating circuit. The gating circuit is used to transmit the data signal provided by the data signal terminal to the four data lines connected to the gating circuit in a time-division manner.

4. The display panel according to claim 3, wherein, The multiple first data lines include multiple first A data lines and multiple first B data lines; the multiple second data lines include multiple second A data lines and multiple second B data lines; the gating circuit includes a first switching unit, a second switching unit, a third switching unit, and a fourth switching unit. The first A data line and the second A data line are respectively connected to the same first pixel circuit column, and the first B data line and the second B data line are respectively connected to the same second pixel circuit column; The first terminals of the first switch unit, the second switch unit, the third switch unit, and the fourth switch unit are respectively connected to the data signal terminal. The second terminal of the first switch unit is connected to the first data line A, the second terminal of the second switch unit is connected to the second data line A, the second terminal of the third switch unit is connected to the first data line B, and the second terminal of the fourth switch unit is connected to the second data line B. The control terminals of the first switch unit, the second switch unit, the third switch unit, and the fourth switch unit are respectively used to receive different control signals.

5. The display panel according to claim 3, wherein, The multiple first data lines include multiple first A data lines and multiple first B data lines, and the multiple second data lines include multiple second A data lines and multiple second B data lines; The first data line A and the second data line A are respectively connected to the same first pixel circuit column, and the first data line B and the second data line B are respectively connected to the same second pixel circuit column; wherein... The first data line A and the second data line B are arranged symmetrically.

6. The display panel according to claim 3, wherein, In the first pixel circuit array, the first pixel circuit is a pixel circuit that drives the first color pixel, and the second pixel circuit is a pixel circuit that drives the second color pixel. In the second pixel circuit column, the first pixel circuit and the second pixel circuit are pixel circuits that drive the third color pixel.

7. The display panel according to claim 6, wherein, The first color pixel is a red pixel, the second color pixel is a blue pixel, and the third color pixel is a green pixel.

8. The display panel according to claim 3, wherein, In the first and second pixel circuit columns connected by the same gating circuit, the layout structures of two adjacent pixel circuits located in the same row are mirrored along the direction of the pixel circuit column.

9. The display panel according to any one of claims 1-8, wherein, The pixel circuits of the pixel circuit column include: A driving transistor is used to provide driving current to a light-emitting element. A storage capacitor, wherein a first terminal of the storage capacitor is used to receive a first power signal, and a second terminal of the storage capacitor is connected to the gate of the driving transistor; A data writing transistor, wherein the first terminal of the data writing transistor is connected to a data line, the second terminal of the data writing transistor is connected to the first terminal of the driving transistor, and the gate of the data writing transistor is used to receive a first scan signal; A threshold compensation transistor is provided, wherein the first terminal of the threshold compensation transistor is connected to the gate of the driving transistor and the second terminal of the storage capacitor, the second terminal of the threshold compensation transistor is connected to the second terminal of the driving transistor, and the gate of the threshold compensation transistor is used to receive the first scan signal.

10. The display panel according to claim 9, wherein, The display panel includes a substrate and, sequentially away from the substrate, a semiconductor layer, a first conductive layer, a capacitive conductive layer, a second conductive layer, and a third conductive layer; wherein... The pixel circuit includes an active layer located in the semiconductor layer. The gate of the driving transistor, the gate of the data writing transistor, the gate of the threshold compensation transistor, and the second terminal of the storage capacitor are respectively located in the first conductive layer. The first terminal of the storage capacitor is located in the capacitor conductive layer. The first data line and the second data line are respectively located in the third conductive layer. In the same pixel circuit array, the active layer of the first pixel circuit and the active layer of the second pixel circuit are mirror images of each other along the direction of the pixel circuit array.

11. The display panel according to claim 10, wherein, The first data line includes a first data line body and a plurality of first data signal output nodes connected together; the second data line includes a second data line body and a plurality of second data signal output nodes connected together. The first data signal output node is connected to the first data signal input node in the first pixel circuit via the first via. The first data signal input node is located on the active layer of the first pixel circuit near the edge of the first data line. The second data signal output node is connected to the second data signal input node in the second pixel circuit via the second via. The second data signal input node is located on the active layer of the second pixel circuit near the edge of the second data line.

12. The display panel according to claim 11, wherein, The first data signal output node is located on the side of the first data line body close to the target pixel circuit column, and the second data signal output node is located on the side of the second data line body close to the target pixel circuit column, wherein the target pixel circuit column is connected to the first data signal output node and the second data signal output node respectively.

13. The display panel according to claim 11, wherein, The first distance between the first data line body and the first data signal output node is the same as the second distance between the second data line body and the second data signal output node.

14. The display panel according to claim 10, further comprising a first power signal line, a first scan signal line, a second scan signal line, a first initialization signal line, a second initialization signal line, and a light emission control signal line; the pixel circuit further comprising a first initialization transistor, a second initialization transistor, a first light emission control transistor, and a second light emission control transistor; wherein, The first power signal line is used to output the first power signal. The first power signal line is located in the second conductive layer and is connected to the first end of the storage capacitor. The first scan signal line is used to output the first scan signal. The first scan signal line is located in the first conductive layer. The first scan signal line is connected to the gate of the data writing transistor, the gate of the threshold compensation transistor, and the gate of the second initialization transistor, respectively. The second scan signal line is used to output a second scan signal. The second scan signal line is located in the first conductive layer and is connected to the gate of the first initialization transistor. The first initialization signal line is used to output a first initialization signal. The first initialization signal line is located in the capacitor conductive layer and is connected to the active layer of the first initialization transistor. The second initialization signal line is used to output a second initialization signal; the second initialization signal line is located in the capacitor conductive layer and is connected to the active layer of the second initialization transistor; The light emission control signal line is used to output a light emission control signal; the light emission control signal line is located in the first conductive layer, and the light emission control signal line is connected to the gate of the first light emission control transistor and the gate of the second light emission control transistor respectively; The first terminal of the first initialization transistor is used to receive the first initialization signal, the second terminal of the first initialization transistor is connected to the gate of the driving transistor, and the gate of the first initialization transistor is used to receive the second scan signal; The first terminal of the second initialization transistor is used to receive the second initialization signal, the second terminal of the second initialization transistor is connected to the anode of the light-emitting element, and the gate of the second initialization transistor is used to receive the first scan signal; The first terminal of the first light-emitting control transistor is used to receive the first power supply signal, the second terminal of the first light-emitting control transistor is connected to the first terminal of the driving transistor, and the gate of the first light-emitting control transistor is used to receive the light-emitting control signal. The first terminal of the second light-emitting control transistor is connected to the second terminal of the driving transistor, the second terminal of the second light-emitting control transistor is connected to the anode of the light-emitting element, and the gate of the second light-emitting control transistor is used to receive the light-emitting control signal; wherein, The gates of the first initialization transistor, the second initialization transistor, the first light-emitting control transistor, and the second light-emitting control transistor are respectively located in the first conductive layer.

15. A display screen, comprising a cover plate and a display panel as claimed in any one of claims 1 to 14, wherein the cover plate is located on a surface of the display panel in the light-emitting direction.

16. A display device comprising the display screen as claimed in claim 15.

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