Multiplier, processor, chip, and electronic device
By arranging the Booth decoding unit around the adder unit in the Booth multiplier, the circuit routing differences are reduced, the glitch problem is solved, and the low power consumption and high performance of the multiplier are achieved.
WO2026123172A1PCT designated stage Publication Date: 2026-06-18BEIJING YOUZHUJU NETWORK TECH CO LTD
Patent Information
- Authority / Receiving Office
- WO · WO
- Patent Type
- Applications
- Current Assignee / Owner
- BEIJING YOUZHUJU NETWORK TECH CO LTD
- Filing Date
- 2024-12-09
- Publication Date
- 2026-06-18
Smart Images
Figure CN2024137906_18062026_PF_FP_ABST
Abstract
Embodiments of the present disclosure provide a multiplier, a processor, a chip, and an electronic device. The multiplier comprises: a plurality of Booth decoding units and a plurality of addition units; each addition unit is divided into one stage of addition of multi-stage addition, and an input end of each addition unit is further connected to an output end of at least one Booth decoding unit; for a first addition unit in first-stage addition in the multi-stage addition, at least two Booth decoding units connected to an input end of the first addition unit are distributed around the first addition unit; each Booth decoding unit is configured to receive a Booth encoded signal, process a multiplicand on the basis of the Booth encoded signal, and output a partial product; and each addition unit is configured to receive at least the partial product outputted by at least one Booth decoding unit connected to the addition unit, perform an addition operation on the basis of at least one partial product, and output an addition operation result. The multiplier provided by the present disclosure involves saved power consumption and has improved performance.
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