Soft repair control circuit, memory, and repair method for memory

Abstract

A soft repair control circuit comprises a lock control circuit, an undo control circuit, a soft repair address latch circuit, and a soft repair address match circuit. The lock control circuit is configured to lock an outputted latch control signal to a first level when a lock enable signal is at an active level. The undo control circuit is configured to maintain an output unchanged when the latch control signal is locked to the first level, and to generate an undo flag signal at an active level on the basis of an undo enable signal at an active level when the latch control signal is an inverted delayed signal of a soft repair pulse signal. The soft repair address latch circuit is configured to maintain an output unchanged when the latch control signal is locked to the first level. The soft repair address match circuit is configured to lock an outputted soft repair match signal to an inactive level when the undo flag signal is at the active level.

Description

A method for repairing a control circuit, a memory, and a memory using a soft repair mechanism.

[0001] Cross-reference to related applications

[0002] This application claims priority to Chinese Patent Application No. 202411815017.2, filed on December 9, 2024, entitled “A Soft Repair Control Circuit, a Memory and a Method for Repairing a Memory”, the entire contents of which are incorporated herein by reference. Technical Field

[0003] This disclosure relates to the field of semiconductor technology, and in particular to a soft repair control circuit, a memory, and a method for repairing the memory. Background Technology

[0004] With the continuous development of semiconductor technology, the integration of memory devices is becoming increasingly higher, and the number of memory cells in a single memory chip is increasing dramatically. However, the increase in the number of memory cells also brings memory defect problems. In order to improve the yield of memory and reduce production costs, redundant memory cells and post-package repair technology have been introduced. Specifically, the traditional hard post-package repair (HPPR) technology stores the address of defective cells through non-volatile memory circuits (e.g., fuse arrays), reads and performs replacement at startup, and ensures high yield.

[0005] In contrast, Soft Post Package Repair (SPPR) technology offers a more flexible and efficient repair solution. It allows address information to be directly written to volatile latch circuits via commands, simplifying the process and improving repair efficiency in field use. However, in semiconductor memories that support SPPR, further simplifying the control circuitry to achieve compatible execution of various soft repair commands sent by the memory controller remains a critical issue that needs to be addressed. Summary of the Invention

[0006] This disclosure provides a method for repairing a soft-repair control circuit, a memory, and a memory.

[0007] In a first aspect, embodiments of this disclosure provide a soft-repair control circuit, comprising: a locking control circuit configured to receive a locking enable signal, a soft-repair activation signal, and a soft-repair pulse signal; and when the locking enable signal is at an active level, locking the output latch control signal to a first level; and when the locking enable signal is at an inactive level, in response to the active soft-repair signal at an active level, outputting an inverted delayed signal of the soft-repair pulse signal as a latch control signal; wherein, when the locking enable signal is at an active level, an execution of a soft-repair locking operation is indicated; and a deactivation control circuit configured to receive a deactivation enable signal and the latch control signal; when the latch control signal is locked to the first level, maintaining the output unchanged; and when the latch control signal is an inverted delayed signal of the soft-repair pulse signal, in response to a pulse on the latch control signal, generating and outputting a deactivation flag signal at an active level based on the active deactivation enable signal; wherein, when the deactivation enable signal is at an active level, an execution of a soft-repair locking operation is indicated. A soft repair undo operation is performed. A soft repair address latch circuit is configured to receive the soft repair failure address and the latch control signal; when the latch control signal is locked to a first level, the output remains unchanged; and when the latch control signal is an inverted delayed signal of the soft repair pulse signal, the circuit latches the soft repair failure address in response to the pulse on the latch control signal and outputs the latched address. A soft repair address matching circuit is configured to receive the latched address and the undo flag signal; when the undo flag signal is at a valid level, the circuit locks the output soft repair matching signal to an invalid level; when the undo flag signal is at an invalid level, the circuit matches the target address with the latched address to generate and output a soft repair matching signal. When the soft repair matching signal is at a valid level, it indicates that the target address and the latched address have successfully matched; when the soft repair matching signal is at an invalid level, it indicates that the target address and the latched address have not successfully matched. The target address is the address corresponding to the access operation in normal working mode.

[0008] In some embodiments, the locking control circuit includes: a locking flag signal generation circuit configured to receive the locking enable signal, the soft repair activation signal, and the soft repair pulse signal; and when the locking enable signal is at an active level and the soft repair activation signal is at an active level, to generate and output a latch control signal at an active level in response to a pulse on the soft repair pulse signal; and when the locking enable signal is at an inactive level, to generate and output a locking flag signal at an inactive level; and a latch control signal generation circuit configured to receive the locking flag signal, the soft repair activation signal, and the soft repair pulse signal; and when the locking flag signal is at an active level, to lock the output latch control signal to a first level; and when the locking flag signal is at an inactive level and the soft repair activation signal is at an active level, to output an inverted delayed signal of the soft repair pulse signal as a latch control signal.

[0009] In some embodiments, the lock flag signal generation circuit includes: a first NAND gate, the input of which receives the lock enable signal, the soft repair activation signal, and the soft repair pulse signal respectively; a D flip-flop, the input of which is electrically connected to a power supply terminal, the clock terminal of which is electrically connected to the output of the first NAND gate, and the output of which is used to output the lock flag signal; the latch control signal generation circuit includes: a delay unit, the input of which receives the soft repair pulse signal; a second NAND gate, the first input of which receives the soft repair activation signal, and the second input of which is electrically connected to the output of the delay unit; and an OR gate, the first input of which is electrically connected to the output of the D flip-flop, the second input of which is electrically connected to the output of the second NAND gate, and the output of which is used to output the latch control signal.

[0010] In some embodiments, the cancellation control circuit includes: a first latch, the input of which receives the cancellation enable signal, and the control terminal of which receives the latch control signal; and a NOT gate, the input of which is electrically connected to the output of the first latch, and the output of which is used to output the cancellation flag signal.

[0011] In some embodiments, the soft-repair address latching circuit includes at least one sub-latch circuit, and a sub-latch circuit is selected as a target sub-latch circuit according to a preset order; the target sub-latch circuit is configured to receive the latch control signal and the soft-repair failure address, and when the latch control signal is locked to a first level, maintain the currently output latch address unchanged, and when the latch control signal is an inverted delayed signal of the soft-repair pulse signal, latch the soft-repair failure address as the latch address in response to the pulse on the latch control signal.

[0012] In some embodiments, the soft-repair address matching circuit includes at least one sub-matching circuit, which is connected one-to-one with the at least one sub-latch circuit. One sub-matching circuit connected to the target sub-latch circuit serves as the target sub-matching circuit. The target sub-matching circuit is configured to receive the cancellation flag signal and the target address. When the cancellation flag signal is at an active level, it locks the output soft-repair matching signal to an inactive level. When the cancellation flag signal is at an inactive level, it matches the corresponding latch address with the target address to generate and output a corresponding soft-repair matching signal.

[0013] In some embodiments, the target sub-latch circuit includes a plurality of second latches, each of which corresponds one-to-one with a plurality of first address signals in the soft repair failure address and a plurality of second address signals in the latch address; the input terminal of the second latch receives a corresponding first address signal, the control terminal of the second latch receives the latch control signal, and the output terminal of the second latch is used to output a corresponding second address signal.

[0014] In some embodiments, the target sub-matching circuit includes multiple XOR gates and AND gates, wherein the multiple XOR gates correspond one-to-one with the multiple second latches and multiple third address signals in the target address; the first input terminal of the XOR gate receives a corresponding third address signal, and the second input terminal of the XOR gate is electrically connected to the output terminal of a corresponding second latch; one input terminal of the AND gate receives the cancellation flag signal, and the other input terminals of the AND gate are electrically connected one-to-one with the output terminals of the multiple XOR gates, and the output terminal of the AND gate is used to output the soft repair matching signal.

[0015] In some embodiments, the locking control circuit is further configured to reset the latch control signal in response to a reset signal; the undo control circuit is further configured to reset the undo flag signal to an invalid level in response to the reset signal; and the soft-repair address latch circuit is further configured to reset the latch address in response to the reset signal.

[0016] Secondly, embodiments of this disclosure also provide a memory, which includes a command decoding circuit and a soft repair control circuit as described in the first aspect; the command decoding circuit is configured to receive a soft repair command, and when the soft repair mode parameter in the soft repair command is a second preset value, generate a deactivation enable signal at an effective level, and when the soft repair mode parameter in the soft repair command is a third preset value, generate a lock enable signal at an effective level; the soft repair control circuit is further configured to receive the deactivation enable signal and the lock enable signal, and when the deactivation enable signal is at an effective level, control the execution of a soft repair deactivation operation, and when the lock enable signal is at an effective level, control the execution of a soft repair lock operation.

[0017] In some embodiments, the command decoding circuit is further configured to generate a soft repair enable signal at a valid level when the soft repair mode parameter in the soft repair command is a first preset value; wherein, when the soft repair enable signal is at a valid level, it indicates that the memory enters the soft repair mode; the command decoding circuit is further configured to, after the memory enters the soft repair mode, sequentially receive an activation command and a write command, and decode the activation command to generate and output a soft repair activation signal and a soft repair failure address, and decode the write command to generate and output a soft repair pulse signal; wherein, when the address information in the activation command indicates the memory bank corresponding to the soft repair control circuit, the soft repair activation signal at a valid level is generated and sent to the soft repair control circuit; the soft repair control circuit is electrically connected to the command decoding circuit and is configured to receive the soft repair activation signal, the soft repair failure address, and the soft repair pulse signal, and when the soft repair activation signal is at a valid level, latch the soft repair failure address as a latched address according to the soft repair pulse signal.

[0018] In some embodiments, the memory further includes: a row address decoding circuit and a memory bank; the command decoding circuit is further configured to generate a soft repair enable signal at an invalid level to indicate that the memory enters a normal operating mode when the soft repair mode parameter in the soft repair command is a fourth preset value; the command decoding circuit is further configured to receive an activation command and decode the activation command to generate and output the target address when the memory is in a normal operating mode; the soft repair control circuit is further configured to match the target address with the latched address when the memory is in a normal operating mode, and generate and output a soft repair matching signal at an active level when the target address and the latched address are successfully matched; the row address decoding circuit is electrically connected to the soft repair control circuit and is configured to receive the soft repair matching signal and the target address, and control the activation of the word line of the corresponding soft repair redundant row in the memory bank according to the active level of the soft repair matching signal when the soft repair matching signal is at an active level.

[0019] In some embodiments, the command decoding circuit includes: a soft repair command decoder, a mode register, a soft repair signal generation circuit, an activation command decoder, and a write command decoder; the soft repair command decoder is configured to receive the soft repair command and write the soft repair mode parameters in the soft repair command into the mode register; the soft repair signal generation circuit is configured to receive the soft repair mode parameters stored in the mode register, and when the soft repair mode parameters are a first preset value, generate a soft repair enable signal at an active level, and when the soft repair mode parameters are a second preset value, generate a deactivation enable signal at an active level. When the soft repair mode parameter is a third preset value, a lock enable signal at an active level is generated; the activation command decoder is configured to receive the soft repair enable signal and the activation command, and when the active level soft repair enable signal indicates that the memory has entered the soft repair mode, decode the activation command to generate and output the soft repair activation signal and the soft repair failure address; the write command decoder is configured to receive the soft repair enable signal and the write command, and when the active level soft repair enable signal indicates that the memory has entered the soft repair mode, decode the write command to generate and output the soft repair pulse signal.

[0020] In some embodiments, the memory further includes: a fuse address matching circuit configured to receive a plurality of standard failure addresses from a fuse array, match the received target address with the plurality of standard failure addresses respectively, and generate a plurality of standard matching signals based on the matching results; the row address decoding circuit is further configured to receive the plurality of standard matching signals, and when any standard matching signal is at an active level, control the activation of the word line of the corresponding standard redundant row in the memory bank based on the active level of the standard matching signal.

[0021] In some embodiments, the row address decoding circuit is further configured to, when both the soft-repair match signal and the standard match signal are at an invalid level, control the activation of the word line of the corresponding storage row in the memory bank according to the target address.

[0022] Thirdly, embodiments of this disclosure also provide a memory repair method, comprising: receiving a soft repair command and decoding the soft repair command; determining the value of a soft repair mode parameter in the soft repair command; when the soft repair mode parameter is a second preset value, generating a deactivation enable signal at a valid level to indicate the execution of a soft repair deactivation operation; in response to the deactivation enable signal at a valid level, locking a soft repair matching signal to an invalid level; when the soft repair mode parameter is a third preset value, generating a lock enable signal at a valid level to indicate the execution of a soft repair lock operation; in response to the lock enable signal at a valid level, maintaining the currently latched soft repair failure address unchanged, and masking the deactivation enable signal; wherein, when the soft repair matching signal is at an invalid level, it indicates that the target address and the latched soft repair failure address have not matched successfully, and the target address is the address corresponding to the access operation in normal working mode.

[0023] In some embodiments, the repair method further includes: when the soft repair mode parameter in the soft repair command is a first preset value, generating a soft repair enable signal at an active level to indicate entering the soft repair mode; after the memory enters the soft repair mode, receiving an activation command and a write command in sequence; decoding the activation command to generate a soft repair activation signal and a soft repair failure address; decoding the write command to generate a soft repair pulse signal; and in response to the active level of the soft repair activation signal, latching the soft repair failure address as a latched address according to the soft repair pulse signal.

[0024] In some embodiments, the repair method further includes: when the soft repair mode parameter in the soft repair command is a fourth preset value, generating a soft repair enable signal at an invalid level to indicate that the memory enters a normal operating mode; when the memory is in a normal operating mode, receiving an activation command; decoding the activation command to generate a target address; matching the target address with the latched soft repair failure address, and generating a soft repair matching signal at an effective level when the matching is successful; and controlling the activation of the word line of the corresponding soft repair redundant row in the memory according to the soft repair matching signal at an effective level.

[0025] This disclosure provides a soft repair control circuit, a memory, and a memory repair method. The soft repair control circuit includes a locking control circuit and a cancellation control circuit. When the locking enable signal is at a valid level indicating a soft repair locking operation, the locking control circuit can shield the soft repair pulse signal and output a locking control signal at a constant first level. This controls the soft repair address latch circuit to maintain a locked state, preventing the latching of new soft repair failure addresses and keeping the currently latched soft repair failure address unchanged, thus enabling the soft repair locking operation. When the cancellation enable signal is at a valid level indicating a soft repair cancellation operation, the cancellation control circuit can output a cancellation flag signal locked at a valid level. This controls the soft repair matching signal output by the soft repair address matching circuit to be locked at an invalid level. Regardless of whether the target address and the latched address match successfully during normal access, a failure result is output, thus shielding the matching result of the previously latched address and preventing the soft repair operation from being executed. This cancels the previous soft repair operation, enabling the soft repair cancellation operation to be executed. In this way, the soft repair control circuit only uses the newly added locking control circuit and undo control circuit, and only uses the locking control signal output by the newly added locking control circuit and the undo flag signal output by the undo control circuit, to complete various operations such as latching, locking, and undoing of the soft repair failure address based on the original soft repair address latching circuit and soft repair address matching circuit. While realizing all the soft repair operations specified in the standard, it simplifies the circuit design and saves circuit area. Attached Figure Description

[0026] Figure 1 is a schematic diagram of the composition structure of a soft repair control circuit provided in an embodiment of this disclosure;

[0027] Figure 2 is a schematic diagram of the composition structure of a locking control circuit provided in an embodiment of this disclosure;

[0028] Figure 3 is a schematic diagram of the composition structure of a locking identifier signal generation circuit and a latch control signal generation circuit provided in an embodiment of this disclosure;

[0029] Figure 4 is a schematic diagram of the composition structure of a cancellation control circuit provided in an embodiment of this disclosure;

[0030] Figure 5A is a schematic diagram of the composition structure of a soft-repair address latch circuit and a soft-repair address matching circuit provided in an embodiment of this disclosure;

[0031] Figure 5B is a schematic diagram of the composition structure of another soft-repair address latch circuit and soft-repair address matching circuit provided in the embodiments of this disclosure;

[0032] Figure 6 is a schematic diagram of the composition structure of a target sub-latch circuit and a target sub-matching circuit provided in an embodiment of this disclosure;

[0033] Figure 7 is a schematic diagram of the composition structure of a memory provided in an embodiment of this disclosure;

[0034] Figure 8 is a schematic diagram of the composition structure of a command decoding circuit provided in an embodiment of this disclosure;

[0035] Figure 9 is a schematic diagram of the composition structure of a memory provided in an embodiment of this disclosure;

[0036] Figure 10 is a signal timing diagram of a memory according to an embodiment of this disclosure;

[0037] Figure 11 is a second signal timing diagram corresponding to a memory provided in an embodiment of this disclosure;

[0038] Figure 12 is a schematic flowchart of a memory repair method provided in an embodiment of this disclosure. Detailed Implementation

[0039] The technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. It should be understood that the specific embodiments described herein are for illustrative purposes only and are not intended to limit the disclosure. Furthermore, it should be noted that, for ease of description, only the parts relevant to the disclosure are shown in the accompanying drawings.

[0040] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. The terminology used herein is for the purpose of describing embodiments of this disclosure only and is not intended to be limiting of this disclosure.

[0041] In the following description, references are made to “some embodiments,” which describe a subset of all possible embodiments. However, it is understood that “some embodiments” may be the same subset or different subsets of all possible embodiments and may be combined with each other without conflict.

[0042] It should be noted that the terms "first, second, third" used in the embodiments of this disclosure are merely to distinguish similar objects and do not represent a specific ordering of objects. It is understood that "first, second, third" can be interchanged in a specific order or sequence where permitted, so that the embodiments of this disclosure described herein can be implemented in an order other than that illustrated or described herein.

[0043] To achieve compatible execution of various soft repair commands sent by the memory controller and improve the yield of memory chips, this disclosure provides a soft repair control circuit including: a locking control circuit, a cancellation control circuit, a soft repair address latch circuit, and a soft repair address matching circuit. The locking control circuit is configured to receive a locking enable signal, a soft repair activation signal, and a soft repair pulse signal; when the locking enable signal is at a valid level indicating the execution of a soft repair locking operation, it locks the output latch control signal to a first level; and when the locking enable signal is at an invalid level, it outputs the soft repair pulse signal as a latch control signal in response to the valid soft repair activation signal. The cancellation control circuit is configured to receive a cancellation enable signal and a latch control signal; when the latch control signal is locked to the first level, it maintains its output unchanged; and when the latch control signal is an inverted delayed signal of the soft repair pulse signal, it executes the soft repair address matching operation according to the indication in response to the pulse on the latch control signal. The system includes a revocation enable signal at an active level for revocation operations, which generates and outputs a revocation flag signal at an active level. A soft-revision address latch circuit is configured to receive the soft-revision failed address and a latch control signal. When the latch control signal is locked to a first level, the output remains unchanged. When the latch control signal is an inverted delayed version of the soft-revision pulse signal, the circuit latches the soft-revision failed address in response to the pulse on the latch control signal and outputs the latched address. A soft-revision address matching circuit is configured to receive the latched address and a revocation flag signal. When the revocation flag signal is active, the circuit locks the output soft-revision matching signal to an inactive level. When the revocation flag signal is inactive, the circuit matches the target address with the latched address to generate and output a soft-revision matching signal. When the soft-revision matching signal is active, it indicates that the target address and the latched address have matched successfully. When the soft-revision matching signal is inactive, it indicates that the target address and the latched address have not matched successfully.

[0044] Thus, when the lock enable signal is at a valid level indicating the execution of a soft repair lock operation, the lock control circuit can shield the soft repair pulse signal and output a lock control signal that is constant at the first level. This controls the soft repair address latch circuit to maintain the lock state, preventing the latching of new soft repair failure addresses and keeping the currently latched soft repair failure addresses unchanged. Furthermore, the first-level lock control signal can also shield the subsequent soft repair cancellation enable signal indicating the execution of a soft repair cancellation operation, thereby enabling the execution of the soft repair lock operation. Simultaneously, when the cancellation enable signal is at a valid level indicating the execution of a soft repair cancellation operation, the cancellation control circuit can output a cancellation flag signal locked at a valid level. This controls the soft repair matching signal output by the soft repair address matching circuit, which is locked at an invalid level, to indicate that the match was unsuccessful. This shields the matching result of the previously latched address and prevents the execution of the soft repair operation, thus canceling the previous soft repair operation and enabling the execution of the soft repair cancellation operation. In this way, the soft repair control circuit only uses the newly added locking control circuit and undo control circuit, and only uses the locking control signal output by the newly added locking control circuit and the undo flag signal output by the undo control circuit, to complete various operations such as latching, locking, and undoing of the soft repair failure address based on the original soft repair address latching circuit and soft repair address matching circuit. While realizing all the functions of soft repair specified in the standard, it simplifies the circuit design and saves circuit area.

[0045] The embodiments of this disclosure will now be described in detail with reference to the accompanying drawings.

[0046] In one embodiment of this disclosure, referring to FIG1, a schematic diagram of the composition structure of a soft repair control circuit 10 provided in an embodiment of this disclosure is shown. As shown in Figure 1, the internal soft-repair control circuit 10 includes: a lock control circuit 11, a cancel control circuit 12, a soft-repair address latch circuit 13, and a soft-repair address matching circuit 14. The lock control circuit 11 is configured to receive a lock enable signal Lock En, a soft-repair activation signal SPPR ACT, and a soft-repair pulse signal SPPR Clk. When the lock enable signal Lock En is at an active level, it locks the output latch control signal SPPR Latch to a first level. When the lock enable signal Lock En is at an inactive level, in response to the active soft-repair activation signal SPPR ACT, it outputs the soft-repair pulse signal SPPR Clk as the latch control signal SPPR Latch. The lock enable signal Lock En indicates the execution of a soft-repair lock operation. The cancel control circuit 12 is configured to receive a cancel enable signal Undo En and the latch control signal SPPR Latch. When the latch control signal SPPR Latch is locked to the first level, it maintains its output unchanged. When the latch control signal SPPR Latch is the soft-repair pulse signal SPPR Clk, it outputs the latch control signal SPPR Latch as the soft-repair pulse signal SPPR Clk. When the inverted delayed signal of Clk is received, in response to the pulse on the latch control signal SPPR Latch, an undo flag signal at an effective level is generated and output according to the undo enable signal Undo En at an effective level; wherein, when the undo enable signal Undo En is at an effective level, it indicates the execution of a soft repair undo operation; the soft repair address latch circuit 13 is configured to receive the soft repair failure address SPPR FA[n:0] and the latch control signal SPPR Latch, and when the latch control signal SPPR Latch is locked at the first level, it keeps the output unchanged, and when the latch control signal SPPR Latch is the inverted delayed signal of the soft repair pulse signal SPPR Clk, it latches the soft repair failure address SPPR FA[n:0] in response to the pulse on the latch control signal SPPR Latch and outputs the latch address Latch FA[n:0]; the soft repair address matching circuit 14 is configured to receive the latch address Latch FA[n:0] and the undo flag signal Undo, and when the undo flag signal Undo... When the flag is at an active level, the output soft repair matching signal SPPR Match is locked to an inactive level. When the undo flag is at an inactive level, the target address RA[n:0] is matched with the latch address Latch FA[n:0] to generate and output the soft repair matching signal SPPR Match.Specifically, when the soft repair matching signal SPPR Match is at an active level, it indicates that the target address RA[n:0] and the latch address Latch FA[n:0] have successfully matched; when the soft repair matching signal SPPR Match is at an inactive level, it indicates that the target address RA[n:0] and the latch address Latch FA[n:0] have not successfully matched. The target address RA[n:0] is the address corresponding to the access operation in normal working mode.

[0047] Specifically, the latch control signal SPPR Latch can simultaneously control the output of the undo control circuit 12 and the soft repair address latch circuit 13 to achieve the soft repair locking function, that is, to lock the result of the already executed soft repair operation (latch address Latch FA[n:0]) unchanged. Specifically, when the Lock En signal at an active level indicates entry into soft repair mode and performs a soft repair locking operation, the Lock control circuit 11 can, based on the Lock En signal, shield the subsequent input soft repair pulse signal SPPR Clk and lock the output latch control signal SPPR Latch at the first level. The first-level latch control signal SPPR Latch can control the undo control circuit 12 to shield the subsequent input undo enable signal Undo En indicating the execution of a soft repair undo operation, so as to keep the original output undo flag unchanged and prevent the undo flag from being displayed. In addition, the first-level latch control signal SPPR Latch can control the soft repair address latch circuit 13 to maintain the locked state and no longer latch the current and subsequent input soft repair failure address SPPR FA[n:0], so as to keep the currently latched soft repair failure address Latch FA[n:0] unchanged. Simultaneously, the latch control signal SPPR Latch can control the matching result output by the soft repair address matching circuit 14 to realize the soft repair cancellation function, that is, to cancel the previously executed soft repair operation and to mask / invalidate the matching result corresponding to the previously latched latch address Latch FA[n:0] in normal working mode. Specifically, when the undo enable signal Undo En, which is at an active level, indicates that the soft repair cancellation operation is to be performed, the undo control circuit 12 can output an undo flag signal locked at an active level. Based on the undo flag signal Undo flag, the soft repair address matching circuit 14 can lock the output soft repair matching signal SPPR Match at an invalid level. Regardless of the matching result of the latch address Latch FA[n:0], it indicates that the match was unsuccessful and the soft repair operation is not performed. At this time, it is equivalent to setting the latched address latched by the soft repair address latch circuit 13 to an invalid state, and the corresponding soft repair redundancy line is set to an unavailable state, that is, the previous soft repair operation is cancelled. Thus, the soft repair control circuit 10 only uses the newly added locking control circuit 11 and undo control circuit 12, and only uses the locking control signal SPPR Latch output by the newly added locking control circuit 11 and the undo flag signal Undo flag output by the undo control circuit, to control the original soft repair address latch circuit 13 and soft repair address matching circuit 14, and complete various operations such as latching, locking, and undoing of the soft repair failure address. While realizing all the soft repair functions specified in the standard, it simplifies the circuit design and saves circuit area.

[0048] Here, "keeping the output unchanged" in the undo control circuit 12 and the soft repair address latch circuit 13 means locking the original output, that is, keeping the original level of the output signal unchanged. For example, after the lock enable signal Lock En is at an active level and indicates the execution of the soft repair lock operation, even if the undo enable signal Undo En, which indicates the execution of the soft repair undo operation, is received again, the undo control circuit 12 cannot respond to the signal by generating an active undo flag signal Undo flag, but will keep the undo flag signal Undo flag at its original level. In other words, in the soft repair control circuit of this embodiment, the soft repair locking operation has a higher priority than the soft repair undo operation. Specifically, if the lock enable signal Lock En indicating the soft repair locking operation is first, the undo enable signal Undo En indicating the soft repair undo operation will be masked / ignored based on the lock control signal SPPR Latch at the first level, and the corresponding soft repair undo operation will not be executed. If the undo enable signal Undo En indicating the soft repair undo operation is first and the lock enable signal Lock En indicating the soft repair locking operation is second, since the undo enable signal Undo En has already set the undo flag signal Undo to an active level, the lock control signal SPPR Latch at the first level will control the original level state (i.e., active level) of the undo flag signal Undo output by the undo control circuit 12 to remain unchanged, and the soft repair control circuit 10 can still continue to execute the soft repair undo operation based on the undo flag signal Undo. That is, the soft repair undo operation and the soft repair locking operation can be executed simultaneously.

[0049] Additionally, if the latch control signal SPPR Latch is the inverted delayed signal of the soft repair pulse signal SPPR Clk, the pulses present on the latch control signal SPPR Latch will switch between high level (logic "1") and low level (logic "0"). Taking the pulse on the soft repair pulse signal SPPR Clk as a positive pulse as an example, the pulse on the latch control signal SPPR Latch will be a negative pulse. The soft repair address latch circuit 13 can "pass through" the input soft repair failure address SPPR FA[n:0] as the output latch address Latch FA[n:0] during the period when the pulse signal is low level (logic "0"), and then latch the output latch address Latch FA[n:0] during the period when the pulse signal is high level (logic "1"). If the latch enable signal is at an active level, the latch control circuit 11 will latch the SPPR control signal SPPR Latch. When the latch is locked at the first level (e.g., high level, logic "1"), the soft repair address latch circuit 13 maintains the latched state based on the high-level (logic "1") latch control signal SPPR Latch, and does not "transmit" the currently input soft repair failure address SPPR FA[n:0]. The latch control signal SPPR Latch has a certain delay compared to the soft repair pulse signal SPPR Clk. This is to ensure that the latch control circuit 11 has sufficient time to determine the states of the input latch enable signal Lock En, the soft repair activation signal SPPR ACT, and the soft repair pulse signal SPPR Clk, thereby determining the correct output latch control signal SPPR Latch.

[0050] Here, the pulse on the soft repair pulse signal SPPR Clk can be a positive pulse or a negative pulse, and the first level can be a high level (logic "1") or a low level (logic "0"). In this embodiment of the disclosure, the pulse on the soft repair pulse signal SPPR Clk is a positive pulse and the first level is a high level (logic "1") for illustration only, but it does not constitute a specific limitation on the embodiments of this disclosure.

[0051] It should be noted that the effective levels of different signals in this embodiment may be different. For example, the effective levels of the Lock En signal, Undo En signal, SPPR ACT signal, and SPPR Match signal may be high level and logic "1", and the invalid level may be low level and logic "0". The effective level of the Undo Flag signal may be low level and logic "0", and the invalid level may be high level and logic "1". In other embodiments, the effective levels of the above signals may also be other combinations of levels, and no limitation is made in this regard.

[0052] It should also be noted that the soft repair operation of the memory can replace a faulty storage row with a soft-repair redundant row in the memory bank. In this case, the soft-repair failure address SPPR FA[n:0], the latch address Latch FA[n:0], and the target address RA[n:0] are all row addresses. In some other embodiments, the soft repair operation of the memory can also replace a faulty storage column with a soft-repair redundant column in the memory bank. In this case, the soft-repair failure address SPPR FA[n:0], the latch address Latch FA[n:0], and the target address RA[n:0] are all column addresses.

[0053] It should also be noted that although the above operations performed by the lock control circuit 11, the undo control circuit 12, and the soft repair address latch circuit 13 are completed in soft repair mode (when a soft repair command is received from the memory controller to instruct the execution of soft repair write, soft repair undo, soft repair lock, etc., the latch control signal SPPR Latch, the undo flag signal Undo flag, and the latch address Latch FA[n:0] output by these circuits can remain unchanged when exiting the soft repair mode, that is, the current soft repair operation can still affect other subsequent operations after it ends. The latch control signal SPPR Latch, locked at the first level, can shield other subsequent soft repair operations, including soft repair write operations and soft repair undo operations. The corresponding latch address Latch FA[n:0] will remain unchanged and will not be overwritten by the subsequently input soft repair failure address. The undo flag signal, which is at an active level, can shield the matching result between the corresponding latch address Latch FA[n:0] and the target address RA[n:0] in the subsequent normal working mode, and output the soft repair matching signal SPPR Match indicating that the match was unsuccessful. The corresponding soft repair redundant line is set to an unavailable state. If the undo flag signal is at an inactive level, the latch address Latch FA[n:0] can be matched with the target address RA[n:0] in the soft repair address matching circuit 14 in the subsequent normal working mode. When the match is successful, the soft repair matching signal SPPR Match, which is at an active level, is output to indicate that the word line of the corresponding soft repair redundant line is enabled, thereby achieving the purpose of soft repair.

[0054] This disclosure relates to the overall framework design of a soft repair control circuit, particularly to a DRAM DDR5 chip. It can also be applied to other DDR series chips and LPDDR series chips, but is not limited to this scope. Other memory chips and other internal repair circuits can also adopt this design.

[0055] Further, regarding the composition of the locking control circuit 11, as shown in Figure 2, the locking control circuit 11 includes: a locking flag signal generation circuit 111, configured to receive a locking enable signal Lock En, a soft repair activation signal SPPR ACT, and a soft repair pulse signal SPPR Clk; and when the locking enable signal Lock En is at an active level and the soft repair activation signal SPPR ACT is at an active level, in response to a pulse on the soft repair pulse signal SPPR Clk, generate and output a latch control signal SPPR Latch at an active level; and when the locking enable signal Lock En is at an inactive level, generate and output a locking flag signal Lock flag at an inactive level; and a latch control signal generation circuit 112, configured to receive the locking flag signal Lock flag, the soft repair activation signal SPPR ACT, and the soft repair pulse signal SPPR Clk; and when the locking flag signal Lock flag is at an active level, lock the output latch control signal SPPR Latch to a first level; and when the locking flag signal Lock flag is at an inactive level and the soft repair activation signal SPPR ACT is at an active level, lock the soft repair pulse signal SPPR Clk to a first level. The inverted delayed signal output of Clk is the latch control signal SPPR Latch.

[0056] Here, the Lock flag signal output by the Lock flag signal generation circuit 111 needs to control whether the latch control signal generation circuit 112 shields the input soft repair pulse signal SPPR Clk. However, the Lock flag signal generation circuit 111 processes all input signals (Lock enable signal Lock En, soft repair activation signal SPPR ACT, and soft repair pulse signal SPPR Clk) to generate the Lock flag signal. The Lock flag signal output at the valid level must be later than the corresponding soft repair pulse signal SPPR Clk. Therefore, the soft repair pulse signal SPPR Clk needs to be inverted and delayed to ensure that the Lock flag signal output at the valid level by the Lock flag signal generation circuit 111 can be earlier than the inverted and delayed signal of the soft repair pulse signal SPPR Clk and shield it, so as to ensure that the latch control signal SPPR Latch output when the Lock flag signal is at the valid level is always at the first level.

[0057] It should be noted that the embodiments of this disclosure use the lock flag signal having an effective level of high level and logic "1" and an invalid level of low level and logic "0" as examples for illustration, but do not constitute a specific limitation on the embodiments of this disclosure.

[0058] In one embodiment of this disclosure, referring to FIG3, the lock flag signal generation circuit 111 includes: a first NAND gate 1111, the input of which receives a lock enable signal Lock En, a soft repair activation signal SPPR ACT, and a soft repair pulse signal SPPR Clk; a D flip-flop 1112, the input of which is electrically connected to the power supply VDD, the clock terminal of which is electrically connected to the output of the first NAND gate 1111, and the output of which is used to output the lock flag signal Lock flag; the latch control signal generation circuit 112 includes: a delay unit 1121, the input of which receives the soft repair pulse signal SPPR Clk; and a second NAND gate 1122, the first input of which receives the soft repair activation signal SPPR ACT. ACT, the second input terminal of the second NAND gate 1122 is electrically connected to the output terminal of the delay unit 1121; OR gate 1123, the first input terminal of OR gate 1123 is electrically connected to the output terminal of the D flip-flop 1112, the second input terminal of OR gate 1123 is electrically connected to the output terminal of the second NAND gate 1122, and the output terminal of OR gate 1123 is used to output the latch control signal SPPR Latch.

[0059] Here, referring to Figure 3, when both the Lock Enable signal Lock En and the Soft Repair Activation signal SPPR ACT are at active level (high level), in response to the positive pulse on the Soft Repair Pulse signal SPPR Clk, the first NAND gate 1111 outputs a negative pulse. The clock terminal CK of the D flip-flop 1112 responds to the rising edge of this negative pulse (i.e., the falling edge of the positive pulse on the Soft Repair Pulse signal SPPR Clk) and outputs the power supply voltage VDD (high level) of the input terminal D to the output terminal Q, that is, setting the Lock flag signal Lock flag to active level (high level). The Lock flag signal Lock flag becomes active level later than the falling edge of the positive pulse on the Soft Repair Pulse signal SPPR Clk. Meanwhile, in the latch control signal generation circuit 112, the delay unit 1121 can make the positive pulse on the pulse delay signal ClkD later than the positive pulse on the soft repair pulse signal SPPR Clk. At this time, the negative pulse signal output by the second NAND gate 1122 will also be later than the time when the lock flag signal Lock flag becomes active. This ensures that the active lock flag signal Lock flag can be shielded by the OR gate 1123 to block the negative pulse output by the second NAND gate 1122 (i.e., the positive pulse on the soft repair pulse signal SPPR Clk). That is, when the lock enable signal Lock En is active, the output latch control signal SPPR Latch can be controlled to not generate a pulse, but to maintain the first level (high level) latch state. This controls the soft repair address latch circuit 13 to maintain the current output latch address Latch FA[n:0] and controls the undo control circuit 12 to maintain the current output undo flag signal Undo flag, thus achieving the purpose of performing the soft repair lock operation.

[0060] In some embodiments of this disclosure, the reset terminal of the D flip-flop 1112 also receives a reset signal reset, and in response to the power-on reset signal reset, sets the output terminal to a low level, logic "0". The reset signal can be a power-on reset signal, or a disable reset signal generated when the HPPR, MBIST, or MPPR functions are enabled.

[0061] In one embodiment of this disclosure, referring to FIG4, the undo control circuit 12 includes: a first latch 121, the input terminal of the first latch 121 receiving an undo enable signal Undo En, and the control terminal of the first latch 121 receiving a latch control signal SPPR Latch; and an NOT gate 122, the input terminal of the NOT gate 122 being electrically connected to the output terminal of the first latch 121, and the output terminal of the NOT gate 122 being used to output an undo flag signal Undo flag.

[0062] Specifically, referring to Figures 3 and 4, when the latch control signal SPPR Latch is the inverted delayed signal of the soft repair pulse signal SPPR Clk, i.e., when the latch control signal SPPR Latch has a negative pulse, and the latch control signal SPPR Latch received by the control terminal Lat of the first latch 121 is at a low level, the first latch 121 is in a "transparent" state, transmitting the undo enable signal Undo En from the input terminal D to the output terminal Q. When the undo enable signal Undo En is at a valid level (high level), the signal output from the output terminal Q of the first latch 121 to the input terminal of the NOT gate 122 is at a high level, and the lock flag signal Undo flag output by the NOT gate 122 is at a valid level (low level). When the latch control signal SPPR Latch received by the control terminal Lat of the first latch 121 becomes high, the first latch 121 is in a "latch" state, locking the signal output from the output terminal Q at a high level, and the lock flag signal Undo flag output by the NOT gate 122... The flag remains at a valid level (low level); when the latch control signal SPPR Latch is locked to the first level (high level), the first latch 121 remains at its initial low level, and the lock flag signal Undo flag output by the NOT gate 122 remains at an invalid level (high level). Here, we will illustrate this by using the example where the valid level of the undo enable signal Undo En is high level and logic "1", and the valid level of the lock flag signal Undo flag is low level and logic "0".

[0063] In some embodiments of this disclosure, the first latch 121 may be a D latch, the reset terminal of the first latch 121 receives a reset signal reset, and in response to the reset signal reset, the output terminal is set to 0.

[0064] In one embodiment of this disclosure, referring to FIG5A, the soft repair address latch circuit 13 includes at least one sub-latch circuit 131, wherein one sub-latch circuit 131 serves as a target sub-latch circuit 132; the target sub-latch circuit 132 is configured to receive a latch control signal SPPR Latch and a soft repair failure address SPPR FA[n:0], and when the latch control signal SPPR Latch is locked at a first level, maintain the currently output latch address Latch FA[n:0] unchanged, and when the latch control signal SPPR Latch is an inverted delayed signal of the soft repair pulse signal SPPR Clk, latch the soft repair failure address SPPR FA[n:0] as latch address Latch FA[n:0] in response to the pulse on the latch control signal SPPR Latch.

[0065] In some embodiments of this disclosure, the soft repair address latch circuit 13 includes only one sub-latch circuit 131. In this case, it is not necessary to select the target sub-latch circuit 132. The one sub-latch circuit 131 can be used only for repairing SPPR after soft packaging, latching the corresponding soft repair failure address SPPR FA[n:0].

[0066] In some embodiments, the soft repair address latch circuit 13 includes multiple sub-latch circuits 131. In this case, it is necessary to select one sub-latch circuit 131 as the target sub-latch circuit 132. The target sub-latch circuit 132 can be selected in sequence to receive the latch control signal SPPR Latch and the soft repair failure address SPPR FA[n:0]. Alternatively, a selection circuit (not shown) can be set to control the selection circuit to enable one of the sub-latch circuits 131 as the target sub-latch circuit 132 according to the relevant configuration signal, and the latch control signal SPPR Latch and the soft repair failure address SPPR FA[n:0] are sent only to the enabled sub-latch circuit 131 (i.e. the target sub-latch circuit 132).

[0067] It should be noted that HPPR and SPPR can share multiple sub-latch circuits 131 in the soft repair address latch circuit 13 and the corresponding soft repair redundant row resources in the memory. Except for one sub-latch circuit 131 selected as the target sub-latch circuit 132, the remaining sub-latch circuits 131 can be used to perform hard-packaging repair of the latched hard repair failure address in HPPR.

[0068] In some embodiments of this disclosure, as shown in FIG5B, the soft repair address latch circuit 13 further includes a selector 133, configured to receive the soft repair failure address SPPR FA[n:0], and select only one sub-latch circuit 131 as the target sub-latch circuit 132 according to a preset order for each soft repair operation, and transmit the soft repair failure address SPPR FA[n:0] to the target sub-latch circuit 132; the target sub-latch circuit 132 is configured to receive the latch control signal SPPR Latch and the soft repair failure address SPPR FA[n:0], and when the latch control signal SPPR Latch is locked to the first level, keep the currently output latch address Latch FA[n:0] unchanged, and when the latch control signal SPPR Latch is the inverse delayed signal of the soft repair pulse signal SPPR Clk, latch the soft repair failure address SPPR FA[n:0] as the latch address Latch in response to the pulse on the latch control signal SPPR Latch. FA[n:0]; The unselected sub-latch circuit 131 failed to receive the soft repair failure address SPPR FA[n:0]. Although it received the latch control signal SPPR Latch, it still kept the original output latch address unchanged.

[0069] In some embodiments of this disclosure, the target sub-latch circuit 131 receives a reset signal reset and sets its output to 0 in response to the reset signal reset, that is, the latch address Latch FA[n:0] is 000…00. At this time, the address signal of all zeros is not used in the memory to identify the memory row.

[0070] In some embodiments of this disclosure, as shown in FIG5A, the soft repair address matching circuit 14 includes at least one sub-matching circuit 141, which is connected one-to-one with at least one sub-latch circuit 131. A sub-matching circuit connected to the target sub-latch circuit 132 is designated as the target sub-matching circuit 142. The target sub-matching circuit 142 is configured to receive an undo flag signal and a target address RA[n:0]. When the undo flag signal is at an active level, it locks the output soft repair matching signal SPPR Match to an inactive level. When the undo flag signal is at an inactive level, it matches the corresponding latch address Latch FA[n:0] with the target address RA[n:0] to generate and output a corresponding soft repair matching signal SPPR Match.

[0071] Here, the target address RA[n:0] is the address information corresponding to the access operation in normal operating mode. The target sub-matching circuit 142 and other sub-matching circuits 141 receive the target address RA[n:0] and perform matching on it, all of which are executed in normal operating mode. In some embodiments, the target sub-matching circuit 142 and other sub-matching circuits 141 are enabled in normal operating mode and disabled in soft repair mode and other repair modes, which can further save the power consumption of the memory in soft repair mode.

[0072] It should be noted that, apart from the target sub-matching circuit 142, the other sub-matching circuits 131 are connected to the corresponding sub-latch circuits 131. These sub-latch circuits 131 are not selected to latch the soft repair failure address SPPR FA[n:0] during the soft repair operation. Instead, they are used to latch other failure addresses during repair processes such as HPPR / MPPR. Therefore, these sub-matching circuits 131 are also used to receive the target address RA[n:0] and match the target address RA[n:0] with other failure addresses received to output a matching signal. However, this matching signal does not correspond to the soft repair redundant line. Instead, it is decoded by the line address decoding circuit and points to the redundant line corresponding to other repair operations such as HPPR / MPPR.

[0073] In some embodiments of this disclosure, as shown in FIG5B, the soft repair address matching circuit 14 includes at least one sub-matching circuit 141, which is connected to at least one sub-latch circuit 131 in a one-to-one correspondence. Each sub-matching circuit 141 is configured to receive an undo flag signal and a target address RA[n:0]. When the undo flag signal is at an active level, it locks the corresponding output soft repair matching signal SPPR Match to an inactive level. When the undo flag signal is at an inactive level, it matches the latch address Latch FA[n:0] output by the corresponding sub-latch circuit 131 with the target address RA[n:0] to generate and output a corresponding soft repair matching signal SPPR Match.

[0074] Here, all sub-latch circuits 131 are used for soft repair and latch a corresponding repair failure address. All sub-matching circuits 141 receive the target address RA[n:0] and match it with the soft repair failure address output by the corresponding sub-latch circuit 131, and output the corresponding soft repair matching signal to point to a corresponding soft repair redundant row. That is, each sub-matching circuit 141 corresponds to a soft repair redundant row. Specifically, referring to Figures 5B and 7, the soft repair address latch circuit 13 includes m sub-latch circuits 131, and the corresponding soft repair address matching circuit 14 also includes m sub-matching circuits 141, where m is an integer greater than or equal to 1. Each sub-latch circuit 131 corresponds to a soft repair redundant row in the memory bank BA. Specifically, the sub-matching circuit i receives the undo flag signal, the target address RA[n:0], and the latch address Latch FAi[n:0] (i.e., the latched soft repair failure address SPPR FAi[n:0], where i is an integer greater than or equal to 1 and less than or equal to m) output by a corresponding sub-latch circuit 131. When the undo flag signal is at an active level, the output soft repair matching signal SPPR Match i is locked to an inactive level. When the undo flag signal is at an inactive level, the latch address Latch FAi[n:0] is matched with the target address RA[n:0], and when the match is successful, the active soft repair matching signal SPPR Match i is released. i is sent to the row address decoding circuit 30, and the row address decoding circuit 30 links the target address RA[n:0] to the i-th soft repair redundant row corresponding to the soft repair matching signal SPPR Match i (sub-matching circuit i), that is, the failed storage row corresponding to the soft repair failure address SPPR FAi[n:0] is replaced with a soft repair redundant row, so as to achieve the purpose of soft repair of the failed storage row in the memory.

[0075] Furthermore, regarding the circuit structure of the target sub-latch circuit 132 and the target sub-matching circuit 142, as shown in Figure 6, the target sub-latch circuit 132 includes multiple second latches 1321, which correspond one-to-one with multiple first address signals in the soft repair failure address SPPR FA[n:0] and multiple second address signals in the latch address Latch FA[n:0]. The input terminal of the second latch 1321 receives a corresponding first address signal, the control terminal of the second latch 1321 receives the latch control signal SPPR Latch, and the output terminal of the second latch 1321 is used to output a corresponding second address signal.

[0076] Here, the multiple second latches 1321 in the target sub-latch circuit 132 latch bit by bit the input soft-repair failure address SPPR FA[n:0] under the control of the latch control signal SPPR Latch. Specifically, the input terminal D of the j-th second latch 1321 receives the j-th first address signal SPPR FA[j-1], where j is a positive integer less than or equal to n+1. The control terminal Lat of the j-th second latch 1321 receives the latch control signal SPPR Latch. When the latch control signal SPPR Latch is low (logic "0"), the j-th first address signal SPPR FA[j-1] received at the input terminal D is "passed through" to the output terminal Q as the j-th second address signal Latch FA[j-1]. When the latch control signal SPPR Latch is high (logic "1"), the j-th second address signal Latch FA[j-1] at the output terminal Q is latched.

[0077] In some embodiments of this disclosure, the second latch 1321 may be a D latch, the reset terminal of the second latch 1321 receives a reset signal reset, and in response to the reset signal reset, sets the output terminal to 0.

[0078] Referring again to Figure 6, the target sub-matching circuit 142 includes multiple XOR gates 1421 and AND gates 1422. The multiple XOR gates 1421 correspond one-to-one with multiple second latches 1321 and multiple third address signals in the target address RA[n:0]. The first input of the XOR gate 1421 receives a corresponding third address signal, and the second input of the XOR gate 1421 is electrically connected to the output of a corresponding second latch 1321. One input of the AND gate 1422 receives the undo flag signal, and the other inputs of the AND gate 1422 are electrically connected one-to-one with the outputs of the multiple XOR gates 1421. The output of the AND gate 1422 is used to output the soft repair matching signal SPPR Match.

[0079] Here, the multiple XOR gates 1421 in the target sub-matching circuit 142 are used to perform bit-by-bit comparison and matching of the Latch FA[n:0] output by the multiple second latches 1321 and the target address RA[n:0]. The AND gate 1422 outputs a valid soft-repair match signal SPPR Match when the comparison result indicates that all address bits are the same. Specifically, the input of the j-th XOR gate 1421 receives the j-th second address signal Latch FA[j-1] and the j-th third address signal RA[j-1] output by the i-th second latch 1321, respectively. When the second address signal Latch FA[j-1] and the third address signal RA[j-1] are the same, the j-th XOR gate 1421 outputs a high-level comparison result RA com[j-1]. If all comparison results RA com[n:0] of multiple XOR gates 1421 are high and the undo flag signal is invalid (high level), the AND gate 1422 outputs a valid soft-repair match signal SPPR Match, indicating a successful match. However, when the undo flag signal received by the AND gate 1422 is valid (low level), regardless of the comparison results RA com[n:0] of multiple XOR gates 1421, the AND gate 1422 outputs an invalid soft-repair match signal SPPR. Match indicates that a match was not successful, thus enabling the soft repair undo function.

[0080] In some embodiments of this disclosure, as shown in FIG1, the locking control circuit 11 is further configured to reset the latch control signal SPPR Latch in response to the reset signal Reset; the undo control circuit 12 is further configured to reset the undo flag signal Undo flag to an invalid level in response to the reset signal Reset; and the soft repair address latch circuit 13 is further configured to reset the latch address Latch FA[n:0] in response to the reset signal Reset.

[0081] Here, in response to the reset signal Reset, the lock control circuit 11, the undo control circuit 12, and the soft repair address latch circuit 13 are all restored to their initial unrepaired state. Specifically, the lock control circuit 11 resets the lock flag signal to an invalid level, and the corresponding latch control signal SPPR Latch is reset to the second level; the undo control circuit 12 resets the undo flag signal to an invalid level, and the soft repair address latch circuit 13 resets all latch addresses Latch FA[n:0] to the second level. Here, we will use the example of the first level being high and logic "1", the second level being low and logic "0", the valid level being high and logic "1", and the invalid level being low and logic "0" for explanation.

[0082] It should be noted that the reset signal Reset can be a power-on reset signal or a disable reset signal generated when HPPR, MBIST (Memory Built-in Self-Test), or MPPR (MBIST Post Package Repair) functions are enabled. In some embodiments, HPPR and SPPR share the soft repair address latch circuit 13 and the corresponding soft repair redundant row resources in the memory bank, and HPPR and SPPR functions cannot be enabled simultaneously. Therefore, if the DRAM supports the optional SPPR undo / lock function, SPPR must be disabled, cleared, and unlocked before entering HPPR or MPPR modes. At this time, a disable reset signal is required to reset the lock control circuit 11, the undo control circuit 12, and the soft repair address latch circuit 13.

[0083] It should also be noted that the features disclosed in the soft repair control circuit provided in the above embodiments can be arbitrarily combined without conflict to obtain new soft repair control circuit embodiments.

[0084] This disclosure also provides a memory, referring to FIG7, the memory 100, including a command decoding circuit 20 and a soft repair control circuit 10 as provided in the above embodiments; the command decoding circuit 20 is configured to receive a soft repair command SPPR CMD, and when the soft repair mode parameter in the soft repair command SPPR CMD is a second preset value, generate an undo enable signal Undo En at an effective level, and when the soft repair mode parameter in the soft repair command SPPR CMD is a third preset value, generate a lock enable signal Lock En at an effective level; the soft repair control circuit 10 is further configured to receive the undo enable signal Undo En and the lock enable signal Lock En, and when the undo enable signal Undo En is at an effective level, control the execution of a soft repair undo operation, and when the lock enable signal Lock En is at an effective level, control the execution of a soft repair lock operation.

[0085] Here, the soft repair command SPPR CMD can be a Mode Register Write (MRW) command. That is, the command decoding circuit 20 writes the soft repair mode parameters carried in the Mode Register Write command MRW into the corresponding mode register MR23, for example, writes it into MR23:OP[2:1], and generates and outputs the corresponding signal according to the soft repair mode parameters stored in the mode register MR23. Specifically, when the soft repair mode parameter MR23:OP[2:1] is the first preset value 01, a soft repair enable signal SPPR En at an active level is generated, which can indicate entering the soft repair mode to perform a regular soft repair write operation; when the soft repair mode parameter MR23:OP[2:1] is the second preset value 10, an undo enable signal Undo En at an active level is generated, which can indicate performing a soft repair undo operation; when the soft repair mode parameter MR23:OP[2:1] is the third preset value 11, a lock enable signal Lock En at an active level is generated, which can indicate performing a soft repair lock operation; when the soft repair mode parameter MR23:OP[2:1] is the fourth preset value 00 (the default initial value), the output soft repair enable signal SPPR En, undo enable signal Undo En, and lock enable signal Lock En are all set to an inactive level.

[0086] It should be noted that the embodiments of this disclosure use the effective level of the soft repair enable signal SPPR En, the undo enable signal Undo En, and the lock enable signal Lock En as high level and logic "1", and the invalid level as low level and logic "0" for illustrative purposes, but this does not constitute a specific limitation on the embodiments of this disclosure.

[0087] It should also be noted that the command decoding circuit 20 in this disclosure can be applied to the decoding operation of executing soft repair commands, as well as the decoding operation of access commands in normal working mode and other repair commands. In some other embodiments, the command decoding circuit 20 is only applied to the decoding operation of executing soft repair commands, and the decoding circuits for executing access commands in normal working mode and other repair commands are all set independently.

[0088] In some embodiments of this disclosure, as shown in FIG7, the command decoding circuit 20 is further configured to generate a soft repair enable signal SPPR En at an effective level when the soft repair mode parameter in the soft repair command SPPR CMD is a first preset value; wherein, when the soft repair enable signal SPPR En is at an effective level, it indicates that the memory 100 enters the soft repair mode; the command decoding circuit 20 is further configured to, after the memory 100 enters the soft repair mode, sequentially receive the activation command ACT CMD and the write command WRITE CMD, and decode the activation command ACT CMD to generate and output the soft repair activation signal SPPR ACT and the soft repair failure address SPPR FA[n:0], and decode the write command WRITE CMD to generate and output the soft repair pulse signal SPPR Clk; wherein, when the address information carried in the activation command ACT CMD indicates the memory bank 40 corresponding to the soft repair control circuit 10, the soft repair activation signal SPPR is generated at an effective level. ACT, and send it to the soft repair control circuit 10; the soft repair control circuit 10 is electrically connected to the command decoding circuit 20, and is configured to receive the soft repair activation signal SPPR ACT, the soft repair failure address SPPR FA[n:0] and the soft repair pulse signal SPPR Clk, and when the soft repair activation signal SPPR ACT is at an active level, latch the soft repair failure address SPPR FA[n:0] as the latch address Latch FA[n:0] according to the soft repair pulse signal SPPR Clk.

[0089] Here, the address information in the activation command ACT CMD includes bank group (BG) information and bank (BA) information. After the soft repair enable signal SPPR En, which is at an active level, instructs the memory 100 to enter the soft repair mode, the command decoding circuit 20 can decode the received activation command ACT CMD and send a valid soft repair activation signal SPPR ACT and a soft repair failure address SPPR FA[n:0] only to the bank indicated by the BG / BA information, so as to instruct to perform a soft repair write operation on the failure address SPPR FA[n:0] of the target bank.

[0090] It should be noted that when the soft repair mode parameter MR23:OP[2:1] in the soft repair command SPPR CMD is the first preset value 01, the second preset value 10, or the third preset value 11, it can instruct the memory 100 to enter the soft repair mode. However, the soft repair operation performed by the three soft repair mode parameters is different. Specifically, when the soft repair mode parameter MR23:OP[2:1] is the first preset value 01, it indicates entering the soft repair mode and performing a regular soft repair write operation. The soft repair write operation writes the soft repair failure address SPPR FA[n:0] in the subsequently received activation command into the soft repair address latch circuit. When the soft repair mode parameter MR23:OP[2:1] is the second preset value 10, it indicates entering the soft repair mode and performing a soft repair cancellation operation. When the soft repair mode parameter MR23:OP[2:1] is the third preset value 11, it indicates entering the soft repair mode and performing a soft repair lock operation. In some embodiments, when the soft repair mode parameter MR23:OP[2:1] is a second preset value 10 or a third preset value 11, in addition to generating the corresponding undo enable signal Undo En and lock enable signal Lock En, a soft repair enable signal SPPR En will also be generated to indicate entering the soft repair mode, so as to enable the activation command decoder 24 and the write command decoder 25, and perform a "normal" soft repair write operation according to the subsequently received activation command ACT CMD and write command WRITE CMD. However, the undo enable signal Undo En and the lock enable signal Lock En will control the execution of the soft repair undo operation and soft repair lock operation with higher priority, and ignore / mask the soft repair write operation corresponding to the soft repair enable signal SPPR En.In some other embodiments, when the soft repair mode parameter MR23:OP[2:1] is the second preset value 10 or the third preset value 11, only the corresponding undo enable signal Undo En and lock enable signal Lock En are generated, and the soft repair enable signal SPPR En is not generated. At this time, the undo enable signal Undo En and the lock enable signal Lock En will also indicate the decoding of the subsequently received activation command ACT CMD and write command WRITE CMD. However, the soft repair write operation is not performed. Instead, the memory group BG / memory BA information in ACT CMD is used to send a soft repair activation signal SPPR Act at an effective level to the target memory, enabling the corresponding target memory to perform the soft repair undo operation and the soft repair lock operation. At this time, the row address information in the activation command ACT CMD and the column address information in the write command WRITE CMD can be ignored. Alternatively, the row address information in the current activation command ACT CMD can be compared with the activation command ACT when the soft repair mode was entered last time. The row address information in CMD (e.g., the soft repair failure address SPPR FA[n:0] in a regular soft repair write operation when the soft repair mode parameter MR23:OP[2:1] is the first preset value 01) is set to the same.

[0091] It should also be noted that after receiving the SPPR CMD command indicating entry into soft repair mode, four consecutive MRW commands are required. These MRW commands carry protection key information to prevent accidental soft repair operations, thus protecting the data in the storage and the repair resources. Specifically, the protection key information carried in the four MRW commands must be entered in a prescribed order, and other MRW / R commands or non-MR commands (such as ACT, WR, RD) are not allowed to interrupt the protection key sequence before truly entering soft repair mode and executing specific soft repair operations (such as soft repair write operations, soft repair undo operations, and soft repair lock operations). If the operation is interrupted by an invalid command or the protection key is not entered in the required order, soft repair mode will not be entered and soft repair operations will not be executed.

[0092] In some embodiments of this disclosure, referring again to FIG7, the memory 100 includes a plurality of memory banks 40 (marked by dashed boxes in the figure), and in some parts of the memory, the plurality of memory banks BA are further divided into a memory bank group BG. Each memory bank BA corresponds to a soft repair control circuit 10 and a soft repair activation signal SPPR ACT, and the soft repair operation is performed independently according to the corresponding soft repair control circuit 10. However, each soft repair command specifies which memory bank 40's failed address to perform the soft repair operation, which needs to be specified by enabling the corresponding soft repair activation signal SPPR ACT according to the memory bank address information (including the memory bank group BG signal and the memory bank BA signal) in the activation command ACT CMD. Specifically, taking the memory 100 comprising eight memory bank groups BG0-BG7 and each memory bank group comprising four memory banks BA0-BA3 as an example, the 32 memory banks correspond to 32 soft repair control circuits and 32 soft repair activation signals SPPR ACT. When BG[2:0] = 000 and BA[1:0] = 00 in the received activation command ACT CMD, it indicates that BA0 in BG0 is performing the current soft repair write operation. The soft repair activation signal SPPR ACT corresponding to this memory bank is set to an active level and sent to the soft repair control circuit 10 corresponding to BG0-BA0 to instruct various soft repair operations to be performed according to the undo enable signal Undo En, the lock enable signal Lock En, the soft repair failure address SPPR FA[n:0], and the soft repair pulse signal SPPR Clk. At this time, the 31 soft repair activation signals SPPR ACT corresponding to the remaining 31 memory banks are all at an inactive level, and the corresponding soft repair control circuits are not enabled, so no soft repair operation is performed.

[0093] In some embodiments of this disclosure, as shown in Figures 7 and 9, the memory 100 further includes: a row address decoding circuit 30 and a memory bank 40; a command decoding circuit 20, further configured to generate a soft repair enable signal SPPR En at an invalid level to indicate that the memory 100 enters a normal operating mode when the soft repair mode parameter in the soft repair command SPPR CMD is a fourth preset value; the command decoding circuit 20, further configured to receive an activation command ACT CMD and decode the activation command ACT CMD to generate and output a target address RA[n:0] when the memory 100 is in a normal operating mode; a soft repair control circuit 10, further configured to match the target address RA[n:0] with the latch address Latch FA[n:0] when the memory 100 is in a normal operating mode, and generate and output a soft repair match signal SPPR Match at an effective level when the target address RA[n:0] and the latch address Latch FA[n:0] are successfully matched; and a row address decoding circuit 30, electrically connected to the soft repair control circuit 10, is configured to receive the soft repair match signal SPPR. Match and target address RA[n:0], and when the soft repair match signal SPPR Match is at an active level, control the word line of the corresponding soft repair redundant row SPPR RWL in memory bank 100 to be enabled according to the active level of the soft repair match signal SPPR Match.

[0094] Here, we illustrate the example by having only one sub-latch circuit 131 in each soft repair control circuit 10 for latching soft repair failure addresses, and only one corresponding soft repair redundant row in the memory bank 40. In some other embodiments, the soft repair control circuit 10 may have multiple sub-latch circuits 131 for latching soft repair failure addresses, and the memory bank 40 may also have multiple corresponding soft repair redundant rows; however, this is not specifically limited here.

[0095] It should be noted that when the soft repair mode parameter MR23:OP[2:1] in the soft repair command SPPR CMD is the fourth preset value 00, it indicates exiting the soft repair mode, that is, entering the normal working mode. Not only do we need to set the soft repair enable signal SPPR En to an invalid level, but we also need to set the undo enable signal Undo En and the lock enable signal Lock En to an invalid level.

[0096] In some embodiments of this disclosure, as shown in FIG8, the command decoding circuit 20 includes: a soft repair command decoder 21, a mode register 22, a soft repair signal generation circuit 23, an activation command decoder 24, and a write command decoder 25; the soft repair command decoder 21 is configured to receive the soft repair command SPPR CMD and write the soft repair mode parameter MR23:OP[2:1] in the soft repair command SPPR CMD into the mode register 22; the soft repair signal generation circuit 23 is configured to receive the soft repair mode parameter MR23:OP[2:1] stored in the mode register 22, and generate a soft repair enable signal SPPR En at an effective level when the soft repair mode parameter MR23:OP[2:1] is a first preset value, generate an undo enable signal Undo En at an effective level when the soft repair mode parameter MR23:OP[2:1] is a second preset value, and generate a lock enable signal Lock at an effective level when the soft repair mode parameter MR23:OP[2:1] is a third preset value. En; Activation command decoder 24, configured to receive the soft repair enable signal SPPR En and the activation command ACT CMD, and when the soft repair enable signal SPPR En at an active level indicates that the memory has entered the soft repair mode, decode the activation command ACT CMD to generate and output the soft repair activation signal SPPR ACT and the soft repair failure address SPPR FA[n:0]; Write command decoder 25, configured to receive the soft repair enable signal SPPR En and the write command WRITE CMD, and when the soft repair enable signal SPPR En at an active level indicates that the memory 100 has entered the soft repair mode, decode the write command WRITE CMD to generate and output the soft repair pulse signal SPPR Clk.

[0097] Here, the activation command decoder 24 is only used to decode the activation command ACT CMD after entering the soft repair mode. The activation command ACT CMD received when the memory 100 is in normal working mode can be decoded by the normal activation command decoder (not shown in the figure) set in the command decoding circuit 20. Both the activation command decoder 24 and the normal activation command decoder receive the activation command ACT CMD. When the soft repair enable signal SPPR En is at an active level indicating that the memory 100 has entered the soft repair mode, the activation command decoder 24 is enabled while the normal activation command decoder is disabled to ensure that only the soft repair activation signal SPPR ACT is output. When the soft repair enable signal SPPR En is at an inactive level indicating that the memory 100 has entered the normal working mode, the normal activation command decoder is enabled while the activation command decoder 24 is disabled to ensure that only the normal activation signal ACT and the target address RA[n:0] are output.

[0098] In some embodiments of this disclosure, as shown in Figures 7 and 9, the memory 100 further includes: a fuse address matching circuit 50, configured to receive multiple standard failure addresses Normal FA[n:0] from a fuse array (not shown in the figures), and match the received target address RA[n:0] with the multiple standard failure addresses Normal FA[n:0] respectively, and generate multiple standard matching signals Normal March 1-p according to the matching results; a row address decoding circuit 30 is further configured to receive multiple standard matching signals Normal March 1-p, and when any standard matching signal is at an active level, control the activation of the word line of the corresponding standard redundant row Normal RWL 1-p in the memory bank 40 according to the active level standard matching signal.

[0099] In some embodiments of this disclosure, as shown in Figures 7 and 9, the row address decoding circuit 30 is further configured to control the enabling of the word line of the corresponding storage row Normal WL 1-q in the memory bank 40 according to the target address RA[n:0] when both the soft repair match signal SPPR Match and the standard match signal Normal March 1-p are at an invalid level.

[0100] Figures 10 and 11 are signal timing diagrams corresponding to the soft repair control circuit and memory provided in the embodiments of this disclosure. The working principle of the soft repair control circuit 10 and memory 100 shown in Figures 1-9 will be explained with reference to Figures 10-11. Here, the explanation is based on the example where the effective levels of the soft repair enable signal SPPR En, lock enable signal Lock En, undo enable signal Undo En, lock flag signal Lock Flag, soft repair activation signal SPPR ACT, and soft repair matching signal SPPR Match are high (logic "1"), the effective level of the undo flag signal Undo flag can be low (logic "0"), and the first level is high (logic "1"), but this does not constitute a limitation on the embodiments of this disclosure.

[0101] First, referring to Figure 10, at time t1, the soft repair command decoder 21 receives the soft repair command SPPR CMD and writes the soft repair mode parameter OP[2:1] = 01 in the soft repair command SPPR CMD to the mode register MR23; since the soft repair mode parameter OP[2:1] is the first preset value 01, the soft repair signal generation circuit 23 generates a soft repair enable signal SPPR En at an effective level (high level), indicating that the memory 100 enters the soft repair mode. Based on the effective level (high level) soft repair enable signal SPPR En, the activation command decoder 24 and the write command decoder 25 are enabled.

[0102] Between time t1 and t2, memory 100 also needs to receive four consecutive MRW commands. After verifying that the protection key information carried in the four consecutive MRW commands is correct, it formally enters the soft repair mode to perform the soft repair operation. In some embodiments, after verifying that the protection key information in the four consecutive MRW commands is correct, a soft repair enable signal SPPR En at an active level (high level) can be generated.

[0103] At time t2, the activation command decoder 24 receives the activation command ACT CMD. Since the effective level (high level) soft repair enable signal SPPR En has enabled the activation command decoder 24, the activation command decoder 24 can decode the activation command ACT CMD to generate and output the soft repair activation signal SPPR ACT and the soft repair failure address SPPR FA[n:0]. Specifically, the memory bank to be soft repaired is determined according to the address information (BG / BA) in the activation command ACT CMD, and the soft repair activation signal SPPR ACT corresponding to memory bank BG0 / BA0 is set to the effective level (high level) and sent to the corresponding soft repair control circuit 10. In addition, the row address information carried in the activation command ACT CMD is determined as the soft repair failure address FA1[n:0].

[0104] At time t3, the write command decoder 25 receives the write command WRITE CMD. Since the effective level (high level) soft repair enable signal SPPR En has enabled the write command decoder 25, the write command decoder 25 can decode the write command WRITE CMD to generate and output a soft repair pulse signal SPPR Clk with a positive pulse.

[0105] It should be noted that in soft repair mode, there is no need to latch the column address; therefore, the column address information in the WRITE CMD command can be ignored.

[0106] At time t4, the delay unit 1121 in the soft repair control circuit 10 delays the soft repair pulse signal SPPR Clk to generate a pulse delay signal ClkD. The positive pulse at time t3 on the soft repair pulse signal SPPR Clk is delayed to the positive pulse at time t4 on the pulse delay signal ClkD. At this time, the lock enable signal Lock En received at the input of the first NAND gate 1111 is at an invalid level (low level), the clock terminal of the D flip-flop 1112 remains at a high level, the lock flag signal Lock flag output by the D flip-flop 1112 remains at the initial invalid level (low level), the latch control signal SPPR Latch output by the OR gate 1123 is equal to the output of the second NAND gate 1122, the soft repair activation signal SPPR ACT received by the second NAND gate 1122 has been set to a high level at time t2, the output of the second NAND gate 1122 is opposite to the pulse delay signal ClkD, and the latch control signal SPPR Latch generates a negative pulse at time t4 corresponding to the positive pulse on the pulse delay signal ClkD.

[0107] Meanwhile, the input terminals D of the multiple second latches 1321 in the soft repair control circuit 10 receive the soft repair failure address SPPR FA[n:0] before time t4. The control terminals Lat of the multiple second latches 1321 "pass through" the received soft repair failure address FA1[n:0] to the output terminal Q as the latch address Latch FA[n:0] according to the negative pulse (low level) generated by the latch control signal SPPR Latch at time t4. When the negative pulse of the latch control signal SPPR Latch ends (becomes high level), it switches to the latching state and latches the output FA1[n:0] as the latch address.

[0108] At time t5, the precharge command PRE CMD sent by the memory controller is received. Based on the precharge command PRE CMD, the soft repair activation signal SPPR Act is set to an invalid level (low level).

[0109] At time t6, the soft repair command decoder 21 in the command decoding circuit 20 receives the soft repair command SPPR CMD. At this time, the soft repair mode parameter OP[2:1] in the soft repair command SPPR CMD is the fourth preset value 00. The soft repair signal generation circuit 23 flips the soft repair enable signal SPPR En from the effective level (high level) to the ineffective level (low level) to indicate that the memory 100 exits the current soft repair mode (t1-t6), that is, enters the normal working mode.

[0110] At time t7, the soft repair command decoder 21 receives a new soft repair command SPPR CMD. At this time, the soft repair mode parameter OP[2:1] in the soft repair command SPPR CMD is the second preset value 10. The soft repair signal generation circuit 23 generates an undo enable signal Undo En at an active level (high level) and a soft repair enable signal SPPR En at an active level (high level), instructing the memory 100 to enter the soft repair mode and perform a soft repair undo operation. Based on the active level (high level) soft repair enable signal SPPR En, the activation command decoder 24 and the write command decoder 25 are also enabled.

[0111] At time t8, the activation command decoder 24 receives the activation command ACT CMD. The enabled activation command decoder 24 determines the memory bank to perform the soft repair based on the address information (BG / BA) in the activation command ACT CMD, sets the soft repair activation signal SPPR ACT corresponding to memory bank BG0 / BA0 to an active level (high level), and sends it to the corresponding soft repair control circuit 10. In addition, the row address information carried in the activation command ACT CMD is determined as the soft repair failure address FA1[n:0].

[0112] It should be noted that after the soft repair command SPPR CMD (carrying the soft repair mode parameter OP[2:1] which instructs the execution of soft repair undo and soft repair lock operations, the address information (BG / BA / SPPR FA[n:0]) carried in the activation command ACT CMD must be the same as the address information carried in the activation command ACT CMD (at time t2) after the most recent soft repair command SPPR CMD (carrying the soft repair mode parameter OP[2:1] which instructs the execution of soft repair write operations, which carries the first preset value 00);

[0113] At time t9, the write command decoder 25 receives the write command WRITE CMD. The enabled write command decoder 25 can decode the write command WRITE CMD to generate and output a soft repair pulse signal SPPR Clk with a positive pulse.

[0114] At time t10, the delay unit 1121 in the soft repair control circuit 10 performs delay processing on the soft repair pulse signal SPPR Clk to generate a pulse delay signal ClkD. The positive pulse at time t9 on the soft repair pulse signal SPPR Clk is delayed to the positive pulse at time t10 on the pulse delay signal ClkD. The latch control signal SPPR Latch generates a negative pulse at time t10 that corresponds to the positive pulse on the pulse delay signal ClkD.

[0115] Meanwhile, the undo enable signal Undo En received at the input of the first latch 121 in the undo control circuit 12 has been set to an effective level (high level) at time t7. The control terminal Lat of the first latch 121, according to the negative pulse (low level) generated by the latch control signal SPPR Latch at time t10, "passes through" the high level signal of the input terminal D to the output terminal Q, and switches to the latch state when the negative pulse of the latch control signal SPPR Latch ends (becomes high level), latching the output terminal Q to a high level (logic "1"). The corresponding undo flag signal Undo Flag is locked at a low level (logic "0"). The multiple second latches 1321 in the soft repair control circuit 10 also switch to the latch state when the negative pulse of the latch control signal SPPR Latch ends, latching FA1[n:0] as the latch address.

[0116] At time t11, according to the received precharge command PRE CMD, the soft repair activation signal SPPR Act is set to an invalid level (low level);

[0117] At time t12, according to the soft repair mode parameter OP[2:1] of the fourth preset value carried in the soft repair command SPPR CMD, the soft repair signal generation circuit 23 flips the soft repair enable signal SPPR En from an active level (high level) to an inactive level (low level) to instruct the memory 100 to exit the current soft repair mode (t7-t12).

[0118] At time t13, the soft repair enable signal SPPR En is at an invalid level, indicating that the memory 100 is in normal working mode. The activation command ACT CMD received by the memory 100 at this time indicates to perform a normal access operation (read / write activation operation). The memory 100 decodes the activation command ACT CMD and obtains the target address RA[n:0], which is the row address FA1[n:0] corresponding to the current access operation. Multiple XOR gates 1421 in the target sub-matching circuit 142 compare the target address RA[n:0] with the latch address Lock FA[n:0] bit by bit. Since the target address RA[n:0] and the latch address Lock FA[n:0] are both row addresses FA1[n:0], the comparison results RA com[0]-RA com[n] output by multiple XOR gates 1421 are all high level.

[0119] However, since the Undo Flag signal was set to an active level (low level) at the previous time t10, and no new soft repair command SPPR CMD was modified during t12-t13, the Undo Flag signal remained at a low level. At this time, even if the comparison result RA com[0]-RA com[n] indicates that the latch address Lock FA[n:0] of the soft repair is successfully matched with the target address RA[n:0], AND gate 1422 will also output an invalid (low level) soft repair match signal SPPR Match, indicating that the match was unsuccessful, thus realizing the soft repair undo function.

[0120] Continuing, referring to Figure 11, the timing sequence during t21-t26 is the same as the timing sequence during t1-t6 in Figure 10. For details, please refer to the above content, which will not be repeated here.

[0121] At time t27, the soft repair command decoder 21 receives a new soft repair command SPPR CMD. At this time, the soft repair mode parameter OP[2:1] in the soft repair command SPPR CMD is the third preset value 11. The soft repair signal generation circuit 23 generates a lock enable signal Lock En at an effective level (high level) and a soft repair enable signal SPPR En at an effective level (high level), instructing the memory 100 to enter the soft repair mode and perform a soft repair undo operation. Based on the soft repair enable signal SPPR En at an effective level (high level), the activation command decoder 24 and the write command decoder 25 are also enabled.

[0122] At time t28, the activation command decoder 24 receives the activation command ACT CMD. The enabled activation command decoder 24 determines the memory bank to perform the soft repair based on the address information (BG / BA) in the activation command ACT CMD, sets the soft repair activation signal SPPR ACT corresponding to memory bank BG0 / BA0 to an active level (high level), and sends it to the corresponding soft repair control circuit 10. In addition, the row address information carried in the activation command ACT CMD is determined as the soft repair failure address FA1[n:0].

[0123] At time t29, the write command decoder 25 receives the write command WRITE CMD. The enabled write command decoder 25 can decode the write command WRITE CMD to generate and output a soft repair pulse signal SPPR Clk with a positive pulse.

[0124] During the time interval t29-t30, the Lock En signal and the SPPR ACT signal received at the input of the first NAND gate 1111 are both at an active level. The output signal of the first NAND gate 1111 is opposite to the SPPR Clk signal of the soft repair pulse. That is, the first NAND gate 1111 outputs a negative pulse CK to the clock terminal of the D flip-flop 1112, which corresponds to the positive pulse on the SPPR Clk signal of the soft repair pulse.

[0125] At time t30, the clock input CK of the D flip-flop 1112 responds to the rising edge of the negative pulse (i.e., the falling edge of the positive pulse on the soft repair pulse signal SPPR Clk), and outputs the power supply voltage VDD (high level) of the input D to the output Q, that is, sets the lock flag signal to an active level (high level).

[0126] Subsequently, the positive pulse of the soft repair pulse signal SPPR Clk at time t29 is delayed to a positive pulse on the pulse delay signal ClkD, arriving later than time t30. However, since the lock flag signal is already at an effective level (high level), the latch control signal SPPR Latch output by the OR gate 1123 maintains the first level (high level) latch state, which shields / filters out the negative pulse (i.e. the positive pulse on the soft repair pulse signal SPPR Clk) output by the second NAND gate 1122. The target sub-latch circuit 132 keeps the currently output latch address Latch FA[n:0] unchanged.

[0127] At time t31, according to the received precharge command PRE CMD, the soft repair activation signal SPPR Act is set to an invalid level (low level);

[0128] At time t32, according to the soft repair mode parameter OP[2:1] of the fourth preset value carried in the soft repair command SPPR CMD, the soft repair signal generation circuit 23 flips the soft repair enable signal SPPR En from the effective level (high level) to the invalid level (low level) to indicate that the memory 100 exits the current soft repair mode (t27-t32).

[0129] At time t33, after the memory 100 receives the soft repair command SPPR CMD and re-enters the soft repair mode, the activation command decoder 24 receives the activation command ACT CMD. The enabled activation command decoder 24 determines the memory bank to perform the soft repair based on the address information (BG / BA) in the activation command ACT CMD, sets the soft repair activation signal SPPR ACT corresponding to memory bank BG0 / BA0 to an effective level (high level), and sends it to the corresponding soft repair control circuit 10. In addition, the row address information carried in the activation command ACT CMD is determined as the new soft repair failure address FA2[n:0].

[0130] At time t34, the enabled write command decoder 25 receives the write command WRITE CMD. The enabled write command decoder 25 can decode the write command WRITE CMD to generate and output a soft repair pulse signal SPPR Clk with a positive pulse. However, since the lock flag signal is set to an active level (high level) at time t30 and remains at a high level until the reset signal Reset (power-on reset signal) arrives, the OR gate 1123 will still shield the positive pulse at time t34 on the soft repair pulse signal SPPR Clk and continue to maintain the output latch control signal SPPR Latch in the latch state at the first level (high level). The target sub-latch circuit 132 keeps the current latch address FA1[n:0] unchanged based on the latch control signal SPPR Latch which is maintained at a high level, and no longer "passes through" and locks the newly input soft repair failure address FA2[n:0], that is, realizes the soft repair locking function.

[0131] It should be noted that the features disclosed in the memory provided in the above embodiments can be arbitrarily combined without conflict to obtain new memory embodiments. Furthermore, the technical details of the soft repair control circuit mentioned in the previous embodiments remain valid in this embodiment, and will not be repeated here to avoid repetition.

[0132] This disclosure also provides a method for repairing a memory. Referring to FIG12, the method for repairing a memory includes:

[0133] Step S1: Receive the soft repair command SPPR CMD and decode the soft repair command SPPR CMD;

[0134] Step S2: Determine the value of the soft repair mode parameter MR23:OP[2:1] in the soft repair command SPPR CMD;

[0135] When the soft repair mode parameter is the second preset value, execute steps S32 and S42;

[0136] Step S32: Generate an undo enable signal Undo En at an active level to indicate the execution of a soft repair undo operation;

[0137] Step S42: In response to the Undo En signal being at an active level, lock the soft repair match signal SPPR Match to an inactive level;

[0138] When the soft repair mode parameter is the third preset value, execute steps S33 and S43;

[0139] Step S33: Generate a lock enable signal Lock En at an active level to indicate the execution of a soft repair lock operation;

[0140] Step S43: In response to the Lock En signal which is at an active level, keep the currently latched soft repair failure address SPPR FA[n:0] unchanged and mask the Undo En signal;

[0141] When the soft repair matching signal SPPR Match is at an invalid level, it indicates that the target address RA[n:0] and the latched soft repair failure address SPPR FA[n:0] have not matched successfully. The target address RA[n:0] is the address corresponding to the access operation in normal working mode.

[0142] In some embodiments of this disclosure, referring further to FIG12, the repair method further includes:

[0143] When the soft repair mode parameters are at the first preset value, step S31 is executed;

[0144] Step S31: Generate a soft repair enable signal SPPR En at an active level to indicate entry into soft repair mode;

[0145] After the memory enters the soft repair mode, it receives the activation command ACT CMD and the write command WRITE CMD in sequence, and continues to execute steps S41, S5 and S6.

[0146] Step S41: Receive the activation command ACT CMD and decode the activation command ACT CMD to generate the soft repair activation signal SPPR ACT and the soft repair failure address SPPR FA[n:0];

[0147] Step S5: Receive the write command WRITE CMD and decode the write command WRITE CMD to generate the soft repair pulse signal SPPR Clk;

[0148] Step S6: In response to the soft repair activation signal SPPR ACT at an active level, latch the soft repair failure address SPPR FA[n:0] as latch address Latch FA[n:0] according to the soft repair pulse signal SPPR Clk.

[0149] In some embodiments of this disclosure, the repair method further includes:

[0150] When the soft repair mode parameter is the fourth preset value, a soft repair enable signal SPPR En at an invalid level is generated to indicate that the memory enters the normal operation mode.

[0151] When the memory is in normal working mode, it receives the activation command ACT CMD, decodes the activation command ACT CMD, and generates the target address RA[n:0].

[0152] Match the target address RA[n:0] with the latched soft repair failure address SPPR FA[n:0], and generate a soft repair match signal SPPR Match at an active level when the match is successful;

[0153] The soft-repair match signal SPPR Match, which is at an active level, controls the activation of the word line of the corresponding soft-repair redundant row in the memory bank.

[0154] It should be noted that the features disclosed in the memory repair method provided in the above embodiments can be arbitrarily combined without conflict to obtain new repair method embodiments. Furthermore, this embodiment can be implemented in conjunction with the memory and soft repair control circuit provided in the previous embodiments. The relevant technical details mentioned in the previous embodiments remain valid in this embodiment, and will not be repeated here to reduce repetition.

[0155] The above description is merely an example embodiment of this disclosure and is not intended to limit the scope of protection of this disclosure.

[0156] It should be noted that, in this disclosure, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element.

[0157] The sequence numbers of the embodiments disclosed above are for descriptive purposes only and do not represent the superiority or inferiority of the embodiments.

[0158] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.

Claims

1. A soft repair control circuit (10), comprising: The locking control circuit (11) is configured to receive a locking enable signal (Lock En), a soft repair activation signal (SPPR ACT), and a soft repair pulse signal (SPPR Clk), and when the locking enable signal (Lock En) is at an active level, lock the output latch control signal (SPPR Latch) to a first level, and when the locking enable signal (Lock En) is at an inactive level, in response to the active soft repair activation signal (SPPR ACT), output the inverted delayed signal of the soft repair pulse signal (SPPR Clk) as the latch control signal (SPPR Latch); wherein, when the locking enable signal (Lock En) is at an active level, it indicates that a soft repair locking operation should be performed; The undo control circuit (12) is configured to receive an undo enable signal (Undo En) and the latch control signal (SPPR Latch), maintain its output unchanged when the latch control signal (SPPR Latch) is locked at a first level, and generate and output an undo flag signal at an effective level in response to a pulse on the latch control signal (SPPR Latch) when the latch control signal (SPPR Latch) is an inverted delayed signal of the soft repair pulse signal (SPPR Clk); wherein, when the undo enable signal (Undo En) is at an effective level, it indicates that a soft repair undo operation should be performed; The soft repair address latch circuit (13) is configured to receive the soft repair failure address (SPPR FA[n:0]) and the latch control signal (SPPR Latch), maintain the output unchanged when the latch control signal (SPPR Latch) is locked at the first level, and latch the soft repair failure address (SPPR FA[n:0]) in response to the pulse on the latch control signal (SPPR Latch) when the latch control signal (SPPR Latch) is the inverted delayed signal of the soft repair pulse signal (SPPR Clk), and output the latch address (Latch FA[n:0]). The soft repair address matching circuit (14) is configured to receive the latch address (Latch FA[n:0]) and the undo flag signal (Undo flag), lock the output soft repair matching signal (SPPR Match) to an invalid level when the undo flag signal (Undo flag) is at an invalid level, and match the target address (RA[n:0]) with the latch address (Latch FA[n:0]) to generate and output the soft repair matching signal (SPPR Match) when the undo flag signal (Undo flag) is at an invalid level. Specifically, when the soft repair match signal (SPPR Match) is at an active level, it indicates that the target address (RA[n:0]) and the latch address (Latch FA[n:0]) have successfully matched; when the soft repair match signal (SPPR Match) is at an inactive level, it indicates that the target address (RA[n:0]) and the latch address (Latch FA[n:0]) have not successfully matched. The target address (RA[n:0]) is the address corresponding to the access operation in normal working mode.

2. The soft repair control circuit (10) as described in claim 1, wherein, The locking control circuit (11) includes: The lock flag signal generation circuit (111) is configured to receive the lock enable signal (Lock En), the soft repair activation signal (SPPR ACT), and the soft repair pulse signal (SPPR Clk), and when the lock enable signal (Lock En) is at an active level and the soft repair activation signal (SPPR ACT) is at an active level, it generates and outputs a latch control signal (SPPR Latch) at an active level in response to a pulse on the soft repair pulse signal (SPPR Clk), and when the lock enable signal (Lock En) is at an inactive level, it generates and outputs a lock flag signal (Lock Flag) at an inactive level. The latch control signal generation circuit (112) is configured to receive the lock flag signal, the soft repair activation signal (SPPR ACT), and the soft repair pulse signal (SPPR Clk), and lock the output latch control signal (SPPR Latch) to a first level when the lock flag signal (Lock Flag) is at an active level, and output the inverted delayed signal of the soft repair pulse signal (SPPR Clk) as the latch control signal (SPPR Latch) when the lock flag signal (Lock Flag) is at an inactive level and the soft repair activation signal (SPPR ACT) is at an active level.

3. The soft repair control circuit (10) as described in claim 2, wherein, The locking identifier signal generation circuit (111) includes: The first NAND gate (1111) receives the Lock En signal, the Soft Repair Activation signal (SPPR ACT), and the Soft Repair Pulse signal (SPPR Clk) at its input terminals respectively. The D flip-flop (1112) has its input terminal electrically connected to the power supply terminal, its clock terminal electrically connected to the output terminal of the first NAND gate (1111), and its output terminal used to output the lock flag signal. The latch control signal generation circuit (112) includes: The delay unit (1121) receives the soft repair pulse signal (SPPR Clk) at its input terminal; The second NAND gate (1122) has its first input terminal receiving the soft repair activation signal (SPPR ACT), and its second input terminal is electrically connected to the output terminal of the delay unit (1121). OR gate (1123), the first input terminal of the OR gate (1123) is electrically connected to the output terminal of the D flip-flop (1112), the second input terminal of the OR gate (1123) is electrically connected to the output terminal of the second NAND gate (1122), and the output terminal of the OR gate (1123) is used to output the latch control signal (SPPR Latch).

4. The soft repair control circuit (10) as described in any one of claims 1-3, wherein, The revocation control circuit (12) includes: The first latch (121) receives the undo enable signal (Undo En) at its input terminal and the first latch (121) receives the latch control signal (SPPR Latch) at its control terminal. NOT gate (122), the input terminal of the NOT gate (122) is electrically connected to the output terminal of the first latch (121), and the output terminal of the NOT gate (122) is used to output the undo flag signal.

5. The soft repair control circuit (10) as described in any one of claims 1-4, wherein, The soft repair address latch circuit (13) includes at least one sub-latch circuit (131), and selects one sub-latch circuit (131) as the target sub-latch circuit (132) according to a preset order; The target sub-latch circuit (132) is configured to receive the latch control signal (SPPR Latch) and the soft repair failure address (SPPR FA[n:0]), and when the latch control signal (SPPR Latch) is locked at a first level, maintain the currently output latch address (Latch FA[n:0]) unchanged, and when the latch control signal (SPPR Latch) is an inverted delayed signal of the soft repair pulse signal (SPPR Clk), latch the soft repair failure address (SPPR FA[n:0]) as the latch address (Latch FA[n:0]) in response to the pulse on the latch control signal (SPPR Latch).

6. The soft repair control circuit (10) as described in claim 5, wherein, The soft repair address matching circuit (14) includes at least one sub-matching circuit (141), which is connected to at least one sub-latch circuit (131) in a one-to-one correspondence. The sub-matching circuit (141) connected to the target sub-latch circuit (132) is used as the target sub-matching circuit (142). The target sub-matching circuit (142) is configured to receive the undo flag signal and the target address (RA[n:0]), lock the output soft repair match signal (SPPR Match) to an invalid level when the undo flag signal is at an active level, and match the corresponding latch address (Latch FA[n:0]) with the target address (RA[n:0]) when the undo flag signal is at an invalid level, so as to generate and output a corresponding soft repair match signal (SPPR Match).

7. The soft repair control circuit (10) as described in claim 6, wherein, The target sub-latch circuit (132) includes a plurality of second latches (1321), and the plurality of second latches (1321) correspond one-to-one with a plurality of first address signals in the soft repair failure address (SPPR FA[n:0]) and a plurality of second address signals in the latch address (Latch FA[n:0]); The input terminal of the second latch (1321) receives a corresponding first address signal, the control terminal of the second latch (1321) receives the latch control signal (SPPR Latch), and the output terminal of the second latch (1321) is used to output a corresponding second address signal.

8. The soft repair control circuit (10) as described in claim 7, wherein, The target sub-matching circuit (142) includes multiple XOR gates (1421) and AND gates (1422), and the multiple XOR gates (1421) correspond one-to-one with the multiple second latches (1321) and the multiple third address signals in the target address (RA[n:0]); The first input terminal of the XOR gate (1421) receives a corresponding third address signal, and the second input terminal of the XOR gate (1421) is electrically connected to the output terminal of a corresponding second latch (1321). One input of the AND gate (1422) receives the undo flag signal, and the other inputs of the AND gate (1422) are electrically connected to the outputs of the multiple XOR NOT gates (1421) in a one-to-one correspondence. The output of the AND gate (1422) is used to output the soft repair match signal (SPPR Match).

9. The soft repair control circuit (10) as described in any one of claims 1-8, wherein, The locking control circuit (11) is further configured to reset the latch control signal (SPPR Latch) in response to a reset signal; The undo control circuit (12) is further configured to reset the undo flag signal to an invalid level in response to the reset signal; The soft-repair address latch circuit (13) is further configured to reset the latch address (Latch FA[n:0]) in response to the reset signal.

10. A memory (100) comprising a command decoding circuit (20) and a soft repair control circuit (10) as described in any one of claims 1-9; The command decoding circuit (20) is configured to receive a soft repair command, and when the soft repair mode parameter in the soft repair command is a second preset value, generate an undo enable signal at an effective level, and when the soft repair mode parameter in the soft repair command is a third preset value, generate a lock enable signal at an effective level. The soft repair control circuit (10) is further configured to receive the undo enable signal and the lock enable signal, and to control the execution of a soft repair undo operation when the undo enable signal is at an active level, and to control the execution of a soft repair lock operation when the lock enable signal is at an active level.

11. The memory (100) as claimed in claim 10, wherein, The command decoding circuit (20) is further configured to generate a soft repair enable signal at an effective level when the soft repair mode parameter in the soft repair command is a first preset value; wherein, when the soft repair enable signal is at an effective level, it instructs the memory (100) to enter the soft repair mode. The command decoding circuit (20) is further configured to, after the memory (100) enters the soft repair mode, sequentially receive an activation command (ACT CMD) and a write command, and decode the activation command (ACT CMD) to generate and output a soft repair activation signal (SPPR ACT) and a soft repair failure address (SPPR FA[n:0]), and decode the write command to generate and output a soft repair pulse signal (SPPR Clk); wherein, when the address information in the activation command (ACT CMD) indicates the memory bank (40) corresponding to the soft repair control circuit (10), the soft repair activation signal (SPPR ACT) at an effective level is generated and sent to the soft repair control circuit (10); The soft repair control circuit (10) is electrically connected to the command decoding circuit (20) and is configured to receive the soft repair activation signal (SPPR ACT), the soft repair failure address (SPPR FA[n:0]), and the soft repair pulse signal (SPPR Clk), and when the soft repair activation signal (SPPR ACT) is at an active level, latch the soft repair failure address (SPPR FA[n:0]) as a latch address (Latch FA[n:0]) according to the soft repair pulse signal (SPPR Clk).

12. The memory (100) of claim 11, further comprising: Row address decoding circuit (30) and memory bank (40); The command decoding circuit (20) is further configured to generate the soft repair enable signal at an invalid level when the soft repair mode parameter in the soft repair command is a fourth preset value, so as to indicate that the memory (100) enters the normal working mode. The command decoding circuit (20) is further configured to receive an activation command (ACT CMD) when the memory (100) is in normal operating mode, and decode the activation command (ACT CMD) to generate and output the target address (RA[n:0]). The soft repair control circuit (10) is further configured to match the target address (RA[n:0]) with the latch address (Latch FA[n:0]) when the memory (100) is in normal working mode, and generate and output a soft repair match signal (SPPR Match) at an active level when the target address (RA[n:0]) and the latch address (Latch FA[n:0]) are successfully matched. The row address decoding circuit (30) is electrically connected to the soft repair control circuit (10) and is configured to receive the soft repair match signal (SPPR Match) and the target address (RA[n:0]), and when the soft repair match signal (SPPR Match) is at an active level, control the opening of the word line of the corresponding soft repair redundant row in the memory bank (40) according to the active level of the soft repair match signal (SPPR Match).

13. The memory (100) as claimed in claim 11, wherein, The command decoding circuit (20) includes: a soft repair command decoder (21), a mode register (22), a soft repair signal generation circuit (23), an activation command decoder (24), and a write command decoder (25); The soft repair command decoder (21) is configured to receive the soft repair command and write the soft repair mode parameter in the soft repair command into the mode register (22); The soft repair signal generation circuit (23) is configured to receive the soft repair mode parameters stored in the mode register (22), and generate a soft repair enable signal (SPPR En) at an effective level when the soft repair mode parameters are a first preset value, generate an undo enable signal (Undo En) at an effective level when the soft repair mode parameters are a second preset value, and generate a lock enable signal (Lock En) at an effective level when the soft repair mode parameters are a third preset value. The activation command decoder (24) is configured to receive the soft repair enable signal (SPPR En) and the activation command (ACT CMD), and when the soft repair enable signal (SPPR En) at an active level indicates that the memory (100) enters the soft repair mode, decode the activation command (ACT CMD) to generate and output the soft repair activation signal (SPPR ACT) and the soft repair failure address (SPPR FA[n:0]); The write command decoder (25) is configured to receive the soft repair enable signal (SPPR En) and the write command (WRITE CMD), and when the soft repair enable signal (SPPR En) at an active level indicates that the memory (100) enters the soft repair mode, decode the write command (WRITE CMD) to generate and output the soft repair pulse signal (SPPR Clk).

14. The memory (100) of claim 12, further comprising: The fuse address matching circuit (50) is configured to receive multiple standard failure addresses from the fuse array, match the received target address (RA[n:0]) with the multiple standard failure addresses respectively, and generate multiple standard matching signals according to the matching results; The row address decoding circuit (30) is further configured to receive the plurality of standard matching signals, and when any standard matching signal is at an active level, control the opening of the word line of the corresponding standard redundant row in the memory bank (40) according to the active level of the standard matching signal.

15. The memory (100) as claimed in claim 14, wherein, The row address decoding circuit (30) is further configured to, when both the soft repair match signal (SPPR Match) and the standard match signal are at an invalid level, control the word line of the corresponding storage row in the memory bank (40) to be turned on according to the target address (RA[n:0]).

16. A method for repairing a memory, comprising: Receive the soft repair command (SPPR CMD) and decode the soft repair command (SPPR CMD); Determine the value of the soft repair mode parameter in the soft repair command (SPPR CMD); When the soft repair mode parameter is a second preset value, an undo enable signal (Undo En) at an active level is generated to indicate the execution of a soft repair undo operation; In response to an active Undo En signal, the SPPR Match signal is locked to an inactive level. When the soft repair mode parameter is a third preset value, a lock enable signal (Lock En) at an active level is generated to indicate the execution of a soft repair lock operation; In response to a lock enable signal (Lock En) at an active level, the currently latched soft repair failure address (SPPR FA[n:0]) remains unchanged, and the undo enable signal (Undo En) is masked. When the soft repair match signal (SPPR Match) is at an invalid level, it indicates that the target address (RA[n:0]) and the latched soft repair failure address (SPPR FA[n:0]) have not matched successfully. The target address (RA[n:0]) is the address corresponding to the access operation in normal working mode.

17. The repair method as described in claim 16, further comprising: When the soft repair mode parameter in the soft repair command (SPPR CMD) is a first preset value, a soft repair enable signal at an active level is generated to indicate entry into soft repair mode. After the memory (100) enters the soft repair mode, it receives the activation command (ACT CMD) and the write command (WRITE CMD) in sequence; The activation command (ACT CMD) is decoded to generate a soft repair activation signal (SPPR ACT) and a soft repair failure address (SPPR FA[n:0]); The write command (WRITE CMD) is decoded to generate a soft repair pulse signal (SPPR Clk); In response to the soft repair activation signal (SPPR ACT) at an active level, the soft repair failure address (SPPR FA[n:0]) is latched as a latch address (Latch FA[n:0]) according to the soft repair pulse signal (SPPR Clk).

18. The repair method as described in claim 17, further comprising: When the soft repair mode parameter in the soft repair command (SPPR CMD) is the fourth preset value, the soft repair enable signal (SPPR En) at an invalid level is generated to indicate that the memory (100) enters the normal operation mode. When the memory (100) is in normal operating mode, an activation command (ACT CMD) is received; The activation command (ACT CMD) is decoded to generate the target address (RA[n:0]); The target address (RA[n:0]) is matched with the latched soft repair failure address (SPPR FA[n:0]), and a soft repair match signal (SPPR Match) at an active level is generated when the match is successful. The soft repair match signal (SPPR Match) at an active level controls the activation of the word line of the corresponding soft repair redundant row in the memory bank (40).

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