Chip energy saving method and related apparatus

Abstract

A chip energy saving method, which can effectively reduce the power consumption of chips. In the chip energy saving method, for a chip that transmits data by means of a plurality of groups of data transmission circuits, when a data transmission demand is low, the chip turns off some data transmission circuits among the plurality of groups of data transmission circuits, and uses the remaining data transmission circuits to transmit data, thereby reducing circuits running in the chip as much as possible while ensuring normal data transmission, and effectively reducing the power consumption of the chip.

Description

A chip energy-saving method and related apparatus

[0001] This application claims priority to Chinese Patent Application No. 202411824251.1, filed on December 10, 2024, entitled "A Chip Energy Saving Method and Related Device", the entire contents of which are incorporated herein by reference. Technical Field

[0002] This application relates to the field of chip technology, and in particular to a chip energy-saving method and related apparatus. Background Technology

[0003] With the rapid development of the communications industry, enterprises are becoming increasingly reliant on communication networks. In these networks, network equipment such as switches, routers, telephones, and access points (APs) that provide wireless access services to terminals are becoming increasingly widespread, and these devices can be found everywhere, including offices, enterprise server rooms, and carrier server rooms.

[0004] Taking switches as an example, with the widespread use of switches, their power consumption has also attracted considerable attention. In most scenarios, because users may have data transmission needs at any time, switches often need to be continuously powered on. Even when the switch is not continuously transmitting data, its power consumption will still be relatively high if it remains powered on continuously.

[0005] Therefore, there is an urgent need for a method that can effectively reduce the power consumption of network devices. Summary of the Invention

[0006] This application provides a chip energy-saving method that can effectively reduce the power consumption of the chip.

[0007] Firstly, a chip power-saving method is provided, which is applied to a chip that implements physical layer data transmission functions. The chip includes K sets of data transmission circuits, where K is an integer greater than 1.

[0008] The chip power saving method includes: when the data transmission status of the chip meets a first condition, the chip shuts down part of the data transmission circuits in the K groups of data transmission circuits, wherein each group of data transmission circuits in the K groups of data transmission circuits is connected to a pair of twisted pairs, and each group of data transmission circuits is used to receive or send data through the connected pair of twisted pairs.

[0009] The chip then uses one or more sets of data transmission circuits that are not turned off to receive or send data. Since each of the K sets of data transmission circuits is connected to an independent twisted pair, turning off a portion of the data transmission circuits will not affect the normal operation of the remaining un-turned data transmission circuits.

[0010] In this solution, for chips that transmit data through multiple sets of data transmission circuits, when the data transmission demand is low, the chip shuts down some of the data transmission circuits in the multiple sets of data transmission circuits and uses the remaining part of the data transmission circuits to transmit data. This ensures normal data transmission while minimizing the number of circuits running in the chip and effectively reducing the chip's power consumption.

[0011] In one possible implementation, the data transmission status of the chip satisfies a first condition, specifically including: the data transmission rate of the chip is continuously lower than a first transmission rate within a preset time range. That is, the chip will only trigger the shutdown of a portion of the data transmission circuit if the data transmission rate of the chip is continuously lower than the first transmission rate within a past period of time.

[0012] In this solution, by setting the chip to shut down part of the data transmission circuit only when the data transmission rate is continuously lower than a certain transmission rate for a period of time, it can ensure that the data transmission circuit that is not shut down can be used stably to complete the data transmission in the future, avoiding frequent start-up and shutdown of the data transmission circuit, thereby minimizing the chip's power consumption.

[0013] In one possible implementation, before shutting down the data transmission circuits, the chip determines the number of data transmission circuits that need to be shut down based on the data transmission situation. That is, the number of data transmission circuits shut down by the chip is actually determined based on the data transmission situation.

[0014] In this solution, the chip determines the number of data transmission circuits that need to be shut down based on the data transmission situation. It can adaptively adjust the shutdown status of data transmission circuits according to actual data transmission needs, so that the chip can shut down as many data transmission circuits as possible without affecting normal data transmission, thereby effectively reducing the chip's power consumption.

[0015] In one possible implementation, when the data transmission rate of the chip within the preset time range is continuously lower than the first transmission rate and not lower than the second transmission rate, the chip shuts down N data transmission circuits in the K data transmission circuits, where N is an integer greater than or equal to 1.

[0016] When the data transmission rate of the chip within the preset time range is continuously lower than the second transmission rate, the chip shuts down M data transmission circuits in the plurality of data transmission circuits, where M is an integer greater than N and less than K.

[0017] In general, the lower the data transmission rate of a chip within a preset time range, the lower the chip's data transmission requirements, and therefore the chip can shut down more data transmission circuits to reduce power consumption.

[0018] In one possible implementation, the chip performs crosstalk cancellation processing on the one or more sets of data transmission circuits that are not turned off before the chip uses them to receive or send data.

[0019] In this solution, after the chip shuts down the data transmission circuit, it re-executes crosstalk cancellation processing on the remaining unshutdown data transmission circuits, thereby ensuring that the remaining unshutdown data transmission circuits can transmit data normally.

[0020] In one possible implementation, before the chip uses one or more sets of data transmission circuits that are not turned off to receive or transmit data, the chip performs clock data recovery (CDR) and transmit / receive synchronization, channel equalization, and echo cancellation on the one or more sets of data transmission circuits that are not turned off.

[0021] In one possible implementation, after the chip uses one or more sets of data transmission circuits that are not turned off to receive or send data, when the data transmission status of the chip meets a second condition, the chip activates some or all of the data transmission circuits that have been turned off.

[0022] In one possible implementation, after the chip activates some or all of the data transmission circuits in the partially shut-down data transmission circuits, the chip performs crosstalk cancellation processing on all activated data transmission circuits.

[0023] In one possible implementation, the chip triggers the shutdown of a portion of the data transmission circuits in the K groups of data transmission circuits after receiving an instruction from the Media Access Control (MAC) chip, and the chip and the MAC chip are deployed in the same network device.

[0024] In one possible implementation, each set of data transmission circuits includes a data sending circuit and a data receiving circuit.

[0025] In one possible implementation, each set of data transmission circuits includes a Physical Medium Attachment (PMA) circuit and an Analog Front End (AFE) circuit.

[0026] In one possible implementation, the chip is an Ethernet physical layer PHY chip or a forwarding chip.

[0027] In a second aspect, a chip is provided, the chip comprising K sets of data transmission circuits, wherein K is an integer greater than 1, and the chip is used to execute the method described in any implementation of the first aspect.

[0028] Thirdly, a network device is provided, comprising: a chip, the chip being configured to perform the method described in any implementation of the first aspect.

[0029] The solutions provided in the second and third aspects above are used to implement or cooperate with the method provided in the first aspect above, and therefore can achieve the same or corresponding beneficial effects as the first aspect, which will not be elaborated here. Attached Figure Description

[0030] Figure 1 is a schematic diagram of the system architecture of an application scenario provided in an embodiment of this application;

[0031] Figure 2 is a schematic flowchart of a chip energy-saving method provided in an embodiment of this application;

[0032] Figure 3 is a schematic diagram of the structure of a chip provided in an embodiment of this application;

[0033] Figure 4 is a schematic diagram of the structure of a chip provided in an embodiment of this application;

[0034] Figure 5 is a schematic diagram of selecting the number of data transmission circuit groups to be turned off based on the data transmission rate according to an embodiment of this application;

[0035] Figure 6 is a schematic diagram of the data transmission circuit of a chip that changes its operation by switching modes, according to an embodiment of this application.

[0036] Figure 7 is a schematic diagram of a rate mode provided in an embodiment of this application;

[0037] Figure 8 is a schematic diagram of the structure of a network device provided in an embodiment of this application. Detailed Implementation

[0038] To make the objectives, technical solutions, and advantages of this application clearer, the embodiments of this application are described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. Those skilled in the art will understand that with the emergence of new application scenarios, the technical solutions provided by the embodiments of this application are also applicable to similar technical problems.

[0039] The terms "first," "second," etc., used in the specification, claims, and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence.

[0040] To facilitate understanding, some technical terms used in this application will be introduced below.

[0041] (1) Twisted Pair (TP)

[0042] Twisted-pair cable consists of a pair of insulated metal wires twisted together. By twisting the two insulated metal wires together at a certain density, the electromagnetic waves radiated by each metal wire during transmission are canceled out by the electromagnetic waves emitted by the other metal wire, effectively reducing the degree of signal interference.

[0043] (2) Ethernet Physical Layer (PHY) Chip

[0044] An Ethernet PHY chip is a component that implements the physical layer functions of network communication. The main function of an Ethernet PHY chip is to convert digital signals into analog signals suitable for transmission over physical media (such as twisted-pair cables), and to convert analog signals back to digital signals at the receiving end. Generally, Ethernet PHY chips handle the lowest-level operations of network communication, namely signal encoding, decoding, modulation, demodulation, and clock recovery.

[0045] (3) Media Access Control (MAC) chip

[0046] The MAC chip is a component that implements the data link layer functions in network communication. The MAC chip is mainly responsible for data frame assembly, address addressing, error detection, and data frame transmission and reception. Specifically, the MAC chip processes the data provided by the network layer, encapsulates the data into data frames, and then sends the data frames to the network through the Ethernet PHY chip.

[0047] (4) Crosstalk

[0048] Crosstalk refers to the phenomenon where, when a signal is transmitted on one cable, some of its energy is coupled to adjacent cables via capacitive electric field coupling and inductive magnetic field coupling, causing crosstalk noise. Simply put, crosstalk is the phenomenon of unexpected noise generated when adjacent signal lines couple with each other. In multi-pair cable transmission scenarios, each pair of cables, when receiving a signal, is usually interfered with by signals being transmitted on other cables.

[0049] Generally speaking, crosstalk is divided into near-end crosstalk and far-end crosstalk.

[0050] Near-end crosstalk (NWC) is a signal interference phenomenon that occurs at the receiving end near the transmitting end. NWC is typically caused by electromagnetic interference on adjacent signal lines, leading to a degraded quality of the received signal. When data is transmitted on a signal line, electromagnetic fields from adjacent signal lines may leak onto that line, interfering with the received signal.

[0051] Far-end crosstalk refers to an interference phenomenon that occurs at the receiving end when the signal from the transmitting end leaks to the signal line of the adjacent receiving end through electromagnetic induction or capacitive coupling during signal transmission. This interference occurs on the signal line between the transmitting and receiving ends, hence the name far-end crosstalk.

[0052] (5) Crosstalk cancellation

[0053] Crosstalk cancellation refers to reducing or eliminating crosstalk between signal lines in electronic devices using crosstalk cancellers. Generally, in multi-pair cable transmission scenarios, three near-end crosstalk cancellers and three far-end crosstalk cancellers are required on each pair of cables to achieve crosstalk cancellation.

[0054] (6) Clock Data Recovery (CDR) and Transmit / Receive Synchronization

[0055] CDR (Continuous Reset) refers to the process of recovering the local operating clock frequency and sampling phase based on the received signal, thereby reducing ISI (Inter-Symbol Interference) in the receiving system and improving system performance. Transmit-receive synchronization refers to the clock module implementing CDR providing loop timing functionality to ensure synchronization between data reception and transmission.

[0056] (7) Channel equalization

[0057] Channel equalization refers to the equalization of channel characteristics. Essentially, it involves creating transmission characteristics that are completely opposite to those of the channel, thereby canceling or reducing inter-symbol interference caused by the channel and preventing signal distortion. Generally, higher frequency signals experience greater attenuation during cable transmission, and this attenuation needs to be compensated for. Furthermore, since channel equalization is typically implemented at the receiver (RX), it is often also referred to as RX equalization.

[0058] Channel equalization techniques typically employ adaptive equalizers, which compensate for signal distortion caused by the frequency attenuation characteristics of cables. An adaptive equalizer is a digital filter that automatically adjusts its parameters to adapt to dynamic changes in the channel.

[0059] (8) Echo cancellation

[0060] Echo cancellation is a technique that uses an adaptive filter to cancel out echoes when the transmitted signal interferes with the signal to be received transmitted in the same pair of cables.

[0061] Currently, with the widespread use of various network devices in communication networks, the power consumption of these devices has attracted widespread attention. Taking switches as an example, in most scenarios, because users may have data transmission needs at any time, switches often need to be continuously powered on. Even if the switch is not continuously transmitting data, its power consumption will still be relatively high when it is continuously powered on.

[0062] The applicant's research revealed that one possible energy-saving strategy for switches is to shut down all data transmission circuits in the switch's chips when there is no data transmission demand, and then restart all data transmission circuits when the switch needs to transmit data to complete the data transmission as quickly as possible. This method of shutting down or starting all data transmission circuits in the chip can effectively reduce the switch's power consumption in scenarios with low data traffic. However, in most scenarios (such as when the actual traffic accounts for more than 25% of the chip's full load traffic), because the chip needs to frequently shut down and start all data transmission circuits, the actual power savings are not significant, making it difficult to effectively reduce the switch's power consumption.

[0063] In view of this, this application provides a chip energy-saving method for physical layer PHY chips that transmit data through multiple sets of data transmission circuits. When the data transmission demand is low, the Ethernet PHY chip shuts down some of the data transmission circuits in the multiple sets of data transmission circuits and uses the remaining data transmission circuits to transmit data. This ensures normal data transmission while minimizing the number of circuits running in the Ethernet PHY chip, effectively reducing the power consumption of the Ethernet PHY chip.

[0064] Please refer to Figure 1, which is a schematic diagram of a system architecture for an application scenario provided in this application embodiment. As shown in Figure 1, the system architecture includes network device 1 and network device 2. Network device 1 includes a chip 1 and an interface 1 with electrical connections. Network device 2 includes a chip 2 and an interface 2 with electrical connections. Furthermore, interface 1 and interface 2 are connected via multiple pairs of twisted-pair cables, meaning that interface 1 and interface 2 use electricity as the data carrying medium.

[0065] In this application, chip 1 or chip 2 can use the chip power-saving method to shut down part of the data transmission circuit and transmit data through the remaining part of the data transmission circuit that is not shut down. Since different data transmission circuits often use different twisted-pair cables to transmit data, when chip 1 or chip 2 shuts down part of the data transmission circuit, it actually uses a portion of the twisted-pair cable between interface 1 and interface 2 to transmit data.

[0066] Please refer to Figure 2, which is a flowchart illustrating a chip power-saving method provided in an embodiment of this application. As shown in Figure 2, the chip power-saving method provided in this application includes the following steps 201-202.

[0067] Step 201: When the data transmission status of the chip meets the first condition, the chip shuts down some of the data transmission circuits in the K groups of data transmission circuits. Each group of data transmission circuits in the K groups of data transmission circuits is connected to a pair of twisted pairs, and each group of data transmission circuits is used to receive or send data through the connected pair of twisted pairs.

[0068] Specifically, the chip power-saving method provided in this application is applied to chips that implement physical layer data transmission functions. Please refer to Figure 3, which is a schematic diagram of the structure of a chip provided in an embodiment of this application. As shown in Figure 3, the chip includes K groups of data transmission circuits (i.e., the first group of data transmission circuits, the second group of data transmission circuits, ..., the Kth group of data transmission circuits in Figure 3), where K is an integer greater than 1. For example, K can be a value of 2, 3, 4, or 8, etc. This application does not limit the specific value of K.

[0069] In the K sets of data transmission circuits, each set includes a data transmitting circuit and a data receiving circuit. The data transmitting circuit of one set is connected to one cable of the twisted pair, and the data receiving circuit is connected to the other cable of the same twisted pair. That is, in one set of data transmission circuits, the data transmitting circuit transmits data through one cable of the twisted pair, and the data receiving circuit receives data through the other cable of the twisted pair. In this way, for the K sets of data transmission circuits, each set can receive or transmit data through the connected pair of twisted pairs. For example, in Figure 3, the first set of data transmission circuits is connected to the first pair of twisted pairs, the second set is connected to the second pair of twisted pairs, and so on, with the Kth set of data transmission circuits connected to the Kth pair of twisted pairs.

[0070] If the chip's data transmission meets the first condition, it means that the chip's current data transmission demand is not high, that is, it is not necessary for all data transmission circuits to work at the same time to complete data transmission. Therefore, the chip shuts down a portion of the data transmission circuits in the K groups of data transmission circuits, leaving the remaining part of the data transmission circuits that are not shut down.

[0071] Step 202: The chip uses one or more sets of data transmission circuits that are not turned off to receive or send data.

[0072] When a portion of the chip's data transmission circuits is disabled, the chip no longer uses those disabled circuits to transmit data. Instead, it uses one or more of the remaining, undisabled data transmission circuits to transmit (i.e., receive or send data). Since each of the K data transmission circuits is connected to an independent twisted pair, disabling a portion of the circuits does not affect the normal operation of the remaining, undisabled circuits.

[0073] It should be noted that in this application, the chip actually only shuts down a portion of the data transmission circuitry and uses the remaining un-shutdown data transmission circuitry to continue data transmission. Therefore, in practical applications, even if the chip continuously receives data that needs to be forwarded, as long as the remaining un-shutdown data transmission circuitry in the chip can complete the data forwarding, the chip will not restart the shut-down data transmission circuitry, thereby ensuring that the data transmission circuitry has a relatively long shutdown duration and effectively reducing the chip's power consumption.

[0074] Optionally, in this application, the aforementioned chip may be, for example, an Ethernet PHY chip or a forwarding chip. When the chip is an Ethernet PHY chip, it triggers the shutdown of a portion of the data transmission circuits in multiple data transmission circuits after receiving an instruction from the MAC chip. The PHY chip and the MAC chip are deployed in the same network device.

[0075] Specifically, since the MAC chip is responsible for processing the data provided by the network layer and encapsulating the data into data frames for transmission, the MAC chip can promptly learn about the data transmission status. Therefore, the MAC chip can notify the Ethernet PHY chip to shut down the data transmission circuit, thereby ensuring that the Ethernet PHY chip can accurately shut down the data transmission circuit based on the data transmission status.

[0076] In the case of the aforementioned chip being a forwarding chip, the forwarding chip integrates circuitry for implementing data link layer data transmission functions and circuitry for implementing physical layer data transmission functions. This means that the functions implemented by the aforementioned MAC chip and Ethernet PHY chip are achieved by a single forwarding chip.

[0077] Optionally, each data transmission circuit in the chip includes a Physical Medium Attachment (PMA) circuit and an Analog Front End (AFE) circuit. Furthermore, since each data transmission circuit includes both transmitting and receiving circuits, a complete transmitting circuit in a data transmission circuit group includes a PMA transmitting circuit and an AFE transmitting circuit, and a complete receiving circuit includes a PMA receiving circuit and an AFE receiving circuit.

[0078] The PMA (Physical Coding Sublayer) is primarily responsible for the serial-to-parallel conversion of data and the transmission and reception of signals. Therefore, the PMA transmitting circuit converts the parallel data from the Physical Coding Sublayer (PCS) into a serial data stream using a serial-to-parallel converter and transmits it via twisted-pair cable. The PMA receiving circuit then converts the received serial data stream back into parallel data using a serial-to-parallel converter and transmits the parallel data to the PCS for decoding and processing.

[0079] In addition, the main functions of the AFE transmitting circuit and AFE receiving circuit include signal amplification, frequency conversion, modulation, demodulation, adjacent channel processing, level adjustment and control, and mixing.

[0080] For example, please refer to Figure 4, which is a schematic diagram of the structure of a chip provided in an embodiment of this application. As shown in Figure 4, both Ethernet PHY chip 1 and Ethernet PHY chip 2 include a PCS transmitting circuit, a PCS receiving circuit, and four sets of data transmission circuits. Each set of data transmission circuits includes a PMA transmitting circuit, a PMA receiving circuit, an AFE transmitting circuit, and an AFE receiving circuit. Furthermore, the PMA transmitting circuit is connected to the PCS transmitting circuit and the AFE transmitting circuit, and the PMA receiving circuit is connected to the PCS receiving circuit and the AFE receiving circuit.

[0081] Specifically, the Ethernet PHY chip 1 includes a PCS transmitting circuit 10, a PMA transmitting circuit 111-PMA transmitting circuit 114, an AFE transmitting circuit 121-AFE transmitting circuit 124, a PCS receiving circuit 13, a PMA receiving circuit 141-PMA receiving circuit 144, and an AFE receiving circuit 151-AFE receiving circuit 154.

[0082] The Ethernet PHY chip 2 includes a PCS transmitting circuit 20, a PMA transmitting circuit 211-PMA transmitting circuit 214, an AFE transmitting circuit 221-AFE transmitting circuit 224, a PCS receiving circuit 23, a PMA receiving circuit 241-PMA receiving circuit 244, and an AFE receiving circuit 251-AFE receiving circuit 254.

[0083] Furthermore, as shown in Figure 4, the PMA transmitting circuit, AFE transmitting circuit, PMA receiving circuit, and AFE receiving circuit in the same data transmission circuit group use the same pair of twisted-pair cables to transmit or receive data. For example, the PMA transmitting circuit 111, AFE transmitting circuit 121, PMA receiving circuit 141, and AFE receiving circuit 151 in Ethernet PHY chip 1 use the same pair of twisted-pair cables to transmit or receive data. Therefore, when a set of data transmission circuits is shut down, the Ethernet PHY chip actually shuts down one PMA transmitting circuit, one AFE transmitting circuit, one PMA receiving circuit, and one AFE receiving circuit.

[0084] The above section detailed the chip's specific structure and how it saves power by shutting down the data transmission circuit. For ease of understanding, the following section will explain in detail how the chip shuts down the data transmission circuit.

[0085] Optionally, to ensure that the chip does not frequently restart the disabled data transmission circuit after it has been shut down, the data transmission status of the chip meets a first condition, specifically including: the chip's data transmission rate is consistently lower than a first transmission rate within a preset time range. That is, the chip will only trigger the shutdown of a portion of the data transmission circuit if the chip's data transmission rate has consistently been lower than the first transmission rate within a past period.

[0086] The preset time range is a time range set according to the actual application scenario, such as 5 hours, 12 hours, one day, one week, or one month, and is not specifically limited here. The first transmission rate is determined based on the maximum transmission rate of the remaining data transmission circuits after some data transmission circuits in the chip are turned off. For example, assuming that the minimum number of data transmission circuits that the chip can turn off is one group, then the first transmission rate is, for example, the maximum transmission rate of the remaining data transmission circuits after the chip turns off one group of data transmission circuits, or the first transmission rate is, for example, 80% of the maximum transmission rate of the remaining data transmission circuits after the chip turns off one group of data transmission circuits.

[0087] In summary, if the chip's data transmission rate remains below the first transmission rate within a preset time range, it means that the chip's data transmission rate is likely to remain below the first transmission rate for a considerable period of time. Therefore, in this data transmission scenario, the chip shuts down a portion of the data transmission circuitry while ensuring that the transmission rate of the remaining unshutdown data transmission circuitry meets the first transmission rate requirement, thereby ensuring that subsequent data transmission can be completed based on the remaining unshutdown data transmission circuitry.

[0088] In this solution, by setting the chip to shut down part of the data transmission circuit only when the data transmission rate is continuously lower than a certain transmission rate for a period of time, it can ensure that the data transmission circuit that is not shut down can be used stably to complete the data transmission in the future, avoiding frequent start-up and shutdown of the data transmission circuit, thereby minimizing the chip's power consumption.

[0089] Optionally, before shutting down the data transmission circuits, the chip determines the number of data transmission circuits that need to be shut down based on the data transmission situation. That is, the number of data transmission circuits that the chip shuts down is actually determined based on the data transmission situation.

[0090] Specifically, if the chip's data transmission status indicates that the amount of data to be transmitted is small, the chip can shut down more data transmission circuits; if the chip's data transmission status indicates that the amount of data to be transmitted is large, the chip can only shut down fewer data transmission circuits.

[0091] In this solution, the chip determines the number of data transmission circuits that need to be shut down based on the data transmission situation. It can adaptively adjust the shutdown status of data transmission circuits according to actual data transmission needs, so that the chip can shut down as many data transmission circuits as possible without affecting normal data transmission, thereby effectively reducing the chip's power consumption.

[0092] For example, the following will illustrate several scenarios in which the chip shuts down the data transmission circuit based on the data transmission rate within a preset time range.

[0093] When the chip's data transmission rate remains below the first transmission rate but not below the second transmission rate within a preset time range, the chip shuts down N data transmission circuits out of the K data transmission circuits, where N is an integer greater than or equal to 1. The first transmission rate is, for example, the maximum transmission rate of the KN data transmission circuits, and the second transmission rate is, for example, the maximum transmission rate of the K-(N+1) data transmission circuits.

[0094] When the chip's data transmission rate remains below the second transmission rate within a preset time range, the chip shuts down M data transmission circuits out of multiple data transmission circuits, where M is an integer greater than N and less than K. For example, M may specifically be N+1.

[0095] It should be noted that the above introduction is based on the example of shutting down N groups of data transmission circuits and M groups of data transmission circuits. In practical applications, the number of data transmission circuits that the chip can shut down can also be other values, and this application does not make any specific limitation on this.

[0096] In general, the lower the data transmission rate of a chip within a preset time range, the lower its data transmission requirements. Therefore, the chip can shut down more data transmission circuits to reduce power consumption. Thus, based on the maximum transmission rate of each data transmission circuit group in the chip and the number of data transmission circuit groups included in the chip, the chip can determine the number of data transmission circuits that need to be shut down at various data transmission rates.

[0097] For example, if a chip includes K sets of data transmission circuits, and each set of data transmission circuits is used as the smallest shutdown unit, the chip can shut down at most K-1 sets of data transmission circuits, meaning only one set of data transmission circuits remains open. Therefore, the chip can divide the data transmission rate into K adjacent ranges, with each range corresponding to shutting down from 0 to K-1 sets of data transmission circuits. In this way, the chip can determine the number of data transmission circuits that need to be shut down based on the data transmission rate range indicated by the data transmission status.

[0098] For example, please refer to Figure 5, which is a schematic diagram of selecting the number of data transmission circuit groups to be turned off based on the data transmission rate according to an embodiment of this application. As shown in Figure 5, assuming that the chip includes a total of 4 data transmission circuit groups, and the maximum transmission rate of each data transmission circuit group is 2.5 megabytes per second (Gbps). Then, when all 4 data transmission circuit groups of the chip are turned off, the maximum transmission rate of the chip is 10Gbps. Based on this, the chip can be divided into 4 data transmission rate ranges: range 1 to range 4. Among them, range 1 is a data transmission rate of not less than 7.5Gbps, range 2 is a data transmission rate of not less than 5Gbps and less than 7.5Gbps, range 3 is a data transmission rate of not less than 2.5Gbps and less than 5Gbps, and range 4 is a data transmission rate of less than 2.5Gbps.

[0099] If the data transmission rate of the chip remains within range 1 within the preset time range, that is, the data transmission rate of the chip within the preset time range is not less than 7.5Gbps, then the number of data transmission circuits that the chip shuts down is 0, meaning that the chip cannot shut down the data transmission circuits.

[0100] If the data transmission rate of the chip remains within range 2 within the preset time range, that is, the data transmission rate of the chip within the preset time range is not less than 5Gbps and less than 7.5Gbps, then the number of data transmission circuit groups that the chip shuts down is 1, that is, the number of data transmission circuit groups that remain not shut down is 3.

[0101] If the data transmission rate of the chip remains within range 3 within the preset time range, that is, the data transmission rate of the chip within the preset time range is not less than 2.5Gbps and less than 5Gbps, then the number of data transmission circuit groups that the chip shuts down is 2, that is, the number of data transmission circuit groups that remain not shut down is 2.

[0102] If the data transmission rate of the chip remains within range 4 within the preset time range, that is, the data transmission rate of the chip within the preset time range is less than 2.5Gbps, then the number of data transmission circuit groups that the chip shuts down is 3, that is, the number of data transmission circuit groups that remain open is 1.

[0103] In general, when determining the number of data transmission circuits to be shut down, the chip needs to ensure that the total transmission rate of the remaining unshut down data transmission circuits is not lower than the chip's data transmission rate within a preset time range, so as to ensure that the chip can still meet normal data transmission requirements after shutting down some data transmission circuits.

[0104] The above describes the process by which the chip shuts down the data transmission circuit based on the data transmission status. The following will describe how to ensure that the chip can work normally using the data transmission circuit that is not shut down after it shuts down the data transmission circuit.

[0105] For example, before the chip has shut down some data transmission circuits and the chip uses one or more sets of data transmission circuits that are not shut down to receive or send data, the chip performs crosstalk cancellation processing on the set of one or more sets of data transmission circuits that are not shut down.

[0106] In other words, after shutting down a portion of the data transmission circuits, the chip needs to perform crosstalk cancellation processing on the remaining unshutdown data transmission circuits in order to continue using the unshutdown data transmission circuits to transmit data.

[0107] Generally, after a chip powers on, it performs crosstalk cancellation on all data transmission circuits to counteract crosstalk caused by simultaneous data transmission between different twisted pairs. However, after a portion of the data transmission circuits is shut down, the twisted pairs used by those circuits will no longer transmit data, thus preventing crosstalk to other twisted pairs. Therefore, the crosstalk experienced by the remaining, active data transmission circuits using twisted pairs will also change.

[0108] For example, if a chip includes four sets of data transmission circuits, each set of circuits will experience crosstalk from the other three pairs of twisted pairs when transmitting data using a single twisted pair. Suppose the chip disables two sets of data transmission circuits. Then, for any remaining set of circuits that is not disabled, it will only experience crosstalk from the other pairs of twisted pairs when transmitting data using a single twisted pair.

[0109] Therefore, in this solution, after shutting down the data transmission circuit, the chip re-performs crosstalk cancellation processing on the remaining unshutdown data transmission circuits, thereby ensuring that the remaining unshutdown data transmission circuits can transmit data normally.

[0110] Optionally, to further ensure normal data transmission, before the chip uses one or more sets of data transmission circuits that are not turned off to receive or send data, the method further includes: the chip performing CDR and transmit / receive synchronization, channel equalization, and echo cancellation on the one or more sets of data transmission circuits that are not turned off.

[0111] Specifically, the environmental conditions (such as ambient temperature) of the chip may change before and after the chip shuts down its data transmission circuits, and these changes may affect the data transmission process. Therefore, in order for the chip to still complete data transmission using the remaining data transmission circuits after shutting down some of them, the chip re-performs CDR, transmit / receive synchronization, channel equalization, and echo cancellation on one or more of the remaining data transmission circuits. The specific process of the chip performing CDR, transmit / receive synchronization, channel equalization, and echo cancellation can be found in the technical terminology described above, and will not be repeated here.

[0112] The above describes the process of a chip disabling part of its data transmission circuitry and continuing data transmission based on the remaining undisabled data transmission circuitry. In some scenarios, after a chip disables part of its data transmission circuitry, its data transmission requirements may change over time, potentially making it difficult to meet these requirements when transmitting data using the remaining undisabled circuitry. Therefore, this application proposes a method to restart the disabled data transmission circuitry after it has partially disabled, thereby satisfying the current data transmission needs.

[0113] For example, after the chip uses one or more sets of data transmission circuits that are not turned off to receive or send data, when the chip's data transmission status meets the second condition, the chip activates some or all of the data transmission circuits in the partially turned-off data transmission circuits.

[0114] When the chip's data transmission status meets the second condition, it indicates that the current data transmission demand is high. If the chip uses the remaining unclosed data transmission circuits to transmit data, it will be difficult to meet the current data transmission demand. Therefore, the chip needs to restart the closed data transmission circuits to avoid data loss due to the failure to transmit data in a timely manner.

[0115] Optionally, the chip's data transmission status satisfies the second condition, specifically including: the chip's data transmission rate at a certain point in time reaches a preset percentage (e.g., 80%, 90%, or 95%) of the total rate of the remaining unclosed data transmission circuits; or, the chip's data transmission rate continuously reaches a preset percentage of the total rate of the remaining unclosed data transmission circuits within a certain time range (e.g., 5 seconds, 10 seconds, or 1 minute). Of course, the second condition can also take other forms, and this application does not specifically limit it.

[0116] For example, assuming there are two groups of data transmission circuits remaining in the chip that are not turned off, and each group has a data transmission rate of 2.5Gbps, the total rate of the remaining data transmission circuits in the chip is 5Gbps. If the chip's data transmission rate reaches 4.5Gbps (90% of 5Gbps), it means that the chip's data transmission status meets the second condition, and therefore the chip activates the data transmission circuits that have been turned off.

[0117] It should be noted that when activating a closed data transmission circuit, the chip can activate all closed data transmission circuits, or only some of the closed data transmission circuits. For example, if the chip has closed two sets of data transmission circuits, and the chip's data transmission status meets the second condition, the chip can either activate both sets of data transmission circuits simultaneously, or only activate one set of the two sets of data transmission circuits.

[0118] Optionally, after the chip activates some or all of the data transmission circuits in the partially shut-down data transmission circuits, since the number of data transmission circuits operating simultaneously and the number of twisted pairs have changed, the chip performs crosstalk cancellation processing on all activated data transmission circuits to ensure that these activated data transmission circuits can transmit data normally.

[0119] Furthermore, if the chip has had its data transmission circuit shut down for a certain period of time, the environmental conditions (such as ambient temperature) around the chip may change when the chip restarts its data transmission circuit compared to the point immediately after the circuit was shut down. These changes in environmental conditions could potentially affect the data transmission process. Therefore, after the chip restarts its previously shut-down data transmission circuits, it can re-perform CDR, transmit / receive synchronization, channel equalization, and echo cancellation on all restarted data transmission circuits to ensure that the restarted data transmission circuits can perform data transmission normally.

[0120] Please refer to Figure 6, which is a flowchart illustrating how a chip changes the operation of its data transmission circuit by switching modes, according to an embodiment of this application. As shown in Figure 6, the process of the chip changing the operation of its data transmission circuit by switching modes specifically includes the following steps 601-608.

[0121] Step 601: The chip enters standard mode and starts all data transmission circuits.

[0122] Specifically, after the chip is powered on, it enters standard mode by default, thereby activating all data transmission circuits in the chip in standard mode.

[0123] Step 602: The chip performs channel training in standard mode, training the channels corresponding to all data transmission circuits.

[0124] When performing channel training in standard mode, the chip trains the channels corresponding to all data transmission circuits, that is, it performs crosstalk cancellation processing, CDR and transmit / receive synchronization, channel equalization and echo cancellation on all data transmission circuits.

[0125] Step 603: The chip uses all data transmission circuits that have been activated in standard mode to perform data transmission services.

[0126] In standard mode, the chip uses all the data transmission circuits that are already activated to perform data transmission.

[0127] Step 604: The chip determines whether it has received an instruction to enter the Flexible Lane mode.

[0128] In the case of an Ethernet PHY chip, the chip specifically determines whether it has received an instruction to enter FlexLane mode from the MAC chip. The MAC chip can decide whether to send an instruction to enter FlexLane mode to the Ethernet PHY chip based on the data transmission status of the Ethernet PHY chip.

[0129] When the chip's data transmission requirements are low, the chip will receive a command to enter FlexLane mode. Furthermore, this command will specify the number of data transmission circuits that must be shut down when entering FlexLane mode. For example, if the chip includes four data transmission circuits, the command will instruct the chip to shut down two data transmission circuits to enter FlexLane mode.

[0130] Step 605: Upon receiving an instruction to enter FlexLane mode, the chip enters FlexLane mode and shuts down some data transmission circuits.

[0131] Step 606: The chip performs channel training in FlexLane mode, training the channels corresponding to the remaining unclosed data transmission circuits.

[0132] After entering FlexLane mode, the chip needs to retrain the channels corresponding to the remaining unclosed data transmission circuits. That is, the chip needs to perform crosstalk cancellation, CDR and transmit / receive synchronization, channel equalization, and echo cancellation on the remaining unclosed data transmission circuits.

[0133] Step 607: The chip uses the remaining unclosed data transmission circuitry in FlexLane mode to perform data transmission services.

[0134] Step 608: The chip determines whether it has received an instruction to exit FlexLane mode.

[0135] While the chip is in FlexLane mode, it may receive an instruction to exit FlexLane mode at any time. Upon receiving this instruction, the chip exits FlexLane mode and proceeds to step 601 described above, thereby re-entering standard mode and activating the previously disabled data transmission circuitry. If the chip does not receive an instruction to exit FlexLane mode, it remains in FlexLane mode, performing data transmission through a portion of the data transmission circuitry.

[0136] For example, please refer to Figure 7, which is a schematic diagram of a rate mode provided in an embodiment of this application. As shown in Figure 7, chips with different rate modes can enter the standard mode and the corresponding FlexLane mode, thereby realizing rate switching. For example, for a chip that supports a maximum rate of 10Gbps, the standard mode that the chip enters is specifically the 10Gbps rate mode. At this time, the number of effective wire pairs used by the chip is 4, that is, the chip uses 4 pairs of twisted pairs to transmit data in the 10Gbps rate mode. In addition, the FlexLane modes that the chip can enter include: 10Gbps Flex3, 10Gbps Flex2, and 10Gbps Flex1. Among them, in the 10Gbps Flex3 rate mode, the number of effective wire pairs used by the chip is 3, and the data transmission rate supported by the chip is 7.5Gbps. In the 10Gbps Flex2 rate mode, the number of effective wire pairs used by the chip is 2, and the data transmission rate supported by the chip is 5Gbps. In the 10Gbps Flex1 rate mode, the chip uses 1 effective line pair and supports a data transfer rate of 2.5Gbps.

[0137] For example, for a chip that supports a maximum speed of 5Gbps, the standard mode it enters is the 5Gbps speed mode. In this mode, the chip uses 4 active wire pairs, meaning it uses 4 pairs of twisted-pair wires to transmit data. Additionally, the chip can enter the FlexLane mode, 5Gbps Flex2. In 5Gbps Flex2 mode, the chip uses 2 active wire pairs, and the supported data transfer rate is 2.5Gbps.

[0138] This application also provides a chip, which includes K sets of data transmission circuits, where K is an integer greater than 1, and the chip is used to perform the chip power saving method described in the above embodiments.

[0139] For example, please refer to Figure 8, which is a schematic diagram of the structure of a network device provided in an embodiment of this application. As shown in Figure 8, this application also provides a network device. The network device includes a chip and an interface. The chip includes K groups of data transmission circuits, where K is an integer greater than 1. Furthermore, the chip is connected to the interface, and thus to K pairs of twisted-pair cables. Each group of data transmission circuits in the chip is connected to a pair of twisted-pair cables. In the network device, the chip is used to execute the chip power-saving method described in the above embodiments.

[0140] Optionally, the network device includes an Ethernet PHY chip and a MAC chip. In the network device, the Ethernet PHY chip and the MAC chip are connected.

[0141] Optionally, the chip included in the network device is a forwarding chip, which can be used to implement link layer data transmission functions and physical layer data transmission functions.

[0142] The various embodiments in this specification are described in a progressive manner. Similar or identical parts between embodiments can be referred to mutually. Each embodiment focuses on describing the differences from other embodiments. Wherein, "A refers to B" means that A is the same as B or A is a simple variation of B.

[0143] The terms "first" and "second," etc., used in the specification and claims of this application are used to distinguish different objects, not to describe a specific order of objects, and should not be construed as indicating or implying relative importance. For example, "first speed limit lane" and "second speed limit lane" are used to distinguish different speed limit lanes, not to describe a specific order of speed limit lanes, and should not be construed as the first speed limit lane being more important than the second speed limit lane.

[0144] In the embodiments of this application, unless otherwise stated, "at least one" means one or more, and "multiple" means two or more.

[0145] The above embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit it. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application.

Claims

1. A chip energy-saving method, characterized in that, The method is applied to a chip that implements physical layer data transmission functions. The chip includes K sets of data transmission circuits, where K is an integer greater than 1. The method includes: When the data transmission status of the chip meets the first condition, the chip shuts down some of the data transmission circuits in the K groups of data transmission circuits, wherein each group of data transmission circuits in the K groups of data transmission circuits is connected to a pair of twisted pairs, and each group of data transmission circuits is used to receive or send data through the connected pair of twisted pairs. The chip uses one or more sets of data transmission circuits that are not turned off to receive or send data.

2. The method according to claim 1, characterized in that, The data transmission status of the chip satisfies the first condition, including: The data transmission rate of the chip is consistently lower than the first transmission rate within a preset time range.

3. The method according to claim 1 or 2, characterized in that, The method further includes: Based on the data transmission status, the chip determines the number of data transmission circuits that need to be shut down.

4. The method according to claim 3, characterized in that, The chip shuts down some data transmission circuits in the K groups of data transmission circuits, including: When the data transmission rate of the chip within the preset time range is continuously lower than the first transmission rate and not lower than the second transmission rate, the chip shuts down N data transmission circuits in the K data transmission circuits, where N is an integer greater than or equal to 1. When the data transmission rate of the chip within the preset time range is continuously lower than the second transmission rate, the chip shuts down M groups of data transmission circuits in the plurality of data transmission circuits, where M is an integer greater than N and less than K.

5. The method according to any one of claims 1-4, characterized in that, Before the chip uses one or more sets of data transmission circuits that are not turned off to receive or send data, the method further includes: The chip performs crosstalk cancellation processing on the one or more sets of data transmission circuits that are not turned off.

6. The method according to any one of claims 1-5, characterized in that, Before the chip uses one or more sets of data transmission circuits that are not turned off to receive or send data, the method further includes: The chip performs clock data recovery (CDR), transmit / receive synchronization, channel equalization, and echo cancellation on the one or more sets of data transmission circuits that are not turned off.

7. The method according to any one of claims 1-5, characterized in that, After the chip uses one or more sets of data transmission circuits that are not turned off to receive or send data, the method further includes: When the data transmission status of the chip meets the second condition, the chip activates one or all of the previously closed data transmission circuits.

8. The method according to claim 6, characterized in that, After the chip activates some or all of the data transmission circuits in the partially disabled data transmission circuit, the method further includes: The chip performs crosstalk cancellation processing on all data transmission circuits that have been activated.

9. The method according to any one of claims 1-7, characterized in that, The chip triggers the shutdown of part of the data transmission circuit in the K groups of data transmission circuits after receiving an instruction from the Media Access Control (MAC) chip. The chip and the MAC chip are deployed in the same network device.

10. The method according to any one of claims 1-8, characterized in that, Each data transmission circuit includes a data sending circuit and a data receiving circuit.

11. The method according to any one of claims 1-9, characterized in that, Each data transmission circuit group includes a Physical Media Adaptor (PMA) circuit and an Analog Front-End (AFE) circuit.

12. The method according to any one of claims 1-11, characterized in that, The chip is an Ethernet physical layer PHY chip or a forwarding chip.

13. A chip, characterized in that, The chip includes K sets of data transmission circuits, where K is an integer greater than 1, and the chip is used to perform the method described in any one of claims 1-12.

14. A network device, characterized in that, Includes: a chip, said chip being used to perform the method according to any one of claims 1-12.

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