Wafer inspection method and apparatus, electronic device, and storage medium

Abstract

The present invention provides a wafer detection method and apparatus, an electronic device, and a storage medium. The method comprises: determining, in an inspection image of a wafer, target die regions and a defect region in each target die region; for each target die region, determining a defect type of the defect region in the target die region by means of a detection model corresponding to the defect region in the target die region; and determining an inspection result of the wafer on the basis of the defect type of the defect region in each target die region.

Description

Wafer inspection methods and apparatus, electronic equipment, and storage media

[0001] This application claims priority to Chinese Patent Application No. 202411830213.7, filed on December 12, 2024, entitled "Method and Apparatus for Inspecting Wafers, Electronic Devices and Storage Media", the entire contents of which are incorporated herein by reference. Technical Field

[0002] This invention relates to the field of image processing technology, and more specifically to a wafer inspection method, a wafer inspection device, an electronic device, a storage medium, and a computer program product. Background Technology

[0003] In the industrial sector, with the continuous development of production technology, people have placed higher demands on the production quality and efficiency of industrial products. Furthermore, with the advancement of image processing, more and more product inspections are based on images. If the detection accuracy is low, the practicality of image-based inspection methods will decrease.

[0004] For example, in the wafer inspection process, related technologies typically use Automated Optical Inspection (AOI) equipment to visually inspect the wafer and determine the types of defects on it. However, different defects on a wafer are highly random and complex. Therefore, how to accurately inspect wafers is a technical problem that urgently needs to be solved by those skilled in the art. Summary of the Invention

[0005] The present invention was proposed in view of the above-mentioned problems. The present invention provides a wafer inspection method, a wafer inspection device, an electronic device, a storage medium, and a computer program product.

[0006] According to a first aspect of the present invention, a method for inspecting a wafer is provided, the method comprising:

[0007] In the image to be tested of the wafer, the target wafer grain region and the defect region in each target wafer grain region are identified, wherein the defect region exists in the target wafer grain region;

[0008] For each target wafer grain region, the defect type of the defect region in the target wafer grain region is determined by the detection model corresponding to the defect region in the target wafer grain region. The detection model corresponding to the defect region is related to the position of the defect region in the target wafer grain region.

[0009] The wafer inspection results are determined based on the defect type of the defect region in each target wafer grain region.

[0010] In one possible implementation, the above detection method further includes:

[0011] Based on the first location information of the target wafer grain region, the wafer grain distribution data of the image under test is determined. The first location information is used to indicate the position of the target wafer grain region in the image under test, and the wafer grain distribution data is used to indicate the position information of each wafer grain in the wafer. In the wafer grain distribution data, the identifier corresponding to the target wafer grain region is different from the identifiers corresponding to other wafer grain regions.

[0012] Using the first model, based on wafer grain distribution data, a defect label is determined for each target wafer grain region. The defect label is used to indicate whether there are defects in the target wafer grain region.

[0013] Based on the defect type of the defect region in each target wafer grain region, the wafer inspection results are determined, including:

[0014] The wafer inspection results are determined based on the defect type and defect label of each target wafer grain region.

[0015] In one possible implementation, the wafer inspection result is determined based on the defect type and defect label of each target wafer grain region, including:

[0016] For each target wafer grain region, a first result for that target wafer grain region is generated based on the defect type of that target wafer grain region and the corresponding location information of that target wafer grain region in the wafer grain distribution data;

[0017] The wafer inspection result is determined based on the first result and defect label of each target wafer grain region.

[0018] In one possible implementation, the above detection method further includes:

[0019] Determine the pad area in each target wafer grain region;

[0020] For each target wafer grain region, the defect type of the defect region in that target wafer grain region is determined using the detection model corresponding to the defect region in that target wafer grain region, including:

[0021] For each defective region

[0022] When there is no intersection between the defective region and any pad region, the defect type of the defective region is determined by the first detection model corresponding to the defective region.

[0023] If the defective region intersects with any pad region, the defect type of the defective region is determined by the second detection model corresponding to the defective region.

[0024] In one possible implementation, the above detection method further includes:

[0025] For each defect region, if there is no positional intersection between the defect region and any pad region, the image to be tested is cropped according to the size of the defect region to obtain the defect region image;

[0026] The defect type of the defect area is determined using the first detection model corresponding to the defect area, including:

[0027] The defect region image is input into the first detection model to obtain the defect type of the defect region.

[0028] In one possible implementation, the above detection method further includes:

[0029] For each defect region, if the defect region intersects with any pad region, the image under test is cropped according to the size of the pad region with the intersection to obtain the pad region image;

[0030] The defect type of the defect area is determined using a second detection model corresponding to that defect area, including:

[0031] The image of the pad area is input into the second detection model to obtain the defect type of the defect area.

[0032] In one possible implementation, the wafer inspection result is determined based on the defect type of the defect region in each target wafer grain region, including:

[0033] Based on the defect type of each defect region and the second location information of the defect region, a second result for the defect region is generated, wherein the second location information is used to indicate the position of the defect region in the target wafer grain region;

[0034] The wafer inspection result is determined based on the second result for each defect region.

[0035] In one possible implementation, the wafer inspection result is determined based on the defect type of the defect region in each target wafer grain region, including:

[0036] For each defect region, the encoder in the language model generates the defect type code and the location information code for that defect region based on the defect type and location information, respectively.

[0037] The defect type code and location information of each defect region are input into the prompting learning module to obtain the wafer description code;

[0038] The user-input query information is fed into the encoder in the language model to obtain the query code;

[0039] The wafer description code and query code are input into the decoder in the language model to generate the detection result of the wafer corresponding to the query information.

[0040] According to a second aspect of the present invention, a wafer inspection apparatus is also provided, the inspection apparatus comprising: a region determination module, a defect type generation module, and an inspection result generation module.

[0041] The region determination module is used to determine the target wafer grain region and the defect region in each target wafer grain region in the image to be tested of the wafer, wherein the defect region exists in the target wafer grain region;

[0042] The defect type generation module is used to determine the defect type of each target wafer grain region by using the detection model corresponding to the defect region in the target wafer grain region. The detection model corresponding to the defect region is related to the position of the defect region in the target wafer grain region.

[0043] The detection result generation module is used to determine the detection result of the wafer based on the defect type of the defect region in each target wafer grain region.

[0044] According to a third aspect of the present invention, an electronic device is also provided. The electronic device includes a processor and a memory. The memory stores computer program instructions, which, when executed by the processor, are used to perform the aforementioned wafer inspection method.

[0045] According to a fourth aspect of the invention, a storage medium is also provided. Program instructions are stored on this storage medium, which, when executed, are used to perform the wafer inspection method described above.

[0046] According to a fifth aspect of the present invention, a computer program product is also provided. The computer program product includes computer program instructions that, when executed, perform the wafer inspection method described above.

[0047] According to the above-described scheme of the present invention, target wafer grain regions and defect regions within each target wafer grain region can be determined in the image to be tested of the wafer. Then, for each target wafer grain region, the defect type of the defect region in that target wafer grain region is determined using the detection model corresponding to the defect region in that target wafer grain region. Finally, based on the defect type of the defect region in each target wafer grain region, the wafer inspection result is determined. The above scheme can generate defect types for different defect regions in the wafer using corresponding detection models. Therefore, for wafer grains belonging to different defect types, the accuracy of the generated defect types is higher, which is beneficial for improving the representativeness of the wafer inspection results. Attached Figure Description

[0048] The above and other objects, features, and advantages of the present invention will become more apparent from the more detailed description of the embodiments of the invention in conjunction with the accompanying drawings. The drawings are provided to further illustrate the embodiments of the invention and form part of the specification. They are used together with the embodiments of the invention to explain the invention and do not constitute a limitation thereof. In the drawings, the same reference numerals generally represent the same parts or steps.

[0049] Figure 1 shows a schematic flowchart of a wafer inspection method according to an embodiment of the present invention;

[0050] Figure 2 shows a schematic diagram of a wafer inspection method according to an embodiment of the present invention;

[0051] Figure 3 shows a schematic diagram of a wafer grain with defects in the pad area according to an embodiment of the present invention;

[0052] Figure 4 shows a schematic diagram of a wafer grain with defects in its surface region according to an embodiment of the present invention;

[0053] Figure 5 shows a schematic diagram of a wafer inspection method according to an embodiment of the present invention;

[0054] Figure 6 shows a schematic block diagram of a wafer inspection apparatus according to an embodiment of the present invention; and

[0055] Figure 7 shows a schematic block diagram of an electronic device according to an embodiment of the present invention. Detailed Implementation

[0056] To make the objectives, technical solutions, and advantages of the present invention more apparent, exemplary embodiments according to the present invention will be described in detail below with reference to the accompanying drawings. Obviously, the described embodiments are merely a part of the embodiments of the present invention, and not all of the embodiments of the present invention. It should be understood that the present invention is not limited to the exemplary embodiments described herein. Based on the embodiments of the present invention described herein, all other embodiments obtained by those skilled in the art without inventive effort should fall within the protection scope of the present invention.

[0057] In the field of component manufacturing, packaging and testing defective industrial components (such as wafers) would be a waste of manpower and resources. Therefore, it is necessary to inspect industrial components to detect and reject defective ones. With the continuous advancement of component technology and the development of industrial component manufacturing techniques, defect detection on industrial components has become an indispensable part of the manufacturing process. As component technology continues to advance, the device density and integration of industrial components are constantly increasing, and the requirements for defect detection on industrial components are becoming increasingly stringent.

[0058] In wafer inspection, manual inspection methods and image processing-based automated inspection methods are commonly used to detect defects on wafers. However, neither of these methods can efficiently and accurately identify various defects on the wafer. Manual inspection, relying on human intervention, is not only time-consuming and labor-intensive, but also lacks guaranteed accuracy. Furthermore, it demands a high level of expertise and experience from the inspectors, making it unsuitable for large-scale wafer image-based defect detection. While existing image processing-based automated inspection methods eliminate the need for manual intervention, they cannot accurately identify defects on the wafer and may result in false positives.

[0059] In conclusion, improving the efficiency and accuracy of defect detection on wafers has become an urgent problem to be solved in the field of component manufacturing.

[0060] To at least partially address the aforementioned problems, embodiments of the present invention provide a wafer inspection method. Figure 1 shows a schematic flowchart of a wafer inspection method according to an embodiment of the present invention. As shown in Figure 1, the method may include steps S110 to S130.

[0061] In step S110, in the image to be tested of the wafer, the target wafer grain region and the defect region in each target wafer grain region are determined.

[0062] The image to be tested on the wafer can be a static image or any video frame from a dynamic video. The image to be tested on the wafer can be a raw image acquired by an image acquisition device (e.g., a raw image acquired by an image sensor in a camera), or an image obtained after preprocessing the raw image (such as digitization, normalization, smoothing, etc.). For example, referring to Figure 2, which shows a schematic diagram of a wafer inspection method according to an embodiment of the present invention, the image to be tested on the wafer can be a grayscale image obtained by capturing the wafer with a black and white low-magnification camera.

[0063] Defective regions may exist in the target wafer grain region, so the wafer grain region with defective regions can be used as the target wafer grain region.

[0064] Optionally, wafer grain regions in the image under test can be determined using template matching. For example, the image under test can be matched with a reference image of wafer grains without defects to obtain the wafer grain regions in the image under test, which correspond to a single wafer grain in the wafer. Then, pixels in the wafer grain region whose difference from the reference image exceeds a threshold can be identified as pixels in defect regions. If a defect is determined to exist in a wafer grain region, that region can be used as the target wafer grain region. Specifically, for example, the reference image is placed at the upper left corner of the image under test on the wafer, and then slid across the image under test, comparing each possible position. For each position in the image under test, the similarity or difference between the corresponding regions of the reference image and the image under test is calculated, which can be a pixel-by-pixel comparison, ultimately yielding a result matrix. Each element in the result matrix represents the degree of matching between the reference image and the corresponding position in the image under test. Given the result matrix, the `cv2.minMaxLoc()` function can be used to analyze it and find the position in the wafer's test image that has the highest matching degree with the aforementioned wafer grain reference image. This position with the highest matching degree can be taken as the corresponding position of the wafer grain in the wafer's test image. Alternatively, a trained region detection model can be used to detect wafer grain regions in the test image, and then an algorithm or model can be used to determine the target wafer grain that may have defects. If a defect is determined to exist in a wafer grain region, that wafer grain region can be taken as the target wafer grain region.

[0065] In step S120, for each target wafer grain region, the defect type of the defect region in the target wafer grain region is determined by the detection model corresponding to the defect region in the target wafer grain region.

[0066] The detection model corresponding to a defect region is related to the location of the defect region within the target wafer grain region. For example, there may be at least two different defect regions, each corresponding to a different detection model. As shown in Figure 2, when an image corresponding to a defect region in the target wafer grain region is obtained, the image of the defect region located in the surface region (refer to the defect image of the surface region in Figure 2) and the image of the defect region located in the pad region (refer to the defect image of the pad region in Figure 2) can be processed by different detection models to obtain their respective defect types (for example, referring to Figure 2, defect images of the surface region can be analyzed to identify defects such as foreign objects and scratches, while defect images of the pad region can be analyzed to identify defects such as pin marks and foreign objects). Specifically, for example, the defect region in the target wafer grain region A may include the pad region, the surface region, and the trimming region, etc. The image of the defect region corresponding to the pad region in the target wafer grain region A can be input into detection model 1, and the images of the defect regions corresponding to the trimming region and the surface region in the target wafer grain region A can be input into detection model 2. For example, the image of the defect area corresponding to the pad area in the target wafer grain region A is input into detection model 1, the image of the defect area corresponding to the trimming area in the target wafer grain region A is input into detection model 3, and the image of the defect area corresponding to the surface area in the target wafer grain region A is input into detection model 4.

[0067] The detection model is used to output the defect type of the defect area based on the image of the defect area input to the detection model. Referring to Figure 3, which shows a schematic diagram of a wafer with defects in its pad area according to an embodiment of the present invention, the defect type of the target wafer can be determined by using the detection model corresponding to the pad area (in this example, part or all of the defect area is located in the pad area, so the detection model corresponding to the pad area can be used as the detection model corresponding to the defect area). For example, the defect type of the pad area may include: misaligned pin marks, foreign matter, pad scratches, shallow pin marks, etc. Referring to Figure 4, which shows a schematic diagram of a wafer with defects in its surface area according to an embodiment of the present invention, the defect type of the target wafer can be determined by using the detection model corresponding to the surface area (in this example, the defect area is located in the surface area, so the detection model corresponding to the surface area can be used as the detection model corresponding to the defect area). For example, surface defects may include: surface scratches, other surface defects (e.g., solid foreign objects, transparent foreign objects, etc.), and color differences.

[0068] A detection model for detecting solder pad regions can input the image corresponding to the defect region into a trained detection model (e.g., a trained convolutional neural network, generative adversarial network, etc.) to output the defect type corresponding to the defect region. This embodiment of the invention provides a training method for a detection model for detecting solder pad regions for reference. The training process of this detection model may include: obtaining a first training dataset; iteratively training the detection model using the first training dataset and adjusting the model parameters of the detection model using a loss function until training is complete. The first training dataset includes multiple images of solder pad regions, each labeled with the defect type corresponding to the solder pad region. The conditions for completing the training may include the loss value calculated by the loss function stabilizing and the number of iterations reaching a preset number. Based on the above training process, a detection model for detecting solder pad regions can be obtained to determine the defect type corresponding to the solder pad region. It should be understood that a detection model for detecting other regions (e.g., trimmed regions, surface regions, etc.) can refer to the above training process, replacing the images in the first training dataset with images of the other regions and replacing the labels of the images with the defect types corresponding to the other regions. This embodiment of the invention will not elaborate further here. It should be understood that, in practical scenarios, users are usually more concerned about the defect types in the pad area. Therefore, one detection model can be used for the pad area and another detection model can be used for all other areas to achieve lightweight deployment of the detection model.

[0069] In step S130, the inspection result of the wafer is determined based on the defect type of the defect region in each target wafer grain region.

[0070] The wafer inspection results can be determined based on the defect regions and defect types within each target wafer grain. In one example, the wafer inspection results can be represented as a holistic result combining the defect types of the target wafer grains. For instance, if the number of detected target wafer grains with the defect type "foreign matter presence" exceeds a preset maximum value, the wafer inspection results can include the presence of a large number of target wafer grains with foreign matter presence. In another example, the wafer inspection results can also be represented as a composite result of the defect types of the target wafer grains. For example, wafer A contains target wafer grain regions A1, A2, and A3. The defect region in target wafer grain region A1 is a pad region, with the corresponding defect type being "pin mark out of bounds"; the defect region in target wafer grain region A2 is a trimming region, with the corresponding defect type being "foreign matter presence"; and the defect region in target wafer grain region A3 is a surface region, with the corresponding defect type being "foreign matter presence". Based on the above, the inspection results of wafer A may include the presence of pin marks outside the boundary of the pad area of ​​wafer A1, the presence of foreign objects in the adjustment area of ​​wafer A2, and the presence of foreign objects on the surface area of ​​wafer A3.

[0071] According to the above-described scheme of the present invention, target wafer grain regions and defect regions within each target wafer grain region can be determined in the image to be tested of the wafer. Then, for each target wafer grain region, the defect type of the defect region in that target wafer grain region is determined using the detection model corresponding to the defect region in that target wafer grain region. Finally, based on the defect type of the defect region in each target wafer grain region, the wafer inspection result is determined. The above scheme can generate defect types for different defect regions in the wafer using corresponding detection models. Therefore, for wafer grains belonging to different defect types, the accuracy of the generated defect types is higher, which is beneficial for improving the representativeness of the wafer inspection results.

[0072] For example, the above detection method may further include: determining the pad area in each target wafer grain region.

[0073] The pad region within each target wafer grain region can be determined using template matching. For example, the image corresponding to the target wafer grain region in the wafer's test image is used as the target wafer grain image. This target wafer grain image is then matched with the image template corresponding to the pad region to obtain the region in the target wafer grain image that successfully matches the image template. This successfully matched region is then designated as the pad region. Specifically, the target wafer grain image and the image template corresponding to the pad region can be preprocessed, such as through grayscale conversion and filtering / denoising, to improve the accuracy and efficiency of the matching. Then, a suitable matching method is selected based on application requirements, such as matching based on squared difference, normalized squared difference, or correlation coefficient. The matching process includes placing the image template corresponding to the pad region at the upper left corner of the target wafer grain image, then sliding it across the target wafer grain image, comparing each possible position. Furthermore, for each position in the target wafer grain image, the similarity or difference between the image template corresponding to the pad region and the corresponding region in the target wafer image is calculated. This can be a pixel-by-pixel comparison, ultimately yielding a result matrix. In the result matrix, each element represents the degree of matching between the image template corresponding to the pad region and its corresponding position in the target wafer grain image. Given the result matrix, the `cv2.minMaxLoc()` function can be used to analyze it and find the position with the highest matching degree. This position with the highest matching degree can be used as the image of the pad region.

[0074] Step S120 may also include step S121.

[0075] In step S121, for each defect region, if there is no positional intersection between the defect region and any pad region, the defect type of the defect region is determined by the first detection model corresponding to the defect region. If there is a positional intersection between the defect region and any pad region, the defect type of the defect region is determined by the second detection model corresponding to the defect region.

[0076] The first detection model is used to determine the defect type of defect regions that do not intersect with the pad area. The second detection model is used to determine the defect type of defect regions that do intersect with the pad area.

[0077] The training methods for the first and second detection models can be referred to above, and will not be repeated here in the embodiments of the present invention. The positional relationship between the defect region and the pad region can be compared to determine whether there is a positional intersection between the defect region and the pad region. For example, the coordinates of the defect region in the image under test can be compared with the coordinates of the pad region in the image under test to determine whether the defect region has a positional intersection with any pad region.

[0078] According to the above-described scheme of the present invention, the defect type of the defect area in the pad region and the defect type of the defect area in the non-pad region can be determined separately by different detection models. Since the defects in the pad region of the wafer are usually more concerned in quality inspection than the defects in other regions, the above scheme can use a separate detection model to specifically determine the defect type of the more important pad region and another detection model to determine the defect type of other regions. This can improve the accuracy of the wafer inspection method while reducing the number of models that need to be trained, which is conducive to the lightweight deployment of the inspection method.

[0079] For example, the wafer inspection method may further include cropping the image to be inspected according to the size of the defect region for each defect region, provided that the defect region does not intersect with any pad region, to obtain a defect region image.

[0080] Optionally, the ratio of the number of pixels occupied by foreign objects in the defect region image to the total number of pixels in the defect region image is greater than the ratio of the number of pixels occupied by foreign objects in the image under test to the total number of pixels in the image under test. For example, if the defect type is the presence of foreign objects, the area containing foreign objects can be taken as the defect region, and the area containing foreign objects can be expanded outward by a certain preset ratio or not expanded outward to obtain the defect region image containing foreign objects. The above preset ratio can be set according to the actual situation, and the present invention does not limit it.

[0081] In step S121, determining the defect type of the defect region using the first detection model corresponding to the defect region may further include: inputting the defect region image into the first detection model to obtain the defect type of the defect region.

[0082] In one example, the defect types output by the first detection model may include color difference in the surface area, color difference in the trimmed area, opaque foreign matter in the surface area, transparent foreign matter in the trimmed area, scratches in the surface area, and scratches in the trimmed area.

[0083] According to the above-described scheme of the present invention, a defect region image can be obtained by cropping the image corresponding to the defect region where there is no positional intersection in the pad region, and then the defect type can be determined based on the defect region image. Redundant regions in the defect region can be removed, thereby highlighting the features of the defect region in the image, which is beneficial to the accuracy of the defect type obtained by the first detection model after recognizing the defect region image.

[0084] For example, the wafer inspection method may further include: for each defect region, if the defect region intersects with any pad region, cropping the image to be tested according to the size of the pad region with the intersecting position to obtain a pad region image.

[0085] Optionally, the ratio of the number of pixels occupied by foreign objects in the pad area image to the total number of pixels in the pad area image is greater than the ratio of the number of pixels occupied by foreign objects in the image under test to the total number of pixels in the image under test. For example, if the defect type is pin mark out of bounds, the pad area can be expanded outward by a certain preset ratio or not expanded at all to obtain a cropped pad area image with pin mark out of bounds. The above preset ratio can be set according to actual conditions, and the present invention does not limit it.

[0086] In step S121, determining the defect type of the defect area using the second detection model corresponding to the defect area may further include: inputting the pad area image into the second detection model to obtain the defect type of the defect area.

[0087] In one example, the defect types output by the second detection model may include: pad area pin marks outside the boundary, pad area pin marks shallow, pad area opaque foreign objects, pad area transparent foreign objects, pad area scratches, etc.

[0088] In some embodiments, the second detection model may include an instance segmentation model and a location analysis model. The instance segmentation model can be used to mark the region containing the defective entity in the pad region image and determine the category of the defective entity. For example, the category of the defective entity may include: transparent foreign objects, solid foreign objects, pin marks, etc. The location analysis model can determine the defect type of the defective region based on the relationship between the pad region and the region containing the defective entity, the number of defective entities, etc. For example, if the area containing the pin marks partially overlaps with the pad region, the defect type can be determined as pin mark out of bounds. If the area containing the pin marks is completely within the pad region, and the number of pin marks is greater than a preset threshold, the defect type can be determined as excessive number of pin marks. The specific rules of the location analysis model may vary depending on the quality inspection standards, and will not be elaborated upon in this embodiment. It should be understood that the second detection model may also directly output the defect type based on the image features of the pad region image without going through instance segmentation and location analysis steps; this is not limited in this embodiment. For example, the second detection model can be trained using multiple pad area images and the defect types of each pad area image. The specific process can be found in the training process of the detection model described above.

[0089] According to the above-described scheme of the present invention, the image of the pad region corresponding to the defect region that intersects with any pad region can be cropped to obtain a pad region image. Then, the defect type can be determined based on the pad region image. This allows for comprehensive detection of various complex defects that may exist in the pad region, such as pin marks outside the boundary or excessive pin marks as mentioned above. Furthermore, inputting only the pad region image into the second detection model can increase the second detection model's focus on the characteristics of defects in the pad region image, which is beneficial for improving the accuracy of the obtained defect types.

[0090] For example, the wafer inspection method provided by the present invention further includes steps S210 and S220.

[0091] In step S210, based on the first location information of the target wafer grain region, the wafer grain distribution data of the image to be tested is determined.

[0092] The first location information is used to represent the position of the target wafer grain region in the image under test. For example, the first location information can be the coordinates of the target wafer grain region in the image under test. Specifically, the first location information can be the coordinates of each vertex of the target wafer grain region in the image under test. More specifically, the first location information can be the coordinates of the center point of the target wafer grain region in the image under test. It should be understood that since the image under test includes multiple wafer grains, and the wafer grain distribution data also includes multiple wafer grains, the first location information can be used to determine the position of the target wafer grain (or the corresponding target wafer grain region) in the wafer grain distribution data. It should be understood that the image under test may include images of some wafer grains in the wafer, while the wafer grain distribution data includes all wafer grains in the wafer. Therefore, the wafer grains in multiple images under test can be mapped separately to obtain the wafer grain distribution data. The specific mapping rules are not limited in this embodiment of the invention; the target wafer grain in the image under test can be matched with the wafer grain in the wafer grain distribution data. Accordingly, the wafer grain corresponding to the target wafer grain region in the wafer grain distribution data can be determined by the first position information of the target wafer grain region in the image to be tested, so as to determine the position information of the wafer grain in the wafer.

[0093] Wafer grain distribution data is used to represent the location information of each wafer grain within the wafer, and the identifier corresponding to the target wafer grain region in the wafer grain distribution data is different from the identifiers corresponding to other wafer grain regions. In one example, the above wafer grain distribution data can be a wafer grain distribution map. For example, referring to Figure 2, the map used in the stage of "comprehensive analysis of the location of defective wafer grains in the wafer grain distribution data and the location of defects in the wafer grains" in Figure 2 can be the above wafer grain distribution map. The circular areas in this wafer grain distribution map can be used to represent the area corresponding to the wafer in the map. Each point (or rectangular grid) in the circular area can be used to represent a wafer grain on the wafer. The points corresponding to the target wafer grains in the wafer are filled with a first preset color, and the points corresponding to non-target wafer grains in the wafer are filled with a second preset color. The first preset color can be red, and the second preset color can be green. The first preset color and the second preset color can be determined according to the actual situation, and the present invention does not limit them. In yet another example, the above wafer grain distribution data can also be a wafer grain distribution table. For example, the wafer grain distribution table records whether each wafer grain is a target wafer grain that may contain defects, according to its position. Specifically, a target wafer grain may correspond to the number 1, and other wafer grains may correspond to the number 0, in order to distinguish the target wafer grains in the wafer.

[0094] In step S220, the defect label for each target wafer grain region is determined using the first model based on the wafer grain distribution data.

[0095] The first model is used to determine the target wafer grain region in the wafer based on wafer grain distribution data. Defect labels are used to indicate whether a defect exists in the target wafer grain region. Using the mapping relationship described above and the first location information corresponding to the target wafer grain region, the location information of the target wafer grain in the wafer grain distribution data can be obtained, thus establishing the association between the target wafer grain region and the target wafer grain in the wafer grain distribution data. Then, the defect label determined for the target wafer grain can be used as the defect label for the target wafer grain region corresponding to that target wafer grain.

[0096] In one example, the first model can determine a defect label for each target wafer grain region corresponding to its respective target wafer grain. For each target wafer grain region, the input to the first model may include wafer grain distribution data and the location information of the target wafer grain within the wafer grain distribution data. Alternatively, the input to the first model may include wafer grain distribution data, the location information of the target wafer grain within the wafer grain distribution data, and an image of the target wafer grain region corresponding to the target wafer grain in the image to be tested. It should be understood that the input to the first model may also be a portion of the wafer grain distribution data, for example, data within a preset range of the target wafer grain in the wafer grain distribution data. The specific training process for the first model may include: acquiring a second training dataset; iteratively training the first model using the second training dataset and adjusting the model parameters of the first model using a loss function until training is complete. The aforementioned second training dataset may include wafer grain distribution data used for training and the location information of the target wafer grain within the wafer grain distribution data. The training image is an image of a wafer. The second training dataset may also include wafer grain distribution data for training, the location information of the target wafer grain in the wafer grain distribution data, and the image of the target wafer grain region corresponding to the target wafer grain in the training image. The conditions for completing the above training may include the loss value calculated by the loss function stabilizing and the number of iterations reaching a preset number. Based on the above training process, a first model can be obtained to determine the defect labels of each target wafer grain region in the target wafer grain distribution data. The first model can determine the defect label of the target wafer grain based on the location information of the input target wafer grain in the wafer grain distribution data, combined with the identifiers of all or some wafer grains in the wafer grain distribution data.

[0097] The aforementioned defect labels may include labels indicating the presence of defects in the target wafer grain region, and labels indicating the absence of defects in the target wafer grain region.

[0098] The first model can determine whether the defect label corresponding to a target wafer is a defect label indicating the presence of a defect based on the number of target wafers in its row or column. In practical scenarios, a defective target wafer might be located in a region of the wafer; for example, an anomaly during the processing stage could cause defects in all wafers in a column or row. The first model can comprehensively consider the distribution characteristics of the target wafer in the wafer distribution data to determine whether the target wafer has an anomaly.

[0099] In some implementations, a preset algorithm can also be used to assist the first model in determining defect labels. For example, based on the number of other target wafers surrounding the target wafer in the wafer distribution data, it can be determined whether the defect label corresponding to the target wafer (equivalent to the defect label of the target wafer region corresponding to the target wafer) is a defect label indicating the presence of a defect. For example, a circle can be drawn with the target wafer A as the center (or the center of a rectangle) and a radius of 10 wafers. The number of other target wafers in this circular region is also input into the first model to assist the first model in determining the defect labels.

[0100] If the above detection method includes steps S210 and S220, then step S130 may include step S131a.

[0101] In step S131a, the detection result of the wafer is determined based on the defect type and defect label of each target wafer grain region.

[0102] The wafer inspection result can be determined by comprehensively considering the defect type and defect label corresponding to each target wafer grain region. For example, if the defect type corresponding to target wafer grain region B is pin mark misalignment, and the defect label corresponding to target wafer grain region B is a label used to indicate the presence of a defect in the target wafer grain region, then the wafer inspection result is determined to include the presence of a pin mark misalignment defect in target wafer grain region B. As another example, if the defect type corresponding to target wafer grain region C is pin mark misalignment, but the defect label corresponding to target wafer grain region C is a label used to indicate the absence of a defect in the target wafer grain region, then the wafer inspection result is determined to include the absence of a defect in target wafer grain region C.

[0103] According to the above-described scheme of the present invention, not only can the detection model be used to specifically detect defective regions in various areas of the target wafer region, but it can also determine wafer grain distribution data based on the position of the target wafer grain region in the image under test, and determine whether there is a possibility of misjudgment of the target wafer grain region based on the distribution of each target wafer grain region in the wafer grain distribution data. Combining the target wafer grain distribution data, the presence of defects in the target wafer grain can be determined from a global perspective, while combining the defect type can determine the presence of defects in the target wafer grain from a local perspective. Therefore, the above scheme can combine global and local perspectives to comprehensively determine the defects of the target wafer grain, which is beneficial to improving the accuracy of wafer detection results.

[0104] For example, step S131a may include steps S131a1 and S131a2.

[0105] In step S131a1, for each target wafer grain region, a first result for the target wafer grain region is generated based on the defect type of the target wafer grain region and the corresponding location information of the target wafer grain region in the wafer grain distribution data.

[0106] In one example, the defect type of the target wafer grain region and its corresponding location information in the wafer grain distribution data can be concatenated using the concat or add operator to obtain the first result mentioned above. In another example, the defect type of the target wafer grain region and its corresponding location information in the wafer grain distribution data can also be subjected to feature fusion operations in related technologies to obtain the first result. In yet another example, the first result can be determined directly according to preset rules, combining the defect type of the target wafer grain region and its corresponding location information in the wafer grain distribution data; that is, the first result can be used to represent defect types with high confidence.

[0107] In step S131a2, the detection result of the wafer is determined based on the first result and defect label of each target wafer grain region.

[0108] In one example, the first result and the defect label can be concatenated using the `concat` or `add` operator, and then input into a decision model or decision algorithm to obtain the detection result. The decision logic of this decision model or decision algorithm can be adjusted according to the relevant process of step S131a above, referring to quality inspection requirements; this embodiment of the invention does not impose any limitations here. In another example, the first result and the defect label can also undergo feature fusion operations in related technologies, and then be input into a decision model or decision algorithm to obtain the detection result. In yet another example, the detection result can also be determined directly according to preset rules, combining the first result and the defect label, referring to the relevant process of step S131a above.

[0109] This embodiment of the invention provides an example for reference. If the first result of the target wafer grain region matches the defect label (the first result indicates the defect type, and the defect label indicates the presence of a defect; therefore, the first result and the defect label are considered a match, i.e., they do not conflict), it can be determined that the target wafer grain region has a defect type corresponding to the first result. If the first result of the target wafer grain region does not match the defect label (the first result indicates the defect type, and the defect label indicates the absence of a defect; therefore, the first result and the defect label are considered a mismatch, i.e., they conflict), it can be determined that the target wafer grain region does not have a defect type corresponding to the first result. For example, consider target wafer grain regions E, F, and G in the image under test. If the first result of target wafer grain region E indicates the presence of a foreign object on the surface of target wafer grain region E, and the defect label of target wafer grain region E indicates the presence of a defect in target wafer grain region E, then it can be determined that target wafer grain region E has a defect of a foreign object on its surface. That is, the defect type of target wafer grain region E is the presence of a foreign object on its surface. The first result for target wafer grain region F indicates that the pin mark in target wafer grain region F is out of bounds, and the defect label for target wafer grain region F indicates that target wafer grain region F has a defect. Therefore, it can be determined that target wafer grain region F has a defect of pin mark out of bounds. That is, the defect type of target wafer grain region F is pin mark out of bounds. The first result for target wafer grain region G indicates that the adjustment area of ​​target wafer grain region G has scratches, and the defect label for target wafer grain region G indicates that target wafer grain region G does not have defects. Therefore, it can be determined that target wafer grain region G does not have a defect of scratches in the adjustment area. That is, target wafer grain region G does not have defects. In summary, the wafer inspection results may include the presence of foreign objects on the surface area of ​​wafer grain region E and the presence of pin mark out of bounds in target wafer grain region F. It should be understood that if the first result and the defect label do not match, the mismatched target wafer grain region can also be regarded as an indistinguishable wafer grain and output in the inspection results. Then, it can be further determined whether there are defects in the difficult-to-distinguish wafer grains through manual or more precise detection models.

[0110] According to the above-described scheme provided by the embodiments of the present invention, for each target wafer grain region, a first result for that target wafer grain region can be generated based on the defect type of that target wafer grain region and the corresponding location information of that target wafer grain region in the wafer grain distribution data. Then, based on the first result and defect label for each target wafer grain region, the wafer inspection result is determined. In the above scheme, the first result is obtained based on the location information of the target wafer grain region in the wafer grain distribution data. Therefore, based on this location information, defect type, and defect label, the wafer inspection result can be comprehensively determined, thereby enabling a comprehensive judgment on whether the target wafer grain has defects by considering other potentially defective wafer grains nearby, which is beneficial for improving the accuracy of the inspection results.

[0111] For example, step S130 may include steps S131b and S132b.

[0112] In step S131b, a second result for each defect region is generated based on the defect type and the second location information of that defect region.

[0113] The second location information is used to indicate the position of the defect region within the target wafer grain region. For example, when the image to be tested is an image captured by a camera, the second location information can be the relative coordinates of the defect region within the target wafer grain region (e.g., the coordinates of the defect region in a newly established coordinate system based on the wafer grain region). Specifically, the second location information can be the relative coordinates of each vertex of the defect region within the target wafer grain region. Another example is the relative coordinates of the center point of the defect region within the target wafer grain region. Taking the case where the defect region intersects with the pad region as an example, the second location coordinates of the defect region are the relative coordinates of the pad region image within the target wafer grain region. When the defect region and the pad region do not intersect, the second location coordinates of the defect region are the relative coordinates of the defect region within the target wafer grain region. It should be understood that if all or part of the defect region is located within the pad region, the second location information can also be used to indicate the position of the pad region within the wafer grain region.

[0114] In one example, the defect type and the second location information of the defect region can be concatenated using the `concat` or `add` operator to obtain the second result mentioned above. In another example, the defect type and the second location information of the defect region can be fused using relevant techniques to obtain the second result. In yet another example, the second result can be determined directly based on preset rules, combining the defect type and the second location information of the defect region; that is, the second result can be used to represent defect types with high confidence. It should be understood that the location information, defect type, and second location information used in the process of obtaining the first result can also be concatenated to obtain the second result.

[0115] In step S132b, the inspection result of the wafer is determined based on the second result for each defect region.

[0116] In one example, the second result and the defect label can be concatenated using the `concat` or `add` operator, and then input into a decision model or decision algorithm to obtain the detection result. The decision logic of this decision model or decision algorithm can be adjusted according to the relevant process of step S131a above, referring to quality inspection requirements; this embodiment of the invention does not impose any limitations here. In another example, the second result and the defect label can also undergo feature fusion operations in related technologies, and then be input into a decision model or decision algorithm to obtain the detection result. In yet another example, the detection result can also be determined directly according to preset rules, combining the second result and the defect label, referring to the relevant process of step S131a above.

[0117] According to the above-described scheme of the present invention, a second result for each defect region can be generated based on the defect type and the second location information of that defect region. Then, based on the second result for each defect region, the wafer inspection result is determined. Since the second result in the above scheme is obtained based on the second location information, the wafer inspection result can be comprehensively determined based on the defect type and the location of the defect region within the wafer grain region, which is beneficial for improving the accuracy of the inspection result.

[0118] For example, step S130 also includes steps S131c to S134c.

[0119] In step S131c, for each defect region, the encoder in the language model generates the defect type code and the location information code for the defect region based on the defect type and location information of the defect region, respectively.

[0120] The aforementioned location information may include at least one of the target wafer grain region's corresponding location information in the wafer grain distribution data, the first location information, and the second location information.

[0121] The encoder in a language model is used to convert the defect type, location information, and defect label of a defect region into a form that the language model can process. For example, the encoder in a language model can convert text containing defect types into defect type codes that the language model can process. As another example, the encoder in a language model can convert text containing location information into location information codes that the language model can process. And yet another example, the encoder in a language model can convert text containing defect labels into defect label codes that the language model can process.

[0122] In step S132c, the defect type code and location information code of each defect region are input into the prompt learning module to obtain the wafer description code.

[0123] Referring to Figure 5, which illustrates a schematic diagram of a wafer inspection method according to an embodiment of the present invention, the location information encoding may include a first location code obtained by an encoder, which encodes the location information of the target wafer grain region in the wafer grain distribution data, and a second location code obtained by an encoder, which encodes the second location information. In one example, the concatenation result obtained by splicing the defect type code and the first location code (e.g., the first result mentioned above) may be input to the prompt learning module. In another example, the concatenation result obtained by splicing the defect type code and the second location code (e.g., the second result mentioned above) may also be input to the prompt learning module. In yet another example, the concatenation result obtained by splicing the defect type code, the first location code, and the second location code (referring to the example in Figure 5) may also be input to the prompt learning module. In yet another example, the concatenation result obtained by splicing the defect label code and the first location code may also be input to the prompt learning module.

[0124] For example, for defects in the pad region, the defect type code of the pad region, the location code of the pad region in the target wafer grain region, and the location code of the target wafer grain region in the wafer grain distribution data (or the location code of the target wafer grain in the image under test) can be concatenated as features and then input into the prompting learning module. Similarly, for defects in the surface region, the defect type code of the surface region, the location code of the defect in the image under test, and the location code of the target wafer grain containing the defect in the wafer grain distribution data (or the location code of the target wafer grain in the image under test) can be concatenated as features and then input into the prompting learning module. The prompting learning module can process the concatenated features using operations such as convolution, activation, and pooling (the representativeness of the features can be enhanced by performing the above processing five or more times) to obtain enhanced features. Then, the enhanced features after convolution can be concatenated with the learnable prompting encoding vector to obtain the wafer description encoding, which is then input into the language model. The learnable cue encoding vectors mentioned above can be preset encoding vectors, which can be obtained by extracting features from text related to the field of wafer defect detection. They can be used to improve the language model's focus on the field of wafer inspection.

[0125] In step S133c, the query information input by the user is input into the encoder in the language model to obtain the query code.

[0126] The query encoding obtained by the encoder can help the language model understand the user's intent.

[0127] In step S134c, the wafer description code and query code are input into the decoder in the language model to generate the detection result of the wafer corresponding to the query information.

[0128] The wafer description code and query code can be fused or concatenated to allow the language model to determine the output detection result code based on the features obtained from the fused or concatenated features. Alternatively, feature enhancement processing can be applied to the wafer description code and query code before feature fusion or concatenation to obtain the detection result code. Inputting the detection result code into the decoder generates a natural language-based detection result that responds to the query information.

[0129] In practical scenarios, for example, a user could input the query "Does the wafer die in row i, column j have a defect, and what is the defect type?" (i can be a positive integer less than or equal to the total number of rows, and j can be a positive integer less than or equal to the total number of columns). The language model's detection result could be "A defect exists on the pad, the pad's position coordinates are (x1, y1), and the defect type is pin mark deviation. There is also a scratch defect on the surface, the defect location is (x2, y2)" (x1 and x2 are the horizontal coordinates, and y1 and y2 are the vertical coordinates. In this example, the specific values ​​are not restricted; they can simply represent the position of the pad and the defect location).

[0130] According to the above-described scheme of the present invention, for each defect region, the encoder in the language model generates a defect type code and a location information code for that defect region based on its defect type and location information, respectively. Then, the defect type code and location information code for each defect region are input to the prompting learning module to obtain a wafer description code. Next, the user-inputted query information is input to the encoder in the language model to obtain a query code. Finally, the wafer description code and query code are input to the decoder in the language model to generate the wafer detection result corresponding to the query information. This scheme, by using a language model, enables users to perform targeted queries on wafer dies, facilitating an intuitive and convenient interactive wafer inspection process.

[0131] This invention also provides a wafer inspection device 300. FIG6 shows a schematic block diagram of a wafer inspection device 300 according to an embodiment of the present invention. Referring to FIG6, the inspection device 300 may include: a region determination module 310, a defect type generation module 320, and an inspection result generation module 330.

[0132] The region determination module 310 is used to determine the target wafer grain region and the defect region within each target wafer grain region in the image to be tested on the wafer, wherein defect regions exist within the target wafer grain regions. The defect type generation module 320 is used to determine the defect type of the defect region in each target wafer grain region using the detection model corresponding to the defect region in that target wafer grain region, wherein the detection model corresponding to the defect region is related to the position of the defect region in the target wafer grain region. The detection result generation module 330 is used to determine the detection result of the wafer based on the defect type of the defect region in each target wafer grain region.

[0133] For example, the detection device 300 further includes a wafer grain distribution data determination module and a defect label determination module.

[0134] The wafer grain distribution data determination module is used to determine the wafer grain distribution data of the image under test based on the first location information of the target wafer grain region. The first location information indicates the position of the target wafer grain region in the image under test, and the wafer grain distribution data indicates the position of each wafer grain within the wafer. Furthermore, the identifier corresponding to the target wafer grain region in the wafer grain distribution data is different from the identifiers corresponding to other wafer grain regions. The defect label determination module is used to determine a defect label for each target wafer grain region based on the wafer grain distribution data using a first model. The defect label indicates whether a defect exists in the target wafer grain region.

[0135] The detection result generation module 330 may include a first detection result generation module.

[0136] The first module for generating test results is used to determine the test results of the wafer based on the defect type and defect label of each target wafer grain region.

[0137] For example, the first detection result generation module may include: a first result generation module and a first result and label integrated judgment module.

[0138] The first result generation module generates a first result for each target wafer grain region based on its defect type and location information in the wafer grain distribution data. The first result and label integration and determination module determines the wafer inspection result based on the first result and defect label for each target wafer grain region.

[0139] For example, the detection device 300 may further include a pad area determination module.

[0140] The pad area determination module is used to determine the pad area in each target wafer die region.

[0141] The defect type generation module 320 may include: a first intersection determination module and a second intersection determination module.

[0142] The first intersection determination module is used to determine the defect type of each defect region by using a first detection model corresponding to the defect region, provided that the defect region does not intersect with any pad region. The second intersection determination module is used to determine the defect type of each defect region by using a second detection model corresponding to the defect region, provided that the defect region intersects with any pad region.

[0143] For example, the detection device 300 may further include a defect area image generation module.

[0144] The defect region image generation module is used to crop the image under test according to the size of the defect region for each defect region, provided that the defect region does not intersect with any pad region, in order to obtain the defect region image.

[0145] The first intersection determination module may include the first detection module.

[0146] The first detection module is used to input the defect region image into the first detection model to obtain the defect type of the defect region.

[0147] For example, the detection device 300 may further include a pad area image generation module.

[0148] The pad area image generation module is used to crop the image under test according to the size of the pad area where the defect area intersects with any pad area for each defect area, so as to obtain the pad area image.

[0149] The second intersection determination module may include a second detection module.

[0150] The second detection module is used to input the pad area image into the second detection model to obtain the defect type of the defect area.

[0151] For example, the detection result generation module 330 may include a second result generation module and a second result comprehensive judgment module.

[0152] The second result generation module generates a second result for each defective region based on its defect type and second location information, where the second location information indicates the location of the defective region within the target wafer grain region. The second result synthesis and judgment module determines the wafer's inspection result based on the second result for each defective region.

[0153] For example, the detection result generation module 330 may include: a first encoding generation module, a wafer description encoding generation module, a query encoding generation module, and a decoding generation module.

[0154] The first encoding generation module generates a defect type code and a location information code for each defect region using the encoder in the language model, based on the defect type and location information of that region. The wafer description encoding generation module inputs the defect type code and location information code for each defect region into the prompting learning module to obtain the wafer description code. The query encoding generation module inputs the user-provided query information into the encoder in the language model to obtain the query code. The decoding generation module inputs the wafer description code and the query code into the decoder in the language model to generate the detection result of the wafer corresponding to the query information.

[0155] According to a third aspect of the present invention, an electronic device is also provided. FIG7 shows a schematic block diagram of an electronic device 400 according to an embodiment of the present invention. As shown in FIG7, the electronic device 400 includes a processor 410 and a memory 420, wherein the memory 420 stores a computer program, and the computer program instructions are executed by the processor 410 to perform the above-described wafer inspection method.

[0156] Furthermore, according to a fourth aspect of the present invention, a storage medium is provided, on which program instructions are stored, which, when executed by a computer or processor, cause the computer or processor to perform corresponding steps of the wafer inspection method described in the embodiments of the present invention, and are used to implement corresponding modules in the wafer inspection apparatus or electronic device described in the embodiments of the present invention. The storage medium may, for example, include a memory card of a smartphone, a storage component of a tablet computer, a hard disk of a personal computer, a read-only memory (ROM), an erasable programmable read-only memory (EPROM), a portable compact disc read-only memory (CD-ROM), a USB memory, or any combination of the above storage media. The computer-readable storage medium may be any combination of one or more computer-readable storage media. According to a fifth aspect of the present invention, a computer program product is also provided, comprising computer program instructions, which, when executed by a computer or processor, cause the computer or processor to perform corresponding steps of the wafer inspection method described above.

[0157] Those skilled in the art can understand the specific implementation schemes of the above-mentioned electronic devices and storage media by reading the relevant descriptions of the wafer inspection methods. For the sake of brevity, they will not be described in detail here.

[0158] Although exemplary embodiments have been described herein with reference to the accompanying drawings, it should be understood that the above exemplary embodiments are merely illustrative and are not intended to limit the scope of the invention. Various changes and modifications can be made therein by those skilled in the art without departing from the scope and spirit of the invention. All such changes and modifications are intended to be included within the scope of the invention as claimed in the appended claims.

[0159] Those skilled in the art will recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementations should not be considered beyond the scope of this invention.

[0160] In the several embodiments provided by this invention, it should be understood that the disclosed devices and methods can be implemented in other ways. For example, the device embodiments described above are merely illustrative. For instance, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another device, or some features may be ignored or not executed.

[0161] Numerous specific details are set forth in the specification provided herein. However, it will be understood that embodiments of the invention may be practiced without these specific details. In some instances, well-known methods, structures, and techniques have not been shown in detail so as not to obscure the understanding of this specification.

[0162] Similarly, it should be understood that, in order to streamline the invention and aid in understanding one or more of the various aspects of the invention, features of the invention are sometimes grouped together in a single embodiment, figure, or description thereof in the description of exemplary embodiments of the invention. However, this approach should not be construed as reflecting an intention that the claimed invention requires more features than are expressly recited in each claim. Rather, as reflected in the corresponding claims, its inventive point lies in solving the corresponding technical problem with fewer features than all of those in a single disclosed embodiment. Therefore, the claims following the detailed description are hereby expressly incorporated into that detailed description, wherein each claim itself is a separate embodiment of the invention.

[0163] Those skilled in the art will understand that, apart from the mutual exclusion of features, all features disclosed in this specification (including the accompanying claims, abstract, and drawings) and all processes or units of any method or apparatus so disclosed can be combined in any combination. Unless otherwise expressly stated, each feature disclosed in this specification (including the accompanying claims, abstract, and drawings) may be replaced by an alternative feature that serves the same, equivalent, or similar purpose.

[0164] Furthermore, those skilled in the art will understand that although some embodiments described herein include certain features but not others included in other embodiments, combinations of features from different embodiments are intended to be within the scope of the invention and form different embodiments. For example, in the claims, any of the claimed embodiments can be used in any combination.

[0165] The various component embodiments of the present invention can be implemented in hardware, or as software modules running on one or more processors, or a combination thereof. Those skilled in the art will understand that microprocessors or digital signal processors (DSPs) can be used in practice to implement some or all of the functions of some modules in the wafer inspection apparatus according to embodiments of the present invention. The present invention can also be implemented as an apparatus program (e.g., a computer program and computer program product) for performing part or all of the methods described herein. Such programs implementing the present invention can be stored on a computer-readable medium or can be in the form of one or more signals. Such signals can be downloaded from an Internet website, provided on a carrier signal, or provided in any other form.

[0166] It should be noted that the above embodiments are illustrative of the invention and not restrictive, and that those skilled in the art can devise alternative embodiments without departing from the scope of the appended claims. In the claims, any reference signs placed between parentheses should not be construed as limiting the claims. The word "comprising" does not exclude the presence of elements or steps not listed in the claims. The word "a" or "an" preceding an element does not exclude the presence of a plurality of such elements. The invention can be implemented by means of hardware comprising several different elements and by means of a suitably programmed computer. In the unit claims enumerating several means, several of these means may be embodied by the same item of hardware. The use of the words first, second, and third, etc., does not indicate any order. These words can be interpreted as names.

[0167] The above description is merely a specific embodiment of the present invention or an explanation of that embodiment. The scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention should be included within the scope of protection of the present invention. The scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A method for inspecting wafers, characterized in that, The method includes: In the image to be tested of the wafer, target wafer grain regions and defect regions in each target wafer grain region are identified, wherein defect regions exist in the target wafer grain regions; For each target wafer grain region, the defect type of the defect region in the target wafer grain region is determined by the detection model corresponding to the defect region in the target wafer grain region. The detection model corresponding to the defect region is related to the position of the defect region in the target wafer grain region. The detection result of the wafer is determined based on the defect type of the defect region in each target wafer grain region.

2. The method as described in claim 1, characterized in that, The method further includes: Based on the first location information of the target wafer grain region, the wafer grain distribution data of the image under test is determined, wherein the first location information is used to indicate the position of the target wafer grain region in the image under test, the wafer grain distribution data is used to indicate the position information of each wafer grain in the wafer, and the identifier corresponding to the target wafer grain region in the wafer grain distribution data is different from the identifiers corresponding to other wafer grain regions; Using the first model, based on the wafer grain distribution data, a defect label is determined for each target wafer grain region. The defect label is used to indicate whether a defect exists in the target wafer grain region. The determination of the wafer's inspection result based on the defect type of the defect region in each target wafer grain region includes: The detection result of the wafer is determined based on the defect type and defect label of each target wafer grain region.

3. The method as described in claim 2, characterized in that, The determination of the wafer's inspection result based on the defect type and defect label of each target wafer grain region includes: For each target wafer grain region, a first result for that target wafer grain region is generated based on the defect type of that target wafer grain region and the corresponding location information of that target wafer grain region in the wafer grain distribution data; The detection result of the wafer is determined based on the first result and defect label of each target wafer grain region.

4. The method as described in claim 1, characterized in that, The method further includes: Determine the pad area in each target wafer grain region; For each target wafer grain region, the defect type of the defect region in that target wafer grain region is determined using the detection model corresponding to the defect region in that target wafer grain region, including: For each defective region When there is no intersection between the defective region and any pad region, the defect type of the defective region is determined by the first detection model corresponding to the defective region. If the defective region intersects with any pad region, the defect type of the defective region is determined by the second detection model corresponding to the defective region.

5. The method as described in claim 4, characterized in that, The method further includes: For each defect region, if there is no positional intersection between the defect region and any pad region, the image to be tested is cropped according to the size of the defect region to obtain the defect region image; The step of determining the defect type of the defect area using a first detection model corresponding to the defect area includes: The defect region image is input into the first detection model to obtain the defect type of the defect region.

6. The method as described in claim 4, characterized in that, The method further includes: For each defect region, if the defect region intersects with any pad region, the image to be tested is cropped according to the size of the pad region with the intersection to obtain the pad region image. The step of determining the defect type of the defect area using a second detection model corresponding to the defect area includes: The image of the pad area is input into the second detection model to obtain the defect type of the defect area.

7. The method as described in claim 1, characterized in that, The determination of the wafer's inspection result based on the defect type of the defect region in each target wafer grain region includes: Based on the defect type of each defect region and the second location information of the defect region, a second result for the defect region is generated, wherein the second location information is used to indicate the position of the defect region in the target wafer grain region; The detection result of the wafer is determined based on the second result for each defect region.

8. The method according to any one of claims 1 to 7, characterized in that, The determination of the wafer's inspection result based on the defect type of the defect region in each target wafer grain region includes: For each defect region, the encoder in the language model generates the defect type code and the location information code for that defect region based on the defect type and location information, respectively. The defect type code and location information of each defect region are input into the prompting learning module to obtain the wafer description code; The query information entered by the user is input into the encoder in the language model to obtain the query code; The wafer description code and the query code are input into the decoder in the language model to generate a detection result for the wafer corresponding to the query information.

9. A wafer inspection device, characterized in that, The device includes: The region determination module is used to determine the target wafer grain region and the defect region in each target wafer grain region in the image to be tested of the wafer, wherein the defect region exists in the target wafer grain region; The defect type generation module is used to determine the defect type of each target wafer grain region by using the detection model corresponding to the defect region in the target wafer grain region. The detection model corresponding to the defect region is related to the position of the defect region in the target wafer grain region. The detection result generation module is used to determine the detection result of the wafer based on the defect type of the defect region in each target wafer grain region.

10. An electronic device, characterized in that, The device includes a memory and a processor, wherein the memory is used to store a computer program; and the processor is used to execute the computer program to implement the wafer inspection method as described in any one of claims 1-8.

11. A storage medium storing a computer program / instructions, characterized in that, The computer program / instructions, when running, are used to perform the wafer inspection method as described in any one of claims 1-8.

12. A computer program product comprising computer program instructions, characterized in that, The computer program instructions, when executed, are used to perform the wafer inspection method as described in any one of claims 1-8.

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